1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2003-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/sched.h> 8 #include <linux/wait.h> 9 #include <linux/gfp.h> 10 11 #include "iwl-prph.h" 12 #include "iwl-io.h" 13 #include "internal.h" 14 #include "iwl-op-mode.h" 15 #include "iwl-context-info-gen3.h" 16 17 /****************************************************************************** 18 * 19 * RX path functions 20 * 21 ******************************************************************************/ 22 23 /* 24 * Rx theory of operation 25 * 26 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 27 * each of which point to Receive Buffers to be filled by the NIC. These get 28 * used not only for Rx frames, but for any command response or notification 29 * from the NIC. The driver and NIC manage the Rx buffers by means 30 * of indexes into the circular buffer. 31 * 32 * Rx Queue Indexes 33 * The host/firmware share two index registers for managing the Rx buffers. 34 * 35 * The READ index maps to the first position that the firmware may be writing 36 * to -- the driver can read up to (but not including) this position and get 37 * good data. 38 * The READ index is managed by the firmware once the card is enabled. 39 * 40 * The WRITE index maps to the last position the driver has read from -- the 41 * position preceding WRITE is the last slot the firmware can place a packet. 42 * 43 * The queue is empty (no good data) if WRITE = READ - 1, and is full if 44 * WRITE = READ. 45 * 46 * During initialization, the host sets up the READ queue position to the first 47 * INDEX position, and WRITE to the last (READ - 1 wrapped) 48 * 49 * When the firmware places a packet in a buffer, it will advance the READ index 50 * and fire the RX interrupt. The driver can then query the READ index and 51 * process as many packets as possible, moving the WRITE index forward as it 52 * resets the Rx queue buffers with new memory. 53 * 54 * The management in the driver is as follows: 55 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 56 * When the interrupt handler is called, the request is processed. 57 * The page is either stolen - transferred to the upper layer 58 * or reused - added immediately to the iwl->rxq->rx_free list. 59 * + When the page is stolen - the driver updates the matching queue's used 60 * count, detaches the RBD and transfers it to the queue used list. 61 * When there are two used RBDs - they are transferred to the allocator empty 62 * list. Work is then scheduled for the allocator to start allocating 63 * eight buffers. 64 * When there are another 6 used RBDs - they are transferred to the allocator 65 * empty list and the driver tries to claim the pre-allocated buffers and 66 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 67 * until ready. 68 * When there are 8+ buffers in the free list - either from allocation or from 69 * 8 reused unstolen pages - restock is called to update the FW and indexes. 70 * + In order to make sure the allocator always has RBDs to use for allocation 71 * the allocator has initial pool in the size of num_queues*(8-2) - the 72 * maximum missing RBDs per allocation request (request posted with 2 73 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 74 * The queues supplies the recycle of the rest of the RBDs. 75 * + A received packet is processed and handed to the kernel network stack, 76 * detached from the iwl->rxq. The driver 'processed' index is updated. 77 * + If there are no allocated buffers in iwl->rxq->rx_free, 78 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 79 * If there were enough free buffers and RX_STALLED is set it is cleared. 80 * 81 * 82 * Driver sequence: 83 * 84 * iwl_rxq_alloc() Allocates rx_free 85 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 86 * iwl_pcie_rxq_restock. 87 * Used only during initialization. 88 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 89 * queue, updates firmware pointers, and updates 90 * the WRITE index. 91 * iwl_pcie_rx_allocator() Background work for allocating pages. 92 * 93 * -- enable interrupts -- 94 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 95 * READ INDEX, detaching the SKB from the pool. 96 * Moves the packet buffer from queue to rx_used. 97 * Posts and claims requests to the allocator. 98 * Calls iwl_pcie_rxq_restock to refill any empty 99 * slots. 100 * 101 * RBD life-cycle: 102 * 103 * Init: 104 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 105 * 106 * Regular Receive interrupt: 107 * Page Stolen: 108 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 109 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 110 * Page not Stolen: 111 * rxq.queue -> rxq.rx_free -> rxq.queue 112 * ... 113 * 114 */ 115 116 /* 117 * iwl_rxq_space - Return number of free slots available in queue. 118 */ 119 static int iwl_rxq_space(const struct iwl_rxq *rxq) 120 { 121 /* Make sure rx queue size is a power of 2 */ 122 WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 123 124 /* 125 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 126 * between empty and completely full queues. 127 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 128 * defined for negative dividends. 129 */ 130 return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 131 } 132 133 /* 134 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 135 */ 136 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 137 { 138 return cpu_to_le32((u32)(dma_addr >> 8)); 139 } 140 141 /* 142 * iwl_pcie_rx_stop - stops the Rx DMA 143 */ 144 int iwl_pcie_rx_stop(struct iwl_trans *trans) 145 { 146 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 147 /* TODO: remove this once fw does it */ 148 iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 149 return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3, 150 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 151 } else if (trans->trans_cfg->mq_rx_supported) { 152 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 153 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 154 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 155 } else { 156 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 157 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 158 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 159 1000); 160 } 161 } 162 163 /* 164 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 165 */ 166 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 167 struct iwl_rxq *rxq) 168 { 169 u32 reg; 170 171 lockdep_assert_held(&rxq->lock); 172 173 /* 174 * explicitly wake up the NIC if: 175 * 1. shadow registers aren't enabled 176 * 2. there is a chance that the NIC is asleep 177 */ 178 if (!trans->trans_cfg->base_params->shadow_reg_enable && 179 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 180 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 181 182 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 183 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 184 reg); 185 iwl_set_bit(trans, CSR_GP_CNTRL, 186 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 187 rxq->need_update = true; 188 return; 189 } 190 } 191 192 rxq->write_actual = round_down(rxq->write, 8); 193 if (trans->trans_cfg->mq_rx_supported) 194 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 195 rxq->write_actual); 196 else 197 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 198 } 199 200 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 201 { 202 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 203 int i; 204 205 for (i = 0; i < trans->num_rx_queues; i++) { 206 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 207 208 if (!rxq->need_update) 209 continue; 210 spin_lock_bh(&rxq->lock); 211 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 212 rxq->need_update = false; 213 spin_unlock_bh(&rxq->lock); 214 } 215 } 216 217 static void iwl_pcie_restock_bd(struct iwl_trans *trans, 218 struct iwl_rxq *rxq, 219 struct iwl_rx_mem_buffer *rxb) 220 { 221 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 222 struct iwl_rx_transfer_desc *bd = rxq->bd; 223 224 BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64)); 225 226 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 227 bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 228 } else { 229 __le64 *bd = rxq->bd; 230 231 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 232 } 233 234 IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n", 235 (u32)rxb->vid, rxq->id, rxq->write); 236 } 237 238 /* 239 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 240 */ 241 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 242 struct iwl_rxq *rxq) 243 { 244 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 245 struct iwl_rx_mem_buffer *rxb; 246 247 /* 248 * If the device isn't enabled - no need to try to add buffers... 249 * This can happen when we stop the device and still have an interrupt 250 * pending. We stop the APM before we sync the interrupts because we 251 * have to (see comment there). On the other hand, since the APM is 252 * stopped, we cannot access the HW (in particular not prph). 253 * So don't try to restock if the APM has been already stopped. 254 */ 255 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 256 return; 257 258 spin_lock_bh(&rxq->lock); 259 while (rxq->free_count) { 260 /* Get next free Rx buffer, remove from free list */ 261 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 262 list); 263 list_del(&rxb->list); 264 rxb->invalid = false; 265 /* some low bits are expected to be unset (depending on hw) */ 266 WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask); 267 /* Point to Rx buffer via next RBD in circular buffer */ 268 iwl_pcie_restock_bd(trans, rxq, rxb); 269 rxq->write = (rxq->write + 1) & (rxq->queue_size - 1); 270 rxq->free_count--; 271 } 272 spin_unlock_bh(&rxq->lock); 273 274 /* 275 * If we've added more space for the firmware to place data, tell it. 276 * Increment device's write pointer in multiples of 8. 277 */ 278 if (rxq->write_actual != (rxq->write & ~0x7)) { 279 spin_lock_bh(&rxq->lock); 280 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 281 spin_unlock_bh(&rxq->lock); 282 } 283 } 284 285 /* 286 * iwl_pcie_rxsq_restock - restock implementation for single queue rx 287 */ 288 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 289 struct iwl_rxq *rxq) 290 { 291 struct iwl_rx_mem_buffer *rxb; 292 293 /* 294 * If the device isn't enabled - not need to try to add buffers... 295 * This can happen when we stop the device and still have an interrupt 296 * pending. We stop the APM before we sync the interrupts because we 297 * have to (see comment there). On the other hand, since the APM is 298 * stopped, we cannot access the HW (in particular not prph). 299 * So don't try to restock if the APM has been already stopped. 300 */ 301 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 302 return; 303 304 spin_lock_bh(&rxq->lock); 305 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 306 __le32 *bd = (__le32 *)rxq->bd; 307 /* The overwritten rxb must be a used one */ 308 rxb = rxq->queue[rxq->write]; 309 BUG_ON(rxb && rxb->page); 310 311 /* Get next free Rx buffer, remove from free list */ 312 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 313 list); 314 list_del(&rxb->list); 315 rxb->invalid = false; 316 317 /* Point to Rx buffer via next RBD in circular buffer */ 318 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 319 rxq->queue[rxq->write] = rxb; 320 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 321 rxq->free_count--; 322 } 323 spin_unlock_bh(&rxq->lock); 324 325 /* If we've added more space for the firmware to place data, tell it. 326 * Increment device's write pointer in multiples of 8. */ 327 if (rxq->write_actual != (rxq->write & ~0x7)) { 328 spin_lock_bh(&rxq->lock); 329 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 330 spin_unlock_bh(&rxq->lock); 331 } 332 } 333 334 /* 335 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 336 * 337 * If there are slots in the RX queue that need to be restocked, 338 * and we have free pre-allocated buffers, fill the ranks as much 339 * as we can, pulling from rx_free. 340 * 341 * This moves the 'write' index forward to catch up with 'processed', and 342 * also updates the memory address in the firmware to reference the new 343 * target buffer. 344 */ 345 static 346 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 347 { 348 if (trans->trans_cfg->mq_rx_supported) 349 iwl_pcie_rxmq_restock(trans, rxq); 350 else 351 iwl_pcie_rxsq_restock(trans, rxq); 352 } 353 354 /* 355 * iwl_pcie_rx_alloc_page - allocates and returns a page. 356 * 357 */ 358 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 359 u32 *offset, gfp_t priority) 360 { 361 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 362 unsigned int rbsize = iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 363 unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order; 364 struct page *page; 365 gfp_t gfp_mask = priority; 366 367 if (trans_pcie->rx_page_order > 0) 368 gfp_mask |= __GFP_COMP; 369 370 if (trans_pcie->alloc_page) { 371 spin_lock_bh(&trans_pcie->alloc_page_lock); 372 /* recheck */ 373 if (trans_pcie->alloc_page) { 374 *offset = trans_pcie->alloc_page_used; 375 page = trans_pcie->alloc_page; 376 trans_pcie->alloc_page_used += rbsize; 377 if (trans_pcie->alloc_page_used >= allocsize) 378 trans_pcie->alloc_page = NULL; 379 else 380 get_page(page); 381 spin_unlock_bh(&trans_pcie->alloc_page_lock); 382 return page; 383 } 384 spin_unlock_bh(&trans_pcie->alloc_page_lock); 385 } 386 387 /* Alloc a new receive buffer */ 388 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 389 if (!page) { 390 if (net_ratelimit()) 391 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 392 trans_pcie->rx_page_order); 393 /* 394 * Issue an error if we don't have enough pre-allocated 395 * buffers. 396 */ 397 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 398 IWL_CRIT(trans, 399 "Failed to alloc_pages\n"); 400 return NULL; 401 } 402 403 if (2 * rbsize <= allocsize) { 404 spin_lock_bh(&trans_pcie->alloc_page_lock); 405 if (!trans_pcie->alloc_page) { 406 get_page(page); 407 trans_pcie->alloc_page = page; 408 trans_pcie->alloc_page_used = rbsize; 409 } 410 spin_unlock_bh(&trans_pcie->alloc_page_lock); 411 } 412 413 *offset = 0; 414 return page; 415 } 416 417 /* 418 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 419 * 420 * A used RBD is an Rx buffer that has been given to the stack. To use it again 421 * a page must be allocated and the RBD must point to the page. This function 422 * doesn't change the HW pointer but handles the list of pages that is used by 423 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 424 * allocated buffers. 425 */ 426 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 427 struct iwl_rxq *rxq) 428 { 429 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 430 struct iwl_rx_mem_buffer *rxb; 431 struct page *page; 432 433 while (1) { 434 unsigned int offset; 435 436 spin_lock_bh(&rxq->lock); 437 if (list_empty(&rxq->rx_used)) { 438 spin_unlock_bh(&rxq->lock); 439 return; 440 } 441 spin_unlock_bh(&rxq->lock); 442 443 page = iwl_pcie_rx_alloc_page(trans, &offset, priority); 444 if (!page) 445 return; 446 447 spin_lock_bh(&rxq->lock); 448 449 if (list_empty(&rxq->rx_used)) { 450 spin_unlock_bh(&rxq->lock); 451 __free_pages(page, trans_pcie->rx_page_order); 452 return; 453 } 454 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 455 list); 456 list_del(&rxb->list); 457 spin_unlock_bh(&rxq->lock); 458 459 BUG_ON(rxb->page); 460 rxb->page = page; 461 rxb->offset = offset; 462 /* Get physical address of the RB */ 463 rxb->page_dma = 464 dma_map_page(trans->dev, page, rxb->offset, 465 trans_pcie->rx_buf_bytes, 466 DMA_FROM_DEVICE); 467 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 468 rxb->page = NULL; 469 spin_lock_bh(&rxq->lock); 470 list_add(&rxb->list, &rxq->rx_used); 471 spin_unlock_bh(&rxq->lock); 472 __free_pages(page, trans_pcie->rx_page_order); 473 return; 474 } 475 476 spin_lock_bh(&rxq->lock); 477 478 list_add_tail(&rxb->list, &rxq->rx_free); 479 rxq->free_count++; 480 481 spin_unlock_bh(&rxq->lock); 482 } 483 } 484 485 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 486 { 487 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 488 int i; 489 490 if (!trans_pcie->rx_pool) 491 return; 492 493 for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) { 494 if (!trans_pcie->rx_pool[i].page) 495 continue; 496 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 497 trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE); 498 __free_pages(trans_pcie->rx_pool[i].page, 499 trans_pcie->rx_page_order); 500 trans_pcie->rx_pool[i].page = NULL; 501 } 502 } 503 504 /* 505 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 506 * 507 * Allocates for each received request 8 pages 508 * Called as a scheduled work item. 509 */ 510 static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 511 { 512 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 513 struct iwl_rb_allocator *rba = &trans_pcie->rba; 514 struct list_head local_empty; 515 int pending = atomic_read(&rba->req_pending); 516 517 IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending); 518 519 /* If we were scheduled - there is at least one request */ 520 spin_lock_bh(&rba->lock); 521 /* swap out the rba->rbd_empty to a local list */ 522 list_replace_init(&rba->rbd_empty, &local_empty); 523 spin_unlock_bh(&rba->lock); 524 525 while (pending) { 526 int i; 527 LIST_HEAD(local_allocated); 528 gfp_t gfp_mask = GFP_KERNEL; 529 530 /* Do not post a warning if there are only a few requests */ 531 if (pending < RX_PENDING_WATERMARK) 532 gfp_mask |= __GFP_NOWARN; 533 534 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 535 struct iwl_rx_mem_buffer *rxb; 536 struct page *page; 537 538 /* List should never be empty - each reused RBD is 539 * returned to the list, and initial pool covers any 540 * possible gap between the time the page is allocated 541 * to the time the RBD is added. 542 */ 543 BUG_ON(list_empty(&local_empty)); 544 /* Get the first rxb from the rbd list */ 545 rxb = list_first_entry(&local_empty, 546 struct iwl_rx_mem_buffer, list); 547 BUG_ON(rxb->page); 548 549 /* Alloc a new receive buffer */ 550 page = iwl_pcie_rx_alloc_page(trans, &rxb->offset, 551 gfp_mask); 552 if (!page) 553 continue; 554 rxb->page = page; 555 556 /* Get physical address of the RB */ 557 rxb->page_dma = dma_map_page(trans->dev, page, 558 rxb->offset, 559 trans_pcie->rx_buf_bytes, 560 DMA_FROM_DEVICE); 561 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 562 rxb->page = NULL; 563 __free_pages(page, trans_pcie->rx_page_order); 564 continue; 565 } 566 567 /* move the allocated entry to the out list */ 568 list_move(&rxb->list, &local_allocated); 569 i++; 570 } 571 572 atomic_dec(&rba->req_pending); 573 pending--; 574 575 if (!pending) { 576 pending = atomic_read(&rba->req_pending); 577 if (pending) 578 IWL_DEBUG_TPT(trans, 579 "Got more pending allocation requests = %d\n", 580 pending); 581 } 582 583 spin_lock_bh(&rba->lock); 584 /* add the allocated rbds to the allocator allocated list */ 585 list_splice_tail(&local_allocated, &rba->rbd_allocated); 586 /* get more empty RBDs for current pending requests */ 587 list_splice_tail_init(&rba->rbd_empty, &local_empty); 588 spin_unlock_bh(&rba->lock); 589 590 atomic_inc(&rba->req_ready); 591 592 } 593 594 spin_lock_bh(&rba->lock); 595 /* return unused rbds to the allocator empty list */ 596 list_splice_tail(&local_empty, &rba->rbd_empty); 597 spin_unlock_bh(&rba->lock); 598 599 IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__); 600 } 601 602 /* 603 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 604 .* 605 .* Called by queue when the queue posted allocation request and 606 * has freed 8 RBDs in order to restock itself. 607 * This function directly moves the allocated RBs to the queue's ownership 608 * and updates the relevant counters. 609 */ 610 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 611 struct iwl_rxq *rxq) 612 { 613 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 614 struct iwl_rb_allocator *rba = &trans_pcie->rba; 615 int i; 616 617 lockdep_assert_held(&rxq->lock); 618 619 /* 620 * atomic_dec_if_positive returns req_ready - 1 for any scenario. 621 * If req_ready is 0 atomic_dec_if_positive will return -1 and this 622 * function will return early, as there are no ready requests. 623 * atomic_dec_if_positive will perofrm the *actual* decrement only if 624 * req_ready > 0, i.e. - there are ready requests and the function 625 * hands one request to the caller. 626 */ 627 if (atomic_dec_if_positive(&rba->req_ready) < 0) 628 return; 629 630 spin_lock(&rba->lock); 631 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 632 /* Get next free Rx buffer, remove it from free list */ 633 struct iwl_rx_mem_buffer *rxb = 634 list_first_entry(&rba->rbd_allocated, 635 struct iwl_rx_mem_buffer, list); 636 637 list_move(&rxb->list, &rxq->rx_free); 638 } 639 spin_unlock(&rba->lock); 640 641 rxq->used_count -= RX_CLAIM_REQ_ALLOC; 642 rxq->free_count += RX_CLAIM_REQ_ALLOC; 643 } 644 645 void iwl_pcie_rx_allocator_work(struct work_struct *data) 646 { 647 struct iwl_rb_allocator *rba_p = 648 container_of(data, struct iwl_rb_allocator, rx_alloc); 649 struct iwl_trans_pcie *trans_pcie = 650 container_of(rba_p, struct iwl_trans_pcie, rba); 651 652 iwl_pcie_rx_allocator(trans_pcie->trans); 653 } 654 655 static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td) 656 { 657 struct iwl_rx_transfer_desc *rx_td; 658 659 if (use_rx_td) 660 return sizeof(*rx_td); 661 else 662 return trans->trans_cfg->mq_rx_supported ? sizeof(__le64) : 663 sizeof(__le32); 664 } 665 666 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 667 struct iwl_rxq *rxq) 668 { 669 bool use_rx_td = (trans->trans_cfg->device_family >= 670 IWL_DEVICE_FAMILY_AX210); 671 int free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 672 673 if (rxq->bd) 674 dma_free_coherent(trans->dev, 675 free_size * rxq->queue_size, 676 rxq->bd, rxq->bd_dma); 677 rxq->bd_dma = 0; 678 rxq->bd = NULL; 679 680 rxq->rb_stts_dma = 0; 681 rxq->rb_stts = NULL; 682 683 if (rxq->used_bd) 684 dma_free_coherent(trans->dev, 685 (use_rx_td ? sizeof(*rxq->cd) : 686 sizeof(__le32)) * rxq->queue_size, 687 rxq->used_bd, rxq->used_bd_dma); 688 rxq->used_bd_dma = 0; 689 rxq->used_bd = NULL; 690 } 691 692 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 693 struct iwl_rxq *rxq) 694 { 695 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 696 struct device *dev = trans->dev; 697 int i; 698 int free_size; 699 bool use_rx_td = (trans->trans_cfg->device_family >= 700 IWL_DEVICE_FAMILY_AX210); 701 size_t rb_stts_size = use_rx_td ? sizeof(__le16) : 702 sizeof(struct iwl_rb_status); 703 704 spin_lock_init(&rxq->lock); 705 if (trans->trans_cfg->mq_rx_supported) 706 rxq->queue_size = trans->cfg->num_rbds; 707 else 708 rxq->queue_size = RX_QUEUE_SIZE; 709 710 free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 711 712 /* 713 * Allocate the circular buffer of Read Buffer Descriptors 714 * (RBDs) 715 */ 716 rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size, 717 &rxq->bd_dma, GFP_KERNEL); 718 if (!rxq->bd) 719 goto err; 720 721 if (trans->trans_cfg->mq_rx_supported) { 722 rxq->used_bd = dma_alloc_coherent(dev, 723 (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size, 724 &rxq->used_bd_dma, 725 GFP_KERNEL); 726 if (!rxq->used_bd) 727 goto err; 728 } 729 730 rxq->rb_stts = trans_pcie->base_rb_stts + rxq->id * rb_stts_size; 731 rxq->rb_stts_dma = 732 trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size; 733 734 return 0; 735 736 err: 737 for (i = 0; i < trans->num_rx_queues; i++) { 738 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 739 740 iwl_pcie_free_rxq_dma(trans, rxq); 741 } 742 743 return -ENOMEM; 744 } 745 746 static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 747 { 748 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 749 struct iwl_rb_allocator *rba = &trans_pcie->rba; 750 int i, ret; 751 size_t rb_stts_size = trans->trans_cfg->device_family >= 752 IWL_DEVICE_FAMILY_AX210 ? 753 sizeof(__le16) : sizeof(struct iwl_rb_status); 754 755 if (WARN_ON(trans_pcie->rxq)) 756 return -EINVAL; 757 758 trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 759 GFP_KERNEL); 760 trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 761 sizeof(trans_pcie->rx_pool[0]), 762 GFP_KERNEL); 763 trans_pcie->global_table = 764 kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 765 sizeof(trans_pcie->global_table[0]), 766 GFP_KERNEL); 767 if (!trans_pcie->rxq || !trans_pcie->rx_pool || 768 !trans_pcie->global_table) { 769 ret = -ENOMEM; 770 goto err; 771 } 772 773 spin_lock_init(&rba->lock); 774 775 /* 776 * Allocate the driver's pointer to receive buffer status. 777 * Allocate for all queues continuously (HW requirement). 778 */ 779 trans_pcie->base_rb_stts = 780 dma_alloc_coherent(trans->dev, 781 rb_stts_size * trans->num_rx_queues, 782 &trans_pcie->base_rb_stts_dma, 783 GFP_KERNEL); 784 if (!trans_pcie->base_rb_stts) { 785 ret = -ENOMEM; 786 goto err; 787 } 788 789 for (i = 0; i < trans->num_rx_queues; i++) { 790 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 791 792 rxq->id = i; 793 ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 794 if (ret) 795 goto err; 796 } 797 return 0; 798 799 err: 800 if (trans_pcie->base_rb_stts) { 801 dma_free_coherent(trans->dev, 802 rb_stts_size * trans->num_rx_queues, 803 trans_pcie->base_rb_stts, 804 trans_pcie->base_rb_stts_dma); 805 trans_pcie->base_rb_stts = NULL; 806 trans_pcie->base_rb_stts_dma = 0; 807 } 808 kfree(trans_pcie->rx_pool); 809 trans_pcie->rx_pool = NULL; 810 kfree(trans_pcie->global_table); 811 trans_pcie->global_table = NULL; 812 kfree(trans_pcie->rxq); 813 trans_pcie->rxq = NULL; 814 815 return ret; 816 } 817 818 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 819 { 820 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 821 u32 rb_size; 822 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 823 824 switch (trans_pcie->rx_buf_size) { 825 case IWL_AMSDU_4K: 826 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 827 break; 828 case IWL_AMSDU_8K: 829 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 830 break; 831 case IWL_AMSDU_12K: 832 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 833 break; 834 default: 835 WARN_ON(1); 836 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 837 } 838 839 if (!iwl_trans_grab_nic_access(trans)) 840 return; 841 842 /* Stop Rx DMA */ 843 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 844 /* reset and flush pointers */ 845 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 846 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 847 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 848 849 /* Reset driver's Rx queue write index */ 850 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 851 852 /* Tell device where to find RBD circular buffer in DRAM */ 853 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 854 (u32)(rxq->bd_dma >> 8)); 855 856 /* Tell device where in DRAM to update its Rx status */ 857 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 858 rxq->rb_stts_dma >> 4); 859 860 /* Enable Rx DMA 861 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 862 * the credit mechanism in 5000 HW RX FIFO 863 * Direct rx interrupts to hosts 864 * Rx buffer size 4 or 8k or 12k 865 * RB timeout 0x10 866 * 256 RBDs 867 */ 868 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 869 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 870 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 871 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 872 rb_size | 873 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 874 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 875 876 iwl_trans_release_nic_access(trans); 877 878 /* Set interrupt coalescing timer to default (2048 usecs) */ 879 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 880 881 /* W/A for interrupt coalescing bug in 7260 and 3160 */ 882 if (trans->cfg->host_interrupt_operation_mode) 883 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 884 } 885 886 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 887 { 888 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 889 u32 rb_size, enabled = 0; 890 int i; 891 892 switch (trans_pcie->rx_buf_size) { 893 case IWL_AMSDU_2K: 894 rb_size = RFH_RXF_DMA_RB_SIZE_2K; 895 break; 896 case IWL_AMSDU_4K: 897 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 898 break; 899 case IWL_AMSDU_8K: 900 rb_size = RFH_RXF_DMA_RB_SIZE_8K; 901 break; 902 case IWL_AMSDU_12K: 903 rb_size = RFH_RXF_DMA_RB_SIZE_12K; 904 break; 905 default: 906 WARN_ON(1); 907 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 908 } 909 910 if (!iwl_trans_grab_nic_access(trans)) 911 return; 912 913 /* Stop Rx DMA */ 914 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 915 /* disable free amd used rx queue operation */ 916 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 917 918 for (i = 0; i < trans->num_rx_queues; i++) { 919 /* Tell device where to find RBD free table in DRAM */ 920 iwl_write_prph64_no_grab(trans, 921 RFH_Q_FRBDCB_BA_LSB(i), 922 trans_pcie->rxq[i].bd_dma); 923 /* Tell device where to find RBD used table in DRAM */ 924 iwl_write_prph64_no_grab(trans, 925 RFH_Q_URBDCB_BA_LSB(i), 926 trans_pcie->rxq[i].used_bd_dma); 927 /* Tell device where in DRAM to update its Rx status */ 928 iwl_write_prph64_no_grab(trans, 929 RFH_Q_URBD_STTS_WPTR_LSB(i), 930 trans_pcie->rxq[i].rb_stts_dma); 931 /* Reset device indice tables */ 932 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 933 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 934 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 935 936 enabled |= BIT(i) | BIT(i + 16); 937 } 938 939 /* 940 * Enable Rx DMA 941 * Rx buffer size 4 or 8k or 12k 942 * Min RB size 4 or 8 943 * Drop frames that exceed RB size 944 * 512 RBDs 945 */ 946 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 947 RFH_DMA_EN_ENABLE_VAL | rb_size | 948 RFH_RXF_DMA_MIN_RB_4_8 | 949 RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 950 RFH_RXF_DMA_RBDCB_SIZE_512); 951 952 /* 953 * Activate DMA snooping. 954 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 955 * Default queue is 0 956 */ 957 iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 958 RFH_GEN_CFG_RFH_DMA_SNOOP | 959 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 960 RFH_GEN_CFG_SERVICE_DMA_SNOOP | 961 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 962 trans->trans_cfg->integrated ? 963 RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 964 RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 965 /* Enable the relevant rx queues */ 966 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 967 968 iwl_trans_release_nic_access(trans); 969 970 /* Set interrupt coalescing timer to default (2048 usecs) */ 971 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 972 } 973 974 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 975 { 976 lockdep_assert_held(&rxq->lock); 977 978 INIT_LIST_HEAD(&rxq->rx_free); 979 INIT_LIST_HEAD(&rxq->rx_used); 980 rxq->free_count = 0; 981 rxq->used_count = 0; 982 } 983 984 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget); 985 986 static int iwl_pcie_napi_poll(struct napi_struct *napi, int budget) 987 { 988 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 989 struct iwl_trans_pcie *trans_pcie; 990 struct iwl_trans *trans; 991 int ret; 992 993 trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 994 trans = trans_pcie->trans; 995 996 ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 997 998 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", 999 rxq->id, ret, budget); 1000 1001 if (ret < budget) { 1002 spin_lock(&trans_pcie->irq_lock); 1003 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1004 _iwl_enable_interrupts(trans); 1005 spin_unlock(&trans_pcie->irq_lock); 1006 1007 napi_complete_done(&rxq->napi, ret); 1008 } 1009 1010 return ret; 1011 } 1012 1013 static int iwl_pcie_napi_poll_msix(struct napi_struct *napi, int budget) 1014 { 1015 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 1016 struct iwl_trans_pcie *trans_pcie; 1017 struct iwl_trans *trans; 1018 int ret; 1019 1020 trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 1021 trans = trans_pcie->trans; 1022 1023 ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 1024 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", rxq->id, ret, 1025 budget); 1026 1027 if (ret < budget) { 1028 int irq_line = rxq->id; 1029 1030 /* FIRST_RSS is shared with line 0 */ 1031 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS && 1032 rxq->id == 1) 1033 irq_line = 0; 1034 1035 spin_lock(&trans_pcie->irq_lock); 1036 iwl_pcie_clear_irq(trans, irq_line); 1037 spin_unlock(&trans_pcie->irq_lock); 1038 1039 napi_complete_done(&rxq->napi, ret); 1040 } 1041 1042 return ret; 1043 } 1044 1045 static int _iwl_pcie_rx_init(struct iwl_trans *trans) 1046 { 1047 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1048 struct iwl_rxq *def_rxq; 1049 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1050 int i, err, queue_size, allocator_pool_size, num_alloc; 1051 1052 if (!trans_pcie->rxq) { 1053 err = iwl_pcie_rx_alloc(trans); 1054 if (err) 1055 return err; 1056 } 1057 def_rxq = trans_pcie->rxq; 1058 1059 cancel_work_sync(&rba->rx_alloc); 1060 1061 spin_lock_bh(&rba->lock); 1062 atomic_set(&rba->req_pending, 0); 1063 atomic_set(&rba->req_ready, 0); 1064 INIT_LIST_HEAD(&rba->rbd_allocated); 1065 INIT_LIST_HEAD(&rba->rbd_empty); 1066 spin_unlock_bh(&rba->lock); 1067 1068 /* free all first - we overwrite everything here */ 1069 iwl_pcie_free_rbs_pool(trans); 1070 1071 for (i = 0; i < RX_QUEUE_SIZE; i++) 1072 def_rxq->queue[i] = NULL; 1073 1074 for (i = 0; i < trans->num_rx_queues; i++) { 1075 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1076 1077 spin_lock_bh(&rxq->lock); 1078 /* 1079 * Set read write pointer to reflect that we have processed 1080 * and used all buffers, but have not restocked the Rx queue 1081 * with fresh buffers 1082 */ 1083 rxq->read = 0; 1084 rxq->write = 0; 1085 rxq->write_actual = 0; 1086 memset(rxq->rb_stts, 0, 1087 (trans->trans_cfg->device_family >= 1088 IWL_DEVICE_FAMILY_AX210) ? 1089 sizeof(__le16) : sizeof(struct iwl_rb_status)); 1090 1091 iwl_pcie_rx_init_rxb_lists(rxq); 1092 1093 spin_unlock_bh(&rxq->lock); 1094 1095 if (!rxq->napi.poll) { 1096 int (*poll)(struct napi_struct *, int) = iwl_pcie_napi_poll; 1097 1098 if (trans_pcie->msix_enabled) 1099 poll = iwl_pcie_napi_poll_msix; 1100 1101 netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 1102 poll, NAPI_POLL_WEIGHT); 1103 napi_enable(&rxq->napi); 1104 } 1105 1106 } 1107 1108 /* move the pool to the default queue and allocator ownerships */ 1109 queue_size = trans->trans_cfg->mq_rx_supported ? 1110 trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE; 1111 allocator_pool_size = trans->num_rx_queues * 1112 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 1113 num_alloc = queue_size + allocator_pool_size; 1114 1115 for (i = 0; i < num_alloc; i++) { 1116 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 1117 1118 if (i < allocator_pool_size) 1119 list_add(&rxb->list, &rba->rbd_empty); 1120 else 1121 list_add(&rxb->list, &def_rxq->rx_used); 1122 trans_pcie->global_table[i] = rxb; 1123 rxb->vid = (u16)(i + 1); 1124 rxb->invalid = true; 1125 } 1126 1127 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 1128 1129 return 0; 1130 } 1131 1132 int iwl_pcie_rx_init(struct iwl_trans *trans) 1133 { 1134 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1135 int ret = _iwl_pcie_rx_init(trans); 1136 1137 if (ret) 1138 return ret; 1139 1140 if (trans->trans_cfg->mq_rx_supported) 1141 iwl_pcie_rx_mq_hw_init(trans); 1142 else 1143 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 1144 1145 iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 1146 1147 spin_lock_bh(&trans_pcie->rxq->lock); 1148 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 1149 spin_unlock_bh(&trans_pcie->rxq->lock); 1150 1151 return 0; 1152 } 1153 1154 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1155 { 1156 /* Set interrupt coalescing timer to default (2048 usecs) */ 1157 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1158 1159 /* 1160 * We don't configure the RFH. 1161 * Restock will be done at alive, after firmware configured the RFH. 1162 */ 1163 return _iwl_pcie_rx_init(trans); 1164 } 1165 1166 void iwl_pcie_rx_free(struct iwl_trans *trans) 1167 { 1168 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1169 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1170 int i; 1171 size_t rb_stts_size = trans->trans_cfg->device_family >= 1172 IWL_DEVICE_FAMILY_AX210 ? 1173 sizeof(__le16) : sizeof(struct iwl_rb_status); 1174 1175 /* 1176 * if rxq is NULL, it means that nothing has been allocated, 1177 * exit now 1178 */ 1179 if (!trans_pcie->rxq) { 1180 IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1181 return; 1182 } 1183 1184 cancel_work_sync(&rba->rx_alloc); 1185 1186 iwl_pcie_free_rbs_pool(trans); 1187 1188 if (trans_pcie->base_rb_stts) { 1189 dma_free_coherent(trans->dev, 1190 rb_stts_size * trans->num_rx_queues, 1191 trans_pcie->base_rb_stts, 1192 trans_pcie->base_rb_stts_dma); 1193 trans_pcie->base_rb_stts = NULL; 1194 trans_pcie->base_rb_stts_dma = 0; 1195 } 1196 1197 for (i = 0; i < trans->num_rx_queues; i++) { 1198 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1199 1200 iwl_pcie_free_rxq_dma(trans, rxq); 1201 1202 if (rxq->napi.poll) { 1203 napi_disable(&rxq->napi); 1204 netif_napi_del(&rxq->napi); 1205 } 1206 } 1207 kfree(trans_pcie->rx_pool); 1208 kfree(trans_pcie->global_table); 1209 kfree(trans_pcie->rxq); 1210 1211 if (trans_pcie->alloc_page) 1212 __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order); 1213 } 1214 1215 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq, 1216 struct iwl_rb_allocator *rba) 1217 { 1218 spin_lock(&rba->lock); 1219 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1220 spin_unlock(&rba->lock); 1221 } 1222 1223 /* 1224 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1225 * 1226 * Called when a RBD can be reused. The RBD is transferred to the allocator. 1227 * When there are 2 empty RBDs - a request for allocation is posted 1228 */ 1229 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1230 struct iwl_rx_mem_buffer *rxb, 1231 struct iwl_rxq *rxq, bool emergency) 1232 { 1233 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1234 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1235 1236 /* Move the RBD to the used list, will be moved to allocator in batches 1237 * before claiming or posting a request*/ 1238 list_add_tail(&rxb->list, &rxq->rx_used); 1239 1240 if (unlikely(emergency)) 1241 return; 1242 1243 /* Count the allocator owned RBDs */ 1244 rxq->used_count++; 1245 1246 /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1247 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1248 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1249 * after but we still need to post another request. 1250 */ 1251 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1252 /* Move the 2 RBDs to the allocator ownership. 1253 Allocator has another 6 from pool for the request completion*/ 1254 iwl_pcie_rx_move_to_allocator(rxq, rba); 1255 1256 atomic_inc(&rba->req_pending); 1257 queue_work(rba->alloc_wq, &rba->rx_alloc); 1258 } 1259 } 1260 1261 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 1262 struct iwl_rxq *rxq, 1263 struct iwl_rx_mem_buffer *rxb, 1264 bool emergency, 1265 int i) 1266 { 1267 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1268 struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id]; 1269 bool page_stolen = false; 1270 int max_len = trans_pcie->rx_buf_bytes; 1271 u32 offset = 0; 1272 1273 if (WARN_ON(!rxb)) 1274 return; 1275 1276 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1277 1278 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1279 struct iwl_rx_packet *pkt; 1280 bool reclaim; 1281 int len; 1282 struct iwl_rx_cmd_buffer rxcb = { 1283 ._offset = rxb->offset + offset, 1284 ._rx_page_order = trans_pcie->rx_page_order, 1285 ._page = rxb->page, 1286 ._page_stolen = false, 1287 .truesize = max_len, 1288 }; 1289 1290 pkt = rxb_addr(&rxcb); 1291 1292 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 1293 IWL_DEBUG_RX(trans, 1294 "Q %d: RB end marker at offset %d\n", 1295 rxq->id, offset); 1296 break; 1297 } 1298 1299 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1300 FH_RSCSR_RXQ_POS != rxq->id, 1301 "frame on invalid queue - is on %d and indicates %d\n", 1302 rxq->id, 1303 (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1304 FH_RSCSR_RXQ_POS); 1305 1306 IWL_DEBUG_RX(trans, 1307 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 1308 rxq->id, offset, 1309 iwl_get_cmd_string(trans, 1310 WIDE_ID(pkt->hdr.group_id, pkt->hdr.cmd)), 1311 pkt->hdr.group_id, pkt->hdr.cmd, 1312 le16_to_cpu(pkt->hdr.sequence)); 1313 1314 len = iwl_rx_packet_len(pkt); 1315 len += sizeof(u32); /* account for status word */ 1316 1317 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1318 1319 /* check that what the device tells us made sense */ 1320 if (offset > max_len) 1321 break; 1322 1323 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1324 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1325 1326 /* Reclaim a command buffer only if this packet is a response 1327 * to a (driver-originated) command. 1328 * If the packet (e.g. Rx frame) originated from uCode, 1329 * there is no command buffer to reclaim. 1330 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1331 * but apparently a few don't get set; catch them here. */ 1332 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1333 if (reclaim && !pkt->hdr.group_id) { 1334 int i; 1335 1336 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1337 if (trans_pcie->no_reclaim_cmds[i] == 1338 pkt->hdr.cmd) { 1339 reclaim = false; 1340 break; 1341 } 1342 } 1343 } 1344 1345 if (rxq->id == trans_pcie->def_rx_queue) 1346 iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1347 &rxcb); 1348 else 1349 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1350 &rxcb, rxq->id); 1351 1352 /* 1353 * After here, we should always check rxcb._page_stolen, 1354 * if it is true then one of the handlers took the page. 1355 */ 1356 1357 if (reclaim) { 1358 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1359 int index = SEQ_TO_INDEX(sequence); 1360 int cmd_index = iwl_txq_get_cmd_index(txq, index); 1361 1362 kfree_sensitive(txq->entries[cmd_index].free_buf); 1363 txq->entries[cmd_index].free_buf = NULL; 1364 1365 /* Invoke any callbacks, transfer the buffer to caller, 1366 * and fire off the (possibly) blocking 1367 * iwl_trans_send_cmd() 1368 * as we reclaim the driver command queue */ 1369 if (!rxcb._page_stolen) 1370 iwl_pcie_hcmd_complete(trans, &rxcb); 1371 else 1372 IWL_WARN(trans, "Claim null rxb?\n"); 1373 } 1374 1375 page_stolen |= rxcb._page_stolen; 1376 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1377 break; 1378 } 1379 1380 /* page was stolen from us -- free our reference */ 1381 if (page_stolen) { 1382 __free_pages(rxb->page, trans_pcie->rx_page_order); 1383 rxb->page = NULL; 1384 } 1385 1386 /* Reuse the page if possible. For notification packets and 1387 * SKBs that fail to Rx correctly, add them back into the 1388 * rx_free list for reuse later. */ 1389 if (rxb->page != NULL) { 1390 rxb->page_dma = 1391 dma_map_page(trans->dev, rxb->page, rxb->offset, 1392 trans_pcie->rx_buf_bytes, 1393 DMA_FROM_DEVICE); 1394 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1395 /* 1396 * free the page(s) as well to not break 1397 * the invariant that the items on the used 1398 * list have no page(s) 1399 */ 1400 __free_pages(rxb->page, trans_pcie->rx_page_order); 1401 rxb->page = NULL; 1402 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1403 } else { 1404 list_add_tail(&rxb->list, &rxq->rx_free); 1405 rxq->free_count++; 1406 } 1407 } else 1408 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1409 } 1410 1411 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans, 1412 struct iwl_rxq *rxq, int i, 1413 bool *join) 1414 { 1415 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1416 struct iwl_rx_mem_buffer *rxb; 1417 u16 vid; 1418 1419 BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32); 1420 1421 if (!trans->trans_cfg->mq_rx_supported) { 1422 rxb = rxq->queue[i]; 1423 rxq->queue[i] = NULL; 1424 return rxb; 1425 } 1426 1427 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1428 vid = le16_to_cpu(rxq->cd[i].rbid); 1429 *join = rxq->cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED; 1430 } else { 1431 vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; /* 12-bit VID */ 1432 } 1433 1434 if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs)) 1435 goto out_err; 1436 1437 rxb = trans_pcie->global_table[vid - 1]; 1438 if (rxb->invalid) 1439 goto out_err; 1440 1441 IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid); 1442 1443 rxb->invalid = true; 1444 1445 return rxb; 1446 1447 out_err: 1448 WARN(1, "Invalid rxb from HW %u\n", (u32)vid); 1449 iwl_force_nmi(trans); 1450 return NULL; 1451 } 1452 1453 /* 1454 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1455 */ 1456 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget) 1457 { 1458 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1459 struct iwl_rxq *rxq; 1460 u32 r, i, count = 0, handled = 0; 1461 bool emergency = false; 1462 1463 if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd)) 1464 return budget; 1465 1466 rxq = &trans_pcie->rxq[queue]; 1467 1468 restart: 1469 spin_lock(&rxq->lock); 1470 /* uCode's read index (stored in shared DRAM) indicates the last Rx 1471 * buffer that the driver may process (last buffer filled by ucode). */ 1472 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1473 i = rxq->read; 1474 1475 /* W/A 9000 device step A0 wrap-around bug */ 1476 r &= (rxq->queue_size - 1); 1477 1478 /* Rx interrupt, but nothing sent from uCode */ 1479 if (i == r) 1480 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1481 1482 while (i != r && ++handled < budget) { 1483 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1484 struct iwl_rx_mem_buffer *rxb; 1485 /* number of RBDs still waiting for page allocation */ 1486 u32 rb_pending_alloc = 1487 atomic_read(&trans_pcie->rba.req_pending) * 1488 RX_CLAIM_REQ_ALLOC; 1489 bool join = false; 1490 1491 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 && 1492 !emergency)) { 1493 iwl_pcie_rx_move_to_allocator(rxq, rba); 1494 emergency = true; 1495 IWL_DEBUG_TPT(trans, 1496 "RX path is in emergency. Pending allocations %d\n", 1497 rb_pending_alloc); 1498 } 1499 1500 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 1501 1502 rxb = iwl_pcie_get_rxb(trans, rxq, i, &join); 1503 if (!rxb) 1504 goto out; 1505 1506 if (unlikely(join || rxq->next_rb_is_fragment)) { 1507 rxq->next_rb_is_fragment = join; 1508 /* 1509 * We can only get a multi-RB in the following cases: 1510 * - firmware issue, sending a too big notification 1511 * - sniffer mode with a large A-MSDU 1512 * - large MTU frames (>2k) 1513 * since the multi-RB functionality is limited to newer 1514 * hardware that cannot put multiple entries into a 1515 * single RB. 1516 * 1517 * Right now, the higher layers aren't set up to deal 1518 * with that, so discard all of these. 1519 */ 1520 list_add_tail(&rxb->list, &rxq->rx_free); 1521 rxq->free_count++; 1522 } else { 1523 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i); 1524 } 1525 1526 i = (i + 1) & (rxq->queue_size - 1); 1527 1528 /* 1529 * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1530 * try to claim the pre-allocated buffers from the allocator. 1531 * If not ready - will try to reclaim next time. 1532 * There is no need to reschedule work - allocator exits only 1533 * on success 1534 */ 1535 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1536 iwl_pcie_rx_allocator_get(trans, rxq); 1537 1538 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1539 /* Add the remaining empty RBDs for allocator use */ 1540 iwl_pcie_rx_move_to_allocator(rxq, rba); 1541 } else if (emergency) { 1542 count++; 1543 if (count == 8) { 1544 count = 0; 1545 if (rb_pending_alloc < rxq->queue_size / 3) { 1546 IWL_DEBUG_TPT(trans, 1547 "RX path exited emergency. Pending allocations %d\n", 1548 rb_pending_alloc); 1549 emergency = false; 1550 } 1551 1552 rxq->read = i; 1553 spin_unlock(&rxq->lock); 1554 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1555 iwl_pcie_rxq_restock(trans, rxq); 1556 goto restart; 1557 } 1558 } 1559 } 1560 out: 1561 /* Backtrack one entry */ 1562 rxq->read = i; 1563 spin_unlock(&rxq->lock); 1564 1565 /* 1566 * handle a case where in emergency there are some unallocated RBDs. 1567 * those RBDs are in the used list, but are not tracked by the queue's 1568 * used_count which counts allocator owned RBDs. 1569 * unallocated emergency RBDs must be allocated on exit, otherwise 1570 * when called again the function may not be in emergency mode and 1571 * they will be handed to the allocator with no tracking in the RBD 1572 * allocator counters, which will lead to them never being claimed back 1573 * by the queue. 1574 * by allocating them here, they are now in the queue free list, and 1575 * will be restocked by the next call of iwl_pcie_rxq_restock. 1576 */ 1577 if (unlikely(emergency && count)) 1578 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1579 1580 iwl_pcie_rxq_restock(trans, rxq); 1581 1582 return handled; 1583 } 1584 1585 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 1586 { 1587 u8 queue = entry->entry; 1588 struct msix_entry *entries = entry - queue; 1589 1590 return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 1591 } 1592 1593 /* 1594 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 1595 * This interrupt handler should be used with RSS queue only. 1596 */ 1597 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 1598 { 1599 struct msix_entry *entry = dev_id; 1600 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 1601 struct iwl_trans *trans = trans_pcie->trans; 1602 struct iwl_rxq *rxq = &trans_pcie->rxq[entry->entry]; 1603 1604 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1605 1606 if (WARN_ON(entry->entry >= trans->num_rx_queues)) 1607 return IRQ_NONE; 1608 1609 if (WARN_ONCE(!rxq, 1610 "[%d] Got MSI-X interrupt before we have Rx queues", 1611 entry->entry)) 1612 return IRQ_NONE; 1613 1614 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1615 IWL_DEBUG_ISR(trans, "[%d] Got interrupt\n", entry->entry); 1616 1617 local_bh_disable(); 1618 if (napi_schedule_prep(&rxq->napi)) 1619 __napi_schedule(&rxq->napi); 1620 else 1621 iwl_pcie_clear_irq(trans, entry->entry); 1622 local_bh_enable(); 1623 1624 lock_map_release(&trans->sync_cmd_lockdep_map); 1625 1626 return IRQ_HANDLED; 1627 } 1628 1629 /* 1630 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1631 */ 1632 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1633 { 1634 int i; 1635 1636 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1637 if (trans->cfg->internal_wimax_coex && 1638 !trans->cfg->apmg_not_supported && 1639 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1640 APMS_CLK_VAL_MRB_FUNC_MODE) || 1641 (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1642 APMG_PS_CTRL_VAL_RESET_REQ))) { 1643 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1644 iwl_op_mode_wimax_active(trans->op_mode); 1645 wake_up(&trans->wait_command_queue); 1646 return; 1647 } 1648 1649 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 1650 if (!trans->txqs.txq[i]) 1651 continue; 1652 del_timer(&trans->txqs.txq[i]->stuck_timer); 1653 } 1654 1655 /* The STATUS_FW_ERROR bit is set in this function. This must happen 1656 * before we wake up the command caller, to ensure a proper cleanup. */ 1657 iwl_trans_fw_error(trans, false); 1658 1659 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1660 wake_up(&trans->wait_command_queue); 1661 } 1662 1663 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1664 { 1665 u32 inta; 1666 1667 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1668 1669 trace_iwlwifi_dev_irq(trans->dev); 1670 1671 /* Discover which interrupts are active/pending */ 1672 inta = iwl_read32(trans, CSR_INT); 1673 1674 /* the thread will service interrupts and re-enable them */ 1675 return inta; 1676 } 1677 1678 /* a device (PCI-E) page is 4096 bytes long */ 1679 #define ICT_SHIFT 12 1680 #define ICT_SIZE (1 << ICT_SHIFT) 1681 #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1682 1683 /* interrupt handler using ict table, with this interrupt driver will 1684 * stop using INTA register to get device's interrupt, reading this register 1685 * is expensive, device will write interrupts in ICT dram table, increment 1686 * index then will fire interrupt to driver, driver will OR all ICT table 1687 * entries from current index up to table entry with 0 value. the result is 1688 * the interrupt we need to service, driver will set the entries back to 0 and 1689 * set index. 1690 */ 1691 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1692 { 1693 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1694 u32 inta; 1695 u32 val = 0; 1696 u32 read; 1697 1698 trace_iwlwifi_dev_irq(trans->dev); 1699 1700 /* Ignore interrupt if there's nothing in NIC to service. 1701 * This may be due to IRQ shared with another device, 1702 * or due to sporadic interrupts thrown from our NIC. */ 1703 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1704 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1705 if (!read) 1706 return 0; 1707 1708 /* 1709 * Collect all entries up to the first 0, starting from ict_index; 1710 * note we already read at ict_index. 1711 */ 1712 do { 1713 val |= read; 1714 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1715 trans_pcie->ict_index, read); 1716 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1717 trans_pcie->ict_index = 1718 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1719 1720 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1721 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1722 read); 1723 } while (read); 1724 1725 /* We should not get this value, just ignore it. */ 1726 if (val == 0xffffffff) 1727 val = 0; 1728 1729 /* 1730 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1731 * (bit 15 before shifting it to 31) to clear when using interrupt 1732 * coalescing. fortunately, bits 18 and 19 stay set when this happens 1733 * so we use them to decide on the real state of the Rx bit. 1734 * In order words, bit 15 is set if bit 18 or bit 19 are set. 1735 */ 1736 if (val & 0xC0000) 1737 val |= 0x8000; 1738 1739 inta = (0xff & val) | ((0xff00 & val) << 16); 1740 return inta; 1741 } 1742 1743 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 1744 { 1745 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1746 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1747 bool hw_rfkill, prev, report; 1748 1749 mutex_lock(&trans_pcie->mutex); 1750 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1751 hw_rfkill = iwl_is_rfkill_set(trans); 1752 if (hw_rfkill) { 1753 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1754 set_bit(STATUS_RFKILL_HW, &trans->status); 1755 } 1756 if (trans_pcie->opmode_down) 1757 report = hw_rfkill; 1758 else 1759 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1760 1761 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 1762 hw_rfkill ? "disable radio" : "enable radio"); 1763 1764 isr_stats->rfkill++; 1765 1766 if (prev != report) 1767 iwl_trans_pcie_rf_kill(trans, report); 1768 mutex_unlock(&trans_pcie->mutex); 1769 1770 if (hw_rfkill) { 1771 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 1772 &trans->status)) 1773 IWL_DEBUG_RF_KILL(trans, 1774 "Rfkill while SYNC HCMD in flight\n"); 1775 wake_up(&trans->wait_command_queue); 1776 } else { 1777 clear_bit(STATUS_RFKILL_HW, &trans->status); 1778 if (trans_pcie->opmode_down) 1779 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1780 } 1781 } 1782 1783 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1784 { 1785 struct iwl_trans *trans = dev_id; 1786 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1787 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1788 u32 inta = 0; 1789 u32 handled = 0; 1790 bool polling = false; 1791 1792 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1793 1794 spin_lock_bh(&trans_pcie->irq_lock); 1795 1796 /* dram interrupt table not set yet, 1797 * use legacy interrupt. 1798 */ 1799 if (likely(trans_pcie->use_ict)) 1800 inta = iwl_pcie_int_cause_ict(trans); 1801 else 1802 inta = iwl_pcie_int_cause_non_ict(trans); 1803 1804 if (iwl_have_debug_level(IWL_DL_ISR)) { 1805 IWL_DEBUG_ISR(trans, 1806 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1807 inta, trans_pcie->inta_mask, 1808 iwl_read32(trans, CSR_INT_MASK), 1809 iwl_read32(trans, CSR_FH_INT_STATUS)); 1810 if (inta & (~trans_pcie->inta_mask)) 1811 IWL_DEBUG_ISR(trans, 1812 "We got a masked interrupt (0x%08x)\n", 1813 inta & (~trans_pcie->inta_mask)); 1814 } 1815 1816 inta &= trans_pcie->inta_mask; 1817 1818 /* 1819 * Ignore interrupt if there's nothing in NIC to service. 1820 * This may be due to IRQ shared with another device, 1821 * or due to sporadic interrupts thrown from our NIC. 1822 */ 1823 if (unlikely(!inta)) { 1824 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1825 /* 1826 * Re-enable interrupts here since we don't 1827 * have anything to service 1828 */ 1829 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1830 _iwl_enable_interrupts(trans); 1831 spin_unlock_bh(&trans_pcie->irq_lock); 1832 lock_map_release(&trans->sync_cmd_lockdep_map); 1833 return IRQ_NONE; 1834 } 1835 1836 if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1837 /* 1838 * Hardware disappeared. It might have 1839 * already raised an interrupt. 1840 */ 1841 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1842 spin_unlock_bh(&trans_pcie->irq_lock); 1843 goto out; 1844 } 1845 1846 /* Ack/clear/reset pending uCode interrupts. 1847 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1848 */ 1849 /* There is a hardware bug in the interrupt mask function that some 1850 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1851 * they are disabled in the CSR_INT_MASK register. Furthermore the 1852 * ICT interrupt handling mechanism has another bug that might cause 1853 * these unmasked interrupts fail to be detected. We workaround the 1854 * hardware bugs here by ACKing all the possible interrupts so that 1855 * interrupt coalescing can still be achieved. 1856 */ 1857 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1858 1859 if (iwl_have_debug_level(IWL_DL_ISR)) 1860 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1861 inta, iwl_read32(trans, CSR_INT_MASK)); 1862 1863 spin_unlock_bh(&trans_pcie->irq_lock); 1864 1865 /* Now service all interrupt bits discovered above. */ 1866 if (inta & CSR_INT_BIT_HW_ERR) { 1867 IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1868 1869 /* Tell the device to stop sending interrupts */ 1870 iwl_disable_interrupts(trans); 1871 1872 isr_stats->hw++; 1873 iwl_pcie_irq_handle_error(trans); 1874 1875 handled |= CSR_INT_BIT_HW_ERR; 1876 1877 goto out; 1878 } 1879 1880 /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1881 if (inta & CSR_INT_BIT_SCD) { 1882 IWL_DEBUG_ISR(trans, 1883 "Scheduler finished to transmit the frame/frames.\n"); 1884 isr_stats->sch++; 1885 } 1886 1887 /* Alive notification via Rx interrupt will do the real work */ 1888 if (inta & CSR_INT_BIT_ALIVE) { 1889 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1890 isr_stats->alive++; 1891 if (trans->trans_cfg->gen2) { 1892 /* 1893 * We can restock, since firmware configured 1894 * the RFH 1895 */ 1896 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1897 } 1898 1899 handled |= CSR_INT_BIT_ALIVE; 1900 } 1901 1902 /* Safely ignore these bits for debug checks below */ 1903 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1904 1905 /* HW RF KILL switch toggled */ 1906 if (inta & CSR_INT_BIT_RF_KILL) { 1907 iwl_pcie_handle_rfkill_irq(trans); 1908 handled |= CSR_INT_BIT_RF_KILL; 1909 } 1910 1911 /* Chip got too hot and stopped itself */ 1912 if (inta & CSR_INT_BIT_CT_KILL) { 1913 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1914 isr_stats->ctkill++; 1915 handled |= CSR_INT_BIT_CT_KILL; 1916 } 1917 1918 /* Error detected by uCode */ 1919 if (inta & CSR_INT_BIT_SW_ERR) { 1920 IWL_ERR(trans, "Microcode SW error detected. " 1921 " Restarting 0x%X.\n", inta); 1922 isr_stats->sw++; 1923 iwl_pcie_irq_handle_error(trans); 1924 handled |= CSR_INT_BIT_SW_ERR; 1925 } 1926 1927 /* uCode wakes up after power-down sleep */ 1928 if (inta & CSR_INT_BIT_WAKEUP) { 1929 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1930 iwl_pcie_rxq_check_wrptr(trans); 1931 iwl_pcie_txq_check_wrptrs(trans); 1932 1933 isr_stats->wakeup++; 1934 1935 handled |= CSR_INT_BIT_WAKEUP; 1936 } 1937 1938 /* All uCode command responses, including Tx command responses, 1939 * Rx "responses" (frame-received notification), and other 1940 * notifications from uCode come through here*/ 1941 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1942 CSR_INT_BIT_RX_PERIODIC)) { 1943 IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1944 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1945 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1946 iwl_write32(trans, CSR_FH_INT_STATUS, 1947 CSR_FH_INT_RX_MASK); 1948 } 1949 if (inta & CSR_INT_BIT_RX_PERIODIC) { 1950 handled |= CSR_INT_BIT_RX_PERIODIC; 1951 iwl_write32(trans, 1952 CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1953 } 1954 /* Sending RX interrupt require many steps to be done in the 1955 * the device: 1956 * 1- write interrupt to current index in ICT table. 1957 * 2- dma RX frame. 1958 * 3- update RX shared data to indicate last write index. 1959 * 4- send interrupt. 1960 * This could lead to RX race, driver could receive RX interrupt 1961 * but the shared data changes does not reflect this; 1962 * periodic interrupt will detect any dangling Rx activity. 1963 */ 1964 1965 /* Disable periodic interrupt; we use it as just a one-shot. */ 1966 iwl_write8(trans, CSR_INT_PERIODIC_REG, 1967 CSR_INT_PERIODIC_DIS); 1968 1969 /* 1970 * Enable periodic interrupt in 8 msec only if we received 1971 * real RX interrupt (instead of just periodic int), to catch 1972 * any dangling Rx interrupt. If it was just the periodic 1973 * interrupt, there was no dangling Rx activity, and no need 1974 * to extend the periodic interrupt; one-shot is enough. 1975 */ 1976 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1977 iwl_write8(trans, CSR_INT_PERIODIC_REG, 1978 CSR_INT_PERIODIC_ENA); 1979 1980 isr_stats->rx++; 1981 1982 local_bh_disable(); 1983 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 1984 polling = true; 1985 __napi_schedule(&trans_pcie->rxq[0].napi); 1986 } 1987 local_bh_enable(); 1988 } 1989 1990 /* This "Tx" DMA channel is used only for loading uCode */ 1991 if (inta & CSR_INT_BIT_FH_TX) { 1992 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1993 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1994 isr_stats->tx++; 1995 handled |= CSR_INT_BIT_FH_TX; 1996 /* Wake up uCode load routine, now that load is complete */ 1997 trans_pcie->ucode_write_complete = true; 1998 wake_up(&trans_pcie->ucode_write_waitq); 1999 } 2000 2001 if (inta & ~handled) { 2002 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 2003 isr_stats->unhandled++; 2004 } 2005 2006 if (inta & ~(trans_pcie->inta_mask)) { 2007 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 2008 inta & ~trans_pcie->inta_mask); 2009 } 2010 2011 if (!polling) { 2012 spin_lock_bh(&trans_pcie->irq_lock); 2013 /* only Re-enable all interrupt if disabled by irq */ 2014 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 2015 _iwl_enable_interrupts(trans); 2016 /* we are loading the firmware, enable FH_TX interrupt only */ 2017 else if (handled & CSR_INT_BIT_FH_TX) 2018 iwl_enable_fw_load_int(trans); 2019 /* Re-enable RF_KILL if it occurred */ 2020 else if (handled & CSR_INT_BIT_RF_KILL) 2021 iwl_enable_rfkill_int(trans); 2022 /* Re-enable the ALIVE / Rx interrupt if it occurred */ 2023 else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX)) 2024 iwl_enable_fw_load_int_ctx_info(trans); 2025 spin_unlock_bh(&trans_pcie->irq_lock); 2026 } 2027 2028 out: 2029 lock_map_release(&trans->sync_cmd_lockdep_map); 2030 return IRQ_HANDLED; 2031 } 2032 2033 /****************************************************************************** 2034 * 2035 * ICT functions 2036 * 2037 ******************************************************************************/ 2038 2039 /* Free dram table */ 2040 void iwl_pcie_free_ict(struct iwl_trans *trans) 2041 { 2042 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2043 2044 if (trans_pcie->ict_tbl) { 2045 dma_free_coherent(trans->dev, ICT_SIZE, 2046 trans_pcie->ict_tbl, 2047 trans_pcie->ict_tbl_dma); 2048 trans_pcie->ict_tbl = NULL; 2049 trans_pcie->ict_tbl_dma = 0; 2050 } 2051 } 2052 2053 /* 2054 * allocate dram shared table, it is an aligned memory 2055 * block of ICT_SIZE. 2056 * also reset all data related to ICT table interrupt. 2057 */ 2058 int iwl_pcie_alloc_ict(struct iwl_trans *trans) 2059 { 2060 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2061 2062 trans_pcie->ict_tbl = 2063 dma_alloc_coherent(trans->dev, ICT_SIZE, 2064 &trans_pcie->ict_tbl_dma, GFP_KERNEL); 2065 if (!trans_pcie->ict_tbl) 2066 return -ENOMEM; 2067 2068 /* just an API sanity check ... it is guaranteed to be aligned */ 2069 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 2070 iwl_pcie_free_ict(trans); 2071 return -EINVAL; 2072 } 2073 2074 return 0; 2075 } 2076 2077 /* Device is going up inform it about using ICT interrupt table, 2078 * also we need to tell the driver to start using ICT interrupt. 2079 */ 2080 void iwl_pcie_reset_ict(struct iwl_trans *trans) 2081 { 2082 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2083 u32 val; 2084 2085 if (!trans_pcie->ict_tbl) 2086 return; 2087 2088 spin_lock_bh(&trans_pcie->irq_lock); 2089 _iwl_disable_interrupts(trans); 2090 2091 memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 2092 2093 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 2094 2095 val |= CSR_DRAM_INT_TBL_ENABLE | 2096 CSR_DRAM_INIT_TBL_WRAP_CHECK | 2097 CSR_DRAM_INIT_TBL_WRITE_POINTER; 2098 2099 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 2100 2101 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 2102 trans_pcie->use_ict = true; 2103 trans_pcie->ict_index = 0; 2104 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 2105 _iwl_enable_interrupts(trans); 2106 spin_unlock_bh(&trans_pcie->irq_lock); 2107 } 2108 2109 /* Device is going down disable ict interrupt usage */ 2110 void iwl_pcie_disable_ict(struct iwl_trans *trans) 2111 { 2112 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2113 2114 spin_lock_bh(&trans_pcie->irq_lock); 2115 trans_pcie->use_ict = false; 2116 spin_unlock_bh(&trans_pcie->irq_lock); 2117 } 2118 2119 irqreturn_t iwl_pcie_isr(int irq, void *data) 2120 { 2121 struct iwl_trans *trans = data; 2122 2123 if (!trans) 2124 return IRQ_NONE; 2125 2126 /* Disable (but don't clear!) interrupts here to avoid 2127 * back-to-back ISRs and sporadic interrupts from our NIC. 2128 * If we have something to service, the tasklet will re-enable ints. 2129 * If we *don't* have something, we'll re-enable before leaving here. 2130 */ 2131 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2132 2133 return IRQ_WAKE_THREAD; 2134 } 2135 2136 irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 2137 { 2138 return IRQ_WAKE_THREAD; 2139 } 2140 2141 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 2142 { 2143 struct msix_entry *entry = dev_id; 2144 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 2145 struct iwl_trans *trans = trans_pcie->trans; 2146 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2147 u32 inta_fh_msk = ~MSIX_FH_INT_CAUSES_DATA_QUEUE; 2148 u32 inta_fh, inta_hw; 2149 bool polling = false; 2150 bool sw_err; 2151 2152 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 2153 inta_fh_msk |= MSIX_FH_INT_CAUSES_Q0; 2154 2155 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 2156 inta_fh_msk |= MSIX_FH_INT_CAUSES_Q1; 2157 2158 lock_map_acquire(&trans->sync_cmd_lockdep_map); 2159 2160 spin_lock_bh(&trans_pcie->irq_lock); 2161 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 2162 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 2163 /* 2164 * Clear causes registers to avoid being handling the same cause. 2165 */ 2166 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk); 2167 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 2168 spin_unlock_bh(&trans_pcie->irq_lock); 2169 2170 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2171 2172 if (unlikely(!(inta_fh | inta_hw))) { 2173 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 2174 lock_map_release(&trans->sync_cmd_lockdep_map); 2175 return IRQ_NONE; 2176 } 2177 2178 if (iwl_have_debug_level(IWL_DL_ISR)) { 2179 IWL_DEBUG_ISR(trans, 2180 "ISR[%d] inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 2181 entry->entry, inta_fh, trans_pcie->fh_mask, 2182 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 2183 if (inta_fh & ~trans_pcie->fh_mask) 2184 IWL_DEBUG_ISR(trans, 2185 "We got a masked interrupt (0x%08x)\n", 2186 inta_fh & ~trans_pcie->fh_mask); 2187 } 2188 2189 inta_fh &= trans_pcie->fh_mask; 2190 2191 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2192 inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2193 local_bh_disable(); 2194 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 2195 polling = true; 2196 __napi_schedule(&trans_pcie->rxq[0].napi); 2197 } 2198 local_bh_enable(); 2199 } 2200 2201 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2202 inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2203 local_bh_disable(); 2204 if (napi_schedule_prep(&trans_pcie->rxq[1].napi)) { 2205 polling = true; 2206 __napi_schedule(&trans_pcie->rxq[1].napi); 2207 } 2208 local_bh_enable(); 2209 } 2210 2211 /* This "Tx" DMA channel is used only for loading uCode */ 2212 if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 2213 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 2214 isr_stats->tx++; 2215 /* 2216 * Wake up uCode load routine, 2217 * now that load is complete 2218 */ 2219 trans_pcie->ucode_write_complete = true; 2220 wake_up(&trans_pcie->ucode_write_waitq); 2221 } 2222 2223 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2224 sw_err = inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 2225 else 2226 sw_err = inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR; 2227 2228 /* Error detected by uCode */ 2229 if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || sw_err) { 2230 IWL_ERR(trans, 2231 "Microcode SW error detected. Restarting 0x%X.\n", 2232 inta_fh); 2233 isr_stats->sw++; 2234 /* during FW reset flow report errors from there */ 2235 if (trans_pcie->fw_reset_state == FW_RESET_REQUESTED) { 2236 trans_pcie->fw_reset_state = FW_RESET_ERROR; 2237 wake_up(&trans_pcie->fw_reset_waitq); 2238 } else { 2239 iwl_pcie_irq_handle_error(trans); 2240 } 2241 } 2242 2243 /* After checking FH register check HW register */ 2244 if (iwl_have_debug_level(IWL_DL_ISR)) { 2245 IWL_DEBUG_ISR(trans, 2246 "ISR[%d] inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 2247 entry->entry, inta_hw, trans_pcie->hw_mask, 2248 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 2249 if (inta_hw & ~trans_pcie->hw_mask) 2250 IWL_DEBUG_ISR(trans, 2251 "We got a masked interrupt 0x%08x\n", 2252 inta_hw & ~trans_pcie->hw_mask); 2253 } 2254 2255 inta_hw &= trans_pcie->hw_mask; 2256 2257 /* Alive notification via Rx interrupt will do the real work */ 2258 if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 2259 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 2260 isr_stats->alive++; 2261 if (trans->trans_cfg->gen2) { 2262 /* We can restock, since firmware configured the RFH */ 2263 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2264 } 2265 } 2266 2267 /* 2268 * In some rare cases when the HW is in a bad state, we may 2269 * get this interrupt too early, when prph_info is still NULL. 2270 * So make sure that it's not NULL to prevent crashing. 2271 */ 2272 if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP && trans_pcie->prph_info) { 2273 u32 sleep_notif = 2274 le32_to_cpu(trans_pcie->prph_info->sleep_notif); 2275 if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND || 2276 sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) { 2277 IWL_DEBUG_ISR(trans, 2278 "Sx interrupt: sleep notification = 0x%x\n", 2279 sleep_notif); 2280 trans_pcie->sx_complete = true; 2281 wake_up(&trans_pcie->sx_waitq); 2282 } else { 2283 /* uCode wakes up after power-down sleep */ 2284 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 2285 iwl_pcie_rxq_check_wrptr(trans); 2286 iwl_pcie_txq_check_wrptrs(trans); 2287 2288 isr_stats->wakeup++; 2289 } 2290 } 2291 2292 /* Chip got too hot and stopped itself */ 2293 if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 2294 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 2295 isr_stats->ctkill++; 2296 } 2297 2298 /* HW RF KILL switch toggled */ 2299 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 2300 iwl_pcie_handle_rfkill_irq(trans); 2301 2302 if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 2303 IWL_ERR(trans, 2304 "Hardware error detected. Restarting.\n"); 2305 2306 isr_stats->hw++; 2307 trans->dbg.hw_error = true; 2308 iwl_pcie_irq_handle_error(trans); 2309 } 2310 2311 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE) { 2312 IWL_DEBUG_ISR(trans, "Reset flow completed\n"); 2313 trans_pcie->fw_reset_state = FW_RESET_OK; 2314 wake_up(&trans_pcie->fw_reset_waitq); 2315 } 2316 2317 if (!polling) 2318 iwl_pcie_clear_irq(trans, entry->entry); 2319 2320 lock_map_release(&trans->sync_cmd_lockdep_map); 2321 2322 return IRQ_HANDLED; 2323 } 2324