1 /****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6 * Copyright(c) 2018 Intel Corporation 7 * 8 * Portions of this file are derived from the ipw3945 project, as well 9 * as portions of the ieee80211 subsystem header files. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * You should have received a copy of the GNU General Public License along with 21 * this program; if not, write to the Free Software Foundation, Inc., 22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 23 * 24 * The full GNU General Public License is included in this distribution in the 25 * file called LICENSE. 26 * 27 * Contact Information: 28 * Intel Linux Wireless <linuxwifi@intel.com> 29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 30 * 31 *****************************************************************************/ 32 #include <linux/sched.h> 33 #include <linux/wait.h> 34 #include <linux/gfp.h> 35 36 #include "iwl-prph.h" 37 #include "iwl-io.h" 38 #include "internal.h" 39 #include "iwl-op-mode.h" 40 41 /****************************************************************************** 42 * 43 * RX path functions 44 * 45 ******************************************************************************/ 46 47 /* 48 * Rx theory of operation 49 * 50 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 51 * each of which point to Receive Buffers to be filled by the NIC. These get 52 * used not only for Rx frames, but for any command response or notification 53 * from the NIC. The driver and NIC manage the Rx buffers by means 54 * of indexes into the circular buffer. 55 * 56 * Rx Queue Indexes 57 * The host/firmware share two index registers for managing the Rx buffers. 58 * 59 * The READ index maps to the first position that the firmware may be writing 60 * to -- the driver can read up to (but not including) this position and get 61 * good data. 62 * The READ index is managed by the firmware once the card is enabled. 63 * 64 * The WRITE index maps to the last position the driver has read from -- the 65 * position preceding WRITE is the last slot the firmware can place a packet. 66 * 67 * The queue is empty (no good data) if WRITE = READ - 1, and is full if 68 * WRITE = READ. 69 * 70 * During initialization, the host sets up the READ queue position to the first 71 * INDEX position, and WRITE to the last (READ - 1 wrapped) 72 * 73 * When the firmware places a packet in a buffer, it will advance the READ index 74 * and fire the RX interrupt. The driver can then query the READ index and 75 * process as many packets as possible, moving the WRITE index forward as it 76 * resets the Rx queue buffers with new memory. 77 * 78 * The management in the driver is as follows: 79 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 80 * When the interrupt handler is called, the request is processed. 81 * The page is either stolen - transferred to the upper layer 82 * or reused - added immediately to the iwl->rxq->rx_free list. 83 * + When the page is stolen - the driver updates the matching queue's used 84 * count, detaches the RBD and transfers it to the queue used list. 85 * When there are two used RBDs - they are transferred to the allocator empty 86 * list. Work is then scheduled for the allocator to start allocating 87 * eight buffers. 88 * When there are another 6 used RBDs - they are transferred to the allocator 89 * empty list and the driver tries to claim the pre-allocated buffers and 90 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 91 * until ready. 92 * When there are 8+ buffers in the free list - either from allocation or from 93 * 8 reused unstolen pages - restock is called to update the FW and indexes. 94 * + In order to make sure the allocator always has RBDs to use for allocation 95 * the allocator has initial pool in the size of num_queues*(8-2) - the 96 * maximum missing RBDs per allocation request (request posted with 2 97 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 98 * The queues supplies the recycle of the rest of the RBDs. 99 * + A received packet is processed and handed to the kernel network stack, 100 * detached from the iwl->rxq. The driver 'processed' index is updated. 101 * + If there are no allocated buffers in iwl->rxq->rx_free, 102 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 103 * If there were enough free buffers and RX_STALLED is set it is cleared. 104 * 105 * 106 * Driver sequence: 107 * 108 * iwl_rxq_alloc() Allocates rx_free 109 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 110 * iwl_pcie_rxq_restock. 111 * Used only during initialization. 112 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 113 * queue, updates firmware pointers, and updates 114 * the WRITE index. 115 * iwl_pcie_rx_allocator() Background work for allocating pages. 116 * 117 * -- enable interrupts -- 118 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 119 * READ INDEX, detaching the SKB from the pool. 120 * Moves the packet buffer from queue to rx_used. 121 * Posts and claims requests to the allocator. 122 * Calls iwl_pcie_rxq_restock to refill any empty 123 * slots. 124 * 125 * RBD life-cycle: 126 * 127 * Init: 128 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 129 * 130 * Regular Receive interrupt: 131 * Page Stolen: 132 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 133 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 134 * Page not Stolen: 135 * rxq.queue -> rxq.rx_free -> rxq.queue 136 * ... 137 * 138 */ 139 140 /* 141 * iwl_rxq_space - Return number of free slots available in queue. 142 */ 143 static int iwl_rxq_space(const struct iwl_rxq *rxq) 144 { 145 /* Make sure rx queue size is a power of 2 */ 146 WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 147 148 /* 149 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 150 * between empty and completely full queues. 151 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 152 * defined for negative dividends. 153 */ 154 return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 155 } 156 157 /* 158 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 159 */ 160 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 161 { 162 return cpu_to_le32((u32)(dma_addr >> 8)); 163 } 164 165 /* 166 * iwl_pcie_rx_stop - stops the Rx DMA 167 */ 168 int iwl_pcie_rx_stop(struct iwl_trans *trans) 169 { 170 if (trans->cfg->mq_rx_supported) { 171 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 172 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 173 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 174 } else { 175 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 176 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 177 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 178 1000); 179 } 180 } 181 182 /* 183 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 184 */ 185 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 186 struct iwl_rxq *rxq) 187 { 188 u32 reg; 189 190 lockdep_assert_held(&rxq->lock); 191 192 /* 193 * explicitly wake up the NIC if: 194 * 1. shadow registers aren't enabled 195 * 2. there is a chance that the NIC is asleep 196 */ 197 if (!trans->cfg->base_params->shadow_reg_enable && 198 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 199 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 200 201 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 202 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 203 reg); 204 iwl_set_bit(trans, CSR_GP_CNTRL, 205 BIT(trans->cfg->csr->flag_mac_access_req)); 206 rxq->need_update = true; 207 return; 208 } 209 } 210 211 rxq->write_actual = round_down(rxq->write, 8); 212 if (trans->cfg->mq_rx_supported) 213 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 214 rxq->write_actual); 215 else 216 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 217 } 218 219 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 220 { 221 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 222 int i; 223 224 for (i = 0; i < trans->num_rx_queues; i++) { 225 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 226 227 if (!rxq->need_update) 228 continue; 229 spin_lock(&rxq->lock); 230 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 231 rxq->need_update = false; 232 spin_unlock(&rxq->lock); 233 } 234 } 235 236 /* 237 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 238 */ 239 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 240 struct iwl_rxq *rxq) 241 { 242 struct iwl_rx_mem_buffer *rxb; 243 244 /* 245 * If the device isn't enabled - no need to try to add buffers... 246 * This can happen when we stop the device and still have an interrupt 247 * pending. We stop the APM before we sync the interrupts because we 248 * have to (see comment there). On the other hand, since the APM is 249 * stopped, we cannot access the HW (in particular not prph). 250 * So don't try to restock if the APM has been already stopped. 251 */ 252 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 253 return; 254 255 spin_lock(&rxq->lock); 256 while (rxq->free_count) { 257 __le64 *bd = (__le64 *)rxq->bd; 258 259 /* Get next free Rx buffer, remove from free list */ 260 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 261 list); 262 list_del(&rxb->list); 263 rxb->invalid = false; 264 /* 12 first bits are expected to be empty */ 265 WARN_ON(rxb->page_dma & DMA_BIT_MASK(12)); 266 /* Point to Rx buffer via next RBD in circular buffer */ 267 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 268 rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK; 269 rxq->free_count--; 270 } 271 spin_unlock(&rxq->lock); 272 273 /* 274 * If we've added more space for the firmware to place data, tell it. 275 * Increment device's write pointer in multiples of 8. 276 */ 277 if (rxq->write_actual != (rxq->write & ~0x7)) { 278 spin_lock(&rxq->lock); 279 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 280 spin_unlock(&rxq->lock); 281 } 282 } 283 284 /* 285 * iwl_pcie_rxsq_restock - restock implementation for single queue rx 286 */ 287 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 288 struct iwl_rxq *rxq) 289 { 290 struct iwl_rx_mem_buffer *rxb; 291 292 /* 293 * If the device isn't enabled - not need to try to add buffers... 294 * This can happen when we stop the device and still have an interrupt 295 * pending. We stop the APM before we sync the interrupts because we 296 * have to (see comment there). On the other hand, since the APM is 297 * stopped, we cannot access the HW (in particular not prph). 298 * So don't try to restock if the APM has been already stopped. 299 */ 300 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 301 return; 302 303 spin_lock(&rxq->lock); 304 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 305 __le32 *bd = (__le32 *)rxq->bd; 306 /* The overwritten rxb must be a used one */ 307 rxb = rxq->queue[rxq->write]; 308 BUG_ON(rxb && rxb->page); 309 310 /* Get next free Rx buffer, remove from free list */ 311 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 312 list); 313 list_del(&rxb->list); 314 rxb->invalid = false; 315 316 /* Point to Rx buffer via next RBD in circular buffer */ 317 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 318 rxq->queue[rxq->write] = rxb; 319 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 320 rxq->free_count--; 321 } 322 spin_unlock(&rxq->lock); 323 324 /* If we've added more space for the firmware to place data, tell it. 325 * Increment device's write pointer in multiples of 8. */ 326 if (rxq->write_actual != (rxq->write & ~0x7)) { 327 spin_lock(&rxq->lock); 328 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 329 spin_unlock(&rxq->lock); 330 } 331 } 332 333 /* 334 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 335 * 336 * If there are slots in the RX queue that need to be restocked, 337 * and we have free pre-allocated buffers, fill the ranks as much 338 * as we can, pulling from rx_free. 339 * 340 * This moves the 'write' index forward to catch up with 'processed', and 341 * also updates the memory address in the firmware to reference the new 342 * target buffer. 343 */ 344 static 345 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 346 { 347 if (trans->cfg->mq_rx_supported) 348 iwl_pcie_rxmq_restock(trans, rxq); 349 else 350 iwl_pcie_rxsq_restock(trans, rxq); 351 } 352 353 /* 354 * iwl_pcie_rx_alloc_page - allocates and returns a page. 355 * 356 */ 357 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 358 gfp_t priority) 359 { 360 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 361 struct page *page; 362 gfp_t gfp_mask = priority; 363 364 if (trans_pcie->rx_page_order > 0) 365 gfp_mask |= __GFP_COMP; 366 367 /* Alloc a new receive buffer */ 368 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 369 if (!page) { 370 if (net_ratelimit()) 371 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 372 trans_pcie->rx_page_order); 373 /* 374 * Issue an error if we don't have enough pre-allocated 375 * buffers. 376 ` */ 377 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 378 IWL_CRIT(trans, 379 "Failed to alloc_pages\n"); 380 return NULL; 381 } 382 return page; 383 } 384 385 /* 386 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 387 * 388 * A used RBD is an Rx buffer that has been given to the stack. To use it again 389 * a page must be allocated and the RBD must point to the page. This function 390 * doesn't change the HW pointer but handles the list of pages that is used by 391 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 392 * allocated buffers. 393 */ 394 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 395 struct iwl_rxq *rxq) 396 { 397 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 398 struct iwl_rx_mem_buffer *rxb; 399 struct page *page; 400 401 while (1) { 402 spin_lock(&rxq->lock); 403 if (list_empty(&rxq->rx_used)) { 404 spin_unlock(&rxq->lock); 405 return; 406 } 407 spin_unlock(&rxq->lock); 408 409 /* Alloc a new receive buffer */ 410 page = iwl_pcie_rx_alloc_page(trans, priority); 411 if (!page) 412 return; 413 414 spin_lock(&rxq->lock); 415 416 if (list_empty(&rxq->rx_used)) { 417 spin_unlock(&rxq->lock); 418 __free_pages(page, trans_pcie->rx_page_order); 419 return; 420 } 421 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 422 list); 423 list_del(&rxb->list); 424 spin_unlock(&rxq->lock); 425 426 BUG_ON(rxb->page); 427 rxb->page = page; 428 /* Get physical address of the RB */ 429 rxb->page_dma = 430 dma_map_page(trans->dev, page, 0, 431 PAGE_SIZE << trans_pcie->rx_page_order, 432 DMA_FROM_DEVICE); 433 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 434 rxb->page = NULL; 435 spin_lock(&rxq->lock); 436 list_add(&rxb->list, &rxq->rx_used); 437 spin_unlock(&rxq->lock); 438 __free_pages(page, trans_pcie->rx_page_order); 439 return; 440 } 441 442 spin_lock(&rxq->lock); 443 444 list_add_tail(&rxb->list, &rxq->rx_free); 445 rxq->free_count++; 446 447 spin_unlock(&rxq->lock); 448 } 449 } 450 451 static void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 452 { 453 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 454 int i; 455 456 for (i = 0; i < RX_POOL_SIZE; i++) { 457 if (!trans_pcie->rx_pool[i].page) 458 continue; 459 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 460 PAGE_SIZE << trans_pcie->rx_page_order, 461 DMA_FROM_DEVICE); 462 __free_pages(trans_pcie->rx_pool[i].page, 463 trans_pcie->rx_page_order); 464 trans_pcie->rx_pool[i].page = NULL; 465 } 466 } 467 468 /* 469 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 470 * 471 * Allocates for each received request 8 pages 472 * Called as a scheduled work item. 473 */ 474 static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 475 { 476 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 477 struct iwl_rb_allocator *rba = &trans_pcie->rba; 478 struct list_head local_empty; 479 int pending = atomic_xchg(&rba->req_pending, 0); 480 481 IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending); 482 483 /* If we were scheduled - there is at least one request */ 484 spin_lock(&rba->lock); 485 /* swap out the rba->rbd_empty to a local list */ 486 list_replace_init(&rba->rbd_empty, &local_empty); 487 spin_unlock(&rba->lock); 488 489 while (pending) { 490 int i; 491 LIST_HEAD(local_allocated); 492 gfp_t gfp_mask = GFP_KERNEL; 493 494 /* Do not post a warning if there are only a few requests */ 495 if (pending < RX_PENDING_WATERMARK) 496 gfp_mask |= __GFP_NOWARN; 497 498 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 499 struct iwl_rx_mem_buffer *rxb; 500 struct page *page; 501 502 /* List should never be empty - each reused RBD is 503 * returned to the list, and initial pool covers any 504 * possible gap between the time the page is allocated 505 * to the time the RBD is added. 506 */ 507 BUG_ON(list_empty(&local_empty)); 508 /* Get the first rxb from the rbd list */ 509 rxb = list_first_entry(&local_empty, 510 struct iwl_rx_mem_buffer, list); 511 BUG_ON(rxb->page); 512 513 /* Alloc a new receive buffer */ 514 page = iwl_pcie_rx_alloc_page(trans, gfp_mask); 515 if (!page) 516 continue; 517 rxb->page = page; 518 519 /* Get physical address of the RB */ 520 rxb->page_dma = dma_map_page(trans->dev, page, 0, 521 PAGE_SIZE << trans_pcie->rx_page_order, 522 DMA_FROM_DEVICE); 523 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 524 rxb->page = NULL; 525 __free_pages(page, trans_pcie->rx_page_order); 526 continue; 527 } 528 529 /* move the allocated entry to the out list */ 530 list_move(&rxb->list, &local_allocated); 531 i++; 532 } 533 534 pending--; 535 if (!pending) { 536 pending = atomic_xchg(&rba->req_pending, 0); 537 IWL_DEBUG_RX(trans, 538 "Pending allocation requests = %d\n", 539 pending); 540 } 541 542 spin_lock(&rba->lock); 543 /* add the allocated rbds to the allocator allocated list */ 544 list_splice_tail(&local_allocated, &rba->rbd_allocated); 545 /* get more empty RBDs for current pending requests */ 546 list_splice_tail_init(&rba->rbd_empty, &local_empty); 547 spin_unlock(&rba->lock); 548 549 atomic_inc(&rba->req_ready); 550 } 551 552 spin_lock(&rba->lock); 553 /* return unused rbds to the allocator empty list */ 554 list_splice_tail(&local_empty, &rba->rbd_empty); 555 spin_unlock(&rba->lock); 556 } 557 558 /* 559 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 560 .* 561 .* Called by queue when the queue posted allocation request and 562 * has freed 8 RBDs in order to restock itself. 563 * This function directly moves the allocated RBs to the queue's ownership 564 * and updates the relevant counters. 565 */ 566 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 567 struct iwl_rxq *rxq) 568 { 569 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 570 struct iwl_rb_allocator *rba = &trans_pcie->rba; 571 int i; 572 573 lockdep_assert_held(&rxq->lock); 574 575 /* 576 * atomic_dec_if_positive returns req_ready - 1 for any scenario. 577 * If req_ready is 0 atomic_dec_if_positive will return -1 and this 578 * function will return early, as there are no ready requests. 579 * atomic_dec_if_positive will perofrm the *actual* decrement only if 580 * req_ready > 0, i.e. - there are ready requests and the function 581 * hands one request to the caller. 582 */ 583 if (atomic_dec_if_positive(&rba->req_ready) < 0) 584 return; 585 586 spin_lock(&rba->lock); 587 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 588 /* Get next free Rx buffer, remove it from free list */ 589 struct iwl_rx_mem_buffer *rxb = 590 list_first_entry(&rba->rbd_allocated, 591 struct iwl_rx_mem_buffer, list); 592 593 list_move(&rxb->list, &rxq->rx_free); 594 } 595 spin_unlock(&rba->lock); 596 597 rxq->used_count -= RX_CLAIM_REQ_ALLOC; 598 rxq->free_count += RX_CLAIM_REQ_ALLOC; 599 } 600 601 void iwl_pcie_rx_allocator_work(struct work_struct *data) 602 { 603 struct iwl_rb_allocator *rba_p = 604 container_of(data, struct iwl_rb_allocator, rx_alloc); 605 struct iwl_trans_pcie *trans_pcie = 606 container_of(rba_p, struct iwl_trans_pcie, rba); 607 608 iwl_pcie_rx_allocator(trans_pcie->trans); 609 } 610 611 static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 612 { 613 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 614 struct iwl_rb_allocator *rba = &trans_pcie->rba; 615 struct device *dev = trans->dev; 616 int i; 617 int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) : 618 sizeof(__le32); 619 620 if (WARN_ON(trans_pcie->rxq)) 621 return -EINVAL; 622 623 trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 624 GFP_KERNEL); 625 if (!trans_pcie->rxq) 626 return -EINVAL; 627 628 spin_lock_init(&rba->lock); 629 630 for (i = 0; i < trans->num_rx_queues; i++) { 631 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 632 633 spin_lock_init(&rxq->lock); 634 if (trans->cfg->mq_rx_supported) 635 rxq->queue_size = MQ_RX_TABLE_SIZE; 636 else 637 rxq->queue_size = RX_QUEUE_SIZE; 638 639 /* 640 * Allocate the circular buffer of Read Buffer Descriptors 641 * (RBDs) 642 */ 643 rxq->bd = dma_zalloc_coherent(dev, 644 free_size * rxq->queue_size, 645 &rxq->bd_dma, GFP_KERNEL); 646 if (!rxq->bd) 647 goto err; 648 649 if (trans->cfg->mq_rx_supported) { 650 rxq->used_bd = dma_zalloc_coherent(dev, 651 sizeof(__le32) * 652 rxq->queue_size, 653 &rxq->used_bd_dma, 654 GFP_KERNEL); 655 if (!rxq->used_bd) 656 goto err; 657 } 658 659 /*Allocate the driver's pointer to receive buffer status */ 660 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts), 661 &rxq->rb_stts_dma, 662 GFP_KERNEL); 663 if (!rxq->rb_stts) 664 goto err; 665 } 666 return 0; 667 668 err: 669 for (i = 0; i < trans->num_rx_queues; i++) { 670 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 671 672 if (rxq->bd) 673 dma_free_coherent(dev, free_size * rxq->queue_size, 674 rxq->bd, rxq->bd_dma); 675 rxq->bd_dma = 0; 676 rxq->bd = NULL; 677 678 if (rxq->rb_stts) 679 dma_free_coherent(trans->dev, 680 sizeof(struct iwl_rb_status), 681 rxq->rb_stts, rxq->rb_stts_dma); 682 683 if (rxq->used_bd) 684 dma_free_coherent(dev, sizeof(__le32) * rxq->queue_size, 685 rxq->used_bd, rxq->used_bd_dma); 686 rxq->used_bd_dma = 0; 687 rxq->used_bd = NULL; 688 } 689 kfree(trans_pcie->rxq); 690 691 return -ENOMEM; 692 } 693 694 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 695 { 696 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 697 u32 rb_size; 698 unsigned long flags; 699 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 700 701 switch (trans_pcie->rx_buf_size) { 702 case IWL_AMSDU_4K: 703 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 704 break; 705 case IWL_AMSDU_8K: 706 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 707 break; 708 case IWL_AMSDU_12K: 709 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 710 break; 711 default: 712 WARN_ON(1); 713 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 714 } 715 716 if (!iwl_trans_grab_nic_access(trans, &flags)) 717 return; 718 719 /* Stop Rx DMA */ 720 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 721 /* reset and flush pointers */ 722 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 723 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 724 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 725 726 /* Reset driver's Rx queue write index */ 727 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 728 729 /* Tell device where to find RBD circular buffer in DRAM */ 730 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 731 (u32)(rxq->bd_dma >> 8)); 732 733 /* Tell device where in DRAM to update its Rx status */ 734 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 735 rxq->rb_stts_dma >> 4); 736 737 /* Enable Rx DMA 738 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 739 * the credit mechanism in 5000 HW RX FIFO 740 * Direct rx interrupts to hosts 741 * Rx buffer size 4 or 8k or 12k 742 * RB timeout 0x10 743 * 256 RBDs 744 */ 745 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 746 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 747 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 748 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 749 rb_size | 750 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 751 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 752 753 iwl_trans_release_nic_access(trans, &flags); 754 755 /* Set interrupt coalescing timer to default (2048 usecs) */ 756 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 757 758 /* W/A for interrupt coalescing bug in 7260 and 3160 */ 759 if (trans->cfg->host_interrupt_operation_mode) 760 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 761 } 762 763 void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable) 764 { 765 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_9000) 766 return; 767 768 if (CSR_HW_REV_STEP(trans->hw_rev) != SILICON_A_STEP) 769 return; 770 771 if (!trans->cfg->integrated) 772 return; 773 774 /* 775 * Turn on the chicken-bits that cause MAC wakeup for RX-related 776 * values. 777 * This costs some power, but needed for W/A 9000 integrated A-step 778 * bug where shadow registers are not in the retention list and their 779 * value is lost when NIC powers down 780 */ 781 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 782 CSR_MAC_SHADOW_REG_CTRL_RX_WAKE); 783 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTL2, 784 CSR_MAC_SHADOW_REG_CTL2_RX_WAKE); 785 } 786 787 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 788 { 789 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 790 u32 rb_size, enabled = 0; 791 unsigned long flags; 792 int i; 793 794 switch (trans_pcie->rx_buf_size) { 795 case IWL_AMSDU_4K: 796 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 797 break; 798 case IWL_AMSDU_8K: 799 rb_size = RFH_RXF_DMA_RB_SIZE_8K; 800 break; 801 case IWL_AMSDU_12K: 802 rb_size = RFH_RXF_DMA_RB_SIZE_12K; 803 break; 804 default: 805 WARN_ON(1); 806 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 807 } 808 809 if (!iwl_trans_grab_nic_access(trans, &flags)) 810 return; 811 812 /* Stop Rx DMA */ 813 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 814 /* disable free amd used rx queue operation */ 815 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 816 817 for (i = 0; i < trans->num_rx_queues; i++) { 818 /* Tell device where to find RBD free table in DRAM */ 819 iwl_write_prph64_no_grab(trans, 820 RFH_Q_FRBDCB_BA_LSB(i), 821 trans_pcie->rxq[i].bd_dma); 822 /* Tell device where to find RBD used table in DRAM */ 823 iwl_write_prph64_no_grab(trans, 824 RFH_Q_URBDCB_BA_LSB(i), 825 trans_pcie->rxq[i].used_bd_dma); 826 /* Tell device where in DRAM to update its Rx status */ 827 iwl_write_prph64_no_grab(trans, 828 RFH_Q_URBD_STTS_WPTR_LSB(i), 829 trans_pcie->rxq[i].rb_stts_dma); 830 /* Reset device indice tables */ 831 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 832 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 833 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 834 835 enabled |= BIT(i) | BIT(i + 16); 836 } 837 838 /* 839 * Enable Rx DMA 840 * Rx buffer size 4 or 8k or 12k 841 * Min RB size 4 or 8 842 * Drop frames that exceed RB size 843 * 512 RBDs 844 */ 845 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 846 RFH_DMA_EN_ENABLE_VAL | rb_size | 847 RFH_RXF_DMA_MIN_RB_4_8 | 848 RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 849 RFH_RXF_DMA_RBDCB_SIZE_512); 850 851 /* 852 * Activate DMA snooping. 853 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 854 * Default queue is 0 855 */ 856 iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 857 RFH_GEN_CFG_RFH_DMA_SNOOP | 858 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 859 RFH_GEN_CFG_SERVICE_DMA_SNOOP | 860 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 861 trans->cfg->integrated ? 862 RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 863 RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 864 /* Enable the relevant rx queues */ 865 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 866 867 iwl_trans_release_nic_access(trans, &flags); 868 869 /* Set interrupt coalescing timer to default (2048 usecs) */ 870 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 871 872 iwl_pcie_enable_rx_wake(trans, true); 873 } 874 875 static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 876 { 877 lockdep_assert_held(&rxq->lock); 878 879 INIT_LIST_HEAD(&rxq->rx_free); 880 INIT_LIST_HEAD(&rxq->rx_used); 881 rxq->free_count = 0; 882 rxq->used_count = 0; 883 } 884 885 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) 886 { 887 WARN_ON(1); 888 return 0; 889 } 890 891 static int _iwl_pcie_rx_init(struct iwl_trans *trans) 892 { 893 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 894 struct iwl_rxq *def_rxq; 895 struct iwl_rb_allocator *rba = &trans_pcie->rba; 896 int i, err, queue_size, allocator_pool_size, num_alloc; 897 898 if (!trans_pcie->rxq) { 899 err = iwl_pcie_rx_alloc(trans); 900 if (err) 901 return err; 902 } 903 def_rxq = trans_pcie->rxq; 904 905 spin_lock(&rba->lock); 906 atomic_set(&rba->req_pending, 0); 907 atomic_set(&rba->req_ready, 0); 908 INIT_LIST_HEAD(&rba->rbd_allocated); 909 INIT_LIST_HEAD(&rba->rbd_empty); 910 spin_unlock(&rba->lock); 911 912 /* free all first - we might be reconfigured for a different size */ 913 iwl_pcie_free_rbs_pool(trans); 914 915 for (i = 0; i < RX_QUEUE_SIZE; i++) 916 def_rxq->queue[i] = NULL; 917 918 for (i = 0; i < trans->num_rx_queues; i++) { 919 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 920 921 rxq->id = i; 922 923 spin_lock(&rxq->lock); 924 /* 925 * Set read write pointer to reflect that we have processed 926 * and used all buffers, but have not restocked the Rx queue 927 * with fresh buffers 928 */ 929 rxq->read = 0; 930 rxq->write = 0; 931 rxq->write_actual = 0; 932 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts)); 933 934 iwl_pcie_rx_init_rxb_lists(rxq); 935 936 if (!rxq->napi.poll) 937 netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 938 iwl_pcie_dummy_napi_poll, 64); 939 940 spin_unlock(&rxq->lock); 941 } 942 943 /* move the pool to the default queue and allocator ownerships */ 944 queue_size = trans->cfg->mq_rx_supported ? 945 MQ_RX_NUM_RBDS : RX_QUEUE_SIZE; 946 allocator_pool_size = trans->num_rx_queues * 947 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 948 num_alloc = queue_size + allocator_pool_size; 949 BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) != 950 ARRAY_SIZE(trans_pcie->rx_pool)); 951 for (i = 0; i < num_alloc; i++) { 952 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 953 954 if (i < allocator_pool_size) 955 list_add(&rxb->list, &rba->rbd_empty); 956 else 957 list_add(&rxb->list, &def_rxq->rx_used); 958 trans_pcie->global_table[i] = rxb; 959 rxb->vid = (u16)(i + 1); 960 rxb->invalid = true; 961 } 962 963 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 964 965 return 0; 966 } 967 968 int iwl_pcie_rx_init(struct iwl_trans *trans) 969 { 970 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 971 int ret = _iwl_pcie_rx_init(trans); 972 973 if (ret) 974 return ret; 975 976 if (trans->cfg->mq_rx_supported) 977 iwl_pcie_rx_mq_hw_init(trans); 978 else 979 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 980 981 iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 982 983 spin_lock(&trans_pcie->rxq->lock); 984 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 985 spin_unlock(&trans_pcie->rxq->lock); 986 987 return 0; 988 } 989 990 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 991 { 992 /* 993 * We don't configure the RFH. 994 * Restock will be done at alive, after firmware configured the RFH. 995 */ 996 return _iwl_pcie_rx_init(trans); 997 } 998 999 void iwl_pcie_rx_free(struct iwl_trans *trans) 1000 { 1001 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1002 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1003 int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) : 1004 sizeof(__le32); 1005 int i; 1006 1007 /* 1008 * if rxq is NULL, it means that nothing has been allocated, 1009 * exit now 1010 */ 1011 if (!trans_pcie->rxq) { 1012 IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1013 return; 1014 } 1015 1016 cancel_work_sync(&rba->rx_alloc); 1017 1018 iwl_pcie_free_rbs_pool(trans); 1019 1020 for (i = 0; i < trans->num_rx_queues; i++) { 1021 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1022 1023 if (rxq->bd) 1024 dma_free_coherent(trans->dev, 1025 free_size * rxq->queue_size, 1026 rxq->bd, rxq->bd_dma); 1027 rxq->bd_dma = 0; 1028 rxq->bd = NULL; 1029 1030 if (rxq->rb_stts) 1031 dma_free_coherent(trans->dev, 1032 sizeof(struct iwl_rb_status), 1033 rxq->rb_stts, rxq->rb_stts_dma); 1034 else 1035 IWL_DEBUG_INFO(trans, 1036 "Free rxq->rb_stts which is NULL\n"); 1037 1038 if (rxq->used_bd) 1039 dma_free_coherent(trans->dev, 1040 sizeof(__le32) * rxq->queue_size, 1041 rxq->used_bd, rxq->used_bd_dma); 1042 rxq->used_bd_dma = 0; 1043 rxq->used_bd = NULL; 1044 1045 if (rxq->napi.poll) 1046 netif_napi_del(&rxq->napi); 1047 } 1048 kfree(trans_pcie->rxq); 1049 } 1050 1051 /* 1052 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1053 * 1054 * Called when a RBD can be reused. The RBD is transferred to the allocator. 1055 * When there are 2 empty RBDs - a request for allocation is posted 1056 */ 1057 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1058 struct iwl_rx_mem_buffer *rxb, 1059 struct iwl_rxq *rxq, bool emergency) 1060 { 1061 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1062 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1063 1064 /* Move the RBD to the used list, will be moved to allocator in batches 1065 * before claiming or posting a request*/ 1066 list_add_tail(&rxb->list, &rxq->rx_used); 1067 1068 if (unlikely(emergency)) 1069 return; 1070 1071 /* Count the allocator owned RBDs */ 1072 rxq->used_count++; 1073 1074 /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1075 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1076 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1077 * after but we still need to post another request. 1078 */ 1079 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1080 /* Move the 2 RBDs to the allocator ownership. 1081 Allocator has another 6 from pool for the request completion*/ 1082 spin_lock(&rba->lock); 1083 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1084 spin_unlock(&rba->lock); 1085 1086 atomic_inc(&rba->req_pending); 1087 queue_work(rba->alloc_wq, &rba->rx_alloc); 1088 } 1089 } 1090 1091 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 1092 struct iwl_rxq *rxq, 1093 struct iwl_rx_mem_buffer *rxb, 1094 bool emergency) 1095 { 1096 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1097 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1098 bool page_stolen = false; 1099 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 1100 u32 offset = 0; 1101 1102 if (WARN_ON(!rxb)) 1103 return; 1104 1105 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1106 1107 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1108 struct iwl_rx_packet *pkt; 1109 u16 sequence; 1110 bool reclaim; 1111 int index, cmd_index, len; 1112 struct iwl_rx_cmd_buffer rxcb = { 1113 ._offset = offset, 1114 ._rx_page_order = trans_pcie->rx_page_order, 1115 ._page = rxb->page, 1116 ._page_stolen = false, 1117 .truesize = max_len, 1118 }; 1119 1120 pkt = rxb_addr(&rxcb); 1121 1122 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 1123 IWL_DEBUG_RX(trans, 1124 "Q %d: RB end marker at offset %d\n", 1125 rxq->id, offset); 1126 break; 1127 } 1128 1129 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1130 FH_RSCSR_RXQ_POS != rxq->id, 1131 "frame on invalid queue - is on %d and indicates %d\n", 1132 rxq->id, 1133 (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1134 FH_RSCSR_RXQ_POS); 1135 1136 IWL_DEBUG_RX(trans, 1137 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 1138 rxq->id, offset, 1139 iwl_get_cmd_string(trans, 1140 iwl_cmd_id(pkt->hdr.cmd, 1141 pkt->hdr.group_id, 1142 0)), 1143 pkt->hdr.group_id, pkt->hdr.cmd, 1144 le16_to_cpu(pkt->hdr.sequence)); 1145 1146 len = iwl_rx_packet_len(pkt); 1147 len += sizeof(u32); /* account for status word */ 1148 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1149 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1150 1151 /* Reclaim a command buffer only if this packet is a response 1152 * to a (driver-originated) command. 1153 * If the packet (e.g. Rx frame) originated from uCode, 1154 * there is no command buffer to reclaim. 1155 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1156 * but apparently a few don't get set; catch them here. */ 1157 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1158 if (reclaim && !pkt->hdr.group_id) { 1159 int i; 1160 1161 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1162 if (trans_pcie->no_reclaim_cmds[i] == 1163 pkt->hdr.cmd) { 1164 reclaim = false; 1165 break; 1166 } 1167 } 1168 } 1169 1170 sequence = le16_to_cpu(pkt->hdr.sequence); 1171 index = SEQ_TO_INDEX(sequence); 1172 cmd_index = iwl_pcie_get_cmd_index(txq, index); 1173 1174 if (rxq->id == 0) 1175 iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1176 &rxcb); 1177 else 1178 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1179 &rxcb, rxq->id); 1180 1181 if (reclaim) { 1182 kzfree(txq->entries[cmd_index].free_buf); 1183 txq->entries[cmd_index].free_buf = NULL; 1184 } 1185 1186 /* 1187 * After here, we should always check rxcb._page_stolen, 1188 * if it is true then one of the handlers took the page. 1189 */ 1190 1191 if (reclaim) { 1192 /* Invoke any callbacks, transfer the buffer to caller, 1193 * and fire off the (possibly) blocking 1194 * iwl_trans_send_cmd() 1195 * as we reclaim the driver command queue */ 1196 if (!rxcb._page_stolen) 1197 iwl_pcie_hcmd_complete(trans, &rxcb); 1198 else 1199 IWL_WARN(trans, "Claim null rxb?\n"); 1200 } 1201 1202 page_stolen |= rxcb._page_stolen; 1203 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1204 } 1205 1206 /* page was stolen from us -- free our reference */ 1207 if (page_stolen) { 1208 __free_pages(rxb->page, trans_pcie->rx_page_order); 1209 rxb->page = NULL; 1210 } 1211 1212 /* Reuse the page if possible. For notification packets and 1213 * SKBs that fail to Rx correctly, add them back into the 1214 * rx_free list for reuse later. */ 1215 if (rxb->page != NULL) { 1216 rxb->page_dma = 1217 dma_map_page(trans->dev, rxb->page, 0, 1218 PAGE_SIZE << trans_pcie->rx_page_order, 1219 DMA_FROM_DEVICE); 1220 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1221 /* 1222 * free the page(s) as well to not break 1223 * the invariant that the items on the used 1224 * list have no page(s) 1225 */ 1226 __free_pages(rxb->page, trans_pcie->rx_page_order); 1227 rxb->page = NULL; 1228 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1229 } else { 1230 list_add_tail(&rxb->list, &rxq->rx_free); 1231 rxq->free_count++; 1232 } 1233 } else 1234 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1235 } 1236 1237 /* 1238 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1239 */ 1240 static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue) 1241 { 1242 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1243 struct iwl_rxq *rxq = &trans_pcie->rxq[queue]; 1244 u32 r, i, count = 0; 1245 bool emergency = false; 1246 1247 restart: 1248 spin_lock(&rxq->lock); 1249 /* uCode's read index (stored in shared DRAM) indicates the last Rx 1250 * buffer that the driver may process (last buffer filled by ucode). */ 1251 r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 1252 i = rxq->read; 1253 1254 /* W/A 9000 device step A0 wrap-around bug */ 1255 r &= (rxq->queue_size - 1); 1256 1257 /* Rx interrupt, but nothing sent from uCode */ 1258 if (i == r) 1259 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1260 1261 while (i != r) { 1262 struct iwl_rx_mem_buffer *rxb; 1263 1264 if (unlikely(rxq->used_count == rxq->queue_size / 2)) 1265 emergency = true; 1266 1267 if (trans->cfg->mq_rx_supported) { 1268 /* 1269 * used_bd is a 32 bit but only 12 are used to retrieve 1270 * the vid 1271 */ 1272 u16 vid = le32_to_cpu(rxq->used_bd[i]) & 0x0FFF; 1273 1274 if (WARN(!vid || 1275 vid > ARRAY_SIZE(trans_pcie->global_table), 1276 "Invalid rxb index from HW %u\n", (u32)vid)) { 1277 iwl_force_nmi(trans); 1278 goto out; 1279 } 1280 rxb = trans_pcie->global_table[vid - 1]; 1281 if (WARN(rxb->invalid, 1282 "Invalid rxb from HW %u\n", (u32)vid)) { 1283 iwl_force_nmi(trans); 1284 goto out; 1285 } 1286 rxb->invalid = true; 1287 } else { 1288 rxb = rxq->queue[i]; 1289 rxq->queue[i] = NULL; 1290 } 1291 1292 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 1293 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency); 1294 1295 i = (i + 1) & (rxq->queue_size - 1); 1296 1297 /* 1298 * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1299 * try to claim the pre-allocated buffers from the allocator. 1300 * If not ready - will try to reclaim next time. 1301 * There is no need to reschedule work - allocator exits only 1302 * on success 1303 */ 1304 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1305 iwl_pcie_rx_allocator_get(trans, rxq); 1306 1307 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1308 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1309 1310 /* Add the remaining empty RBDs for allocator use */ 1311 spin_lock(&rba->lock); 1312 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1313 spin_unlock(&rba->lock); 1314 } else if (emergency) { 1315 count++; 1316 if (count == 8) { 1317 count = 0; 1318 if (rxq->used_count < rxq->queue_size / 3) 1319 emergency = false; 1320 1321 rxq->read = i; 1322 spin_unlock(&rxq->lock); 1323 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1324 iwl_pcie_rxq_restock(trans, rxq); 1325 goto restart; 1326 } 1327 } 1328 } 1329 out: 1330 /* Backtrack one entry */ 1331 rxq->read = i; 1332 spin_unlock(&rxq->lock); 1333 1334 /* 1335 * handle a case where in emergency there are some unallocated RBDs. 1336 * those RBDs are in the used list, but are not tracked by the queue's 1337 * used_count which counts allocator owned RBDs. 1338 * unallocated emergency RBDs must be allocated on exit, otherwise 1339 * when called again the function may not be in emergency mode and 1340 * they will be handed to the allocator with no tracking in the RBD 1341 * allocator counters, which will lead to them never being claimed back 1342 * by the queue. 1343 * by allocating them here, they are now in the queue free list, and 1344 * will be restocked by the next call of iwl_pcie_rxq_restock. 1345 */ 1346 if (unlikely(emergency && count)) 1347 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1348 1349 if (rxq->napi.poll) 1350 napi_gro_flush(&rxq->napi, false); 1351 1352 iwl_pcie_rxq_restock(trans, rxq); 1353 } 1354 1355 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 1356 { 1357 u8 queue = entry->entry; 1358 struct msix_entry *entries = entry - queue; 1359 1360 return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 1361 } 1362 1363 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 1364 struct msix_entry *entry) 1365 { 1366 /* 1367 * Before sending the interrupt the HW disables it to prevent 1368 * a nested interrupt. This is done by writing 1 to the corresponding 1369 * bit in the mask register. After handling the interrupt, it should be 1370 * re-enabled by clearing this bit. This register is defined as 1371 * write 1 clear (W1C) register, meaning that it's being clear 1372 * by writing 1 to the bit. 1373 */ 1374 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 1375 } 1376 1377 /* 1378 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 1379 * This interrupt handler should be used with RSS queue only. 1380 */ 1381 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 1382 { 1383 struct msix_entry *entry = dev_id; 1384 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 1385 struct iwl_trans *trans = trans_pcie->trans; 1386 1387 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1388 1389 if (WARN_ON(entry->entry >= trans->num_rx_queues)) 1390 return IRQ_NONE; 1391 1392 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1393 1394 local_bh_disable(); 1395 iwl_pcie_rx_handle(trans, entry->entry); 1396 local_bh_enable(); 1397 1398 iwl_pcie_clear_irq(trans, entry); 1399 1400 lock_map_release(&trans->sync_cmd_lockdep_map); 1401 1402 return IRQ_HANDLED; 1403 } 1404 1405 /* 1406 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1407 */ 1408 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1409 { 1410 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1411 int i; 1412 1413 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1414 if (trans->cfg->internal_wimax_coex && 1415 !trans->cfg->apmg_not_supported && 1416 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1417 APMS_CLK_VAL_MRB_FUNC_MODE) || 1418 (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1419 APMG_PS_CTRL_VAL_RESET_REQ))) { 1420 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1421 iwl_op_mode_wimax_active(trans->op_mode); 1422 wake_up(&trans_pcie->wait_command_queue); 1423 return; 1424 } 1425 1426 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 1427 if (!trans_pcie->txq[i]) 1428 continue; 1429 del_timer(&trans_pcie->txq[i]->stuck_timer); 1430 } 1431 1432 /* The STATUS_FW_ERROR bit is set in this function. This must happen 1433 * before we wake up the command caller, to ensure a proper cleanup. */ 1434 iwl_trans_fw_error(trans); 1435 1436 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1437 wake_up(&trans_pcie->wait_command_queue); 1438 } 1439 1440 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1441 { 1442 u32 inta; 1443 1444 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1445 1446 trace_iwlwifi_dev_irq(trans->dev); 1447 1448 /* Discover which interrupts are active/pending */ 1449 inta = iwl_read32(trans, CSR_INT); 1450 1451 /* the thread will service interrupts and re-enable them */ 1452 return inta; 1453 } 1454 1455 /* a device (PCI-E) page is 4096 bytes long */ 1456 #define ICT_SHIFT 12 1457 #define ICT_SIZE (1 << ICT_SHIFT) 1458 #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1459 1460 /* interrupt handler using ict table, with this interrupt driver will 1461 * stop using INTA register to get device's interrupt, reading this register 1462 * is expensive, device will write interrupts in ICT dram table, increment 1463 * index then will fire interrupt to driver, driver will OR all ICT table 1464 * entries from current index up to table entry with 0 value. the result is 1465 * the interrupt we need to service, driver will set the entries back to 0 and 1466 * set index. 1467 */ 1468 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1469 { 1470 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1471 u32 inta; 1472 u32 val = 0; 1473 u32 read; 1474 1475 trace_iwlwifi_dev_irq(trans->dev); 1476 1477 /* Ignore interrupt if there's nothing in NIC to service. 1478 * This may be due to IRQ shared with another device, 1479 * or due to sporadic interrupts thrown from our NIC. */ 1480 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1481 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1482 if (!read) 1483 return 0; 1484 1485 /* 1486 * Collect all entries up to the first 0, starting from ict_index; 1487 * note we already read at ict_index. 1488 */ 1489 do { 1490 val |= read; 1491 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1492 trans_pcie->ict_index, read); 1493 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1494 trans_pcie->ict_index = 1495 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1496 1497 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1498 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1499 read); 1500 } while (read); 1501 1502 /* We should not get this value, just ignore it. */ 1503 if (val == 0xffffffff) 1504 val = 0; 1505 1506 /* 1507 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1508 * (bit 15 before shifting it to 31) to clear when using interrupt 1509 * coalescing. fortunately, bits 18 and 19 stay set when this happens 1510 * so we use them to decide on the real state of the Rx bit. 1511 * In order words, bit 15 is set if bit 18 or bit 19 are set. 1512 */ 1513 if (val & 0xC0000) 1514 val |= 0x8000; 1515 1516 inta = (0xff & val) | ((0xff00 & val) << 16); 1517 return inta; 1518 } 1519 1520 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 1521 { 1522 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1523 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1524 bool hw_rfkill, prev, report; 1525 1526 mutex_lock(&trans_pcie->mutex); 1527 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1528 hw_rfkill = iwl_is_rfkill_set(trans); 1529 if (hw_rfkill) { 1530 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1531 set_bit(STATUS_RFKILL_HW, &trans->status); 1532 } 1533 if (trans_pcie->opmode_down) 1534 report = hw_rfkill; 1535 else 1536 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1537 1538 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 1539 hw_rfkill ? "disable radio" : "enable radio"); 1540 1541 isr_stats->rfkill++; 1542 1543 if (prev != report) 1544 iwl_trans_pcie_rf_kill(trans, report); 1545 mutex_unlock(&trans_pcie->mutex); 1546 1547 if (hw_rfkill) { 1548 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 1549 &trans->status)) 1550 IWL_DEBUG_RF_KILL(trans, 1551 "Rfkill while SYNC HCMD in flight\n"); 1552 wake_up(&trans_pcie->wait_command_queue); 1553 } else { 1554 clear_bit(STATUS_RFKILL_HW, &trans->status); 1555 if (trans_pcie->opmode_down) 1556 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1557 } 1558 } 1559 1560 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1561 { 1562 struct iwl_trans *trans = dev_id; 1563 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1564 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1565 u32 inta = 0; 1566 u32 handled = 0; 1567 1568 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1569 1570 spin_lock(&trans_pcie->irq_lock); 1571 1572 /* dram interrupt table not set yet, 1573 * use legacy interrupt. 1574 */ 1575 if (likely(trans_pcie->use_ict)) 1576 inta = iwl_pcie_int_cause_ict(trans); 1577 else 1578 inta = iwl_pcie_int_cause_non_ict(trans); 1579 1580 if (iwl_have_debug_level(IWL_DL_ISR)) { 1581 IWL_DEBUG_ISR(trans, 1582 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1583 inta, trans_pcie->inta_mask, 1584 iwl_read32(trans, CSR_INT_MASK), 1585 iwl_read32(trans, CSR_FH_INT_STATUS)); 1586 if (inta & (~trans_pcie->inta_mask)) 1587 IWL_DEBUG_ISR(trans, 1588 "We got a masked interrupt (0x%08x)\n", 1589 inta & (~trans_pcie->inta_mask)); 1590 } 1591 1592 inta &= trans_pcie->inta_mask; 1593 1594 /* 1595 * Ignore interrupt if there's nothing in NIC to service. 1596 * This may be due to IRQ shared with another device, 1597 * or due to sporadic interrupts thrown from our NIC. 1598 */ 1599 if (unlikely(!inta)) { 1600 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1601 /* 1602 * Re-enable interrupts here since we don't 1603 * have anything to service 1604 */ 1605 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1606 _iwl_enable_interrupts(trans); 1607 spin_unlock(&trans_pcie->irq_lock); 1608 lock_map_release(&trans->sync_cmd_lockdep_map); 1609 return IRQ_NONE; 1610 } 1611 1612 if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1613 /* 1614 * Hardware disappeared. It might have 1615 * already raised an interrupt. 1616 */ 1617 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1618 spin_unlock(&trans_pcie->irq_lock); 1619 goto out; 1620 } 1621 1622 /* Ack/clear/reset pending uCode interrupts. 1623 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1624 */ 1625 /* There is a hardware bug in the interrupt mask function that some 1626 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1627 * they are disabled in the CSR_INT_MASK register. Furthermore the 1628 * ICT interrupt handling mechanism has another bug that might cause 1629 * these unmasked interrupts fail to be detected. We workaround the 1630 * hardware bugs here by ACKing all the possible interrupts so that 1631 * interrupt coalescing can still be achieved. 1632 */ 1633 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1634 1635 if (iwl_have_debug_level(IWL_DL_ISR)) 1636 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1637 inta, iwl_read32(trans, CSR_INT_MASK)); 1638 1639 spin_unlock(&trans_pcie->irq_lock); 1640 1641 /* Now service all interrupt bits discovered above. */ 1642 if (inta & CSR_INT_BIT_HW_ERR) { 1643 IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1644 1645 /* Tell the device to stop sending interrupts */ 1646 iwl_disable_interrupts(trans); 1647 1648 isr_stats->hw++; 1649 iwl_pcie_irq_handle_error(trans); 1650 1651 handled |= CSR_INT_BIT_HW_ERR; 1652 1653 goto out; 1654 } 1655 1656 if (iwl_have_debug_level(IWL_DL_ISR)) { 1657 /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1658 if (inta & CSR_INT_BIT_SCD) { 1659 IWL_DEBUG_ISR(trans, 1660 "Scheduler finished to transmit the frame/frames.\n"); 1661 isr_stats->sch++; 1662 } 1663 1664 /* Alive notification via Rx interrupt will do the real work */ 1665 if (inta & CSR_INT_BIT_ALIVE) { 1666 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1667 isr_stats->alive++; 1668 if (trans->cfg->gen2) { 1669 /* 1670 * We can restock, since firmware configured 1671 * the RFH 1672 */ 1673 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1674 } 1675 } 1676 } 1677 1678 /* Safely ignore these bits for debug checks below */ 1679 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1680 1681 /* HW RF KILL switch toggled */ 1682 if (inta & CSR_INT_BIT_RF_KILL) { 1683 iwl_pcie_handle_rfkill_irq(trans); 1684 handled |= CSR_INT_BIT_RF_KILL; 1685 } 1686 1687 /* Chip got too hot and stopped itself */ 1688 if (inta & CSR_INT_BIT_CT_KILL) { 1689 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1690 isr_stats->ctkill++; 1691 handled |= CSR_INT_BIT_CT_KILL; 1692 } 1693 1694 /* Error detected by uCode */ 1695 if (inta & CSR_INT_BIT_SW_ERR) { 1696 IWL_ERR(trans, "Microcode SW error detected. " 1697 " Restarting 0x%X.\n", inta); 1698 isr_stats->sw++; 1699 iwl_pcie_irq_handle_error(trans); 1700 handled |= CSR_INT_BIT_SW_ERR; 1701 } 1702 1703 /* uCode wakes up after power-down sleep */ 1704 if (inta & CSR_INT_BIT_WAKEUP) { 1705 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1706 iwl_pcie_rxq_check_wrptr(trans); 1707 iwl_pcie_txq_check_wrptrs(trans); 1708 1709 isr_stats->wakeup++; 1710 1711 handled |= CSR_INT_BIT_WAKEUP; 1712 } 1713 1714 /* All uCode command responses, including Tx command responses, 1715 * Rx "responses" (frame-received notification), and other 1716 * notifications from uCode come through here*/ 1717 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1718 CSR_INT_BIT_RX_PERIODIC)) { 1719 IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1720 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1721 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1722 iwl_write32(trans, CSR_FH_INT_STATUS, 1723 CSR_FH_INT_RX_MASK); 1724 } 1725 if (inta & CSR_INT_BIT_RX_PERIODIC) { 1726 handled |= CSR_INT_BIT_RX_PERIODIC; 1727 iwl_write32(trans, 1728 CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1729 } 1730 /* Sending RX interrupt require many steps to be done in the 1731 * the device: 1732 * 1- write interrupt to current index in ICT table. 1733 * 2- dma RX frame. 1734 * 3- update RX shared data to indicate last write index. 1735 * 4- send interrupt. 1736 * This could lead to RX race, driver could receive RX interrupt 1737 * but the shared data changes does not reflect this; 1738 * periodic interrupt will detect any dangling Rx activity. 1739 */ 1740 1741 /* Disable periodic interrupt; we use it as just a one-shot. */ 1742 iwl_write8(trans, CSR_INT_PERIODIC_REG, 1743 CSR_INT_PERIODIC_DIS); 1744 1745 /* 1746 * Enable periodic interrupt in 8 msec only if we received 1747 * real RX interrupt (instead of just periodic int), to catch 1748 * any dangling Rx interrupt. If it was just the periodic 1749 * interrupt, there was no dangling Rx activity, and no need 1750 * to extend the periodic interrupt; one-shot is enough. 1751 */ 1752 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1753 iwl_write8(trans, CSR_INT_PERIODIC_REG, 1754 CSR_INT_PERIODIC_ENA); 1755 1756 isr_stats->rx++; 1757 1758 local_bh_disable(); 1759 iwl_pcie_rx_handle(trans, 0); 1760 local_bh_enable(); 1761 } 1762 1763 /* This "Tx" DMA channel is used only for loading uCode */ 1764 if (inta & CSR_INT_BIT_FH_TX) { 1765 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1766 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1767 isr_stats->tx++; 1768 handled |= CSR_INT_BIT_FH_TX; 1769 /* Wake up uCode load routine, now that load is complete */ 1770 trans_pcie->ucode_write_complete = true; 1771 wake_up(&trans_pcie->ucode_write_waitq); 1772 } 1773 1774 if (inta & ~handled) { 1775 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 1776 isr_stats->unhandled++; 1777 } 1778 1779 if (inta & ~(trans_pcie->inta_mask)) { 1780 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 1781 inta & ~trans_pcie->inta_mask); 1782 } 1783 1784 spin_lock(&trans_pcie->irq_lock); 1785 /* only Re-enable all interrupt if disabled by irq */ 1786 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1787 _iwl_enable_interrupts(trans); 1788 /* we are loading the firmware, enable FH_TX interrupt only */ 1789 else if (handled & CSR_INT_BIT_FH_TX) 1790 iwl_enable_fw_load_int(trans); 1791 /* Re-enable RF_KILL if it occurred */ 1792 else if (handled & CSR_INT_BIT_RF_KILL) 1793 iwl_enable_rfkill_int(trans); 1794 spin_unlock(&trans_pcie->irq_lock); 1795 1796 out: 1797 lock_map_release(&trans->sync_cmd_lockdep_map); 1798 return IRQ_HANDLED; 1799 } 1800 1801 /****************************************************************************** 1802 * 1803 * ICT functions 1804 * 1805 ******************************************************************************/ 1806 1807 /* Free dram table */ 1808 void iwl_pcie_free_ict(struct iwl_trans *trans) 1809 { 1810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1811 1812 if (trans_pcie->ict_tbl) { 1813 dma_free_coherent(trans->dev, ICT_SIZE, 1814 trans_pcie->ict_tbl, 1815 trans_pcie->ict_tbl_dma); 1816 trans_pcie->ict_tbl = NULL; 1817 trans_pcie->ict_tbl_dma = 0; 1818 } 1819 } 1820 1821 /* 1822 * allocate dram shared table, it is an aligned memory 1823 * block of ICT_SIZE. 1824 * also reset all data related to ICT table interrupt. 1825 */ 1826 int iwl_pcie_alloc_ict(struct iwl_trans *trans) 1827 { 1828 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1829 1830 trans_pcie->ict_tbl = 1831 dma_zalloc_coherent(trans->dev, ICT_SIZE, 1832 &trans_pcie->ict_tbl_dma, 1833 GFP_KERNEL); 1834 if (!trans_pcie->ict_tbl) 1835 return -ENOMEM; 1836 1837 /* just an API sanity check ... it is guaranteed to be aligned */ 1838 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 1839 iwl_pcie_free_ict(trans); 1840 return -EINVAL; 1841 } 1842 1843 return 0; 1844 } 1845 1846 /* Device is going up inform it about using ICT interrupt table, 1847 * also we need to tell the driver to start using ICT interrupt. 1848 */ 1849 void iwl_pcie_reset_ict(struct iwl_trans *trans) 1850 { 1851 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1852 u32 val; 1853 1854 if (!trans_pcie->ict_tbl) 1855 return; 1856 1857 spin_lock(&trans_pcie->irq_lock); 1858 _iwl_disable_interrupts(trans); 1859 1860 memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 1861 1862 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 1863 1864 val |= CSR_DRAM_INT_TBL_ENABLE | 1865 CSR_DRAM_INIT_TBL_WRAP_CHECK | 1866 CSR_DRAM_INIT_TBL_WRITE_POINTER; 1867 1868 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 1869 1870 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 1871 trans_pcie->use_ict = true; 1872 trans_pcie->ict_index = 0; 1873 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 1874 _iwl_enable_interrupts(trans); 1875 spin_unlock(&trans_pcie->irq_lock); 1876 } 1877 1878 /* Device is going down disable ict interrupt usage */ 1879 void iwl_pcie_disable_ict(struct iwl_trans *trans) 1880 { 1881 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1882 1883 spin_lock(&trans_pcie->irq_lock); 1884 trans_pcie->use_ict = false; 1885 spin_unlock(&trans_pcie->irq_lock); 1886 } 1887 1888 irqreturn_t iwl_pcie_isr(int irq, void *data) 1889 { 1890 struct iwl_trans *trans = data; 1891 1892 if (!trans) 1893 return IRQ_NONE; 1894 1895 /* Disable (but don't clear!) interrupts here to avoid 1896 * back-to-back ISRs and sporadic interrupts from our NIC. 1897 * If we have something to service, the tasklet will re-enable ints. 1898 * If we *don't* have something, we'll re-enable before leaving here. 1899 */ 1900 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 1901 1902 return IRQ_WAKE_THREAD; 1903 } 1904 1905 irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 1906 { 1907 return IRQ_WAKE_THREAD; 1908 } 1909 1910 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 1911 { 1912 struct msix_entry *entry = dev_id; 1913 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 1914 struct iwl_trans *trans = trans_pcie->trans; 1915 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1916 u32 inta_fh, inta_hw; 1917 1918 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1919 1920 spin_lock(&trans_pcie->irq_lock); 1921 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 1922 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 1923 /* 1924 * Clear causes registers to avoid being handling the same cause. 1925 */ 1926 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 1927 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 1928 spin_unlock(&trans_pcie->irq_lock); 1929 1930 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 1931 1932 if (unlikely(!(inta_fh | inta_hw))) { 1933 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1934 lock_map_release(&trans->sync_cmd_lockdep_map); 1935 return IRQ_NONE; 1936 } 1937 1938 if (iwl_have_debug_level(IWL_DL_ISR)) 1939 IWL_DEBUG_ISR(trans, "ISR inta_fh 0x%08x, enabled 0x%08x\n", 1940 inta_fh, 1941 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 1942 1943 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 1944 inta_fh & MSIX_FH_INT_CAUSES_Q0) { 1945 local_bh_disable(); 1946 iwl_pcie_rx_handle(trans, 0); 1947 local_bh_enable(); 1948 } 1949 1950 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 1951 inta_fh & MSIX_FH_INT_CAUSES_Q1) { 1952 local_bh_disable(); 1953 iwl_pcie_rx_handle(trans, 1); 1954 local_bh_enable(); 1955 } 1956 1957 /* This "Tx" DMA channel is used only for loading uCode */ 1958 if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 1959 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1960 isr_stats->tx++; 1961 /* 1962 * Wake up uCode load routine, 1963 * now that load is complete 1964 */ 1965 trans_pcie->ucode_write_complete = true; 1966 wake_up(&trans_pcie->ucode_write_waitq); 1967 } 1968 1969 /* Error detected by uCode */ 1970 if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 1971 (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) { 1972 IWL_ERR(trans, 1973 "Microcode SW error detected. Restarting 0x%X.\n", 1974 inta_fh); 1975 isr_stats->sw++; 1976 iwl_pcie_irq_handle_error(trans); 1977 } 1978 1979 /* After checking FH register check HW register */ 1980 if (iwl_have_debug_level(IWL_DL_ISR)) 1981 IWL_DEBUG_ISR(trans, 1982 "ISR inta_hw 0x%08x, enabled 0x%08x\n", 1983 inta_hw, 1984 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 1985 1986 /* Alive notification via Rx interrupt will do the real work */ 1987 if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 1988 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1989 isr_stats->alive++; 1990 if (trans->cfg->gen2) { 1991 /* We can restock, since firmware configured the RFH */ 1992 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1993 } 1994 } 1995 1996 /* uCode wakes up after power-down sleep */ 1997 if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 1998 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1999 iwl_pcie_rxq_check_wrptr(trans); 2000 iwl_pcie_txq_check_wrptrs(trans); 2001 2002 isr_stats->wakeup++; 2003 } 2004 2005 /* Chip got too hot and stopped itself */ 2006 if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 2007 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 2008 isr_stats->ctkill++; 2009 } 2010 2011 /* HW RF KILL switch toggled */ 2012 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 2013 iwl_pcie_handle_rfkill_irq(trans); 2014 2015 if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 2016 IWL_ERR(trans, 2017 "Hardware error detected. Restarting.\n"); 2018 2019 isr_stats->hw++; 2020 iwl_pcie_irq_handle_error(trans); 2021 } 2022 2023 iwl_pcie_clear_irq(trans, entry); 2024 2025 lock_map_release(&trans->sync_cmd_lockdep_map); 2026 2027 return IRQ_HANDLED; 2028 } 2029