1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2003-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/sched.h> 8 #include <linux/wait.h> 9 #include <linux/gfp.h> 10 11 #include "iwl-prph.h" 12 #include "iwl-io.h" 13 #include "internal.h" 14 #include "iwl-op-mode.h" 15 #include "iwl-context-info-gen3.h" 16 17 /****************************************************************************** 18 * 19 * RX path functions 20 * 21 ******************************************************************************/ 22 23 /* 24 * Rx theory of operation 25 * 26 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 27 * each of which point to Receive Buffers to be filled by the NIC. These get 28 * used not only for Rx frames, but for any command response or notification 29 * from the NIC. The driver and NIC manage the Rx buffers by means 30 * of indexes into the circular buffer. 31 * 32 * Rx Queue Indexes 33 * The host/firmware share two index registers for managing the Rx buffers. 34 * 35 * The READ index maps to the first position that the firmware may be writing 36 * to -- the driver can read up to (but not including) this position and get 37 * good data. 38 * The READ index is managed by the firmware once the card is enabled. 39 * 40 * The WRITE index maps to the last position the driver has read from -- the 41 * position preceding WRITE is the last slot the firmware can place a packet. 42 * 43 * The queue is empty (no good data) if WRITE = READ - 1, and is full if 44 * WRITE = READ. 45 * 46 * During initialization, the host sets up the READ queue position to the first 47 * INDEX position, and WRITE to the last (READ - 1 wrapped) 48 * 49 * When the firmware places a packet in a buffer, it will advance the READ index 50 * and fire the RX interrupt. The driver can then query the READ index and 51 * process as many packets as possible, moving the WRITE index forward as it 52 * resets the Rx queue buffers with new memory. 53 * 54 * The management in the driver is as follows: 55 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 56 * When the interrupt handler is called, the request is processed. 57 * The page is either stolen - transferred to the upper layer 58 * or reused - added immediately to the iwl->rxq->rx_free list. 59 * + When the page is stolen - the driver updates the matching queue's used 60 * count, detaches the RBD and transfers it to the queue used list. 61 * When there are two used RBDs - they are transferred to the allocator empty 62 * list. Work is then scheduled for the allocator to start allocating 63 * eight buffers. 64 * When there are another 6 used RBDs - they are transferred to the allocator 65 * empty list and the driver tries to claim the pre-allocated buffers and 66 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 67 * until ready. 68 * When there are 8+ buffers in the free list - either from allocation or from 69 * 8 reused unstolen pages - restock is called to update the FW and indexes. 70 * + In order to make sure the allocator always has RBDs to use for allocation 71 * the allocator has initial pool in the size of num_queues*(8-2) - the 72 * maximum missing RBDs per allocation request (request posted with 2 73 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 74 * The queues supplies the recycle of the rest of the RBDs. 75 * + A received packet is processed and handed to the kernel network stack, 76 * detached from the iwl->rxq. The driver 'processed' index is updated. 77 * + If there are no allocated buffers in iwl->rxq->rx_free, 78 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 79 * If there were enough free buffers and RX_STALLED is set it is cleared. 80 * 81 * 82 * Driver sequence: 83 * 84 * iwl_rxq_alloc() Allocates rx_free 85 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 86 * iwl_pcie_rxq_restock. 87 * Used only during initialization. 88 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 89 * queue, updates firmware pointers, and updates 90 * the WRITE index. 91 * iwl_pcie_rx_allocator() Background work for allocating pages. 92 * 93 * -- enable interrupts -- 94 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 95 * READ INDEX, detaching the SKB from the pool. 96 * Moves the packet buffer from queue to rx_used. 97 * Posts and claims requests to the allocator. 98 * Calls iwl_pcie_rxq_restock to refill any empty 99 * slots. 100 * 101 * RBD life-cycle: 102 * 103 * Init: 104 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 105 * 106 * Regular Receive interrupt: 107 * Page Stolen: 108 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 109 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 110 * Page not Stolen: 111 * rxq.queue -> rxq.rx_free -> rxq.queue 112 * ... 113 * 114 */ 115 116 /* 117 * iwl_rxq_space - Return number of free slots available in queue. 118 */ 119 static int iwl_rxq_space(const struct iwl_rxq *rxq) 120 { 121 /* Make sure rx queue size is a power of 2 */ 122 WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 123 124 /* 125 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 126 * between empty and completely full queues. 127 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 128 * defined for negative dividends. 129 */ 130 return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 131 } 132 133 /* 134 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 135 */ 136 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 137 { 138 return cpu_to_le32((u32)(dma_addr >> 8)); 139 } 140 141 /* 142 * iwl_pcie_rx_stop - stops the Rx DMA 143 */ 144 int iwl_pcie_rx_stop(struct iwl_trans *trans) 145 { 146 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 147 /* TODO: remove this once fw does it */ 148 iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 149 return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3, 150 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 151 } else if (trans->trans_cfg->mq_rx_supported) { 152 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 153 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 154 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 155 } else { 156 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 157 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 158 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 159 1000); 160 } 161 } 162 163 /* 164 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 165 */ 166 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 167 struct iwl_rxq *rxq) 168 { 169 u32 reg; 170 171 lockdep_assert_held(&rxq->lock); 172 173 /* 174 * explicitly wake up the NIC if: 175 * 1. shadow registers aren't enabled 176 * 2. there is a chance that the NIC is asleep 177 */ 178 if (!trans->trans_cfg->base_params->shadow_reg_enable && 179 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 180 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 181 182 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 183 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 184 reg); 185 iwl_set_bit(trans, CSR_GP_CNTRL, 186 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 187 rxq->need_update = true; 188 return; 189 } 190 } 191 192 rxq->write_actual = round_down(rxq->write, 8); 193 if (trans->trans_cfg->mq_rx_supported) 194 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 195 rxq->write_actual); 196 else 197 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 198 } 199 200 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 201 { 202 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 203 int i; 204 205 for (i = 0; i < trans->num_rx_queues; i++) { 206 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 207 208 if (!rxq->need_update) 209 continue; 210 spin_lock_bh(&rxq->lock); 211 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 212 rxq->need_update = false; 213 spin_unlock_bh(&rxq->lock); 214 } 215 } 216 217 static void iwl_pcie_restock_bd(struct iwl_trans *trans, 218 struct iwl_rxq *rxq, 219 struct iwl_rx_mem_buffer *rxb) 220 { 221 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 222 struct iwl_rx_transfer_desc *bd = rxq->bd; 223 224 BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64)); 225 226 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 227 bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 228 } else { 229 __le64 *bd = rxq->bd; 230 231 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 232 } 233 234 IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n", 235 (u32)rxb->vid, rxq->id, rxq->write); 236 } 237 238 /* 239 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 240 */ 241 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 242 struct iwl_rxq *rxq) 243 { 244 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 245 struct iwl_rx_mem_buffer *rxb; 246 247 /* 248 * If the device isn't enabled - no need to try to add buffers... 249 * This can happen when we stop the device and still have an interrupt 250 * pending. We stop the APM before we sync the interrupts because we 251 * have to (see comment there). On the other hand, since the APM is 252 * stopped, we cannot access the HW (in particular not prph). 253 * So don't try to restock if the APM has been already stopped. 254 */ 255 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 256 return; 257 258 spin_lock_bh(&rxq->lock); 259 while (rxq->free_count) { 260 /* Get next free Rx buffer, remove from free list */ 261 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 262 list); 263 list_del(&rxb->list); 264 rxb->invalid = false; 265 /* some low bits are expected to be unset (depending on hw) */ 266 WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask); 267 /* Point to Rx buffer via next RBD in circular buffer */ 268 iwl_pcie_restock_bd(trans, rxq, rxb); 269 rxq->write = (rxq->write + 1) & (rxq->queue_size - 1); 270 rxq->free_count--; 271 } 272 spin_unlock_bh(&rxq->lock); 273 274 /* 275 * If we've added more space for the firmware to place data, tell it. 276 * Increment device's write pointer in multiples of 8. 277 */ 278 if (rxq->write_actual != (rxq->write & ~0x7)) { 279 spin_lock_bh(&rxq->lock); 280 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 281 spin_unlock_bh(&rxq->lock); 282 } 283 } 284 285 /* 286 * iwl_pcie_rxsq_restock - restock implementation for single queue rx 287 */ 288 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 289 struct iwl_rxq *rxq) 290 { 291 struct iwl_rx_mem_buffer *rxb; 292 293 /* 294 * If the device isn't enabled - not need to try to add buffers... 295 * This can happen when we stop the device and still have an interrupt 296 * pending. We stop the APM before we sync the interrupts because we 297 * have to (see comment there). On the other hand, since the APM is 298 * stopped, we cannot access the HW (in particular not prph). 299 * So don't try to restock if the APM has been already stopped. 300 */ 301 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 302 return; 303 304 spin_lock_bh(&rxq->lock); 305 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 306 __le32 *bd = (__le32 *)rxq->bd; 307 /* The overwritten rxb must be a used one */ 308 rxb = rxq->queue[rxq->write]; 309 BUG_ON(rxb && rxb->page); 310 311 /* Get next free Rx buffer, remove from free list */ 312 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 313 list); 314 list_del(&rxb->list); 315 rxb->invalid = false; 316 317 /* Point to Rx buffer via next RBD in circular buffer */ 318 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 319 rxq->queue[rxq->write] = rxb; 320 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 321 rxq->free_count--; 322 } 323 spin_unlock_bh(&rxq->lock); 324 325 /* If we've added more space for the firmware to place data, tell it. 326 * Increment device's write pointer in multiples of 8. */ 327 if (rxq->write_actual != (rxq->write & ~0x7)) { 328 spin_lock_bh(&rxq->lock); 329 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 330 spin_unlock_bh(&rxq->lock); 331 } 332 } 333 334 /* 335 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 336 * 337 * If there are slots in the RX queue that need to be restocked, 338 * and we have free pre-allocated buffers, fill the ranks as much 339 * as we can, pulling from rx_free. 340 * 341 * This moves the 'write' index forward to catch up with 'processed', and 342 * also updates the memory address in the firmware to reference the new 343 * target buffer. 344 */ 345 static 346 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 347 { 348 if (trans->trans_cfg->mq_rx_supported) 349 iwl_pcie_rxmq_restock(trans, rxq); 350 else 351 iwl_pcie_rxsq_restock(trans, rxq); 352 } 353 354 /* 355 * iwl_pcie_rx_alloc_page - allocates and returns a page. 356 * 357 */ 358 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 359 u32 *offset, gfp_t priority) 360 { 361 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 362 unsigned int rbsize = iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 363 unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order; 364 struct page *page; 365 gfp_t gfp_mask = priority; 366 367 if (trans_pcie->rx_page_order > 0) 368 gfp_mask |= __GFP_COMP; 369 370 if (trans_pcie->alloc_page) { 371 spin_lock_bh(&trans_pcie->alloc_page_lock); 372 /* recheck */ 373 if (trans_pcie->alloc_page) { 374 *offset = trans_pcie->alloc_page_used; 375 page = trans_pcie->alloc_page; 376 trans_pcie->alloc_page_used += rbsize; 377 if (trans_pcie->alloc_page_used >= allocsize) 378 trans_pcie->alloc_page = NULL; 379 else 380 get_page(page); 381 spin_unlock_bh(&trans_pcie->alloc_page_lock); 382 return page; 383 } 384 spin_unlock_bh(&trans_pcie->alloc_page_lock); 385 } 386 387 /* Alloc a new receive buffer */ 388 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 389 if (!page) { 390 if (net_ratelimit()) 391 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 392 trans_pcie->rx_page_order); 393 /* 394 * Issue an error if we don't have enough pre-allocated 395 * buffers. 396 */ 397 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 398 IWL_CRIT(trans, 399 "Failed to alloc_pages\n"); 400 return NULL; 401 } 402 403 if (2 * rbsize <= allocsize) { 404 spin_lock_bh(&trans_pcie->alloc_page_lock); 405 if (!trans_pcie->alloc_page) { 406 get_page(page); 407 trans_pcie->alloc_page = page; 408 trans_pcie->alloc_page_used = rbsize; 409 } 410 spin_unlock_bh(&trans_pcie->alloc_page_lock); 411 } 412 413 *offset = 0; 414 return page; 415 } 416 417 /* 418 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 419 * 420 * A used RBD is an Rx buffer that has been given to the stack. To use it again 421 * a page must be allocated and the RBD must point to the page. This function 422 * doesn't change the HW pointer but handles the list of pages that is used by 423 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 424 * allocated buffers. 425 */ 426 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 427 struct iwl_rxq *rxq) 428 { 429 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 430 struct iwl_rx_mem_buffer *rxb; 431 struct page *page; 432 433 while (1) { 434 unsigned int offset; 435 436 spin_lock_bh(&rxq->lock); 437 if (list_empty(&rxq->rx_used)) { 438 spin_unlock_bh(&rxq->lock); 439 return; 440 } 441 spin_unlock_bh(&rxq->lock); 442 443 page = iwl_pcie_rx_alloc_page(trans, &offset, priority); 444 if (!page) 445 return; 446 447 spin_lock_bh(&rxq->lock); 448 449 if (list_empty(&rxq->rx_used)) { 450 spin_unlock_bh(&rxq->lock); 451 __free_pages(page, trans_pcie->rx_page_order); 452 return; 453 } 454 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 455 list); 456 list_del(&rxb->list); 457 spin_unlock_bh(&rxq->lock); 458 459 BUG_ON(rxb->page); 460 rxb->page = page; 461 rxb->offset = offset; 462 /* Get physical address of the RB */ 463 rxb->page_dma = 464 dma_map_page(trans->dev, page, rxb->offset, 465 trans_pcie->rx_buf_bytes, 466 DMA_FROM_DEVICE); 467 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 468 rxb->page = NULL; 469 spin_lock_bh(&rxq->lock); 470 list_add(&rxb->list, &rxq->rx_used); 471 spin_unlock_bh(&rxq->lock); 472 __free_pages(page, trans_pcie->rx_page_order); 473 return; 474 } 475 476 spin_lock_bh(&rxq->lock); 477 478 list_add_tail(&rxb->list, &rxq->rx_free); 479 rxq->free_count++; 480 481 spin_unlock_bh(&rxq->lock); 482 } 483 } 484 485 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 486 { 487 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 488 int i; 489 490 for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) { 491 if (!trans_pcie->rx_pool[i].page) 492 continue; 493 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 494 trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE); 495 __free_pages(trans_pcie->rx_pool[i].page, 496 trans_pcie->rx_page_order); 497 trans_pcie->rx_pool[i].page = NULL; 498 } 499 } 500 501 /* 502 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 503 * 504 * Allocates for each received request 8 pages 505 * Called as a scheduled work item. 506 */ 507 static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 508 { 509 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 510 struct iwl_rb_allocator *rba = &trans_pcie->rba; 511 struct list_head local_empty; 512 int pending = atomic_read(&rba->req_pending); 513 514 IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending); 515 516 /* If we were scheduled - there is at least one request */ 517 spin_lock_bh(&rba->lock); 518 /* swap out the rba->rbd_empty to a local list */ 519 list_replace_init(&rba->rbd_empty, &local_empty); 520 spin_unlock_bh(&rba->lock); 521 522 while (pending) { 523 int i; 524 LIST_HEAD(local_allocated); 525 gfp_t gfp_mask = GFP_KERNEL; 526 527 /* Do not post a warning if there are only a few requests */ 528 if (pending < RX_PENDING_WATERMARK) 529 gfp_mask |= __GFP_NOWARN; 530 531 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 532 struct iwl_rx_mem_buffer *rxb; 533 struct page *page; 534 535 /* List should never be empty - each reused RBD is 536 * returned to the list, and initial pool covers any 537 * possible gap between the time the page is allocated 538 * to the time the RBD is added. 539 */ 540 BUG_ON(list_empty(&local_empty)); 541 /* Get the first rxb from the rbd list */ 542 rxb = list_first_entry(&local_empty, 543 struct iwl_rx_mem_buffer, list); 544 BUG_ON(rxb->page); 545 546 /* Alloc a new receive buffer */ 547 page = iwl_pcie_rx_alloc_page(trans, &rxb->offset, 548 gfp_mask); 549 if (!page) 550 continue; 551 rxb->page = page; 552 553 /* Get physical address of the RB */ 554 rxb->page_dma = dma_map_page(trans->dev, page, 555 rxb->offset, 556 trans_pcie->rx_buf_bytes, 557 DMA_FROM_DEVICE); 558 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 559 rxb->page = NULL; 560 __free_pages(page, trans_pcie->rx_page_order); 561 continue; 562 } 563 564 /* move the allocated entry to the out list */ 565 list_move(&rxb->list, &local_allocated); 566 i++; 567 } 568 569 atomic_dec(&rba->req_pending); 570 pending--; 571 572 if (!pending) { 573 pending = atomic_read(&rba->req_pending); 574 if (pending) 575 IWL_DEBUG_TPT(trans, 576 "Got more pending allocation requests = %d\n", 577 pending); 578 } 579 580 spin_lock_bh(&rba->lock); 581 /* add the allocated rbds to the allocator allocated list */ 582 list_splice_tail(&local_allocated, &rba->rbd_allocated); 583 /* get more empty RBDs for current pending requests */ 584 list_splice_tail_init(&rba->rbd_empty, &local_empty); 585 spin_unlock_bh(&rba->lock); 586 587 atomic_inc(&rba->req_ready); 588 589 } 590 591 spin_lock_bh(&rba->lock); 592 /* return unused rbds to the allocator empty list */ 593 list_splice_tail(&local_empty, &rba->rbd_empty); 594 spin_unlock_bh(&rba->lock); 595 596 IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__); 597 } 598 599 /* 600 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 601 .* 602 .* Called by queue when the queue posted allocation request and 603 * has freed 8 RBDs in order to restock itself. 604 * This function directly moves the allocated RBs to the queue's ownership 605 * and updates the relevant counters. 606 */ 607 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 608 struct iwl_rxq *rxq) 609 { 610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 611 struct iwl_rb_allocator *rba = &trans_pcie->rba; 612 int i; 613 614 lockdep_assert_held(&rxq->lock); 615 616 /* 617 * atomic_dec_if_positive returns req_ready - 1 for any scenario. 618 * If req_ready is 0 atomic_dec_if_positive will return -1 and this 619 * function will return early, as there are no ready requests. 620 * atomic_dec_if_positive will perofrm the *actual* decrement only if 621 * req_ready > 0, i.e. - there are ready requests and the function 622 * hands one request to the caller. 623 */ 624 if (atomic_dec_if_positive(&rba->req_ready) < 0) 625 return; 626 627 spin_lock(&rba->lock); 628 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 629 /* Get next free Rx buffer, remove it from free list */ 630 struct iwl_rx_mem_buffer *rxb = 631 list_first_entry(&rba->rbd_allocated, 632 struct iwl_rx_mem_buffer, list); 633 634 list_move(&rxb->list, &rxq->rx_free); 635 } 636 spin_unlock(&rba->lock); 637 638 rxq->used_count -= RX_CLAIM_REQ_ALLOC; 639 rxq->free_count += RX_CLAIM_REQ_ALLOC; 640 } 641 642 void iwl_pcie_rx_allocator_work(struct work_struct *data) 643 { 644 struct iwl_rb_allocator *rba_p = 645 container_of(data, struct iwl_rb_allocator, rx_alloc); 646 struct iwl_trans_pcie *trans_pcie = 647 container_of(rba_p, struct iwl_trans_pcie, rba); 648 649 iwl_pcie_rx_allocator(trans_pcie->trans); 650 } 651 652 static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td) 653 { 654 struct iwl_rx_transfer_desc *rx_td; 655 656 if (use_rx_td) 657 return sizeof(*rx_td); 658 else 659 return trans->trans_cfg->mq_rx_supported ? sizeof(__le64) : 660 sizeof(__le32); 661 } 662 663 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 664 struct iwl_rxq *rxq) 665 { 666 struct device *dev = trans->dev; 667 bool use_rx_td = (trans->trans_cfg->device_family >= 668 IWL_DEVICE_FAMILY_AX210); 669 int free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 670 671 if (rxq->bd) 672 dma_free_coherent(trans->dev, 673 free_size * rxq->queue_size, 674 rxq->bd, rxq->bd_dma); 675 rxq->bd_dma = 0; 676 rxq->bd = NULL; 677 678 rxq->rb_stts_dma = 0; 679 rxq->rb_stts = NULL; 680 681 if (rxq->used_bd) 682 dma_free_coherent(trans->dev, 683 (use_rx_td ? sizeof(*rxq->cd) : 684 sizeof(__le32)) * rxq->queue_size, 685 rxq->used_bd, rxq->used_bd_dma); 686 rxq->used_bd_dma = 0; 687 rxq->used_bd = NULL; 688 689 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 690 return; 691 692 if (rxq->tr_tail) 693 dma_free_coherent(dev, sizeof(__le16), 694 rxq->tr_tail, rxq->tr_tail_dma); 695 rxq->tr_tail_dma = 0; 696 rxq->tr_tail = NULL; 697 698 if (rxq->cr_tail) 699 dma_free_coherent(dev, sizeof(__le16), 700 rxq->cr_tail, rxq->cr_tail_dma); 701 rxq->cr_tail_dma = 0; 702 rxq->cr_tail = NULL; 703 } 704 705 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 706 struct iwl_rxq *rxq) 707 { 708 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 709 struct device *dev = trans->dev; 710 int i; 711 int free_size; 712 bool use_rx_td = (trans->trans_cfg->device_family >= 713 IWL_DEVICE_FAMILY_AX210); 714 size_t rb_stts_size = use_rx_td ? sizeof(__le16) : 715 sizeof(struct iwl_rb_status); 716 717 spin_lock_init(&rxq->lock); 718 if (trans->trans_cfg->mq_rx_supported) 719 rxq->queue_size = trans->cfg->num_rbds; 720 else 721 rxq->queue_size = RX_QUEUE_SIZE; 722 723 free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 724 725 /* 726 * Allocate the circular buffer of Read Buffer Descriptors 727 * (RBDs) 728 */ 729 rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size, 730 &rxq->bd_dma, GFP_KERNEL); 731 if (!rxq->bd) 732 goto err; 733 734 if (trans->trans_cfg->mq_rx_supported) { 735 rxq->used_bd = dma_alloc_coherent(dev, 736 (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size, 737 &rxq->used_bd_dma, 738 GFP_KERNEL); 739 if (!rxq->used_bd) 740 goto err; 741 } 742 743 rxq->rb_stts = trans_pcie->base_rb_stts + rxq->id * rb_stts_size; 744 rxq->rb_stts_dma = 745 trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size; 746 747 if (!use_rx_td) 748 return 0; 749 750 /* Allocate the driver's pointer to TR tail */ 751 rxq->tr_tail = dma_alloc_coherent(dev, sizeof(__le16), 752 &rxq->tr_tail_dma, GFP_KERNEL); 753 if (!rxq->tr_tail) 754 goto err; 755 756 /* Allocate the driver's pointer to CR tail */ 757 rxq->cr_tail = dma_alloc_coherent(dev, sizeof(__le16), 758 &rxq->cr_tail_dma, GFP_KERNEL); 759 if (!rxq->cr_tail) 760 goto err; 761 762 return 0; 763 764 err: 765 for (i = 0; i < trans->num_rx_queues; i++) { 766 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 767 768 iwl_pcie_free_rxq_dma(trans, rxq); 769 } 770 771 return -ENOMEM; 772 } 773 774 static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 775 { 776 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 777 struct iwl_rb_allocator *rba = &trans_pcie->rba; 778 int i, ret; 779 size_t rb_stts_size = trans->trans_cfg->device_family >= 780 IWL_DEVICE_FAMILY_AX210 ? 781 sizeof(__le16) : sizeof(struct iwl_rb_status); 782 783 if (WARN_ON(trans_pcie->rxq)) 784 return -EINVAL; 785 786 trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 787 GFP_KERNEL); 788 trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 789 sizeof(trans_pcie->rx_pool[0]), 790 GFP_KERNEL); 791 trans_pcie->global_table = 792 kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 793 sizeof(trans_pcie->global_table[0]), 794 GFP_KERNEL); 795 if (!trans_pcie->rxq || !trans_pcie->rx_pool || 796 !trans_pcie->global_table) { 797 ret = -ENOMEM; 798 goto err; 799 } 800 801 spin_lock_init(&rba->lock); 802 803 /* 804 * Allocate the driver's pointer to receive buffer status. 805 * Allocate for all queues continuously (HW requirement). 806 */ 807 trans_pcie->base_rb_stts = 808 dma_alloc_coherent(trans->dev, 809 rb_stts_size * trans->num_rx_queues, 810 &trans_pcie->base_rb_stts_dma, 811 GFP_KERNEL); 812 if (!trans_pcie->base_rb_stts) { 813 ret = -ENOMEM; 814 goto err; 815 } 816 817 for (i = 0; i < trans->num_rx_queues; i++) { 818 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 819 820 rxq->id = i; 821 ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 822 if (ret) 823 goto err; 824 } 825 return 0; 826 827 err: 828 if (trans_pcie->base_rb_stts) { 829 dma_free_coherent(trans->dev, 830 rb_stts_size * trans->num_rx_queues, 831 trans_pcie->base_rb_stts, 832 trans_pcie->base_rb_stts_dma); 833 trans_pcie->base_rb_stts = NULL; 834 trans_pcie->base_rb_stts_dma = 0; 835 } 836 kfree(trans_pcie->rx_pool); 837 trans_pcie->rx_pool = NULL; 838 kfree(trans_pcie->global_table); 839 trans_pcie->global_table = NULL; 840 kfree(trans_pcie->rxq); 841 trans_pcie->rxq = NULL; 842 843 return ret; 844 } 845 846 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 847 { 848 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 849 u32 rb_size; 850 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 851 852 switch (trans_pcie->rx_buf_size) { 853 case IWL_AMSDU_4K: 854 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 855 break; 856 case IWL_AMSDU_8K: 857 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 858 break; 859 case IWL_AMSDU_12K: 860 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 861 break; 862 default: 863 WARN_ON(1); 864 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 865 } 866 867 if (!iwl_trans_grab_nic_access(trans)) 868 return; 869 870 /* Stop Rx DMA */ 871 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 872 /* reset and flush pointers */ 873 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 874 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 875 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 876 877 /* Reset driver's Rx queue write index */ 878 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 879 880 /* Tell device where to find RBD circular buffer in DRAM */ 881 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 882 (u32)(rxq->bd_dma >> 8)); 883 884 /* Tell device where in DRAM to update its Rx status */ 885 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 886 rxq->rb_stts_dma >> 4); 887 888 /* Enable Rx DMA 889 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 890 * the credit mechanism in 5000 HW RX FIFO 891 * Direct rx interrupts to hosts 892 * Rx buffer size 4 or 8k or 12k 893 * RB timeout 0x10 894 * 256 RBDs 895 */ 896 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 897 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 898 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 899 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 900 rb_size | 901 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 902 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 903 904 iwl_trans_release_nic_access(trans); 905 906 /* Set interrupt coalescing timer to default (2048 usecs) */ 907 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 908 909 /* W/A for interrupt coalescing bug in 7260 and 3160 */ 910 if (trans->cfg->host_interrupt_operation_mode) 911 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 912 } 913 914 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 915 { 916 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 917 u32 rb_size, enabled = 0; 918 int i; 919 920 switch (trans_pcie->rx_buf_size) { 921 case IWL_AMSDU_2K: 922 rb_size = RFH_RXF_DMA_RB_SIZE_2K; 923 break; 924 case IWL_AMSDU_4K: 925 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 926 break; 927 case IWL_AMSDU_8K: 928 rb_size = RFH_RXF_DMA_RB_SIZE_8K; 929 break; 930 case IWL_AMSDU_12K: 931 rb_size = RFH_RXF_DMA_RB_SIZE_12K; 932 break; 933 default: 934 WARN_ON(1); 935 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 936 } 937 938 if (!iwl_trans_grab_nic_access(trans)) 939 return; 940 941 /* Stop Rx DMA */ 942 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 943 /* disable free amd used rx queue operation */ 944 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 945 946 for (i = 0; i < trans->num_rx_queues; i++) { 947 /* Tell device where to find RBD free table in DRAM */ 948 iwl_write_prph64_no_grab(trans, 949 RFH_Q_FRBDCB_BA_LSB(i), 950 trans_pcie->rxq[i].bd_dma); 951 /* Tell device where to find RBD used table in DRAM */ 952 iwl_write_prph64_no_grab(trans, 953 RFH_Q_URBDCB_BA_LSB(i), 954 trans_pcie->rxq[i].used_bd_dma); 955 /* Tell device where in DRAM to update its Rx status */ 956 iwl_write_prph64_no_grab(trans, 957 RFH_Q_URBD_STTS_WPTR_LSB(i), 958 trans_pcie->rxq[i].rb_stts_dma); 959 /* Reset device indice tables */ 960 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 961 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 962 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 963 964 enabled |= BIT(i) | BIT(i + 16); 965 } 966 967 /* 968 * Enable Rx DMA 969 * Rx buffer size 4 or 8k or 12k 970 * Min RB size 4 or 8 971 * Drop frames that exceed RB size 972 * 512 RBDs 973 */ 974 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 975 RFH_DMA_EN_ENABLE_VAL | rb_size | 976 RFH_RXF_DMA_MIN_RB_4_8 | 977 RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 978 RFH_RXF_DMA_RBDCB_SIZE_512); 979 980 /* 981 * Activate DMA snooping. 982 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 983 * Default queue is 0 984 */ 985 iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 986 RFH_GEN_CFG_RFH_DMA_SNOOP | 987 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 988 RFH_GEN_CFG_SERVICE_DMA_SNOOP | 989 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 990 trans->trans_cfg->integrated ? 991 RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 992 RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 993 /* Enable the relevant rx queues */ 994 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 995 996 iwl_trans_release_nic_access(trans); 997 998 /* Set interrupt coalescing timer to default (2048 usecs) */ 999 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1000 } 1001 1002 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 1003 { 1004 lockdep_assert_held(&rxq->lock); 1005 1006 INIT_LIST_HEAD(&rxq->rx_free); 1007 INIT_LIST_HEAD(&rxq->rx_used); 1008 rxq->free_count = 0; 1009 rxq->used_count = 0; 1010 } 1011 1012 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget); 1013 1014 static int iwl_pcie_napi_poll(struct napi_struct *napi, int budget) 1015 { 1016 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 1017 struct iwl_trans_pcie *trans_pcie; 1018 struct iwl_trans *trans; 1019 int ret; 1020 1021 trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 1022 trans = trans_pcie->trans; 1023 1024 ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 1025 1026 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", 1027 rxq->id, ret, budget); 1028 1029 if (ret < budget) { 1030 spin_lock(&trans_pcie->irq_lock); 1031 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1032 _iwl_enable_interrupts(trans); 1033 spin_unlock(&trans_pcie->irq_lock); 1034 1035 napi_complete_done(&rxq->napi, ret); 1036 } 1037 1038 return ret; 1039 } 1040 1041 static int iwl_pcie_napi_poll_msix(struct napi_struct *napi, int budget) 1042 { 1043 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 1044 struct iwl_trans_pcie *trans_pcie; 1045 struct iwl_trans *trans; 1046 int ret; 1047 1048 trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 1049 trans = trans_pcie->trans; 1050 1051 ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 1052 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", rxq->id, ret, 1053 budget); 1054 1055 if (ret < budget) { 1056 int irq_line = rxq->id; 1057 1058 /* FIRST_RSS is shared with line 0 */ 1059 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS && 1060 rxq->id == 1) 1061 irq_line = 0; 1062 1063 spin_lock(&trans_pcie->irq_lock); 1064 iwl_pcie_clear_irq(trans, irq_line); 1065 spin_unlock(&trans_pcie->irq_lock); 1066 1067 napi_complete_done(&rxq->napi, ret); 1068 } 1069 1070 return ret; 1071 } 1072 1073 static int _iwl_pcie_rx_init(struct iwl_trans *trans) 1074 { 1075 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1076 struct iwl_rxq *def_rxq; 1077 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1078 int i, err, queue_size, allocator_pool_size, num_alloc; 1079 1080 if (!trans_pcie->rxq) { 1081 err = iwl_pcie_rx_alloc(trans); 1082 if (err) 1083 return err; 1084 } 1085 def_rxq = trans_pcie->rxq; 1086 1087 cancel_work_sync(&rba->rx_alloc); 1088 1089 spin_lock_bh(&rba->lock); 1090 atomic_set(&rba->req_pending, 0); 1091 atomic_set(&rba->req_ready, 0); 1092 INIT_LIST_HEAD(&rba->rbd_allocated); 1093 INIT_LIST_HEAD(&rba->rbd_empty); 1094 spin_unlock_bh(&rba->lock); 1095 1096 /* free all first - we might be reconfigured for a different size */ 1097 iwl_pcie_free_rbs_pool(trans); 1098 1099 for (i = 0; i < RX_QUEUE_SIZE; i++) 1100 def_rxq->queue[i] = NULL; 1101 1102 for (i = 0; i < trans->num_rx_queues; i++) { 1103 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1104 1105 spin_lock_bh(&rxq->lock); 1106 /* 1107 * Set read write pointer to reflect that we have processed 1108 * and used all buffers, but have not restocked the Rx queue 1109 * with fresh buffers 1110 */ 1111 rxq->read = 0; 1112 rxq->write = 0; 1113 rxq->write_actual = 0; 1114 memset(rxq->rb_stts, 0, 1115 (trans->trans_cfg->device_family >= 1116 IWL_DEVICE_FAMILY_AX210) ? 1117 sizeof(__le16) : sizeof(struct iwl_rb_status)); 1118 1119 iwl_pcie_rx_init_rxb_lists(rxq); 1120 1121 spin_unlock_bh(&rxq->lock); 1122 1123 if (!rxq->napi.poll) { 1124 int (*poll)(struct napi_struct *, int) = iwl_pcie_napi_poll; 1125 1126 if (trans_pcie->msix_enabled) 1127 poll = iwl_pcie_napi_poll_msix; 1128 1129 netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 1130 poll, NAPI_POLL_WEIGHT); 1131 napi_enable(&rxq->napi); 1132 } 1133 1134 } 1135 1136 /* move the pool to the default queue and allocator ownerships */ 1137 queue_size = trans->trans_cfg->mq_rx_supported ? 1138 trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE; 1139 allocator_pool_size = trans->num_rx_queues * 1140 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 1141 num_alloc = queue_size + allocator_pool_size; 1142 1143 for (i = 0; i < num_alloc; i++) { 1144 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 1145 1146 if (i < allocator_pool_size) 1147 list_add(&rxb->list, &rba->rbd_empty); 1148 else 1149 list_add(&rxb->list, &def_rxq->rx_used); 1150 trans_pcie->global_table[i] = rxb; 1151 rxb->vid = (u16)(i + 1); 1152 rxb->invalid = true; 1153 } 1154 1155 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 1156 1157 return 0; 1158 } 1159 1160 int iwl_pcie_rx_init(struct iwl_trans *trans) 1161 { 1162 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1163 int ret = _iwl_pcie_rx_init(trans); 1164 1165 if (ret) 1166 return ret; 1167 1168 if (trans->trans_cfg->mq_rx_supported) 1169 iwl_pcie_rx_mq_hw_init(trans); 1170 else 1171 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 1172 1173 iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 1174 1175 spin_lock_bh(&trans_pcie->rxq->lock); 1176 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 1177 spin_unlock_bh(&trans_pcie->rxq->lock); 1178 1179 return 0; 1180 } 1181 1182 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1183 { 1184 /* Set interrupt coalescing timer to default (2048 usecs) */ 1185 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1186 1187 /* 1188 * We don't configure the RFH. 1189 * Restock will be done at alive, after firmware configured the RFH. 1190 */ 1191 return _iwl_pcie_rx_init(trans); 1192 } 1193 1194 void iwl_pcie_rx_free(struct iwl_trans *trans) 1195 { 1196 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1197 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1198 int i; 1199 size_t rb_stts_size = trans->trans_cfg->device_family >= 1200 IWL_DEVICE_FAMILY_AX210 ? 1201 sizeof(__le16) : sizeof(struct iwl_rb_status); 1202 1203 /* 1204 * if rxq is NULL, it means that nothing has been allocated, 1205 * exit now 1206 */ 1207 if (!trans_pcie->rxq) { 1208 IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1209 return; 1210 } 1211 1212 cancel_work_sync(&rba->rx_alloc); 1213 1214 iwl_pcie_free_rbs_pool(trans); 1215 1216 if (trans_pcie->base_rb_stts) { 1217 dma_free_coherent(trans->dev, 1218 rb_stts_size * trans->num_rx_queues, 1219 trans_pcie->base_rb_stts, 1220 trans_pcie->base_rb_stts_dma); 1221 trans_pcie->base_rb_stts = NULL; 1222 trans_pcie->base_rb_stts_dma = 0; 1223 } 1224 1225 for (i = 0; i < trans->num_rx_queues; i++) { 1226 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1227 1228 iwl_pcie_free_rxq_dma(trans, rxq); 1229 1230 if (rxq->napi.poll) { 1231 napi_disable(&rxq->napi); 1232 netif_napi_del(&rxq->napi); 1233 } 1234 } 1235 kfree(trans_pcie->rx_pool); 1236 kfree(trans_pcie->global_table); 1237 kfree(trans_pcie->rxq); 1238 1239 if (trans_pcie->alloc_page) 1240 __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order); 1241 } 1242 1243 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq, 1244 struct iwl_rb_allocator *rba) 1245 { 1246 spin_lock(&rba->lock); 1247 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1248 spin_unlock(&rba->lock); 1249 } 1250 1251 /* 1252 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1253 * 1254 * Called when a RBD can be reused. The RBD is transferred to the allocator. 1255 * When there are 2 empty RBDs - a request for allocation is posted 1256 */ 1257 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1258 struct iwl_rx_mem_buffer *rxb, 1259 struct iwl_rxq *rxq, bool emergency) 1260 { 1261 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1262 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1263 1264 /* Move the RBD to the used list, will be moved to allocator in batches 1265 * before claiming or posting a request*/ 1266 list_add_tail(&rxb->list, &rxq->rx_used); 1267 1268 if (unlikely(emergency)) 1269 return; 1270 1271 /* Count the allocator owned RBDs */ 1272 rxq->used_count++; 1273 1274 /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1275 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1276 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1277 * after but we still need to post another request. 1278 */ 1279 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1280 /* Move the 2 RBDs to the allocator ownership. 1281 Allocator has another 6 from pool for the request completion*/ 1282 iwl_pcie_rx_move_to_allocator(rxq, rba); 1283 1284 atomic_inc(&rba->req_pending); 1285 queue_work(rba->alloc_wq, &rba->rx_alloc); 1286 } 1287 } 1288 1289 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 1290 struct iwl_rxq *rxq, 1291 struct iwl_rx_mem_buffer *rxb, 1292 bool emergency, 1293 int i) 1294 { 1295 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1296 struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id]; 1297 bool page_stolen = false; 1298 int max_len = trans_pcie->rx_buf_bytes; 1299 u32 offset = 0; 1300 1301 if (WARN_ON(!rxb)) 1302 return; 1303 1304 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1305 1306 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1307 struct iwl_rx_packet *pkt; 1308 bool reclaim; 1309 int len; 1310 struct iwl_rx_cmd_buffer rxcb = { 1311 ._offset = rxb->offset + offset, 1312 ._rx_page_order = trans_pcie->rx_page_order, 1313 ._page = rxb->page, 1314 ._page_stolen = false, 1315 .truesize = max_len, 1316 }; 1317 1318 pkt = rxb_addr(&rxcb); 1319 1320 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 1321 IWL_DEBUG_RX(trans, 1322 "Q %d: RB end marker at offset %d\n", 1323 rxq->id, offset); 1324 break; 1325 } 1326 1327 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1328 FH_RSCSR_RXQ_POS != rxq->id, 1329 "frame on invalid queue - is on %d and indicates %d\n", 1330 rxq->id, 1331 (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1332 FH_RSCSR_RXQ_POS); 1333 1334 IWL_DEBUG_RX(trans, 1335 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 1336 rxq->id, offset, 1337 iwl_get_cmd_string(trans, 1338 iwl_cmd_id(pkt->hdr.cmd, 1339 pkt->hdr.group_id, 1340 0)), 1341 pkt->hdr.group_id, pkt->hdr.cmd, 1342 le16_to_cpu(pkt->hdr.sequence)); 1343 1344 len = iwl_rx_packet_len(pkt); 1345 len += sizeof(u32); /* account for status word */ 1346 1347 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1348 1349 /* check that what the device tells us made sense */ 1350 if (offset > max_len) 1351 break; 1352 1353 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1354 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1355 1356 /* Reclaim a command buffer only if this packet is a response 1357 * to a (driver-originated) command. 1358 * If the packet (e.g. Rx frame) originated from uCode, 1359 * there is no command buffer to reclaim. 1360 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1361 * but apparently a few don't get set; catch them here. */ 1362 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1363 if (reclaim && !pkt->hdr.group_id) { 1364 int i; 1365 1366 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1367 if (trans_pcie->no_reclaim_cmds[i] == 1368 pkt->hdr.cmd) { 1369 reclaim = false; 1370 break; 1371 } 1372 } 1373 } 1374 1375 if (rxq->id == trans_pcie->def_rx_queue) 1376 iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1377 &rxcb); 1378 else 1379 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1380 &rxcb, rxq->id); 1381 1382 /* 1383 * After here, we should always check rxcb._page_stolen, 1384 * if it is true then one of the handlers took the page. 1385 */ 1386 1387 if (reclaim) { 1388 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1389 int index = SEQ_TO_INDEX(sequence); 1390 int cmd_index = iwl_txq_get_cmd_index(txq, index); 1391 1392 kfree_sensitive(txq->entries[cmd_index].free_buf); 1393 txq->entries[cmd_index].free_buf = NULL; 1394 1395 /* Invoke any callbacks, transfer the buffer to caller, 1396 * and fire off the (possibly) blocking 1397 * iwl_trans_send_cmd() 1398 * as we reclaim the driver command queue */ 1399 if (!rxcb._page_stolen) 1400 iwl_pcie_hcmd_complete(trans, &rxcb); 1401 else 1402 IWL_WARN(trans, "Claim null rxb?\n"); 1403 } 1404 1405 page_stolen |= rxcb._page_stolen; 1406 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1407 break; 1408 } 1409 1410 /* page was stolen from us -- free our reference */ 1411 if (page_stolen) { 1412 __free_pages(rxb->page, trans_pcie->rx_page_order); 1413 rxb->page = NULL; 1414 } 1415 1416 /* Reuse the page if possible. For notification packets and 1417 * SKBs that fail to Rx correctly, add them back into the 1418 * rx_free list for reuse later. */ 1419 if (rxb->page != NULL) { 1420 rxb->page_dma = 1421 dma_map_page(trans->dev, rxb->page, rxb->offset, 1422 trans_pcie->rx_buf_bytes, 1423 DMA_FROM_DEVICE); 1424 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1425 /* 1426 * free the page(s) as well to not break 1427 * the invariant that the items on the used 1428 * list have no page(s) 1429 */ 1430 __free_pages(rxb->page, trans_pcie->rx_page_order); 1431 rxb->page = NULL; 1432 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1433 } else { 1434 list_add_tail(&rxb->list, &rxq->rx_free); 1435 rxq->free_count++; 1436 } 1437 } else 1438 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1439 } 1440 1441 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans, 1442 struct iwl_rxq *rxq, int i, 1443 bool *join) 1444 { 1445 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1446 struct iwl_rx_mem_buffer *rxb; 1447 u16 vid; 1448 1449 BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32); 1450 1451 if (!trans->trans_cfg->mq_rx_supported) { 1452 rxb = rxq->queue[i]; 1453 rxq->queue[i] = NULL; 1454 return rxb; 1455 } 1456 1457 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1458 vid = le16_to_cpu(rxq->cd[i].rbid); 1459 *join = rxq->cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED; 1460 } else { 1461 vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; /* 12-bit VID */ 1462 } 1463 1464 if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs)) 1465 goto out_err; 1466 1467 rxb = trans_pcie->global_table[vid - 1]; 1468 if (rxb->invalid) 1469 goto out_err; 1470 1471 IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid); 1472 1473 rxb->invalid = true; 1474 1475 return rxb; 1476 1477 out_err: 1478 WARN(1, "Invalid rxb from HW %u\n", (u32)vid); 1479 iwl_force_nmi(trans); 1480 return NULL; 1481 } 1482 1483 /* 1484 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1485 */ 1486 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget) 1487 { 1488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1489 struct iwl_rxq *rxq; 1490 u32 r, i, count = 0, handled = 0; 1491 bool emergency = false; 1492 1493 if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd)) 1494 return budget; 1495 1496 rxq = &trans_pcie->rxq[queue]; 1497 1498 restart: 1499 spin_lock(&rxq->lock); 1500 /* uCode's read index (stored in shared DRAM) indicates the last Rx 1501 * buffer that the driver may process (last buffer filled by ucode). */ 1502 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1503 i = rxq->read; 1504 1505 /* W/A 9000 device step A0 wrap-around bug */ 1506 r &= (rxq->queue_size - 1); 1507 1508 /* Rx interrupt, but nothing sent from uCode */ 1509 if (i == r) 1510 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1511 1512 while (i != r && ++handled < budget) { 1513 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1514 struct iwl_rx_mem_buffer *rxb; 1515 /* number of RBDs still waiting for page allocation */ 1516 u32 rb_pending_alloc = 1517 atomic_read(&trans_pcie->rba.req_pending) * 1518 RX_CLAIM_REQ_ALLOC; 1519 bool join = false; 1520 1521 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 && 1522 !emergency)) { 1523 iwl_pcie_rx_move_to_allocator(rxq, rba); 1524 emergency = true; 1525 IWL_DEBUG_TPT(trans, 1526 "RX path is in emergency. Pending allocations %d\n", 1527 rb_pending_alloc); 1528 } 1529 1530 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 1531 1532 rxb = iwl_pcie_get_rxb(trans, rxq, i, &join); 1533 if (!rxb) 1534 goto out; 1535 1536 if (unlikely(join || rxq->next_rb_is_fragment)) { 1537 rxq->next_rb_is_fragment = join; 1538 /* 1539 * We can only get a multi-RB in the following cases: 1540 * - firmware issue, sending a too big notification 1541 * - sniffer mode with a large A-MSDU 1542 * - large MTU frames (>2k) 1543 * since the multi-RB functionality is limited to newer 1544 * hardware that cannot put multiple entries into a 1545 * single RB. 1546 * 1547 * Right now, the higher layers aren't set up to deal 1548 * with that, so discard all of these. 1549 */ 1550 list_add_tail(&rxb->list, &rxq->rx_free); 1551 rxq->free_count++; 1552 } else { 1553 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i); 1554 } 1555 1556 i = (i + 1) & (rxq->queue_size - 1); 1557 1558 /* 1559 * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1560 * try to claim the pre-allocated buffers from the allocator. 1561 * If not ready - will try to reclaim next time. 1562 * There is no need to reschedule work - allocator exits only 1563 * on success 1564 */ 1565 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1566 iwl_pcie_rx_allocator_get(trans, rxq); 1567 1568 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1569 /* Add the remaining empty RBDs for allocator use */ 1570 iwl_pcie_rx_move_to_allocator(rxq, rba); 1571 } else if (emergency) { 1572 count++; 1573 if (count == 8) { 1574 count = 0; 1575 if (rb_pending_alloc < rxq->queue_size / 3) { 1576 IWL_DEBUG_TPT(trans, 1577 "RX path exited emergency. Pending allocations %d\n", 1578 rb_pending_alloc); 1579 emergency = false; 1580 } 1581 1582 rxq->read = i; 1583 spin_unlock(&rxq->lock); 1584 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1585 iwl_pcie_rxq_restock(trans, rxq); 1586 goto restart; 1587 } 1588 } 1589 } 1590 out: 1591 /* Backtrack one entry */ 1592 rxq->read = i; 1593 /* update cr tail with the rxq read pointer */ 1594 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1595 *rxq->cr_tail = cpu_to_le16(r); 1596 spin_unlock(&rxq->lock); 1597 1598 /* 1599 * handle a case where in emergency there are some unallocated RBDs. 1600 * those RBDs are in the used list, but are not tracked by the queue's 1601 * used_count which counts allocator owned RBDs. 1602 * unallocated emergency RBDs must be allocated on exit, otherwise 1603 * when called again the function may not be in emergency mode and 1604 * they will be handed to the allocator with no tracking in the RBD 1605 * allocator counters, which will lead to them never being claimed back 1606 * by the queue. 1607 * by allocating them here, they are now in the queue free list, and 1608 * will be restocked by the next call of iwl_pcie_rxq_restock. 1609 */ 1610 if (unlikely(emergency && count)) 1611 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1612 1613 iwl_pcie_rxq_restock(trans, rxq); 1614 1615 return handled; 1616 } 1617 1618 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 1619 { 1620 u8 queue = entry->entry; 1621 struct msix_entry *entries = entry - queue; 1622 1623 return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 1624 } 1625 1626 /* 1627 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 1628 * This interrupt handler should be used with RSS queue only. 1629 */ 1630 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 1631 { 1632 struct msix_entry *entry = dev_id; 1633 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 1634 struct iwl_trans *trans = trans_pcie->trans; 1635 struct iwl_rxq *rxq = &trans_pcie->rxq[entry->entry]; 1636 1637 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1638 1639 if (WARN_ON(entry->entry >= trans->num_rx_queues)) 1640 return IRQ_NONE; 1641 1642 if (WARN_ONCE(!rxq, 1643 "[%d] Got MSI-X interrupt before we have Rx queues", 1644 entry->entry)) 1645 return IRQ_NONE; 1646 1647 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1648 IWL_DEBUG_ISR(trans, "[%d] Got interrupt\n", entry->entry); 1649 1650 local_bh_disable(); 1651 if (napi_schedule_prep(&rxq->napi)) 1652 __napi_schedule(&rxq->napi); 1653 else 1654 iwl_pcie_clear_irq(trans, entry->entry); 1655 local_bh_enable(); 1656 1657 lock_map_release(&trans->sync_cmd_lockdep_map); 1658 1659 return IRQ_HANDLED; 1660 } 1661 1662 /* 1663 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1664 */ 1665 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1666 { 1667 int i; 1668 1669 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1670 if (trans->cfg->internal_wimax_coex && 1671 !trans->cfg->apmg_not_supported && 1672 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1673 APMS_CLK_VAL_MRB_FUNC_MODE) || 1674 (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1675 APMG_PS_CTRL_VAL_RESET_REQ))) { 1676 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1677 iwl_op_mode_wimax_active(trans->op_mode); 1678 wake_up(&trans->wait_command_queue); 1679 return; 1680 } 1681 1682 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 1683 if (!trans->txqs.txq[i]) 1684 continue; 1685 del_timer(&trans->txqs.txq[i]->stuck_timer); 1686 } 1687 1688 /* The STATUS_FW_ERROR bit is set in this function. This must happen 1689 * before we wake up the command caller, to ensure a proper cleanup. */ 1690 iwl_trans_fw_error(trans); 1691 1692 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1693 wake_up(&trans->wait_command_queue); 1694 } 1695 1696 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1697 { 1698 u32 inta; 1699 1700 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1701 1702 trace_iwlwifi_dev_irq(trans->dev); 1703 1704 /* Discover which interrupts are active/pending */ 1705 inta = iwl_read32(trans, CSR_INT); 1706 1707 /* the thread will service interrupts and re-enable them */ 1708 return inta; 1709 } 1710 1711 /* a device (PCI-E) page is 4096 bytes long */ 1712 #define ICT_SHIFT 12 1713 #define ICT_SIZE (1 << ICT_SHIFT) 1714 #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1715 1716 /* interrupt handler using ict table, with this interrupt driver will 1717 * stop using INTA register to get device's interrupt, reading this register 1718 * is expensive, device will write interrupts in ICT dram table, increment 1719 * index then will fire interrupt to driver, driver will OR all ICT table 1720 * entries from current index up to table entry with 0 value. the result is 1721 * the interrupt we need to service, driver will set the entries back to 0 and 1722 * set index. 1723 */ 1724 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1725 { 1726 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1727 u32 inta; 1728 u32 val = 0; 1729 u32 read; 1730 1731 trace_iwlwifi_dev_irq(trans->dev); 1732 1733 /* Ignore interrupt if there's nothing in NIC to service. 1734 * This may be due to IRQ shared with another device, 1735 * or due to sporadic interrupts thrown from our NIC. */ 1736 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1737 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1738 if (!read) 1739 return 0; 1740 1741 /* 1742 * Collect all entries up to the first 0, starting from ict_index; 1743 * note we already read at ict_index. 1744 */ 1745 do { 1746 val |= read; 1747 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1748 trans_pcie->ict_index, read); 1749 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1750 trans_pcie->ict_index = 1751 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1752 1753 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1754 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1755 read); 1756 } while (read); 1757 1758 /* We should not get this value, just ignore it. */ 1759 if (val == 0xffffffff) 1760 val = 0; 1761 1762 /* 1763 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1764 * (bit 15 before shifting it to 31) to clear when using interrupt 1765 * coalescing. fortunately, bits 18 and 19 stay set when this happens 1766 * so we use them to decide on the real state of the Rx bit. 1767 * In order words, bit 15 is set if bit 18 or bit 19 are set. 1768 */ 1769 if (val & 0xC0000) 1770 val |= 0x8000; 1771 1772 inta = (0xff & val) | ((0xff00 & val) << 16); 1773 return inta; 1774 } 1775 1776 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 1777 { 1778 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1779 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1780 bool hw_rfkill, prev, report; 1781 1782 mutex_lock(&trans_pcie->mutex); 1783 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1784 hw_rfkill = iwl_is_rfkill_set(trans); 1785 if (hw_rfkill) { 1786 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1787 set_bit(STATUS_RFKILL_HW, &trans->status); 1788 } 1789 if (trans_pcie->opmode_down) 1790 report = hw_rfkill; 1791 else 1792 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1793 1794 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 1795 hw_rfkill ? "disable radio" : "enable radio"); 1796 1797 isr_stats->rfkill++; 1798 1799 if (prev != report) 1800 iwl_trans_pcie_rf_kill(trans, report); 1801 mutex_unlock(&trans_pcie->mutex); 1802 1803 if (hw_rfkill) { 1804 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 1805 &trans->status)) 1806 IWL_DEBUG_RF_KILL(trans, 1807 "Rfkill while SYNC HCMD in flight\n"); 1808 wake_up(&trans->wait_command_queue); 1809 } else { 1810 clear_bit(STATUS_RFKILL_HW, &trans->status); 1811 if (trans_pcie->opmode_down) 1812 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1813 } 1814 } 1815 1816 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1817 { 1818 struct iwl_trans *trans = dev_id; 1819 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1820 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1821 u32 inta = 0; 1822 u32 handled = 0; 1823 bool polling = false; 1824 1825 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1826 1827 spin_lock_bh(&trans_pcie->irq_lock); 1828 1829 /* dram interrupt table not set yet, 1830 * use legacy interrupt. 1831 */ 1832 if (likely(trans_pcie->use_ict)) 1833 inta = iwl_pcie_int_cause_ict(trans); 1834 else 1835 inta = iwl_pcie_int_cause_non_ict(trans); 1836 1837 if (iwl_have_debug_level(IWL_DL_ISR)) { 1838 IWL_DEBUG_ISR(trans, 1839 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1840 inta, trans_pcie->inta_mask, 1841 iwl_read32(trans, CSR_INT_MASK), 1842 iwl_read32(trans, CSR_FH_INT_STATUS)); 1843 if (inta & (~trans_pcie->inta_mask)) 1844 IWL_DEBUG_ISR(trans, 1845 "We got a masked interrupt (0x%08x)\n", 1846 inta & (~trans_pcie->inta_mask)); 1847 } 1848 1849 inta &= trans_pcie->inta_mask; 1850 1851 /* 1852 * Ignore interrupt if there's nothing in NIC to service. 1853 * This may be due to IRQ shared with another device, 1854 * or due to sporadic interrupts thrown from our NIC. 1855 */ 1856 if (unlikely(!inta)) { 1857 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1858 /* 1859 * Re-enable interrupts here since we don't 1860 * have anything to service 1861 */ 1862 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1863 _iwl_enable_interrupts(trans); 1864 spin_unlock_bh(&trans_pcie->irq_lock); 1865 lock_map_release(&trans->sync_cmd_lockdep_map); 1866 return IRQ_NONE; 1867 } 1868 1869 if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1870 /* 1871 * Hardware disappeared. It might have 1872 * already raised an interrupt. 1873 */ 1874 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1875 spin_unlock_bh(&trans_pcie->irq_lock); 1876 goto out; 1877 } 1878 1879 /* Ack/clear/reset pending uCode interrupts. 1880 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1881 */ 1882 /* There is a hardware bug in the interrupt mask function that some 1883 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1884 * they are disabled in the CSR_INT_MASK register. Furthermore the 1885 * ICT interrupt handling mechanism has another bug that might cause 1886 * these unmasked interrupts fail to be detected. We workaround the 1887 * hardware bugs here by ACKing all the possible interrupts so that 1888 * interrupt coalescing can still be achieved. 1889 */ 1890 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1891 1892 if (iwl_have_debug_level(IWL_DL_ISR)) 1893 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1894 inta, iwl_read32(trans, CSR_INT_MASK)); 1895 1896 spin_unlock_bh(&trans_pcie->irq_lock); 1897 1898 /* Now service all interrupt bits discovered above. */ 1899 if (inta & CSR_INT_BIT_HW_ERR) { 1900 IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1901 1902 /* Tell the device to stop sending interrupts */ 1903 iwl_disable_interrupts(trans); 1904 1905 isr_stats->hw++; 1906 iwl_pcie_irq_handle_error(trans); 1907 1908 handled |= CSR_INT_BIT_HW_ERR; 1909 1910 goto out; 1911 } 1912 1913 /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1914 if (inta & CSR_INT_BIT_SCD) { 1915 IWL_DEBUG_ISR(trans, 1916 "Scheduler finished to transmit the frame/frames.\n"); 1917 isr_stats->sch++; 1918 } 1919 1920 /* Alive notification via Rx interrupt will do the real work */ 1921 if (inta & CSR_INT_BIT_ALIVE) { 1922 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1923 isr_stats->alive++; 1924 if (trans->trans_cfg->gen2) { 1925 /* 1926 * We can restock, since firmware configured 1927 * the RFH 1928 */ 1929 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1930 } 1931 1932 handled |= CSR_INT_BIT_ALIVE; 1933 } 1934 1935 /* Safely ignore these bits for debug checks below */ 1936 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1937 1938 /* HW RF KILL switch toggled */ 1939 if (inta & CSR_INT_BIT_RF_KILL) { 1940 iwl_pcie_handle_rfkill_irq(trans); 1941 handled |= CSR_INT_BIT_RF_KILL; 1942 } 1943 1944 /* Chip got too hot and stopped itself */ 1945 if (inta & CSR_INT_BIT_CT_KILL) { 1946 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1947 isr_stats->ctkill++; 1948 handled |= CSR_INT_BIT_CT_KILL; 1949 } 1950 1951 /* Error detected by uCode */ 1952 if (inta & CSR_INT_BIT_SW_ERR) { 1953 IWL_ERR(trans, "Microcode SW error detected. " 1954 " Restarting 0x%X.\n", inta); 1955 isr_stats->sw++; 1956 iwl_pcie_irq_handle_error(trans); 1957 handled |= CSR_INT_BIT_SW_ERR; 1958 } 1959 1960 /* uCode wakes up after power-down sleep */ 1961 if (inta & CSR_INT_BIT_WAKEUP) { 1962 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1963 iwl_pcie_rxq_check_wrptr(trans); 1964 iwl_pcie_txq_check_wrptrs(trans); 1965 1966 isr_stats->wakeup++; 1967 1968 handled |= CSR_INT_BIT_WAKEUP; 1969 } 1970 1971 /* All uCode command responses, including Tx command responses, 1972 * Rx "responses" (frame-received notification), and other 1973 * notifications from uCode come through here*/ 1974 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1975 CSR_INT_BIT_RX_PERIODIC)) { 1976 IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1977 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1978 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1979 iwl_write32(trans, CSR_FH_INT_STATUS, 1980 CSR_FH_INT_RX_MASK); 1981 } 1982 if (inta & CSR_INT_BIT_RX_PERIODIC) { 1983 handled |= CSR_INT_BIT_RX_PERIODIC; 1984 iwl_write32(trans, 1985 CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1986 } 1987 /* Sending RX interrupt require many steps to be done in the 1988 * the device: 1989 * 1- write interrupt to current index in ICT table. 1990 * 2- dma RX frame. 1991 * 3- update RX shared data to indicate last write index. 1992 * 4- send interrupt. 1993 * This could lead to RX race, driver could receive RX interrupt 1994 * but the shared data changes does not reflect this; 1995 * periodic interrupt will detect any dangling Rx activity. 1996 */ 1997 1998 /* Disable periodic interrupt; we use it as just a one-shot. */ 1999 iwl_write8(trans, CSR_INT_PERIODIC_REG, 2000 CSR_INT_PERIODIC_DIS); 2001 2002 /* 2003 * Enable periodic interrupt in 8 msec only if we received 2004 * real RX interrupt (instead of just periodic int), to catch 2005 * any dangling Rx interrupt. If it was just the periodic 2006 * interrupt, there was no dangling Rx activity, and no need 2007 * to extend the periodic interrupt; one-shot is enough. 2008 */ 2009 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 2010 iwl_write8(trans, CSR_INT_PERIODIC_REG, 2011 CSR_INT_PERIODIC_ENA); 2012 2013 isr_stats->rx++; 2014 2015 local_bh_disable(); 2016 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 2017 polling = true; 2018 __napi_schedule(&trans_pcie->rxq[0].napi); 2019 } 2020 local_bh_enable(); 2021 } 2022 2023 /* This "Tx" DMA channel is used only for loading uCode */ 2024 if (inta & CSR_INT_BIT_FH_TX) { 2025 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 2026 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 2027 isr_stats->tx++; 2028 handled |= CSR_INT_BIT_FH_TX; 2029 /* Wake up uCode load routine, now that load is complete */ 2030 trans_pcie->ucode_write_complete = true; 2031 wake_up(&trans_pcie->ucode_write_waitq); 2032 } 2033 2034 if (inta & ~handled) { 2035 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 2036 isr_stats->unhandled++; 2037 } 2038 2039 if (inta & ~(trans_pcie->inta_mask)) { 2040 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 2041 inta & ~trans_pcie->inta_mask); 2042 } 2043 2044 if (!polling) { 2045 spin_lock_bh(&trans_pcie->irq_lock); 2046 /* only Re-enable all interrupt if disabled by irq */ 2047 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 2048 _iwl_enable_interrupts(trans); 2049 /* we are loading the firmware, enable FH_TX interrupt only */ 2050 else if (handled & CSR_INT_BIT_FH_TX) 2051 iwl_enable_fw_load_int(trans); 2052 /* Re-enable RF_KILL if it occurred */ 2053 else if (handled & CSR_INT_BIT_RF_KILL) 2054 iwl_enable_rfkill_int(trans); 2055 /* Re-enable the ALIVE / Rx interrupt if it occurred */ 2056 else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX)) 2057 iwl_enable_fw_load_int_ctx_info(trans); 2058 spin_unlock_bh(&trans_pcie->irq_lock); 2059 } 2060 2061 out: 2062 lock_map_release(&trans->sync_cmd_lockdep_map); 2063 return IRQ_HANDLED; 2064 } 2065 2066 /****************************************************************************** 2067 * 2068 * ICT functions 2069 * 2070 ******************************************************************************/ 2071 2072 /* Free dram table */ 2073 void iwl_pcie_free_ict(struct iwl_trans *trans) 2074 { 2075 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2076 2077 if (trans_pcie->ict_tbl) { 2078 dma_free_coherent(trans->dev, ICT_SIZE, 2079 trans_pcie->ict_tbl, 2080 trans_pcie->ict_tbl_dma); 2081 trans_pcie->ict_tbl = NULL; 2082 trans_pcie->ict_tbl_dma = 0; 2083 } 2084 } 2085 2086 /* 2087 * allocate dram shared table, it is an aligned memory 2088 * block of ICT_SIZE. 2089 * also reset all data related to ICT table interrupt. 2090 */ 2091 int iwl_pcie_alloc_ict(struct iwl_trans *trans) 2092 { 2093 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2094 2095 trans_pcie->ict_tbl = 2096 dma_alloc_coherent(trans->dev, ICT_SIZE, 2097 &trans_pcie->ict_tbl_dma, GFP_KERNEL); 2098 if (!trans_pcie->ict_tbl) 2099 return -ENOMEM; 2100 2101 /* just an API sanity check ... it is guaranteed to be aligned */ 2102 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 2103 iwl_pcie_free_ict(trans); 2104 return -EINVAL; 2105 } 2106 2107 return 0; 2108 } 2109 2110 /* Device is going up inform it about using ICT interrupt table, 2111 * also we need to tell the driver to start using ICT interrupt. 2112 */ 2113 void iwl_pcie_reset_ict(struct iwl_trans *trans) 2114 { 2115 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2116 u32 val; 2117 2118 if (!trans_pcie->ict_tbl) 2119 return; 2120 2121 spin_lock_bh(&trans_pcie->irq_lock); 2122 _iwl_disable_interrupts(trans); 2123 2124 memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 2125 2126 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 2127 2128 val |= CSR_DRAM_INT_TBL_ENABLE | 2129 CSR_DRAM_INIT_TBL_WRAP_CHECK | 2130 CSR_DRAM_INIT_TBL_WRITE_POINTER; 2131 2132 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 2133 2134 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 2135 trans_pcie->use_ict = true; 2136 trans_pcie->ict_index = 0; 2137 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 2138 _iwl_enable_interrupts(trans); 2139 spin_unlock_bh(&trans_pcie->irq_lock); 2140 } 2141 2142 /* Device is going down disable ict interrupt usage */ 2143 void iwl_pcie_disable_ict(struct iwl_trans *trans) 2144 { 2145 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2146 2147 spin_lock_bh(&trans_pcie->irq_lock); 2148 trans_pcie->use_ict = false; 2149 spin_unlock_bh(&trans_pcie->irq_lock); 2150 } 2151 2152 irqreturn_t iwl_pcie_isr(int irq, void *data) 2153 { 2154 struct iwl_trans *trans = data; 2155 2156 if (!trans) 2157 return IRQ_NONE; 2158 2159 /* Disable (but don't clear!) interrupts here to avoid 2160 * back-to-back ISRs and sporadic interrupts from our NIC. 2161 * If we have something to service, the tasklet will re-enable ints. 2162 * If we *don't* have something, we'll re-enable before leaving here. 2163 */ 2164 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2165 2166 return IRQ_WAKE_THREAD; 2167 } 2168 2169 irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 2170 { 2171 return IRQ_WAKE_THREAD; 2172 } 2173 2174 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 2175 { 2176 struct msix_entry *entry = dev_id; 2177 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 2178 struct iwl_trans *trans = trans_pcie->trans; 2179 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2180 u32 inta_fh_msk = ~MSIX_FH_INT_CAUSES_DATA_QUEUE; 2181 u32 inta_fh, inta_hw; 2182 bool polling = false; 2183 2184 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 2185 inta_fh_msk |= MSIX_FH_INT_CAUSES_Q0; 2186 2187 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 2188 inta_fh_msk |= MSIX_FH_INT_CAUSES_Q1; 2189 2190 lock_map_acquire(&trans->sync_cmd_lockdep_map); 2191 2192 spin_lock_bh(&trans_pcie->irq_lock); 2193 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 2194 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 2195 /* 2196 * Clear causes registers to avoid being handling the same cause. 2197 */ 2198 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk); 2199 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 2200 spin_unlock_bh(&trans_pcie->irq_lock); 2201 2202 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2203 2204 if (unlikely(!(inta_fh | inta_hw))) { 2205 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 2206 lock_map_release(&trans->sync_cmd_lockdep_map); 2207 return IRQ_NONE; 2208 } 2209 2210 if (iwl_have_debug_level(IWL_DL_ISR)) { 2211 IWL_DEBUG_ISR(trans, 2212 "ISR[%d] inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 2213 entry->entry, inta_fh, trans_pcie->fh_mask, 2214 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 2215 if (inta_fh & ~trans_pcie->fh_mask) 2216 IWL_DEBUG_ISR(trans, 2217 "We got a masked interrupt (0x%08x)\n", 2218 inta_fh & ~trans_pcie->fh_mask); 2219 } 2220 2221 inta_fh &= trans_pcie->fh_mask; 2222 2223 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2224 inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2225 local_bh_disable(); 2226 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 2227 polling = true; 2228 __napi_schedule(&trans_pcie->rxq[0].napi); 2229 } 2230 local_bh_enable(); 2231 } 2232 2233 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2234 inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2235 local_bh_disable(); 2236 if (napi_schedule_prep(&trans_pcie->rxq[1].napi)) { 2237 polling = true; 2238 __napi_schedule(&trans_pcie->rxq[1].napi); 2239 } 2240 local_bh_enable(); 2241 } 2242 2243 /* This "Tx" DMA channel is used only for loading uCode */ 2244 if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 2245 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 2246 isr_stats->tx++; 2247 /* 2248 * Wake up uCode load routine, 2249 * now that load is complete 2250 */ 2251 trans_pcie->ucode_write_complete = true; 2252 wake_up(&trans_pcie->ucode_write_waitq); 2253 } 2254 2255 /* Error detected by uCode */ 2256 if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 2257 (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) { 2258 IWL_ERR(trans, 2259 "Microcode SW error detected. Restarting 0x%X.\n", 2260 inta_fh); 2261 isr_stats->sw++; 2262 iwl_pcie_irq_handle_error(trans); 2263 } 2264 2265 /* After checking FH register check HW register */ 2266 if (iwl_have_debug_level(IWL_DL_ISR)) { 2267 IWL_DEBUG_ISR(trans, 2268 "ISR[%d] inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 2269 entry->entry, inta_hw, trans_pcie->hw_mask, 2270 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 2271 if (inta_hw & ~trans_pcie->hw_mask) 2272 IWL_DEBUG_ISR(trans, 2273 "We got a masked interrupt 0x%08x\n", 2274 inta_hw & ~trans_pcie->hw_mask); 2275 } 2276 2277 inta_hw &= trans_pcie->hw_mask; 2278 2279 /* Alive notification via Rx interrupt will do the real work */ 2280 if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 2281 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 2282 isr_stats->alive++; 2283 if (trans->trans_cfg->gen2) { 2284 /* We can restock, since firmware configured the RFH */ 2285 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2286 } 2287 } 2288 2289 if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 2290 u32 sleep_notif = 2291 le32_to_cpu(trans_pcie->prph_info->sleep_notif); 2292 if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND || 2293 sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) { 2294 IWL_DEBUG_ISR(trans, 2295 "Sx interrupt: sleep notification = 0x%x\n", 2296 sleep_notif); 2297 trans_pcie->sx_complete = true; 2298 wake_up(&trans_pcie->sx_waitq); 2299 } else { 2300 /* uCode wakes up after power-down sleep */ 2301 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 2302 iwl_pcie_rxq_check_wrptr(trans); 2303 iwl_pcie_txq_check_wrptrs(trans); 2304 2305 isr_stats->wakeup++; 2306 } 2307 } 2308 2309 /* Chip got too hot and stopped itself */ 2310 if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 2311 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 2312 isr_stats->ctkill++; 2313 } 2314 2315 /* HW RF KILL switch toggled */ 2316 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 2317 iwl_pcie_handle_rfkill_irq(trans); 2318 2319 if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 2320 IWL_ERR(trans, 2321 "Hardware error detected. Restarting.\n"); 2322 2323 isr_stats->hw++; 2324 trans->dbg.hw_error = true; 2325 iwl_pcie_irq_handle_error(trans); 2326 } 2327 2328 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE) { 2329 IWL_DEBUG_ISR(trans, "Reset flow completed\n"); 2330 trans_pcie->fw_reset_done = true; 2331 wake_up(&trans_pcie->fw_reset_waitq); 2332 } 2333 2334 if (!polling) 2335 iwl_pcie_clear_irq(trans, entry->entry); 2336 2337 lock_map_release(&trans->sync_cmd_lockdep_map); 2338 2339 return IRQ_HANDLED; 2340 } 2341