1 /****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6 * Copyright(c) 2018 Intel Corporation 7 * 8 * Portions of this file are derived from the ipw3945 project, as well 9 * as portions of the ieee80211 subsystem header files. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * You should have received a copy of the GNU General Public License along with 21 * this program; if not, write to the Free Software Foundation, Inc., 22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 23 * 24 * The full GNU General Public License is included in this distribution in the 25 * file called LICENSE. 26 * 27 * Contact Information: 28 * Intel Linux Wireless <linuxwifi@intel.com> 29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 30 * 31 *****************************************************************************/ 32 #include <linux/sched.h> 33 #include <linux/wait.h> 34 #include <linux/gfp.h> 35 36 #include "iwl-prph.h" 37 #include "iwl-io.h" 38 #include "internal.h" 39 #include "iwl-op-mode.h" 40 41 /****************************************************************************** 42 * 43 * RX path functions 44 * 45 ******************************************************************************/ 46 47 /* 48 * Rx theory of operation 49 * 50 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 51 * each of which point to Receive Buffers to be filled by the NIC. These get 52 * used not only for Rx frames, but for any command response or notification 53 * from the NIC. The driver and NIC manage the Rx buffers by means 54 * of indexes into the circular buffer. 55 * 56 * Rx Queue Indexes 57 * The host/firmware share two index registers for managing the Rx buffers. 58 * 59 * The READ index maps to the first position that the firmware may be writing 60 * to -- the driver can read up to (but not including) this position and get 61 * good data. 62 * The READ index is managed by the firmware once the card is enabled. 63 * 64 * The WRITE index maps to the last position the driver has read from -- the 65 * position preceding WRITE is the last slot the firmware can place a packet. 66 * 67 * The queue is empty (no good data) if WRITE = READ - 1, and is full if 68 * WRITE = READ. 69 * 70 * During initialization, the host sets up the READ queue position to the first 71 * INDEX position, and WRITE to the last (READ - 1 wrapped) 72 * 73 * When the firmware places a packet in a buffer, it will advance the READ index 74 * and fire the RX interrupt. The driver can then query the READ index and 75 * process as many packets as possible, moving the WRITE index forward as it 76 * resets the Rx queue buffers with new memory. 77 * 78 * The management in the driver is as follows: 79 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 80 * When the interrupt handler is called, the request is processed. 81 * The page is either stolen - transferred to the upper layer 82 * or reused - added immediately to the iwl->rxq->rx_free list. 83 * + When the page is stolen - the driver updates the matching queue's used 84 * count, detaches the RBD and transfers it to the queue used list. 85 * When there are two used RBDs - they are transferred to the allocator empty 86 * list. Work is then scheduled for the allocator to start allocating 87 * eight buffers. 88 * When there are another 6 used RBDs - they are transferred to the allocator 89 * empty list and the driver tries to claim the pre-allocated buffers and 90 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 91 * until ready. 92 * When there are 8+ buffers in the free list - either from allocation or from 93 * 8 reused unstolen pages - restock is called to update the FW and indexes. 94 * + In order to make sure the allocator always has RBDs to use for allocation 95 * the allocator has initial pool in the size of num_queues*(8-2) - the 96 * maximum missing RBDs per allocation request (request posted with 2 97 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 98 * The queues supplies the recycle of the rest of the RBDs. 99 * + A received packet is processed and handed to the kernel network stack, 100 * detached from the iwl->rxq. The driver 'processed' index is updated. 101 * + If there are no allocated buffers in iwl->rxq->rx_free, 102 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 103 * If there were enough free buffers and RX_STALLED is set it is cleared. 104 * 105 * 106 * Driver sequence: 107 * 108 * iwl_rxq_alloc() Allocates rx_free 109 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 110 * iwl_pcie_rxq_restock. 111 * Used only during initialization. 112 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 113 * queue, updates firmware pointers, and updates 114 * the WRITE index. 115 * iwl_pcie_rx_allocator() Background work for allocating pages. 116 * 117 * -- enable interrupts -- 118 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 119 * READ INDEX, detaching the SKB from the pool. 120 * Moves the packet buffer from queue to rx_used. 121 * Posts and claims requests to the allocator. 122 * Calls iwl_pcie_rxq_restock to refill any empty 123 * slots. 124 * 125 * RBD life-cycle: 126 * 127 * Init: 128 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 129 * 130 * Regular Receive interrupt: 131 * Page Stolen: 132 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 133 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 134 * Page not Stolen: 135 * rxq.queue -> rxq.rx_free -> rxq.queue 136 * ... 137 * 138 */ 139 140 /* 141 * iwl_rxq_space - Return number of free slots available in queue. 142 */ 143 static int iwl_rxq_space(const struct iwl_rxq *rxq) 144 { 145 /* Make sure rx queue size is a power of 2 */ 146 WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 147 148 /* 149 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 150 * between empty and completely full queues. 151 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 152 * defined for negative dividends. 153 */ 154 return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 155 } 156 157 /* 158 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 159 */ 160 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 161 { 162 return cpu_to_le32((u32)(dma_addr >> 8)); 163 } 164 165 /* 166 * iwl_pcie_rx_stop - stops the Rx DMA 167 */ 168 int iwl_pcie_rx_stop(struct iwl_trans *trans) 169 { 170 if (trans->cfg->mq_rx_supported) { 171 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 172 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 173 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 174 } else { 175 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 176 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 177 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 178 1000); 179 } 180 } 181 182 /* 183 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 184 */ 185 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 186 struct iwl_rxq *rxq) 187 { 188 u32 reg; 189 190 lockdep_assert_held(&rxq->lock); 191 192 /* 193 * explicitly wake up the NIC if: 194 * 1. shadow registers aren't enabled 195 * 2. there is a chance that the NIC is asleep 196 */ 197 if (!trans->cfg->base_params->shadow_reg_enable && 198 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 199 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 200 201 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 202 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 203 reg); 204 iwl_set_bit(trans, CSR_GP_CNTRL, 205 BIT(trans->cfg->csr->flag_mac_access_req)); 206 rxq->need_update = true; 207 return; 208 } 209 } 210 211 rxq->write_actual = round_down(rxq->write, 8); 212 if (trans->cfg->mq_rx_supported) 213 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 214 rxq->write_actual); 215 else 216 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 217 } 218 219 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 220 { 221 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 222 int i; 223 224 for (i = 0; i < trans->num_rx_queues; i++) { 225 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 226 227 if (!rxq->need_update) 228 continue; 229 spin_lock(&rxq->lock); 230 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 231 rxq->need_update = false; 232 spin_unlock(&rxq->lock); 233 } 234 } 235 236 /* 237 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 238 */ 239 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 240 struct iwl_rxq *rxq) 241 { 242 struct iwl_rx_mem_buffer *rxb; 243 244 /* 245 * If the device isn't enabled - no need to try to add buffers... 246 * This can happen when we stop the device and still have an interrupt 247 * pending. We stop the APM before we sync the interrupts because we 248 * have to (see comment there). On the other hand, since the APM is 249 * stopped, we cannot access the HW (in particular not prph). 250 * So don't try to restock if the APM has been already stopped. 251 */ 252 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 253 return; 254 255 spin_lock(&rxq->lock); 256 while (rxq->free_count) { 257 __le64 *bd = (__le64 *)rxq->bd; 258 259 /* Get next free Rx buffer, remove from free list */ 260 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 261 list); 262 list_del(&rxb->list); 263 rxb->invalid = false; 264 /* 12 first bits are expected to be empty */ 265 WARN_ON(rxb->page_dma & DMA_BIT_MASK(12)); 266 /* Point to Rx buffer via next RBD in circular buffer */ 267 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 268 rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK; 269 rxq->free_count--; 270 } 271 spin_unlock(&rxq->lock); 272 273 /* 274 * If we've added more space for the firmware to place data, tell it. 275 * Increment device's write pointer in multiples of 8. 276 */ 277 if (rxq->write_actual != (rxq->write & ~0x7)) { 278 spin_lock(&rxq->lock); 279 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 280 spin_unlock(&rxq->lock); 281 } 282 } 283 284 /* 285 * iwl_pcie_rxsq_restock - restock implementation for single queue rx 286 */ 287 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 288 struct iwl_rxq *rxq) 289 { 290 struct iwl_rx_mem_buffer *rxb; 291 292 /* 293 * If the device isn't enabled - not need to try to add buffers... 294 * This can happen when we stop the device and still have an interrupt 295 * pending. We stop the APM before we sync the interrupts because we 296 * have to (see comment there). On the other hand, since the APM is 297 * stopped, we cannot access the HW (in particular not prph). 298 * So don't try to restock if the APM has been already stopped. 299 */ 300 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 301 return; 302 303 spin_lock(&rxq->lock); 304 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 305 __le32 *bd = (__le32 *)rxq->bd; 306 /* The overwritten rxb must be a used one */ 307 rxb = rxq->queue[rxq->write]; 308 BUG_ON(rxb && rxb->page); 309 310 /* Get next free Rx buffer, remove from free list */ 311 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 312 list); 313 list_del(&rxb->list); 314 rxb->invalid = false; 315 316 /* Point to Rx buffer via next RBD in circular buffer */ 317 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 318 rxq->queue[rxq->write] = rxb; 319 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 320 rxq->free_count--; 321 } 322 spin_unlock(&rxq->lock); 323 324 /* If we've added more space for the firmware to place data, tell it. 325 * Increment device's write pointer in multiples of 8. */ 326 if (rxq->write_actual != (rxq->write & ~0x7)) { 327 spin_lock(&rxq->lock); 328 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 329 spin_unlock(&rxq->lock); 330 } 331 } 332 333 /* 334 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 335 * 336 * If there are slots in the RX queue that need to be restocked, 337 * and we have free pre-allocated buffers, fill the ranks as much 338 * as we can, pulling from rx_free. 339 * 340 * This moves the 'write' index forward to catch up with 'processed', and 341 * also updates the memory address in the firmware to reference the new 342 * target buffer. 343 */ 344 static 345 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 346 { 347 if (trans->cfg->mq_rx_supported) 348 iwl_pcie_rxmq_restock(trans, rxq); 349 else 350 iwl_pcie_rxsq_restock(trans, rxq); 351 } 352 353 /* 354 * iwl_pcie_rx_alloc_page - allocates and returns a page. 355 * 356 */ 357 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 358 gfp_t priority) 359 { 360 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 361 struct page *page; 362 gfp_t gfp_mask = priority; 363 364 if (trans_pcie->rx_page_order > 0) 365 gfp_mask |= __GFP_COMP; 366 367 /* Alloc a new receive buffer */ 368 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 369 if (!page) { 370 if (net_ratelimit()) 371 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 372 trans_pcie->rx_page_order); 373 /* 374 * Issue an error if we don't have enough pre-allocated 375 * buffers. 376 ` */ 377 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 378 IWL_CRIT(trans, 379 "Failed to alloc_pages\n"); 380 return NULL; 381 } 382 return page; 383 } 384 385 /* 386 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 387 * 388 * A used RBD is an Rx buffer that has been given to the stack. To use it again 389 * a page must be allocated and the RBD must point to the page. This function 390 * doesn't change the HW pointer but handles the list of pages that is used by 391 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 392 * allocated buffers. 393 */ 394 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 395 struct iwl_rxq *rxq) 396 { 397 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 398 struct iwl_rx_mem_buffer *rxb; 399 struct page *page; 400 401 while (1) { 402 spin_lock(&rxq->lock); 403 if (list_empty(&rxq->rx_used)) { 404 spin_unlock(&rxq->lock); 405 return; 406 } 407 spin_unlock(&rxq->lock); 408 409 /* Alloc a new receive buffer */ 410 page = iwl_pcie_rx_alloc_page(trans, priority); 411 if (!page) 412 return; 413 414 spin_lock(&rxq->lock); 415 416 if (list_empty(&rxq->rx_used)) { 417 spin_unlock(&rxq->lock); 418 __free_pages(page, trans_pcie->rx_page_order); 419 return; 420 } 421 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 422 list); 423 list_del(&rxb->list); 424 spin_unlock(&rxq->lock); 425 426 BUG_ON(rxb->page); 427 rxb->page = page; 428 /* Get physical address of the RB */ 429 rxb->page_dma = 430 dma_map_page(trans->dev, page, 0, 431 PAGE_SIZE << trans_pcie->rx_page_order, 432 DMA_FROM_DEVICE); 433 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 434 rxb->page = NULL; 435 spin_lock(&rxq->lock); 436 list_add(&rxb->list, &rxq->rx_used); 437 spin_unlock(&rxq->lock); 438 __free_pages(page, trans_pcie->rx_page_order); 439 return; 440 } 441 442 spin_lock(&rxq->lock); 443 444 list_add_tail(&rxb->list, &rxq->rx_free); 445 rxq->free_count++; 446 447 spin_unlock(&rxq->lock); 448 } 449 } 450 451 static void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 452 { 453 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 454 int i; 455 456 for (i = 0; i < RX_POOL_SIZE; i++) { 457 if (!trans_pcie->rx_pool[i].page) 458 continue; 459 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 460 PAGE_SIZE << trans_pcie->rx_page_order, 461 DMA_FROM_DEVICE); 462 __free_pages(trans_pcie->rx_pool[i].page, 463 trans_pcie->rx_page_order); 464 trans_pcie->rx_pool[i].page = NULL; 465 } 466 } 467 468 /* 469 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 470 * 471 * Allocates for each received request 8 pages 472 * Called as a scheduled work item. 473 */ 474 static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 475 { 476 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 477 struct iwl_rb_allocator *rba = &trans_pcie->rba; 478 struct list_head local_empty; 479 int pending = atomic_xchg(&rba->req_pending, 0); 480 481 IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending); 482 483 /* If we were scheduled - there is at least one request */ 484 spin_lock(&rba->lock); 485 /* swap out the rba->rbd_empty to a local list */ 486 list_replace_init(&rba->rbd_empty, &local_empty); 487 spin_unlock(&rba->lock); 488 489 while (pending) { 490 int i; 491 LIST_HEAD(local_allocated); 492 gfp_t gfp_mask = GFP_KERNEL; 493 494 /* Do not post a warning if there are only a few requests */ 495 if (pending < RX_PENDING_WATERMARK) 496 gfp_mask |= __GFP_NOWARN; 497 498 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 499 struct iwl_rx_mem_buffer *rxb; 500 struct page *page; 501 502 /* List should never be empty - each reused RBD is 503 * returned to the list, and initial pool covers any 504 * possible gap between the time the page is allocated 505 * to the time the RBD is added. 506 */ 507 BUG_ON(list_empty(&local_empty)); 508 /* Get the first rxb from the rbd list */ 509 rxb = list_first_entry(&local_empty, 510 struct iwl_rx_mem_buffer, list); 511 BUG_ON(rxb->page); 512 513 /* Alloc a new receive buffer */ 514 page = iwl_pcie_rx_alloc_page(trans, gfp_mask); 515 if (!page) 516 continue; 517 rxb->page = page; 518 519 /* Get physical address of the RB */ 520 rxb->page_dma = dma_map_page(trans->dev, page, 0, 521 PAGE_SIZE << trans_pcie->rx_page_order, 522 DMA_FROM_DEVICE); 523 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 524 rxb->page = NULL; 525 __free_pages(page, trans_pcie->rx_page_order); 526 continue; 527 } 528 529 /* move the allocated entry to the out list */ 530 list_move(&rxb->list, &local_allocated); 531 i++; 532 } 533 534 pending--; 535 if (!pending) { 536 pending = atomic_xchg(&rba->req_pending, 0); 537 IWL_DEBUG_RX(trans, 538 "Pending allocation requests = %d\n", 539 pending); 540 } 541 542 spin_lock(&rba->lock); 543 /* add the allocated rbds to the allocator allocated list */ 544 list_splice_tail(&local_allocated, &rba->rbd_allocated); 545 /* get more empty RBDs for current pending requests */ 546 list_splice_tail_init(&rba->rbd_empty, &local_empty); 547 spin_unlock(&rba->lock); 548 549 atomic_inc(&rba->req_ready); 550 } 551 552 spin_lock(&rba->lock); 553 /* return unused rbds to the allocator empty list */ 554 list_splice_tail(&local_empty, &rba->rbd_empty); 555 spin_unlock(&rba->lock); 556 } 557 558 /* 559 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 560 .* 561 .* Called by queue when the queue posted allocation request and 562 * has freed 8 RBDs in order to restock itself. 563 * This function directly moves the allocated RBs to the queue's ownership 564 * and updates the relevant counters. 565 */ 566 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 567 struct iwl_rxq *rxq) 568 { 569 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 570 struct iwl_rb_allocator *rba = &trans_pcie->rba; 571 int i; 572 573 lockdep_assert_held(&rxq->lock); 574 575 /* 576 * atomic_dec_if_positive returns req_ready - 1 for any scenario. 577 * If req_ready is 0 atomic_dec_if_positive will return -1 and this 578 * function will return early, as there are no ready requests. 579 * atomic_dec_if_positive will perofrm the *actual* decrement only if 580 * req_ready > 0, i.e. - there are ready requests and the function 581 * hands one request to the caller. 582 */ 583 if (atomic_dec_if_positive(&rba->req_ready) < 0) 584 return; 585 586 spin_lock(&rba->lock); 587 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 588 /* Get next free Rx buffer, remove it from free list */ 589 struct iwl_rx_mem_buffer *rxb = 590 list_first_entry(&rba->rbd_allocated, 591 struct iwl_rx_mem_buffer, list); 592 593 list_move(&rxb->list, &rxq->rx_free); 594 } 595 spin_unlock(&rba->lock); 596 597 rxq->used_count -= RX_CLAIM_REQ_ALLOC; 598 rxq->free_count += RX_CLAIM_REQ_ALLOC; 599 } 600 601 void iwl_pcie_rx_allocator_work(struct work_struct *data) 602 { 603 struct iwl_rb_allocator *rba_p = 604 container_of(data, struct iwl_rb_allocator, rx_alloc); 605 struct iwl_trans_pcie *trans_pcie = 606 container_of(rba_p, struct iwl_trans_pcie, rba); 607 608 iwl_pcie_rx_allocator(trans_pcie->trans); 609 } 610 611 static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 612 { 613 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 614 struct iwl_rb_allocator *rba = &trans_pcie->rba; 615 struct device *dev = trans->dev; 616 int i; 617 int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) : 618 sizeof(__le32); 619 620 if (WARN_ON(trans_pcie->rxq)) 621 return -EINVAL; 622 623 trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 624 GFP_KERNEL); 625 if (!trans_pcie->rxq) 626 return -EINVAL; 627 628 spin_lock_init(&rba->lock); 629 630 for (i = 0; i < trans->num_rx_queues; i++) { 631 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 632 633 spin_lock_init(&rxq->lock); 634 if (trans->cfg->mq_rx_supported) 635 rxq->queue_size = MQ_RX_TABLE_SIZE; 636 else 637 rxq->queue_size = RX_QUEUE_SIZE; 638 639 /* 640 * Allocate the circular buffer of Read Buffer Descriptors 641 * (RBDs) 642 */ 643 rxq->bd = dma_zalloc_coherent(dev, 644 free_size * rxq->queue_size, 645 &rxq->bd_dma, GFP_KERNEL); 646 if (!rxq->bd) 647 goto err; 648 649 if (trans->cfg->mq_rx_supported) { 650 rxq->used_bd = dma_zalloc_coherent(dev, 651 sizeof(__le32) * 652 rxq->queue_size, 653 &rxq->used_bd_dma, 654 GFP_KERNEL); 655 if (!rxq->used_bd) 656 goto err; 657 } 658 659 /*Allocate the driver's pointer to receive buffer status */ 660 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts), 661 &rxq->rb_stts_dma, 662 GFP_KERNEL); 663 if (!rxq->rb_stts) 664 goto err; 665 } 666 return 0; 667 668 err: 669 for (i = 0; i < trans->num_rx_queues; i++) { 670 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 671 672 if (rxq->bd) 673 dma_free_coherent(dev, free_size * rxq->queue_size, 674 rxq->bd, rxq->bd_dma); 675 rxq->bd_dma = 0; 676 rxq->bd = NULL; 677 678 if (rxq->rb_stts) 679 dma_free_coherent(trans->dev, 680 sizeof(struct iwl_rb_status), 681 rxq->rb_stts, rxq->rb_stts_dma); 682 683 if (rxq->used_bd) 684 dma_free_coherent(dev, sizeof(__le32) * rxq->queue_size, 685 rxq->used_bd, rxq->used_bd_dma); 686 rxq->used_bd_dma = 0; 687 rxq->used_bd = NULL; 688 } 689 kfree(trans_pcie->rxq); 690 691 return -ENOMEM; 692 } 693 694 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 695 { 696 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 697 u32 rb_size; 698 unsigned long flags; 699 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 700 701 switch (trans_pcie->rx_buf_size) { 702 case IWL_AMSDU_4K: 703 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 704 break; 705 case IWL_AMSDU_8K: 706 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 707 break; 708 case IWL_AMSDU_12K: 709 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 710 break; 711 default: 712 WARN_ON(1); 713 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 714 } 715 716 if (!iwl_trans_grab_nic_access(trans, &flags)) 717 return; 718 719 /* Stop Rx DMA */ 720 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 721 /* reset and flush pointers */ 722 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 723 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 724 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 725 726 /* Reset driver's Rx queue write index */ 727 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 728 729 /* Tell device where to find RBD circular buffer in DRAM */ 730 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 731 (u32)(rxq->bd_dma >> 8)); 732 733 /* Tell device where in DRAM to update its Rx status */ 734 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 735 rxq->rb_stts_dma >> 4); 736 737 /* Enable Rx DMA 738 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 739 * the credit mechanism in 5000 HW RX FIFO 740 * Direct rx interrupts to hosts 741 * Rx buffer size 4 or 8k or 12k 742 * RB timeout 0x10 743 * 256 RBDs 744 */ 745 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 746 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 747 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 748 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 749 rb_size | 750 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 751 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 752 753 iwl_trans_release_nic_access(trans, &flags); 754 755 /* Set interrupt coalescing timer to default (2048 usecs) */ 756 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 757 758 /* W/A for interrupt coalescing bug in 7260 and 3160 */ 759 if (trans->cfg->host_interrupt_operation_mode) 760 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 761 } 762 763 void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable) 764 { 765 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_9000) 766 return; 767 768 if (CSR_HW_REV_STEP(trans->hw_rev) != SILICON_A_STEP) 769 return; 770 771 if (!trans->cfg->integrated) 772 return; 773 774 /* 775 * Turn on the chicken-bits that cause MAC wakeup for RX-related 776 * values. 777 * This costs some power, but needed for W/A 9000 integrated A-step 778 * bug where shadow registers are not in the retention list and their 779 * value is lost when NIC powers down 780 */ 781 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 782 CSR_MAC_SHADOW_REG_CTRL_RX_WAKE); 783 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTL2, 784 CSR_MAC_SHADOW_REG_CTL2_RX_WAKE); 785 } 786 787 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 788 { 789 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 790 u32 rb_size, enabled = 0; 791 unsigned long flags; 792 int i; 793 794 switch (trans_pcie->rx_buf_size) { 795 case IWL_AMSDU_4K: 796 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 797 break; 798 case IWL_AMSDU_8K: 799 rb_size = RFH_RXF_DMA_RB_SIZE_8K; 800 break; 801 case IWL_AMSDU_12K: 802 rb_size = RFH_RXF_DMA_RB_SIZE_12K; 803 break; 804 default: 805 WARN_ON(1); 806 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 807 } 808 809 if (!iwl_trans_grab_nic_access(trans, &flags)) 810 return; 811 812 /* Stop Rx DMA */ 813 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 814 /* disable free amd used rx queue operation */ 815 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 816 817 for (i = 0; i < trans->num_rx_queues; i++) { 818 /* Tell device where to find RBD free table in DRAM */ 819 iwl_write_prph64_no_grab(trans, 820 RFH_Q_FRBDCB_BA_LSB(i), 821 trans_pcie->rxq[i].bd_dma); 822 /* Tell device where to find RBD used table in DRAM */ 823 iwl_write_prph64_no_grab(trans, 824 RFH_Q_URBDCB_BA_LSB(i), 825 trans_pcie->rxq[i].used_bd_dma); 826 /* Tell device where in DRAM to update its Rx status */ 827 iwl_write_prph64_no_grab(trans, 828 RFH_Q_URBD_STTS_WPTR_LSB(i), 829 trans_pcie->rxq[i].rb_stts_dma); 830 /* Reset device indice tables */ 831 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 832 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 833 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 834 835 enabled |= BIT(i) | BIT(i + 16); 836 } 837 838 /* 839 * Enable Rx DMA 840 * Rx buffer size 4 or 8k or 12k 841 * Min RB size 4 or 8 842 * Drop frames that exceed RB size 843 * 512 RBDs 844 */ 845 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 846 RFH_DMA_EN_ENABLE_VAL | rb_size | 847 RFH_RXF_DMA_MIN_RB_4_8 | 848 RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 849 RFH_RXF_DMA_RBDCB_SIZE_512); 850 851 /* 852 * Activate DMA snooping. 853 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 854 * Default queue is 0 855 */ 856 iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 857 RFH_GEN_CFG_RFH_DMA_SNOOP | 858 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 859 RFH_GEN_CFG_SERVICE_DMA_SNOOP | 860 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 861 trans->cfg->integrated ? 862 RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 863 RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 864 /* Enable the relevant rx queues */ 865 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 866 867 iwl_trans_release_nic_access(trans, &flags); 868 869 /* Set interrupt coalescing timer to default (2048 usecs) */ 870 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 871 872 iwl_pcie_enable_rx_wake(trans, true); 873 } 874 875 static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 876 { 877 lockdep_assert_held(&rxq->lock); 878 879 INIT_LIST_HEAD(&rxq->rx_free); 880 INIT_LIST_HEAD(&rxq->rx_used); 881 rxq->free_count = 0; 882 rxq->used_count = 0; 883 } 884 885 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) 886 { 887 WARN_ON(1); 888 return 0; 889 } 890 891 static int _iwl_pcie_rx_init(struct iwl_trans *trans) 892 { 893 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 894 struct iwl_rxq *def_rxq; 895 struct iwl_rb_allocator *rba = &trans_pcie->rba; 896 int i, err, queue_size, allocator_pool_size, num_alloc; 897 898 if (!trans_pcie->rxq) { 899 err = iwl_pcie_rx_alloc(trans); 900 if (err) 901 return err; 902 } 903 def_rxq = trans_pcie->rxq; 904 905 cancel_work_sync(&rba->rx_alloc); 906 907 spin_lock(&rba->lock); 908 atomic_set(&rba->req_pending, 0); 909 atomic_set(&rba->req_ready, 0); 910 INIT_LIST_HEAD(&rba->rbd_allocated); 911 INIT_LIST_HEAD(&rba->rbd_empty); 912 spin_unlock(&rba->lock); 913 914 /* free all first - we might be reconfigured for a different size */ 915 iwl_pcie_free_rbs_pool(trans); 916 917 for (i = 0; i < RX_QUEUE_SIZE; i++) 918 def_rxq->queue[i] = NULL; 919 920 for (i = 0; i < trans->num_rx_queues; i++) { 921 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 922 923 rxq->id = i; 924 925 spin_lock(&rxq->lock); 926 /* 927 * Set read write pointer to reflect that we have processed 928 * and used all buffers, but have not restocked the Rx queue 929 * with fresh buffers 930 */ 931 rxq->read = 0; 932 rxq->write = 0; 933 rxq->write_actual = 0; 934 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts)); 935 936 iwl_pcie_rx_init_rxb_lists(rxq); 937 938 if (!rxq->napi.poll) 939 netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 940 iwl_pcie_dummy_napi_poll, 64); 941 942 spin_unlock(&rxq->lock); 943 } 944 945 /* move the pool to the default queue and allocator ownerships */ 946 queue_size = trans->cfg->mq_rx_supported ? 947 MQ_RX_NUM_RBDS : RX_QUEUE_SIZE; 948 allocator_pool_size = trans->num_rx_queues * 949 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 950 num_alloc = queue_size + allocator_pool_size; 951 BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) != 952 ARRAY_SIZE(trans_pcie->rx_pool)); 953 for (i = 0; i < num_alloc; i++) { 954 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 955 956 if (i < allocator_pool_size) 957 list_add(&rxb->list, &rba->rbd_empty); 958 else 959 list_add(&rxb->list, &def_rxq->rx_used); 960 trans_pcie->global_table[i] = rxb; 961 rxb->vid = (u16)(i + 1); 962 rxb->invalid = true; 963 } 964 965 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 966 967 return 0; 968 } 969 970 int iwl_pcie_rx_init(struct iwl_trans *trans) 971 { 972 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 973 int ret = _iwl_pcie_rx_init(trans); 974 975 if (ret) 976 return ret; 977 978 if (trans->cfg->mq_rx_supported) 979 iwl_pcie_rx_mq_hw_init(trans); 980 else 981 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 982 983 iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 984 985 spin_lock(&trans_pcie->rxq->lock); 986 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 987 spin_unlock(&trans_pcie->rxq->lock); 988 989 return 0; 990 } 991 992 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 993 { 994 /* 995 * We don't configure the RFH. 996 * Restock will be done at alive, after firmware configured the RFH. 997 */ 998 return _iwl_pcie_rx_init(trans); 999 } 1000 1001 void iwl_pcie_rx_free(struct iwl_trans *trans) 1002 { 1003 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1004 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1005 int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) : 1006 sizeof(__le32); 1007 int i; 1008 1009 /* 1010 * if rxq is NULL, it means that nothing has been allocated, 1011 * exit now 1012 */ 1013 if (!trans_pcie->rxq) { 1014 IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1015 return; 1016 } 1017 1018 cancel_work_sync(&rba->rx_alloc); 1019 1020 iwl_pcie_free_rbs_pool(trans); 1021 1022 for (i = 0; i < trans->num_rx_queues; i++) { 1023 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1024 1025 if (rxq->bd) 1026 dma_free_coherent(trans->dev, 1027 free_size * rxq->queue_size, 1028 rxq->bd, rxq->bd_dma); 1029 rxq->bd_dma = 0; 1030 rxq->bd = NULL; 1031 1032 if (rxq->rb_stts) 1033 dma_free_coherent(trans->dev, 1034 sizeof(struct iwl_rb_status), 1035 rxq->rb_stts, rxq->rb_stts_dma); 1036 else 1037 IWL_DEBUG_INFO(trans, 1038 "Free rxq->rb_stts which is NULL\n"); 1039 1040 if (rxq->used_bd) 1041 dma_free_coherent(trans->dev, 1042 sizeof(__le32) * rxq->queue_size, 1043 rxq->used_bd, rxq->used_bd_dma); 1044 rxq->used_bd_dma = 0; 1045 rxq->used_bd = NULL; 1046 1047 if (rxq->napi.poll) 1048 netif_napi_del(&rxq->napi); 1049 } 1050 kfree(trans_pcie->rxq); 1051 } 1052 1053 /* 1054 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1055 * 1056 * Called when a RBD can be reused. The RBD is transferred to the allocator. 1057 * When there are 2 empty RBDs - a request for allocation is posted 1058 */ 1059 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1060 struct iwl_rx_mem_buffer *rxb, 1061 struct iwl_rxq *rxq, bool emergency) 1062 { 1063 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1064 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1065 1066 /* Move the RBD to the used list, will be moved to allocator in batches 1067 * before claiming or posting a request*/ 1068 list_add_tail(&rxb->list, &rxq->rx_used); 1069 1070 if (unlikely(emergency)) 1071 return; 1072 1073 /* Count the allocator owned RBDs */ 1074 rxq->used_count++; 1075 1076 /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1077 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1078 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1079 * after but we still need to post another request. 1080 */ 1081 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1082 /* Move the 2 RBDs to the allocator ownership. 1083 Allocator has another 6 from pool for the request completion*/ 1084 spin_lock(&rba->lock); 1085 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1086 spin_unlock(&rba->lock); 1087 1088 atomic_inc(&rba->req_pending); 1089 queue_work(rba->alloc_wq, &rba->rx_alloc); 1090 } 1091 } 1092 1093 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 1094 struct iwl_rxq *rxq, 1095 struct iwl_rx_mem_buffer *rxb, 1096 bool emergency) 1097 { 1098 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1099 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1100 bool page_stolen = false; 1101 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 1102 u32 offset = 0; 1103 1104 if (WARN_ON(!rxb)) 1105 return; 1106 1107 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1108 1109 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1110 struct iwl_rx_packet *pkt; 1111 u16 sequence; 1112 bool reclaim; 1113 int index, cmd_index, len; 1114 struct iwl_rx_cmd_buffer rxcb = { 1115 ._offset = offset, 1116 ._rx_page_order = trans_pcie->rx_page_order, 1117 ._page = rxb->page, 1118 ._page_stolen = false, 1119 .truesize = max_len, 1120 }; 1121 1122 pkt = rxb_addr(&rxcb); 1123 1124 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 1125 IWL_DEBUG_RX(trans, 1126 "Q %d: RB end marker at offset %d\n", 1127 rxq->id, offset); 1128 break; 1129 } 1130 1131 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1132 FH_RSCSR_RXQ_POS != rxq->id, 1133 "frame on invalid queue - is on %d and indicates %d\n", 1134 rxq->id, 1135 (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1136 FH_RSCSR_RXQ_POS); 1137 1138 IWL_DEBUG_RX(trans, 1139 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 1140 rxq->id, offset, 1141 iwl_get_cmd_string(trans, 1142 iwl_cmd_id(pkt->hdr.cmd, 1143 pkt->hdr.group_id, 1144 0)), 1145 pkt->hdr.group_id, pkt->hdr.cmd, 1146 le16_to_cpu(pkt->hdr.sequence)); 1147 1148 len = iwl_rx_packet_len(pkt); 1149 len += sizeof(u32); /* account for status word */ 1150 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1151 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1152 1153 /* Reclaim a command buffer only if this packet is a response 1154 * to a (driver-originated) command. 1155 * If the packet (e.g. Rx frame) originated from uCode, 1156 * there is no command buffer to reclaim. 1157 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1158 * but apparently a few don't get set; catch them here. */ 1159 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1160 if (reclaim && !pkt->hdr.group_id) { 1161 int i; 1162 1163 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1164 if (trans_pcie->no_reclaim_cmds[i] == 1165 pkt->hdr.cmd) { 1166 reclaim = false; 1167 break; 1168 } 1169 } 1170 } 1171 1172 sequence = le16_to_cpu(pkt->hdr.sequence); 1173 index = SEQ_TO_INDEX(sequence); 1174 cmd_index = iwl_pcie_get_cmd_index(txq, index); 1175 1176 if (rxq->id == 0) 1177 iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1178 &rxcb); 1179 else 1180 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1181 &rxcb, rxq->id); 1182 1183 if (reclaim) { 1184 kzfree(txq->entries[cmd_index].free_buf); 1185 txq->entries[cmd_index].free_buf = NULL; 1186 } 1187 1188 /* 1189 * After here, we should always check rxcb._page_stolen, 1190 * if it is true then one of the handlers took the page. 1191 */ 1192 1193 if (reclaim) { 1194 /* Invoke any callbacks, transfer the buffer to caller, 1195 * and fire off the (possibly) blocking 1196 * iwl_trans_send_cmd() 1197 * as we reclaim the driver command queue */ 1198 if (!rxcb._page_stolen) 1199 iwl_pcie_hcmd_complete(trans, &rxcb); 1200 else 1201 IWL_WARN(trans, "Claim null rxb?\n"); 1202 } 1203 1204 page_stolen |= rxcb._page_stolen; 1205 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1206 } 1207 1208 /* page was stolen from us -- free our reference */ 1209 if (page_stolen) { 1210 __free_pages(rxb->page, trans_pcie->rx_page_order); 1211 rxb->page = NULL; 1212 } 1213 1214 /* Reuse the page if possible. For notification packets and 1215 * SKBs that fail to Rx correctly, add them back into the 1216 * rx_free list for reuse later. */ 1217 if (rxb->page != NULL) { 1218 rxb->page_dma = 1219 dma_map_page(trans->dev, rxb->page, 0, 1220 PAGE_SIZE << trans_pcie->rx_page_order, 1221 DMA_FROM_DEVICE); 1222 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1223 /* 1224 * free the page(s) as well to not break 1225 * the invariant that the items on the used 1226 * list have no page(s) 1227 */ 1228 __free_pages(rxb->page, trans_pcie->rx_page_order); 1229 rxb->page = NULL; 1230 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1231 } else { 1232 list_add_tail(&rxb->list, &rxq->rx_free); 1233 rxq->free_count++; 1234 } 1235 } else 1236 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1237 } 1238 1239 /* 1240 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1241 */ 1242 static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue) 1243 { 1244 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1245 struct iwl_rxq *rxq = &trans_pcie->rxq[queue]; 1246 u32 r, i, count = 0; 1247 bool emergency = false; 1248 1249 restart: 1250 spin_lock(&rxq->lock); 1251 /* uCode's read index (stored in shared DRAM) indicates the last Rx 1252 * buffer that the driver may process (last buffer filled by ucode). */ 1253 r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 1254 i = rxq->read; 1255 1256 /* W/A 9000 device step A0 wrap-around bug */ 1257 r &= (rxq->queue_size - 1); 1258 1259 /* Rx interrupt, but nothing sent from uCode */ 1260 if (i == r) 1261 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1262 1263 while (i != r) { 1264 struct iwl_rx_mem_buffer *rxb; 1265 1266 if (unlikely(rxq->used_count == rxq->queue_size / 2)) 1267 emergency = true; 1268 1269 if (trans->cfg->mq_rx_supported) { 1270 /* 1271 * used_bd is a 32 bit but only 12 are used to retrieve 1272 * the vid 1273 */ 1274 u16 vid = le32_to_cpu(rxq->used_bd[i]) & 0x0FFF; 1275 1276 if (WARN(!vid || 1277 vid > ARRAY_SIZE(trans_pcie->global_table), 1278 "Invalid rxb index from HW %u\n", (u32)vid)) { 1279 iwl_force_nmi(trans); 1280 goto out; 1281 } 1282 rxb = trans_pcie->global_table[vid - 1]; 1283 if (WARN(rxb->invalid, 1284 "Invalid rxb from HW %u\n", (u32)vid)) { 1285 iwl_force_nmi(trans); 1286 goto out; 1287 } 1288 rxb->invalid = true; 1289 } else { 1290 rxb = rxq->queue[i]; 1291 rxq->queue[i] = NULL; 1292 } 1293 1294 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 1295 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency); 1296 1297 i = (i + 1) & (rxq->queue_size - 1); 1298 1299 /* 1300 * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1301 * try to claim the pre-allocated buffers from the allocator. 1302 * If not ready - will try to reclaim next time. 1303 * There is no need to reschedule work - allocator exits only 1304 * on success 1305 */ 1306 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1307 iwl_pcie_rx_allocator_get(trans, rxq); 1308 1309 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1310 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1311 1312 /* Add the remaining empty RBDs for allocator use */ 1313 spin_lock(&rba->lock); 1314 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1315 spin_unlock(&rba->lock); 1316 } else if (emergency) { 1317 count++; 1318 if (count == 8) { 1319 count = 0; 1320 if (rxq->used_count < rxq->queue_size / 3) 1321 emergency = false; 1322 1323 rxq->read = i; 1324 spin_unlock(&rxq->lock); 1325 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1326 iwl_pcie_rxq_restock(trans, rxq); 1327 goto restart; 1328 } 1329 } 1330 } 1331 out: 1332 /* Backtrack one entry */ 1333 rxq->read = i; 1334 spin_unlock(&rxq->lock); 1335 1336 /* 1337 * handle a case where in emergency there are some unallocated RBDs. 1338 * those RBDs are in the used list, but are not tracked by the queue's 1339 * used_count which counts allocator owned RBDs. 1340 * unallocated emergency RBDs must be allocated on exit, otherwise 1341 * when called again the function may not be in emergency mode and 1342 * they will be handed to the allocator with no tracking in the RBD 1343 * allocator counters, which will lead to them never being claimed back 1344 * by the queue. 1345 * by allocating them here, they are now in the queue free list, and 1346 * will be restocked by the next call of iwl_pcie_rxq_restock. 1347 */ 1348 if (unlikely(emergency && count)) 1349 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1350 1351 if (rxq->napi.poll) 1352 napi_gro_flush(&rxq->napi, false); 1353 1354 iwl_pcie_rxq_restock(trans, rxq); 1355 } 1356 1357 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 1358 { 1359 u8 queue = entry->entry; 1360 struct msix_entry *entries = entry - queue; 1361 1362 return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 1363 } 1364 1365 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 1366 struct msix_entry *entry) 1367 { 1368 /* 1369 * Before sending the interrupt the HW disables it to prevent 1370 * a nested interrupt. This is done by writing 1 to the corresponding 1371 * bit in the mask register. After handling the interrupt, it should be 1372 * re-enabled by clearing this bit. This register is defined as 1373 * write 1 clear (W1C) register, meaning that it's being clear 1374 * by writing 1 to the bit. 1375 */ 1376 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 1377 } 1378 1379 /* 1380 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 1381 * This interrupt handler should be used with RSS queue only. 1382 */ 1383 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 1384 { 1385 struct msix_entry *entry = dev_id; 1386 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 1387 struct iwl_trans *trans = trans_pcie->trans; 1388 1389 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1390 1391 if (WARN_ON(entry->entry >= trans->num_rx_queues)) 1392 return IRQ_NONE; 1393 1394 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1395 1396 local_bh_disable(); 1397 iwl_pcie_rx_handle(trans, entry->entry); 1398 local_bh_enable(); 1399 1400 iwl_pcie_clear_irq(trans, entry); 1401 1402 lock_map_release(&trans->sync_cmd_lockdep_map); 1403 1404 return IRQ_HANDLED; 1405 } 1406 1407 /* 1408 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1409 */ 1410 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1411 { 1412 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1413 int i; 1414 1415 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1416 if (trans->cfg->internal_wimax_coex && 1417 !trans->cfg->apmg_not_supported && 1418 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1419 APMS_CLK_VAL_MRB_FUNC_MODE) || 1420 (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1421 APMG_PS_CTRL_VAL_RESET_REQ))) { 1422 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1423 iwl_op_mode_wimax_active(trans->op_mode); 1424 wake_up(&trans_pcie->wait_command_queue); 1425 return; 1426 } 1427 1428 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 1429 if (!trans_pcie->txq[i]) 1430 continue; 1431 del_timer(&trans_pcie->txq[i]->stuck_timer); 1432 } 1433 1434 /* The STATUS_FW_ERROR bit is set in this function. This must happen 1435 * before we wake up the command caller, to ensure a proper cleanup. */ 1436 iwl_trans_fw_error(trans); 1437 1438 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1439 wake_up(&trans_pcie->wait_command_queue); 1440 } 1441 1442 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1443 { 1444 u32 inta; 1445 1446 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1447 1448 trace_iwlwifi_dev_irq(trans->dev); 1449 1450 /* Discover which interrupts are active/pending */ 1451 inta = iwl_read32(trans, CSR_INT); 1452 1453 /* the thread will service interrupts and re-enable them */ 1454 return inta; 1455 } 1456 1457 /* a device (PCI-E) page is 4096 bytes long */ 1458 #define ICT_SHIFT 12 1459 #define ICT_SIZE (1 << ICT_SHIFT) 1460 #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1461 1462 /* interrupt handler using ict table, with this interrupt driver will 1463 * stop using INTA register to get device's interrupt, reading this register 1464 * is expensive, device will write interrupts in ICT dram table, increment 1465 * index then will fire interrupt to driver, driver will OR all ICT table 1466 * entries from current index up to table entry with 0 value. the result is 1467 * the interrupt we need to service, driver will set the entries back to 0 and 1468 * set index. 1469 */ 1470 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1471 { 1472 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1473 u32 inta; 1474 u32 val = 0; 1475 u32 read; 1476 1477 trace_iwlwifi_dev_irq(trans->dev); 1478 1479 /* Ignore interrupt if there's nothing in NIC to service. 1480 * This may be due to IRQ shared with another device, 1481 * or due to sporadic interrupts thrown from our NIC. */ 1482 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1483 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1484 if (!read) 1485 return 0; 1486 1487 /* 1488 * Collect all entries up to the first 0, starting from ict_index; 1489 * note we already read at ict_index. 1490 */ 1491 do { 1492 val |= read; 1493 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1494 trans_pcie->ict_index, read); 1495 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1496 trans_pcie->ict_index = 1497 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1498 1499 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1500 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1501 read); 1502 } while (read); 1503 1504 /* We should not get this value, just ignore it. */ 1505 if (val == 0xffffffff) 1506 val = 0; 1507 1508 /* 1509 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1510 * (bit 15 before shifting it to 31) to clear when using interrupt 1511 * coalescing. fortunately, bits 18 and 19 stay set when this happens 1512 * so we use them to decide on the real state of the Rx bit. 1513 * In order words, bit 15 is set if bit 18 or bit 19 are set. 1514 */ 1515 if (val & 0xC0000) 1516 val |= 0x8000; 1517 1518 inta = (0xff & val) | ((0xff00 & val) << 16); 1519 return inta; 1520 } 1521 1522 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 1523 { 1524 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1525 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1526 bool hw_rfkill, prev, report; 1527 1528 mutex_lock(&trans_pcie->mutex); 1529 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1530 hw_rfkill = iwl_is_rfkill_set(trans); 1531 if (hw_rfkill) { 1532 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1533 set_bit(STATUS_RFKILL_HW, &trans->status); 1534 } 1535 if (trans_pcie->opmode_down) 1536 report = hw_rfkill; 1537 else 1538 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1539 1540 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 1541 hw_rfkill ? "disable radio" : "enable radio"); 1542 1543 isr_stats->rfkill++; 1544 1545 if (prev != report) 1546 iwl_trans_pcie_rf_kill(trans, report); 1547 mutex_unlock(&trans_pcie->mutex); 1548 1549 if (hw_rfkill) { 1550 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 1551 &trans->status)) 1552 IWL_DEBUG_RF_KILL(trans, 1553 "Rfkill while SYNC HCMD in flight\n"); 1554 wake_up(&trans_pcie->wait_command_queue); 1555 } else { 1556 clear_bit(STATUS_RFKILL_HW, &trans->status); 1557 if (trans_pcie->opmode_down) 1558 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1559 } 1560 } 1561 1562 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1563 { 1564 struct iwl_trans *trans = dev_id; 1565 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1566 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1567 u32 inta = 0; 1568 u32 handled = 0; 1569 1570 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1571 1572 spin_lock(&trans_pcie->irq_lock); 1573 1574 /* dram interrupt table not set yet, 1575 * use legacy interrupt. 1576 */ 1577 if (likely(trans_pcie->use_ict)) 1578 inta = iwl_pcie_int_cause_ict(trans); 1579 else 1580 inta = iwl_pcie_int_cause_non_ict(trans); 1581 1582 if (iwl_have_debug_level(IWL_DL_ISR)) { 1583 IWL_DEBUG_ISR(trans, 1584 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1585 inta, trans_pcie->inta_mask, 1586 iwl_read32(trans, CSR_INT_MASK), 1587 iwl_read32(trans, CSR_FH_INT_STATUS)); 1588 if (inta & (~trans_pcie->inta_mask)) 1589 IWL_DEBUG_ISR(trans, 1590 "We got a masked interrupt (0x%08x)\n", 1591 inta & (~trans_pcie->inta_mask)); 1592 } 1593 1594 inta &= trans_pcie->inta_mask; 1595 1596 /* 1597 * Ignore interrupt if there's nothing in NIC to service. 1598 * This may be due to IRQ shared with another device, 1599 * or due to sporadic interrupts thrown from our NIC. 1600 */ 1601 if (unlikely(!inta)) { 1602 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1603 /* 1604 * Re-enable interrupts here since we don't 1605 * have anything to service 1606 */ 1607 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1608 _iwl_enable_interrupts(trans); 1609 spin_unlock(&trans_pcie->irq_lock); 1610 lock_map_release(&trans->sync_cmd_lockdep_map); 1611 return IRQ_NONE; 1612 } 1613 1614 if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1615 /* 1616 * Hardware disappeared. It might have 1617 * already raised an interrupt. 1618 */ 1619 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1620 spin_unlock(&trans_pcie->irq_lock); 1621 goto out; 1622 } 1623 1624 /* Ack/clear/reset pending uCode interrupts. 1625 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1626 */ 1627 /* There is a hardware bug in the interrupt mask function that some 1628 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1629 * they are disabled in the CSR_INT_MASK register. Furthermore the 1630 * ICT interrupt handling mechanism has another bug that might cause 1631 * these unmasked interrupts fail to be detected. We workaround the 1632 * hardware bugs here by ACKing all the possible interrupts so that 1633 * interrupt coalescing can still be achieved. 1634 */ 1635 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1636 1637 if (iwl_have_debug_level(IWL_DL_ISR)) 1638 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1639 inta, iwl_read32(trans, CSR_INT_MASK)); 1640 1641 spin_unlock(&trans_pcie->irq_lock); 1642 1643 /* Now service all interrupt bits discovered above. */ 1644 if (inta & CSR_INT_BIT_HW_ERR) { 1645 IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1646 1647 /* Tell the device to stop sending interrupts */ 1648 iwl_disable_interrupts(trans); 1649 1650 isr_stats->hw++; 1651 iwl_pcie_irq_handle_error(trans); 1652 1653 handled |= CSR_INT_BIT_HW_ERR; 1654 1655 goto out; 1656 } 1657 1658 if (iwl_have_debug_level(IWL_DL_ISR)) { 1659 /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1660 if (inta & CSR_INT_BIT_SCD) { 1661 IWL_DEBUG_ISR(trans, 1662 "Scheduler finished to transmit the frame/frames.\n"); 1663 isr_stats->sch++; 1664 } 1665 1666 /* Alive notification via Rx interrupt will do the real work */ 1667 if (inta & CSR_INT_BIT_ALIVE) { 1668 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1669 isr_stats->alive++; 1670 if (trans->cfg->gen2) { 1671 /* 1672 * We can restock, since firmware configured 1673 * the RFH 1674 */ 1675 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1676 } 1677 } 1678 } 1679 1680 /* Safely ignore these bits for debug checks below */ 1681 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1682 1683 /* HW RF KILL switch toggled */ 1684 if (inta & CSR_INT_BIT_RF_KILL) { 1685 iwl_pcie_handle_rfkill_irq(trans); 1686 handled |= CSR_INT_BIT_RF_KILL; 1687 } 1688 1689 /* Chip got too hot and stopped itself */ 1690 if (inta & CSR_INT_BIT_CT_KILL) { 1691 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1692 isr_stats->ctkill++; 1693 handled |= CSR_INT_BIT_CT_KILL; 1694 } 1695 1696 /* Error detected by uCode */ 1697 if (inta & CSR_INT_BIT_SW_ERR) { 1698 IWL_ERR(trans, "Microcode SW error detected. " 1699 " Restarting 0x%X.\n", inta); 1700 isr_stats->sw++; 1701 iwl_pcie_irq_handle_error(trans); 1702 handled |= CSR_INT_BIT_SW_ERR; 1703 } 1704 1705 /* uCode wakes up after power-down sleep */ 1706 if (inta & CSR_INT_BIT_WAKEUP) { 1707 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1708 iwl_pcie_rxq_check_wrptr(trans); 1709 iwl_pcie_txq_check_wrptrs(trans); 1710 1711 isr_stats->wakeup++; 1712 1713 handled |= CSR_INT_BIT_WAKEUP; 1714 } 1715 1716 /* All uCode command responses, including Tx command responses, 1717 * Rx "responses" (frame-received notification), and other 1718 * notifications from uCode come through here*/ 1719 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1720 CSR_INT_BIT_RX_PERIODIC)) { 1721 IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1722 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1723 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1724 iwl_write32(trans, CSR_FH_INT_STATUS, 1725 CSR_FH_INT_RX_MASK); 1726 } 1727 if (inta & CSR_INT_BIT_RX_PERIODIC) { 1728 handled |= CSR_INT_BIT_RX_PERIODIC; 1729 iwl_write32(trans, 1730 CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1731 } 1732 /* Sending RX interrupt require many steps to be done in the 1733 * the device: 1734 * 1- write interrupt to current index in ICT table. 1735 * 2- dma RX frame. 1736 * 3- update RX shared data to indicate last write index. 1737 * 4- send interrupt. 1738 * This could lead to RX race, driver could receive RX interrupt 1739 * but the shared data changes does not reflect this; 1740 * periodic interrupt will detect any dangling Rx activity. 1741 */ 1742 1743 /* Disable periodic interrupt; we use it as just a one-shot. */ 1744 iwl_write8(trans, CSR_INT_PERIODIC_REG, 1745 CSR_INT_PERIODIC_DIS); 1746 1747 /* 1748 * Enable periodic interrupt in 8 msec only if we received 1749 * real RX interrupt (instead of just periodic int), to catch 1750 * any dangling Rx interrupt. If it was just the periodic 1751 * interrupt, there was no dangling Rx activity, and no need 1752 * to extend the periodic interrupt; one-shot is enough. 1753 */ 1754 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1755 iwl_write8(trans, CSR_INT_PERIODIC_REG, 1756 CSR_INT_PERIODIC_ENA); 1757 1758 isr_stats->rx++; 1759 1760 local_bh_disable(); 1761 iwl_pcie_rx_handle(trans, 0); 1762 local_bh_enable(); 1763 } 1764 1765 /* This "Tx" DMA channel is used only for loading uCode */ 1766 if (inta & CSR_INT_BIT_FH_TX) { 1767 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1768 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1769 isr_stats->tx++; 1770 handled |= CSR_INT_BIT_FH_TX; 1771 /* Wake up uCode load routine, now that load is complete */ 1772 trans_pcie->ucode_write_complete = true; 1773 wake_up(&trans_pcie->ucode_write_waitq); 1774 } 1775 1776 if (inta & ~handled) { 1777 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 1778 isr_stats->unhandled++; 1779 } 1780 1781 if (inta & ~(trans_pcie->inta_mask)) { 1782 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 1783 inta & ~trans_pcie->inta_mask); 1784 } 1785 1786 spin_lock(&trans_pcie->irq_lock); 1787 /* only Re-enable all interrupt if disabled by irq */ 1788 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1789 _iwl_enable_interrupts(trans); 1790 /* we are loading the firmware, enable FH_TX interrupt only */ 1791 else if (handled & CSR_INT_BIT_FH_TX) 1792 iwl_enable_fw_load_int(trans); 1793 /* Re-enable RF_KILL if it occurred */ 1794 else if (handled & CSR_INT_BIT_RF_KILL) 1795 iwl_enable_rfkill_int(trans); 1796 spin_unlock(&trans_pcie->irq_lock); 1797 1798 out: 1799 lock_map_release(&trans->sync_cmd_lockdep_map); 1800 return IRQ_HANDLED; 1801 } 1802 1803 /****************************************************************************** 1804 * 1805 * ICT functions 1806 * 1807 ******************************************************************************/ 1808 1809 /* Free dram table */ 1810 void iwl_pcie_free_ict(struct iwl_trans *trans) 1811 { 1812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1813 1814 if (trans_pcie->ict_tbl) { 1815 dma_free_coherent(trans->dev, ICT_SIZE, 1816 trans_pcie->ict_tbl, 1817 trans_pcie->ict_tbl_dma); 1818 trans_pcie->ict_tbl = NULL; 1819 trans_pcie->ict_tbl_dma = 0; 1820 } 1821 } 1822 1823 /* 1824 * allocate dram shared table, it is an aligned memory 1825 * block of ICT_SIZE. 1826 * also reset all data related to ICT table interrupt. 1827 */ 1828 int iwl_pcie_alloc_ict(struct iwl_trans *trans) 1829 { 1830 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1831 1832 trans_pcie->ict_tbl = 1833 dma_zalloc_coherent(trans->dev, ICT_SIZE, 1834 &trans_pcie->ict_tbl_dma, 1835 GFP_KERNEL); 1836 if (!trans_pcie->ict_tbl) 1837 return -ENOMEM; 1838 1839 /* just an API sanity check ... it is guaranteed to be aligned */ 1840 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 1841 iwl_pcie_free_ict(trans); 1842 return -EINVAL; 1843 } 1844 1845 return 0; 1846 } 1847 1848 /* Device is going up inform it about using ICT interrupt table, 1849 * also we need to tell the driver to start using ICT interrupt. 1850 */ 1851 void iwl_pcie_reset_ict(struct iwl_trans *trans) 1852 { 1853 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1854 u32 val; 1855 1856 if (!trans_pcie->ict_tbl) 1857 return; 1858 1859 spin_lock(&trans_pcie->irq_lock); 1860 _iwl_disable_interrupts(trans); 1861 1862 memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 1863 1864 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 1865 1866 val |= CSR_DRAM_INT_TBL_ENABLE | 1867 CSR_DRAM_INIT_TBL_WRAP_CHECK | 1868 CSR_DRAM_INIT_TBL_WRITE_POINTER; 1869 1870 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 1871 1872 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 1873 trans_pcie->use_ict = true; 1874 trans_pcie->ict_index = 0; 1875 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 1876 _iwl_enable_interrupts(trans); 1877 spin_unlock(&trans_pcie->irq_lock); 1878 } 1879 1880 /* Device is going down disable ict interrupt usage */ 1881 void iwl_pcie_disable_ict(struct iwl_trans *trans) 1882 { 1883 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1884 1885 spin_lock(&trans_pcie->irq_lock); 1886 trans_pcie->use_ict = false; 1887 spin_unlock(&trans_pcie->irq_lock); 1888 } 1889 1890 irqreturn_t iwl_pcie_isr(int irq, void *data) 1891 { 1892 struct iwl_trans *trans = data; 1893 1894 if (!trans) 1895 return IRQ_NONE; 1896 1897 /* Disable (but don't clear!) interrupts here to avoid 1898 * back-to-back ISRs and sporadic interrupts from our NIC. 1899 * If we have something to service, the tasklet will re-enable ints. 1900 * If we *don't* have something, we'll re-enable before leaving here. 1901 */ 1902 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 1903 1904 return IRQ_WAKE_THREAD; 1905 } 1906 1907 irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 1908 { 1909 return IRQ_WAKE_THREAD; 1910 } 1911 1912 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 1913 { 1914 struct msix_entry *entry = dev_id; 1915 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 1916 struct iwl_trans *trans = trans_pcie->trans; 1917 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1918 u32 inta_fh, inta_hw; 1919 1920 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1921 1922 spin_lock(&trans_pcie->irq_lock); 1923 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 1924 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 1925 /* 1926 * Clear causes registers to avoid being handling the same cause. 1927 */ 1928 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 1929 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 1930 spin_unlock(&trans_pcie->irq_lock); 1931 1932 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 1933 1934 if (unlikely(!(inta_fh | inta_hw))) { 1935 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1936 lock_map_release(&trans->sync_cmd_lockdep_map); 1937 return IRQ_NONE; 1938 } 1939 1940 if (iwl_have_debug_level(IWL_DL_ISR)) 1941 IWL_DEBUG_ISR(trans, "ISR inta_fh 0x%08x, enabled 0x%08x\n", 1942 inta_fh, 1943 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 1944 1945 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 1946 inta_fh & MSIX_FH_INT_CAUSES_Q0) { 1947 local_bh_disable(); 1948 iwl_pcie_rx_handle(trans, 0); 1949 local_bh_enable(); 1950 } 1951 1952 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 1953 inta_fh & MSIX_FH_INT_CAUSES_Q1) { 1954 local_bh_disable(); 1955 iwl_pcie_rx_handle(trans, 1); 1956 local_bh_enable(); 1957 } 1958 1959 /* This "Tx" DMA channel is used only for loading uCode */ 1960 if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 1961 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1962 isr_stats->tx++; 1963 /* 1964 * Wake up uCode load routine, 1965 * now that load is complete 1966 */ 1967 trans_pcie->ucode_write_complete = true; 1968 wake_up(&trans_pcie->ucode_write_waitq); 1969 } 1970 1971 /* Error detected by uCode */ 1972 if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 1973 (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) { 1974 IWL_ERR(trans, 1975 "Microcode SW error detected. Restarting 0x%X.\n", 1976 inta_fh); 1977 isr_stats->sw++; 1978 iwl_pcie_irq_handle_error(trans); 1979 } 1980 1981 /* After checking FH register check HW register */ 1982 if (iwl_have_debug_level(IWL_DL_ISR)) 1983 IWL_DEBUG_ISR(trans, 1984 "ISR inta_hw 0x%08x, enabled 0x%08x\n", 1985 inta_hw, 1986 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 1987 1988 /* Alive notification via Rx interrupt will do the real work */ 1989 if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 1990 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1991 isr_stats->alive++; 1992 if (trans->cfg->gen2) { 1993 /* We can restock, since firmware configured the RFH */ 1994 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1995 } 1996 } 1997 1998 /* uCode wakes up after power-down sleep */ 1999 if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 2000 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 2001 iwl_pcie_rxq_check_wrptr(trans); 2002 iwl_pcie_txq_check_wrptrs(trans); 2003 2004 isr_stats->wakeup++; 2005 } 2006 2007 /* Chip got too hot and stopped itself */ 2008 if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 2009 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 2010 isr_stats->ctkill++; 2011 } 2012 2013 /* HW RF KILL switch toggled */ 2014 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 2015 iwl_pcie_handle_rfkill_irq(trans); 2016 2017 if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 2018 IWL_ERR(trans, 2019 "Hardware error detected. Restarting.\n"); 2020 2021 isr_stats->hw++; 2022 iwl_pcie_irq_handle_error(trans); 2023 } 2024 2025 iwl_pcie_clear_irq(trans, entry); 2026 2027 lock_map_release(&trans->sync_cmd_lockdep_map); 2028 2029 return IRQ_HANDLED; 2030 } 2031