1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2003-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/sched.h> 8 #include <linux/wait.h> 9 #include <linux/gfp.h> 10 11 #include "iwl-prph.h" 12 #include "iwl-io.h" 13 #include "internal.h" 14 #include "iwl-op-mode.h" 15 #include "iwl-context-info-gen3.h" 16 17 /****************************************************************************** 18 * 19 * RX path functions 20 * 21 ******************************************************************************/ 22 23 /* 24 * Rx theory of operation 25 * 26 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 27 * each of which point to Receive Buffers to be filled by the NIC. These get 28 * used not only for Rx frames, but for any command response or notification 29 * from the NIC. The driver and NIC manage the Rx buffers by means 30 * of indexes into the circular buffer. 31 * 32 * Rx Queue Indexes 33 * The host/firmware share two index registers for managing the Rx buffers. 34 * 35 * The READ index maps to the first position that the firmware may be writing 36 * to -- the driver can read up to (but not including) this position and get 37 * good data. 38 * The READ index is managed by the firmware once the card is enabled. 39 * 40 * The WRITE index maps to the last position the driver has read from -- the 41 * position preceding WRITE is the last slot the firmware can place a packet. 42 * 43 * The queue is empty (no good data) if WRITE = READ - 1, and is full if 44 * WRITE = READ. 45 * 46 * During initialization, the host sets up the READ queue position to the first 47 * INDEX position, and WRITE to the last (READ - 1 wrapped) 48 * 49 * When the firmware places a packet in a buffer, it will advance the READ index 50 * and fire the RX interrupt. The driver can then query the READ index and 51 * process as many packets as possible, moving the WRITE index forward as it 52 * resets the Rx queue buffers with new memory. 53 * 54 * The management in the driver is as follows: 55 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 56 * When the interrupt handler is called, the request is processed. 57 * The page is either stolen - transferred to the upper layer 58 * or reused - added immediately to the iwl->rxq->rx_free list. 59 * + When the page is stolen - the driver updates the matching queue's used 60 * count, detaches the RBD and transfers it to the queue used list. 61 * When there are two used RBDs - they are transferred to the allocator empty 62 * list. Work is then scheduled for the allocator to start allocating 63 * eight buffers. 64 * When there are another 6 used RBDs - they are transferred to the allocator 65 * empty list and the driver tries to claim the pre-allocated buffers and 66 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 67 * until ready. 68 * When there are 8+ buffers in the free list - either from allocation or from 69 * 8 reused unstolen pages - restock is called to update the FW and indexes. 70 * + In order to make sure the allocator always has RBDs to use for allocation 71 * the allocator has initial pool in the size of num_queues*(8-2) - the 72 * maximum missing RBDs per allocation request (request posted with 2 73 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 74 * The queues supplies the recycle of the rest of the RBDs. 75 * + A received packet is processed and handed to the kernel network stack, 76 * detached from the iwl->rxq. The driver 'processed' index is updated. 77 * + If there are no allocated buffers in iwl->rxq->rx_free, 78 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 79 * If there were enough free buffers and RX_STALLED is set it is cleared. 80 * 81 * 82 * Driver sequence: 83 * 84 * iwl_rxq_alloc() Allocates rx_free 85 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 86 * iwl_pcie_rxq_restock. 87 * Used only during initialization. 88 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 89 * queue, updates firmware pointers, and updates 90 * the WRITE index. 91 * iwl_pcie_rx_allocator() Background work for allocating pages. 92 * 93 * -- enable interrupts -- 94 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 95 * READ INDEX, detaching the SKB from the pool. 96 * Moves the packet buffer from queue to rx_used. 97 * Posts and claims requests to the allocator. 98 * Calls iwl_pcie_rxq_restock to refill any empty 99 * slots. 100 * 101 * RBD life-cycle: 102 * 103 * Init: 104 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 105 * 106 * Regular Receive interrupt: 107 * Page Stolen: 108 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 109 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 110 * Page not Stolen: 111 * rxq.queue -> rxq.rx_free -> rxq.queue 112 * ... 113 * 114 */ 115 116 /* 117 * iwl_rxq_space - Return number of free slots available in queue. 118 */ 119 static int iwl_rxq_space(const struct iwl_rxq *rxq) 120 { 121 /* Make sure rx queue size is a power of 2 */ 122 WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 123 124 /* 125 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 126 * between empty and completely full queues. 127 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 128 * defined for negative dividends. 129 */ 130 return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 131 } 132 133 /* 134 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 135 */ 136 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 137 { 138 return cpu_to_le32((u32)(dma_addr >> 8)); 139 } 140 141 /* 142 * iwl_pcie_rx_stop - stops the Rx DMA 143 */ 144 int iwl_pcie_rx_stop(struct iwl_trans *trans) 145 { 146 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 147 /* TODO: remove this once fw does it */ 148 iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 149 return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3, 150 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 151 } else if (trans->trans_cfg->mq_rx_supported) { 152 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 153 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 154 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 155 } else { 156 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 157 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 158 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 159 1000); 160 } 161 } 162 163 /* 164 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 165 */ 166 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 167 struct iwl_rxq *rxq) 168 { 169 u32 reg; 170 171 lockdep_assert_held(&rxq->lock); 172 173 /* 174 * explicitly wake up the NIC if: 175 * 1. shadow registers aren't enabled 176 * 2. there is a chance that the NIC is asleep 177 */ 178 if (!trans->trans_cfg->base_params->shadow_reg_enable && 179 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 180 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 181 182 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 183 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 184 reg); 185 iwl_set_bit(trans, CSR_GP_CNTRL, 186 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 187 rxq->need_update = true; 188 return; 189 } 190 } 191 192 rxq->write_actual = round_down(rxq->write, 8); 193 if (trans->trans_cfg->mq_rx_supported) 194 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 195 rxq->write_actual); 196 else 197 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 198 } 199 200 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 201 { 202 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 203 int i; 204 205 for (i = 0; i < trans->num_rx_queues; i++) { 206 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 207 208 if (!rxq->need_update) 209 continue; 210 spin_lock_bh(&rxq->lock); 211 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 212 rxq->need_update = false; 213 spin_unlock_bh(&rxq->lock); 214 } 215 } 216 217 static void iwl_pcie_restock_bd(struct iwl_trans *trans, 218 struct iwl_rxq *rxq, 219 struct iwl_rx_mem_buffer *rxb) 220 { 221 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 222 struct iwl_rx_transfer_desc *bd = rxq->bd; 223 224 BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64)); 225 226 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 227 bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 228 } else { 229 __le64 *bd = rxq->bd; 230 231 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 232 } 233 234 IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n", 235 (u32)rxb->vid, rxq->id, rxq->write); 236 } 237 238 /* 239 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 240 */ 241 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 242 struct iwl_rxq *rxq) 243 { 244 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 245 struct iwl_rx_mem_buffer *rxb; 246 247 /* 248 * If the device isn't enabled - no need to try to add buffers... 249 * This can happen when we stop the device and still have an interrupt 250 * pending. We stop the APM before we sync the interrupts because we 251 * have to (see comment there). On the other hand, since the APM is 252 * stopped, we cannot access the HW (in particular not prph). 253 * So don't try to restock if the APM has been already stopped. 254 */ 255 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 256 return; 257 258 spin_lock_bh(&rxq->lock); 259 while (rxq->free_count) { 260 /* Get next free Rx buffer, remove from free list */ 261 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 262 list); 263 list_del(&rxb->list); 264 rxb->invalid = false; 265 /* some low bits are expected to be unset (depending on hw) */ 266 WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask); 267 /* Point to Rx buffer via next RBD in circular buffer */ 268 iwl_pcie_restock_bd(trans, rxq, rxb); 269 rxq->write = (rxq->write + 1) & (rxq->queue_size - 1); 270 rxq->free_count--; 271 } 272 spin_unlock_bh(&rxq->lock); 273 274 /* 275 * If we've added more space for the firmware to place data, tell it. 276 * Increment device's write pointer in multiples of 8. 277 */ 278 if (rxq->write_actual != (rxq->write & ~0x7)) { 279 spin_lock_bh(&rxq->lock); 280 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 281 spin_unlock_bh(&rxq->lock); 282 } 283 } 284 285 /* 286 * iwl_pcie_rxsq_restock - restock implementation for single queue rx 287 */ 288 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 289 struct iwl_rxq *rxq) 290 { 291 struct iwl_rx_mem_buffer *rxb; 292 293 /* 294 * If the device isn't enabled - not need to try to add buffers... 295 * This can happen when we stop the device and still have an interrupt 296 * pending. We stop the APM before we sync the interrupts because we 297 * have to (see comment there). On the other hand, since the APM is 298 * stopped, we cannot access the HW (in particular not prph). 299 * So don't try to restock if the APM has been already stopped. 300 */ 301 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 302 return; 303 304 spin_lock_bh(&rxq->lock); 305 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 306 __le32 *bd = (__le32 *)rxq->bd; 307 /* The overwritten rxb must be a used one */ 308 rxb = rxq->queue[rxq->write]; 309 BUG_ON(rxb && rxb->page); 310 311 /* Get next free Rx buffer, remove from free list */ 312 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 313 list); 314 list_del(&rxb->list); 315 rxb->invalid = false; 316 317 /* Point to Rx buffer via next RBD in circular buffer */ 318 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 319 rxq->queue[rxq->write] = rxb; 320 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 321 rxq->free_count--; 322 } 323 spin_unlock_bh(&rxq->lock); 324 325 /* If we've added more space for the firmware to place data, tell it. 326 * Increment device's write pointer in multiples of 8. */ 327 if (rxq->write_actual != (rxq->write & ~0x7)) { 328 spin_lock_bh(&rxq->lock); 329 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 330 spin_unlock_bh(&rxq->lock); 331 } 332 } 333 334 /* 335 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 336 * 337 * If there are slots in the RX queue that need to be restocked, 338 * and we have free pre-allocated buffers, fill the ranks as much 339 * as we can, pulling from rx_free. 340 * 341 * This moves the 'write' index forward to catch up with 'processed', and 342 * also updates the memory address in the firmware to reference the new 343 * target buffer. 344 */ 345 static 346 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 347 { 348 if (trans->trans_cfg->mq_rx_supported) 349 iwl_pcie_rxmq_restock(trans, rxq); 350 else 351 iwl_pcie_rxsq_restock(trans, rxq); 352 } 353 354 /* 355 * iwl_pcie_rx_alloc_page - allocates and returns a page. 356 * 357 */ 358 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 359 u32 *offset, gfp_t priority) 360 { 361 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 362 unsigned int rbsize = iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 363 unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order; 364 struct page *page; 365 gfp_t gfp_mask = priority; 366 367 if (trans_pcie->rx_page_order > 0) 368 gfp_mask |= __GFP_COMP; 369 370 if (trans_pcie->alloc_page) { 371 spin_lock_bh(&trans_pcie->alloc_page_lock); 372 /* recheck */ 373 if (trans_pcie->alloc_page) { 374 *offset = trans_pcie->alloc_page_used; 375 page = trans_pcie->alloc_page; 376 trans_pcie->alloc_page_used += rbsize; 377 if (trans_pcie->alloc_page_used >= allocsize) 378 trans_pcie->alloc_page = NULL; 379 else 380 get_page(page); 381 spin_unlock_bh(&trans_pcie->alloc_page_lock); 382 return page; 383 } 384 spin_unlock_bh(&trans_pcie->alloc_page_lock); 385 } 386 387 /* Alloc a new receive buffer */ 388 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 389 if (!page) { 390 if (net_ratelimit()) 391 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 392 trans_pcie->rx_page_order); 393 /* 394 * Issue an error if we don't have enough pre-allocated 395 * buffers. 396 */ 397 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 398 IWL_CRIT(trans, 399 "Failed to alloc_pages\n"); 400 return NULL; 401 } 402 403 if (2 * rbsize <= allocsize) { 404 spin_lock_bh(&trans_pcie->alloc_page_lock); 405 if (!trans_pcie->alloc_page) { 406 get_page(page); 407 trans_pcie->alloc_page = page; 408 trans_pcie->alloc_page_used = rbsize; 409 } 410 spin_unlock_bh(&trans_pcie->alloc_page_lock); 411 } 412 413 *offset = 0; 414 return page; 415 } 416 417 /* 418 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 419 * 420 * A used RBD is an Rx buffer that has been given to the stack. To use it again 421 * a page must be allocated and the RBD must point to the page. This function 422 * doesn't change the HW pointer but handles the list of pages that is used by 423 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 424 * allocated buffers. 425 */ 426 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 427 struct iwl_rxq *rxq) 428 { 429 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 430 struct iwl_rx_mem_buffer *rxb; 431 struct page *page; 432 433 while (1) { 434 unsigned int offset; 435 436 spin_lock_bh(&rxq->lock); 437 if (list_empty(&rxq->rx_used)) { 438 spin_unlock_bh(&rxq->lock); 439 return; 440 } 441 spin_unlock_bh(&rxq->lock); 442 443 page = iwl_pcie_rx_alloc_page(trans, &offset, priority); 444 if (!page) 445 return; 446 447 spin_lock_bh(&rxq->lock); 448 449 if (list_empty(&rxq->rx_used)) { 450 spin_unlock_bh(&rxq->lock); 451 __free_pages(page, trans_pcie->rx_page_order); 452 return; 453 } 454 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 455 list); 456 list_del(&rxb->list); 457 spin_unlock_bh(&rxq->lock); 458 459 BUG_ON(rxb->page); 460 rxb->page = page; 461 rxb->offset = offset; 462 /* Get physical address of the RB */ 463 rxb->page_dma = 464 dma_map_page(trans->dev, page, rxb->offset, 465 trans_pcie->rx_buf_bytes, 466 DMA_FROM_DEVICE); 467 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 468 rxb->page = NULL; 469 spin_lock_bh(&rxq->lock); 470 list_add(&rxb->list, &rxq->rx_used); 471 spin_unlock_bh(&rxq->lock); 472 __free_pages(page, trans_pcie->rx_page_order); 473 return; 474 } 475 476 spin_lock_bh(&rxq->lock); 477 478 list_add_tail(&rxb->list, &rxq->rx_free); 479 rxq->free_count++; 480 481 spin_unlock_bh(&rxq->lock); 482 } 483 } 484 485 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 486 { 487 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 488 int i; 489 490 for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) { 491 if (!trans_pcie->rx_pool[i].page) 492 continue; 493 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 494 trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE); 495 __free_pages(trans_pcie->rx_pool[i].page, 496 trans_pcie->rx_page_order); 497 trans_pcie->rx_pool[i].page = NULL; 498 } 499 } 500 501 /* 502 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 503 * 504 * Allocates for each received request 8 pages 505 * Called as a scheduled work item. 506 */ 507 static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 508 { 509 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 510 struct iwl_rb_allocator *rba = &trans_pcie->rba; 511 struct list_head local_empty; 512 int pending = atomic_read(&rba->req_pending); 513 514 IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending); 515 516 /* If we were scheduled - there is at least one request */ 517 spin_lock_bh(&rba->lock); 518 /* swap out the rba->rbd_empty to a local list */ 519 list_replace_init(&rba->rbd_empty, &local_empty); 520 spin_unlock_bh(&rba->lock); 521 522 while (pending) { 523 int i; 524 LIST_HEAD(local_allocated); 525 gfp_t gfp_mask = GFP_KERNEL; 526 527 /* Do not post a warning if there are only a few requests */ 528 if (pending < RX_PENDING_WATERMARK) 529 gfp_mask |= __GFP_NOWARN; 530 531 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 532 struct iwl_rx_mem_buffer *rxb; 533 struct page *page; 534 535 /* List should never be empty - each reused RBD is 536 * returned to the list, and initial pool covers any 537 * possible gap between the time the page is allocated 538 * to the time the RBD is added. 539 */ 540 BUG_ON(list_empty(&local_empty)); 541 /* Get the first rxb from the rbd list */ 542 rxb = list_first_entry(&local_empty, 543 struct iwl_rx_mem_buffer, list); 544 BUG_ON(rxb->page); 545 546 /* Alloc a new receive buffer */ 547 page = iwl_pcie_rx_alloc_page(trans, &rxb->offset, 548 gfp_mask); 549 if (!page) 550 continue; 551 rxb->page = page; 552 553 /* Get physical address of the RB */ 554 rxb->page_dma = dma_map_page(trans->dev, page, 555 rxb->offset, 556 trans_pcie->rx_buf_bytes, 557 DMA_FROM_DEVICE); 558 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 559 rxb->page = NULL; 560 __free_pages(page, trans_pcie->rx_page_order); 561 continue; 562 } 563 564 /* move the allocated entry to the out list */ 565 list_move(&rxb->list, &local_allocated); 566 i++; 567 } 568 569 atomic_dec(&rba->req_pending); 570 pending--; 571 572 if (!pending) { 573 pending = atomic_read(&rba->req_pending); 574 if (pending) 575 IWL_DEBUG_TPT(trans, 576 "Got more pending allocation requests = %d\n", 577 pending); 578 } 579 580 spin_lock_bh(&rba->lock); 581 /* add the allocated rbds to the allocator allocated list */ 582 list_splice_tail(&local_allocated, &rba->rbd_allocated); 583 /* get more empty RBDs for current pending requests */ 584 list_splice_tail_init(&rba->rbd_empty, &local_empty); 585 spin_unlock_bh(&rba->lock); 586 587 atomic_inc(&rba->req_ready); 588 589 } 590 591 spin_lock_bh(&rba->lock); 592 /* return unused rbds to the allocator empty list */ 593 list_splice_tail(&local_empty, &rba->rbd_empty); 594 spin_unlock_bh(&rba->lock); 595 596 IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__); 597 } 598 599 /* 600 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 601 .* 602 .* Called by queue when the queue posted allocation request and 603 * has freed 8 RBDs in order to restock itself. 604 * This function directly moves the allocated RBs to the queue's ownership 605 * and updates the relevant counters. 606 */ 607 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 608 struct iwl_rxq *rxq) 609 { 610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 611 struct iwl_rb_allocator *rba = &trans_pcie->rba; 612 int i; 613 614 lockdep_assert_held(&rxq->lock); 615 616 /* 617 * atomic_dec_if_positive returns req_ready - 1 for any scenario. 618 * If req_ready is 0 atomic_dec_if_positive will return -1 and this 619 * function will return early, as there are no ready requests. 620 * atomic_dec_if_positive will perofrm the *actual* decrement only if 621 * req_ready > 0, i.e. - there are ready requests and the function 622 * hands one request to the caller. 623 */ 624 if (atomic_dec_if_positive(&rba->req_ready) < 0) 625 return; 626 627 spin_lock(&rba->lock); 628 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 629 /* Get next free Rx buffer, remove it from free list */ 630 struct iwl_rx_mem_buffer *rxb = 631 list_first_entry(&rba->rbd_allocated, 632 struct iwl_rx_mem_buffer, list); 633 634 list_move(&rxb->list, &rxq->rx_free); 635 } 636 spin_unlock(&rba->lock); 637 638 rxq->used_count -= RX_CLAIM_REQ_ALLOC; 639 rxq->free_count += RX_CLAIM_REQ_ALLOC; 640 } 641 642 void iwl_pcie_rx_allocator_work(struct work_struct *data) 643 { 644 struct iwl_rb_allocator *rba_p = 645 container_of(data, struct iwl_rb_allocator, rx_alloc); 646 struct iwl_trans_pcie *trans_pcie = 647 container_of(rba_p, struct iwl_trans_pcie, rba); 648 649 iwl_pcie_rx_allocator(trans_pcie->trans); 650 } 651 652 static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td) 653 { 654 struct iwl_rx_transfer_desc *rx_td; 655 656 if (use_rx_td) 657 return sizeof(*rx_td); 658 else 659 return trans->trans_cfg->mq_rx_supported ? sizeof(__le64) : 660 sizeof(__le32); 661 } 662 663 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 664 struct iwl_rxq *rxq) 665 { 666 bool use_rx_td = (trans->trans_cfg->device_family >= 667 IWL_DEVICE_FAMILY_AX210); 668 int free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 669 670 if (rxq->bd) 671 dma_free_coherent(trans->dev, 672 free_size * rxq->queue_size, 673 rxq->bd, rxq->bd_dma); 674 rxq->bd_dma = 0; 675 rxq->bd = NULL; 676 677 rxq->rb_stts_dma = 0; 678 rxq->rb_stts = NULL; 679 680 if (rxq->used_bd) 681 dma_free_coherent(trans->dev, 682 (use_rx_td ? sizeof(*rxq->cd) : 683 sizeof(__le32)) * rxq->queue_size, 684 rxq->used_bd, rxq->used_bd_dma); 685 rxq->used_bd_dma = 0; 686 rxq->used_bd = NULL; 687 } 688 689 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 690 struct iwl_rxq *rxq) 691 { 692 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 693 struct device *dev = trans->dev; 694 int i; 695 int free_size; 696 bool use_rx_td = (trans->trans_cfg->device_family >= 697 IWL_DEVICE_FAMILY_AX210); 698 size_t rb_stts_size = use_rx_td ? sizeof(__le16) : 699 sizeof(struct iwl_rb_status); 700 701 spin_lock_init(&rxq->lock); 702 if (trans->trans_cfg->mq_rx_supported) 703 rxq->queue_size = trans->cfg->num_rbds; 704 else 705 rxq->queue_size = RX_QUEUE_SIZE; 706 707 free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 708 709 /* 710 * Allocate the circular buffer of Read Buffer Descriptors 711 * (RBDs) 712 */ 713 rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size, 714 &rxq->bd_dma, GFP_KERNEL); 715 if (!rxq->bd) 716 goto err; 717 718 if (trans->trans_cfg->mq_rx_supported) { 719 rxq->used_bd = dma_alloc_coherent(dev, 720 (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size, 721 &rxq->used_bd_dma, 722 GFP_KERNEL); 723 if (!rxq->used_bd) 724 goto err; 725 } 726 727 rxq->rb_stts = trans_pcie->base_rb_stts + rxq->id * rb_stts_size; 728 rxq->rb_stts_dma = 729 trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size; 730 731 return 0; 732 733 err: 734 for (i = 0; i < trans->num_rx_queues; i++) { 735 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 736 737 iwl_pcie_free_rxq_dma(trans, rxq); 738 } 739 740 return -ENOMEM; 741 } 742 743 static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 744 { 745 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 746 struct iwl_rb_allocator *rba = &trans_pcie->rba; 747 int i, ret; 748 size_t rb_stts_size = trans->trans_cfg->device_family >= 749 IWL_DEVICE_FAMILY_AX210 ? 750 sizeof(__le16) : sizeof(struct iwl_rb_status); 751 752 if (WARN_ON(trans_pcie->rxq)) 753 return -EINVAL; 754 755 trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 756 GFP_KERNEL); 757 trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 758 sizeof(trans_pcie->rx_pool[0]), 759 GFP_KERNEL); 760 trans_pcie->global_table = 761 kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 762 sizeof(trans_pcie->global_table[0]), 763 GFP_KERNEL); 764 if (!trans_pcie->rxq || !trans_pcie->rx_pool || 765 !trans_pcie->global_table) { 766 ret = -ENOMEM; 767 goto err; 768 } 769 770 spin_lock_init(&rba->lock); 771 772 /* 773 * Allocate the driver's pointer to receive buffer status. 774 * Allocate for all queues continuously (HW requirement). 775 */ 776 trans_pcie->base_rb_stts = 777 dma_alloc_coherent(trans->dev, 778 rb_stts_size * trans->num_rx_queues, 779 &trans_pcie->base_rb_stts_dma, 780 GFP_KERNEL); 781 if (!trans_pcie->base_rb_stts) { 782 ret = -ENOMEM; 783 goto err; 784 } 785 786 for (i = 0; i < trans->num_rx_queues; i++) { 787 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 788 789 rxq->id = i; 790 ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 791 if (ret) 792 goto err; 793 } 794 return 0; 795 796 err: 797 if (trans_pcie->base_rb_stts) { 798 dma_free_coherent(trans->dev, 799 rb_stts_size * trans->num_rx_queues, 800 trans_pcie->base_rb_stts, 801 trans_pcie->base_rb_stts_dma); 802 trans_pcie->base_rb_stts = NULL; 803 trans_pcie->base_rb_stts_dma = 0; 804 } 805 kfree(trans_pcie->rx_pool); 806 trans_pcie->rx_pool = NULL; 807 kfree(trans_pcie->global_table); 808 trans_pcie->global_table = NULL; 809 kfree(trans_pcie->rxq); 810 trans_pcie->rxq = NULL; 811 812 return ret; 813 } 814 815 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 816 { 817 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 818 u32 rb_size; 819 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 820 821 switch (trans_pcie->rx_buf_size) { 822 case IWL_AMSDU_4K: 823 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 824 break; 825 case IWL_AMSDU_8K: 826 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 827 break; 828 case IWL_AMSDU_12K: 829 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 830 break; 831 default: 832 WARN_ON(1); 833 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 834 } 835 836 if (!iwl_trans_grab_nic_access(trans)) 837 return; 838 839 /* Stop Rx DMA */ 840 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 841 /* reset and flush pointers */ 842 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 843 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 844 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 845 846 /* Reset driver's Rx queue write index */ 847 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 848 849 /* Tell device where to find RBD circular buffer in DRAM */ 850 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 851 (u32)(rxq->bd_dma >> 8)); 852 853 /* Tell device where in DRAM to update its Rx status */ 854 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 855 rxq->rb_stts_dma >> 4); 856 857 /* Enable Rx DMA 858 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 859 * the credit mechanism in 5000 HW RX FIFO 860 * Direct rx interrupts to hosts 861 * Rx buffer size 4 or 8k or 12k 862 * RB timeout 0x10 863 * 256 RBDs 864 */ 865 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 866 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 867 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 868 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 869 rb_size | 870 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 871 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 872 873 iwl_trans_release_nic_access(trans); 874 875 /* Set interrupt coalescing timer to default (2048 usecs) */ 876 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 877 878 /* W/A for interrupt coalescing bug in 7260 and 3160 */ 879 if (trans->cfg->host_interrupt_operation_mode) 880 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 881 } 882 883 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 884 { 885 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 886 u32 rb_size, enabled = 0; 887 int i; 888 889 switch (trans_pcie->rx_buf_size) { 890 case IWL_AMSDU_2K: 891 rb_size = RFH_RXF_DMA_RB_SIZE_2K; 892 break; 893 case IWL_AMSDU_4K: 894 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 895 break; 896 case IWL_AMSDU_8K: 897 rb_size = RFH_RXF_DMA_RB_SIZE_8K; 898 break; 899 case IWL_AMSDU_12K: 900 rb_size = RFH_RXF_DMA_RB_SIZE_12K; 901 break; 902 default: 903 WARN_ON(1); 904 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 905 } 906 907 if (!iwl_trans_grab_nic_access(trans)) 908 return; 909 910 /* Stop Rx DMA */ 911 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 912 /* disable free amd used rx queue operation */ 913 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 914 915 for (i = 0; i < trans->num_rx_queues; i++) { 916 /* Tell device where to find RBD free table in DRAM */ 917 iwl_write_prph64_no_grab(trans, 918 RFH_Q_FRBDCB_BA_LSB(i), 919 trans_pcie->rxq[i].bd_dma); 920 /* Tell device where to find RBD used table in DRAM */ 921 iwl_write_prph64_no_grab(trans, 922 RFH_Q_URBDCB_BA_LSB(i), 923 trans_pcie->rxq[i].used_bd_dma); 924 /* Tell device where in DRAM to update its Rx status */ 925 iwl_write_prph64_no_grab(trans, 926 RFH_Q_URBD_STTS_WPTR_LSB(i), 927 trans_pcie->rxq[i].rb_stts_dma); 928 /* Reset device indice tables */ 929 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 930 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 931 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 932 933 enabled |= BIT(i) | BIT(i + 16); 934 } 935 936 /* 937 * Enable Rx DMA 938 * Rx buffer size 4 or 8k or 12k 939 * Min RB size 4 or 8 940 * Drop frames that exceed RB size 941 * 512 RBDs 942 */ 943 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 944 RFH_DMA_EN_ENABLE_VAL | rb_size | 945 RFH_RXF_DMA_MIN_RB_4_8 | 946 RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 947 RFH_RXF_DMA_RBDCB_SIZE_512); 948 949 /* 950 * Activate DMA snooping. 951 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 952 * Default queue is 0 953 */ 954 iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 955 RFH_GEN_CFG_RFH_DMA_SNOOP | 956 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 957 RFH_GEN_CFG_SERVICE_DMA_SNOOP | 958 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 959 trans->trans_cfg->integrated ? 960 RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 961 RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 962 /* Enable the relevant rx queues */ 963 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 964 965 iwl_trans_release_nic_access(trans); 966 967 /* Set interrupt coalescing timer to default (2048 usecs) */ 968 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 969 } 970 971 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 972 { 973 lockdep_assert_held(&rxq->lock); 974 975 INIT_LIST_HEAD(&rxq->rx_free); 976 INIT_LIST_HEAD(&rxq->rx_used); 977 rxq->free_count = 0; 978 rxq->used_count = 0; 979 } 980 981 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget); 982 983 static int iwl_pcie_napi_poll(struct napi_struct *napi, int budget) 984 { 985 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 986 struct iwl_trans_pcie *trans_pcie; 987 struct iwl_trans *trans; 988 int ret; 989 990 trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 991 trans = trans_pcie->trans; 992 993 ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 994 995 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", 996 rxq->id, ret, budget); 997 998 if (ret < budget) { 999 spin_lock(&trans_pcie->irq_lock); 1000 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1001 _iwl_enable_interrupts(trans); 1002 spin_unlock(&trans_pcie->irq_lock); 1003 1004 napi_complete_done(&rxq->napi, ret); 1005 } 1006 1007 return ret; 1008 } 1009 1010 static int iwl_pcie_napi_poll_msix(struct napi_struct *napi, int budget) 1011 { 1012 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 1013 struct iwl_trans_pcie *trans_pcie; 1014 struct iwl_trans *trans; 1015 int ret; 1016 1017 trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 1018 trans = trans_pcie->trans; 1019 1020 ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 1021 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", rxq->id, ret, 1022 budget); 1023 1024 if (ret < budget) { 1025 int irq_line = rxq->id; 1026 1027 /* FIRST_RSS is shared with line 0 */ 1028 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS && 1029 rxq->id == 1) 1030 irq_line = 0; 1031 1032 spin_lock(&trans_pcie->irq_lock); 1033 iwl_pcie_clear_irq(trans, irq_line); 1034 spin_unlock(&trans_pcie->irq_lock); 1035 1036 napi_complete_done(&rxq->napi, ret); 1037 } 1038 1039 return ret; 1040 } 1041 1042 static int _iwl_pcie_rx_init(struct iwl_trans *trans) 1043 { 1044 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1045 struct iwl_rxq *def_rxq; 1046 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1047 int i, err, queue_size, allocator_pool_size, num_alloc; 1048 1049 if (!trans_pcie->rxq) { 1050 err = iwl_pcie_rx_alloc(trans); 1051 if (err) 1052 return err; 1053 } 1054 def_rxq = trans_pcie->rxq; 1055 1056 cancel_work_sync(&rba->rx_alloc); 1057 1058 spin_lock_bh(&rba->lock); 1059 atomic_set(&rba->req_pending, 0); 1060 atomic_set(&rba->req_ready, 0); 1061 INIT_LIST_HEAD(&rba->rbd_allocated); 1062 INIT_LIST_HEAD(&rba->rbd_empty); 1063 spin_unlock_bh(&rba->lock); 1064 1065 /* free all first - we might be reconfigured for a different size */ 1066 iwl_pcie_free_rbs_pool(trans); 1067 1068 for (i = 0; i < RX_QUEUE_SIZE; i++) 1069 def_rxq->queue[i] = NULL; 1070 1071 for (i = 0; i < trans->num_rx_queues; i++) { 1072 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1073 1074 spin_lock_bh(&rxq->lock); 1075 /* 1076 * Set read write pointer to reflect that we have processed 1077 * and used all buffers, but have not restocked the Rx queue 1078 * with fresh buffers 1079 */ 1080 rxq->read = 0; 1081 rxq->write = 0; 1082 rxq->write_actual = 0; 1083 memset(rxq->rb_stts, 0, 1084 (trans->trans_cfg->device_family >= 1085 IWL_DEVICE_FAMILY_AX210) ? 1086 sizeof(__le16) : sizeof(struct iwl_rb_status)); 1087 1088 iwl_pcie_rx_init_rxb_lists(rxq); 1089 1090 spin_unlock_bh(&rxq->lock); 1091 1092 if (!rxq->napi.poll) { 1093 int (*poll)(struct napi_struct *, int) = iwl_pcie_napi_poll; 1094 1095 if (trans_pcie->msix_enabled) 1096 poll = iwl_pcie_napi_poll_msix; 1097 1098 netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 1099 poll, NAPI_POLL_WEIGHT); 1100 napi_enable(&rxq->napi); 1101 } 1102 1103 } 1104 1105 /* move the pool to the default queue and allocator ownerships */ 1106 queue_size = trans->trans_cfg->mq_rx_supported ? 1107 trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE; 1108 allocator_pool_size = trans->num_rx_queues * 1109 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 1110 num_alloc = queue_size + allocator_pool_size; 1111 1112 for (i = 0; i < num_alloc; i++) { 1113 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 1114 1115 if (i < allocator_pool_size) 1116 list_add(&rxb->list, &rba->rbd_empty); 1117 else 1118 list_add(&rxb->list, &def_rxq->rx_used); 1119 trans_pcie->global_table[i] = rxb; 1120 rxb->vid = (u16)(i + 1); 1121 rxb->invalid = true; 1122 } 1123 1124 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 1125 1126 return 0; 1127 } 1128 1129 int iwl_pcie_rx_init(struct iwl_trans *trans) 1130 { 1131 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1132 int ret = _iwl_pcie_rx_init(trans); 1133 1134 if (ret) 1135 return ret; 1136 1137 if (trans->trans_cfg->mq_rx_supported) 1138 iwl_pcie_rx_mq_hw_init(trans); 1139 else 1140 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 1141 1142 iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 1143 1144 spin_lock_bh(&trans_pcie->rxq->lock); 1145 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 1146 spin_unlock_bh(&trans_pcie->rxq->lock); 1147 1148 return 0; 1149 } 1150 1151 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1152 { 1153 /* Set interrupt coalescing timer to default (2048 usecs) */ 1154 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1155 1156 /* 1157 * We don't configure the RFH. 1158 * Restock will be done at alive, after firmware configured the RFH. 1159 */ 1160 return _iwl_pcie_rx_init(trans); 1161 } 1162 1163 void iwl_pcie_rx_free(struct iwl_trans *trans) 1164 { 1165 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1166 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1167 int i; 1168 size_t rb_stts_size = trans->trans_cfg->device_family >= 1169 IWL_DEVICE_FAMILY_AX210 ? 1170 sizeof(__le16) : sizeof(struct iwl_rb_status); 1171 1172 /* 1173 * if rxq is NULL, it means that nothing has been allocated, 1174 * exit now 1175 */ 1176 if (!trans_pcie->rxq) { 1177 IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1178 return; 1179 } 1180 1181 cancel_work_sync(&rba->rx_alloc); 1182 1183 iwl_pcie_free_rbs_pool(trans); 1184 1185 if (trans_pcie->base_rb_stts) { 1186 dma_free_coherent(trans->dev, 1187 rb_stts_size * trans->num_rx_queues, 1188 trans_pcie->base_rb_stts, 1189 trans_pcie->base_rb_stts_dma); 1190 trans_pcie->base_rb_stts = NULL; 1191 trans_pcie->base_rb_stts_dma = 0; 1192 } 1193 1194 for (i = 0; i < trans->num_rx_queues; i++) { 1195 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1196 1197 iwl_pcie_free_rxq_dma(trans, rxq); 1198 1199 if (rxq->napi.poll) { 1200 napi_disable(&rxq->napi); 1201 netif_napi_del(&rxq->napi); 1202 } 1203 } 1204 kfree(trans_pcie->rx_pool); 1205 kfree(trans_pcie->global_table); 1206 kfree(trans_pcie->rxq); 1207 1208 if (trans_pcie->alloc_page) 1209 __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order); 1210 } 1211 1212 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq, 1213 struct iwl_rb_allocator *rba) 1214 { 1215 spin_lock(&rba->lock); 1216 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1217 spin_unlock(&rba->lock); 1218 } 1219 1220 /* 1221 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1222 * 1223 * Called when a RBD can be reused. The RBD is transferred to the allocator. 1224 * When there are 2 empty RBDs - a request for allocation is posted 1225 */ 1226 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1227 struct iwl_rx_mem_buffer *rxb, 1228 struct iwl_rxq *rxq, bool emergency) 1229 { 1230 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1231 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1232 1233 /* Move the RBD to the used list, will be moved to allocator in batches 1234 * before claiming or posting a request*/ 1235 list_add_tail(&rxb->list, &rxq->rx_used); 1236 1237 if (unlikely(emergency)) 1238 return; 1239 1240 /* Count the allocator owned RBDs */ 1241 rxq->used_count++; 1242 1243 /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1244 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1245 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1246 * after but we still need to post another request. 1247 */ 1248 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1249 /* Move the 2 RBDs to the allocator ownership. 1250 Allocator has another 6 from pool for the request completion*/ 1251 iwl_pcie_rx_move_to_allocator(rxq, rba); 1252 1253 atomic_inc(&rba->req_pending); 1254 queue_work(rba->alloc_wq, &rba->rx_alloc); 1255 } 1256 } 1257 1258 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 1259 struct iwl_rxq *rxq, 1260 struct iwl_rx_mem_buffer *rxb, 1261 bool emergency, 1262 int i) 1263 { 1264 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1265 struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id]; 1266 bool page_stolen = false; 1267 int max_len = trans_pcie->rx_buf_bytes; 1268 u32 offset = 0; 1269 1270 if (WARN_ON(!rxb)) 1271 return; 1272 1273 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1274 1275 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1276 struct iwl_rx_packet *pkt; 1277 bool reclaim; 1278 int len; 1279 struct iwl_rx_cmd_buffer rxcb = { 1280 ._offset = rxb->offset + offset, 1281 ._rx_page_order = trans_pcie->rx_page_order, 1282 ._page = rxb->page, 1283 ._page_stolen = false, 1284 .truesize = max_len, 1285 }; 1286 1287 pkt = rxb_addr(&rxcb); 1288 1289 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 1290 IWL_DEBUG_RX(trans, 1291 "Q %d: RB end marker at offset %d\n", 1292 rxq->id, offset); 1293 break; 1294 } 1295 1296 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1297 FH_RSCSR_RXQ_POS != rxq->id, 1298 "frame on invalid queue - is on %d and indicates %d\n", 1299 rxq->id, 1300 (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1301 FH_RSCSR_RXQ_POS); 1302 1303 IWL_DEBUG_RX(trans, 1304 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 1305 rxq->id, offset, 1306 iwl_get_cmd_string(trans, 1307 iwl_cmd_id(pkt->hdr.cmd, 1308 pkt->hdr.group_id, 1309 0)), 1310 pkt->hdr.group_id, pkt->hdr.cmd, 1311 le16_to_cpu(pkt->hdr.sequence)); 1312 1313 len = iwl_rx_packet_len(pkt); 1314 len += sizeof(u32); /* account for status word */ 1315 1316 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1317 1318 /* check that what the device tells us made sense */ 1319 if (offset > max_len) 1320 break; 1321 1322 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1323 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1324 1325 /* Reclaim a command buffer only if this packet is a response 1326 * to a (driver-originated) command. 1327 * If the packet (e.g. Rx frame) originated from uCode, 1328 * there is no command buffer to reclaim. 1329 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1330 * but apparently a few don't get set; catch them here. */ 1331 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1332 if (reclaim && !pkt->hdr.group_id) { 1333 int i; 1334 1335 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1336 if (trans_pcie->no_reclaim_cmds[i] == 1337 pkt->hdr.cmd) { 1338 reclaim = false; 1339 break; 1340 } 1341 } 1342 } 1343 1344 if (rxq->id == trans_pcie->def_rx_queue) 1345 iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1346 &rxcb); 1347 else 1348 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1349 &rxcb, rxq->id); 1350 1351 /* 1352 * After here, we should always check rxcb._page_stolen, 1353 * if it is true then one of the handlers took the page. 1354 */ 1355 1356 if (reclaim) { 1357 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1358 int index = SEQ_TO_INDEX(sequence); 1359 int cmd_index = iwl_txq_get_cmd_index(txq, index); 1360 1361 kfree_sensitive(txq->entries[cmd_index].free_buf); 1362 txq->entries[cmd_index].free_buf = NULL; 1363 1364 /* Invoke any callbacks, transfer the buffer to caller, 1365 * and fire off the (possibly) blocking 1366 * iwl_trans_send_cmd() 1367 * as we reclaim the driver command queue */ 1368 if (!rxcb._page_stolen) 1369 iwl_pcie_hcmd_complete(trans, &rxcb); 1370 else 1371 IWL_WARN(trans, "Claim null rxb?\n"); 1372 } 1373 1374 page_stolen |= rxcb._page_stolen; 1375 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1376 break; 1377 } 1378 1379 /* page was stolen from us -- free our reference */ 1380 if (page_stolen) { 1381 __free_pages(rxb->page, trans_pcie->rx_page_order); 1382 rxb->page = NULL; 1383 } 1384 1385 /* Reuse the page if possible. For notification packets and 1386 * SKBs that fail to Rx correctly, add them back into the 1387 * rx_free list for reuse later. */ 1388 if (rxb->page != NULL) { 1389 rxb->page_dma = 1390 dma_map_page(trans->dev, rxb->page, rxb->offset, 1391 trans_pcie->rx_buf_bytes, 1392 DMA_FROM_DEVICE); 1393 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1394 /* 1395 * free the page(s) as well to not break 1396 * the invariant that the items on the used 1397 * list have no page(s) 1398 */ 1399 __free_pages(rxb->page, trans_pcie->rx_page_order); 1400 rxb->page = NULL; 1401 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1402 } else { 1403 list_add_tail(&rxb->list, &rxq->rx_free); 1404 rxq->free_count++; 1405 } 1406 } else 1407 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1408 } 1409 1410 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans, 1411 struct iwl_rxq *rxq, int i, 1412 bool *join) 1413 { 1414 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1415 struct iwl_rx_mem_buffer *rxb; 1416 u16 vid; 1417 1418 BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32); 1419 1420 if (!trans->trans_cfg->mq_rx_supported) { 1421 rxb = rxq->queue[i]; 1422 rxq->queue[i] = NULL; 1423 return rxb; 1424 } 1425 1426 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1427 vid = le16_to_cpu(rxq->cd[i].rbid); 1428 *join = rxq->cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED; 1429 } else { 1430 vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; /* 12-bit VID */ 1431 } 1432 1433 if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs)) 1434 goto out_err; 1435 1436 rxb = trans_pcie->global_table[vid - 1]; 1437 if (rxb->invalid) 1438 goto out_err; 1439 1440 IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid); 1441 1442 rxb->invalid = true; 1443 1444 return rxb; 1445 1446 out_err: 1447 WARN(1, "Invalid rxb from HW %u\n", (u32)vid); 1448 iwl_force_nmi(trans); 1449 return NULL; 1450 } 1451 1452 /* 1453 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1454 */ 1455 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget) 1456 { 1457 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1458 struct iwl_rxq *rxq; 1459 u32 r, i, count = 0, handled = 0; 1460 bool emergency = false; 1461 1462 if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd)) 1463 return budget; 1464 1465 rxq = &trans_pcie->rxq[queue]; 1466 1467 restart: 1468 spin_lock(&rxq->lock); 1469 /* uCode's read index (stored in shared DRAM) indicates the last Rx 1470 * buffer that the driver may process (last buffer filled by ucode). */ 1471 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1472 i = rxq->read; 1473 1474 /* W/A 9000 device step A0 wrap-around bug */ 1475 r &= (rxq->queue_size - 1); 1476 1477 /* Rx interrupt, but nothing sent from uCode */ 1478 if (i == r) 1479 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1480 1481 while (i != r && ++handled < budget) { 1482 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1483 struct iwl_rx_mem_buffer *rxb; 1484 /* number of RBDs still waiting for page allocation */ 1485 u32 rb_pending_alloc = 1486 atomic_read(&trans_pcie->rba.req_pending) * 1487 RX_CLAIM_REQ_ALLOC; 1488 bool join = false; 1489 1490 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 && 1491 !emergency)) { 1492 iwl_pcie_rx_move_to_allocator(rxq, rba); 1493 emergency = true; 1494 IWL_DEBUG_TPT(trans, 1495 "RX path is in emergency. Pending allocations %d\n", 1496 rb_pending_alloc); 1497 } 1498 1499 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 1500 1501 rxb = iwl_pcie_get_rxb(trans, rxq, i, &join); 1502 if (!rxb) 1503 goto out; 1504 1505 if (unlikely(join || rxq->next_rb_is_fragment)) { 1506 rxq->next_rb_is_fragment = join; 1507 /* 1508 * We can only get a multi-RB in the following cases: 1509 * - firmware issue, sending a too big notification 1510 * - sniffer mode with a large A-MSDU 1511 * - large MTU frames (>2k) 1512 * since the multi-RB functionality is limited to newer 1513 * hardware that cannot put multiple entries into a 1514 * single RB. 1515 * 1516 * Right now, the higher layers aren't set up to deal 1517 * with that, so discard all of these. 1518 */ 1519 list_add_tail(&rxb->list, &rxq->rx_free); 1520 rxq->free_count++; 1521 } else { 1522 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i); 1523 } 1524 1525 i = (i + 1) & (rxq->queue_size - 1); 1526 1527 /* 1528 * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1529 * try to claim the pre-allocated buffers from the allocator. 1530 * If not ready - will try to reclaim next time. 1531 * There is no need to reschedule work - allocator exits only 1532 * on success 1533 */ 1534 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1535 iwl_pcie_rx_allocator_get(trans, rxq); 1536 1537 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1538 /* Add the remaining empty RBDs for allocator use */ 1539 iwl_pcie_rx_move_to_allocator(rxq, rba); 1540 } else if (emergency) { 1541 count++; 1542 if (count == 8) { 1543 count = 0; 1544 if (rb_pending_alloc < rxq->queue_size / 3) { 1545 IWL_DEBUG_TPT(trans, 1546 "RX path exited emergency. Pending allocations %d\n", 1547 rb_pending_alloc); 1548 emergency = false; 1549 } 1550 1551 rxq->read = i; 1552 spin_unlock(&rxq->lock); 1553 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1554 iwl_pcie_rxq_restock(trans, rxq); 1555 goto restart; 1556 } 1557 } 1558 } 1559 out: 1560 /* Backtrack one entry */ 1561 rxq->read = i; 1562 spin_unlock(&rxq->lock); 1563 1564 /* 1565 * handle a case where in emergency there are some unallocated RBDs. 1566 * those RBDs are in the used list, but are not tracked by the queue's 1567 * used_count which counts allocator owned RBDs. 1568 * unallocated emergency RBDs must be allocated on exit, otherwise 1569 * when called again the function may not be in emergency mode and 1570 * they will be handed to the allocator with no tracking in the RBD 1571 * allocator counters, which will lead to them never being claimed back 1572 * by the queue. 1573 * by allocating them here, they are now in the queue free list, and 1574 * will be restocked by the next call of iwl_pcie_rxq_restock. 1575 */ 1576 if (unlikely(emergency && count)) 1577 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1578 1579 iwl_pcie_rxq_restock(trans, rxq); 1580 1581 return handled; 1582 } 1583 1584 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 1585 { 1586 u8 queue = entry->entry; 1587 struct msix_entry *entries = entry - queue; 1588 1589 return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 1590 } 1591 1592 /* 1593 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 1594 * This interrupt handler should be used with RSS queue only. 1595 */ 1596 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 1597 { 1598 struct msix_entry *entry = dev_id; 1599 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 1600 struct iwl_trans *trans = trans_pcie->trans; 1601 struct iwl_rxq *rxq = &trans_pcie->rxq[entry->entry]; 1602 1603 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1604 1605 if (WARN_ON(entry->entry >= trans->num_rx_queues)) 1606 return IRQ_NONE; 1607 1608 if (WARN_ONCE(!rxq, 1609 "[%d] Got MSI-X interrupt before we have Rx queues", 1610 entry->entry)) 1611 return IRQ_NONE; 1612 1613 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1614 IWL_DEBUG_ISR(trans, "[%d] Got interrupt\n", entry->entry); 1615 1616 local_bh_disable(); 1617 if (napi_schedule_prep(&rxq->napi)) 1618 __napi_schedule(&rxq->napi); 1619 else 1620 iwl_pcie_clear_irq(trans, entry->entry); 1621 local_bh_enable(); 1622 1623 lock_map_release(&trans->sync_cmd_lockdep_map); 1624 1625 return IRQ_HANDLED; 1626 } 1627 1628 /* 1629 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1630 */ 1631 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1632 { 1633 int i; 1634 1635 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1636 if (trans->cfg->internal_wimax_coex && 1637 !trans->cfg->apmg_not_supported && 1638 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1639 APMS_CLK_VAL_MRB_FUNC_MODE) || 1640 (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1641 APMG_PS_CTRL_VAL_RESET_REQ))) { 1642 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1643 iwl_op_mode_wimax_active(trans->op_mode); 1644 wake_up(&trans->wait_command_queue); 1645 return; 1646 } 1647 1648 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 1649 if (!trans->txqs.txq[i]) 1650 continue; 1651 del_timer(&trans->txqs.txq[i]->stuck_timer); 1652 } 1653 1654 /* The STATUS_FW_ERROR bit is set in this function. This must happen 1655 * before we wake up the command caller, to ensure a proper cleanup. */ 1656 iwl_trans_fw_error(trans); 1657 1658 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1659 wake_up(&trans->wait_command_queue); 1660 } 1661 1662 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1663 { 1664 u32 inta; 1665 1666 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1667 1668 trace_iwlwifi_dev_irq(trans->dev); 1669 1670 /* Discover which interrupts are active/pending */ 1671 inta = iwl_read32(trans, CSR_INT); 1672 1673 /* the thread will service interrupts and re-enable them */ 1674 return inta; 1675 } 1676 1677 /* a device (PCI-E) page is 4096 bytes long */ 1678 #define ICT_SHIFT 12 1679 #define ICT_SIZE (1 << ICT_SHIFT) 1680 #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1681 1682 /* interrupt handler using ict table, with this interrupt driver will 1683 * stop using INTA register to get device's interrupt, reading this register 1684 * is expensive, device will write interrupts in ICT dram table, increment 1685 * index then will fire interrupt to driver, driver will OR all ICT table 1686 * entries from current index up to table entry with 0 value. the result is 1687 * the interrupt we need to service, driver will set the entries back to 0 and 1688 * set index. 1689 */ 1690 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1691 { 1692 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1693 u32 inta; 1694 u32 val = 0; 1695 u32 read; 1696 1697 trace_iwlwifi_dev_irq(trans->dev); 1698 1699 /* Ignore interrupt if there's nothing in NIC to service. 1700 * This may be due to IRQ shared with another device, 1701 * or due to sporadic interrupts thrown from our NIC. */ 1702 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1703 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1704 if (!read) 1705 return 0; 1706 1707 /* 1708 * Collect all entries up to the first 0, starting from ict_index; 1709 * note we already read at ict_index. 1710 */ 1711 do { 1712 val |= read; 1713 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1714 trans_pcie->ict_index, read); 1715 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1716 trans_pcie->ict_index = 1717 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1718 1719 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1720 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1721 read); 1722 } while (read); 1723 1724 /* We should not get this value, just ignore it. */ 1725 if (val == 0xffffffff) 1726 val = 0; 1727 1728 /* 1729 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1730 * (bit 15 before shifting it to 31) to clear when using interrupt 1731 * coalescing. fortunately, bits 18 and 19 stay set when this happens 1732 * so we use them to decide on the real state of the Rx bit. 1733 * In order words, bit 15 is set if bit 18 or bit 19 are set. 1734 */ 1735 if (val & 0xC0000) 1736 val |= 0x8000; 1737 1738 inta = (0xff & val) | ((0xff00 & val) << 16); 1739 return inta; 1740 } 1741 1742 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 1743 { 1744 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1745 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1746 bool hw_rfkill, prev, report; 1747 1748 mutex_lock(&trans_pcie->mutex); 1749 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1750 hw_rfkill = iwl_is_rfkill_set(trans); 1751 if (hw_rfkill) { 1752 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1753 set_bit(STATUS_RFKILL_HW, &trans->status); 1754 } 1755 if (trans_pcie->opmode_down) 1756 report = hw_rfkill; 1757 else 1758 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1759 1760 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 1761 hw_rfkill ? "disable radio" : "enable radio"); 1762 1763 isr_stats->rfkill++; 1764 1765 if (prev != report) 1766 iwl_trans_pcie_rf_kill(trans, report); 1767 mutex_unlock(&trans_pcie->mutex); 1768 1769 if (hw_rfkill) { 1770 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 1771 &trans->status)) 1772 IWL_DEBUG_RF_KILL(trans, 1773 "Rfkill while SYNC HCMD in flight\n"); 1774 wake_up(&trans->wait_command_queue); 1775 } else { 1776 clear_bit(STATUS_RFKILL_HW, &trans->status); 1777 if (trans_pcie->opmode_down) 1778 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1779 } 1780 } 1781 1782 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1783 { 1784 struct iwl_trans *trans = dev_id; 1785 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1786 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1787 u32 inta = 0; 1788 u32 handled = 0; 1789 bool polling = false; 1790 1791 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1792 1793 spin_lock_bh(&trans_pcie->irq_lock); 1794 1795 /* dram interrupt table not set yet, 1796 * use legacy interrupt. 1797 */ 1798 if (likely(trans_pcie->use_ict)) 1799 inta = iwl_pcie_int_cause_ict(trans); 1800 else 1801 inta = iwl_pcie_int_cause_non_ict(trans); 1802 1803 if (iwl_have_debug_level(IWL_DL_ISR)) { 1804 IWL_DEBUG_ISR(trans, 1805 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1806 inta, trans_pcie->inta_mask, 1807 iwl_read32(trans, CSR_INT_MASK), 1808 iwl_read32(trans, CSR_FH_INT_STATUS)); 1809 if (inta & (~trans_pcie->inta_mask)) 1810 IWL_DEBUG_ISR(trans, 1811 "We got a masked interrupt (0x%08x)\n", 1812 inta & (~trans_pcie->inta_mask)); 1813 } 1814 1815 inta &= trans_pcie->inta_mask; 1816 1817 /* 1818 * Ignore interrupt if there's nothing in NIC to service. 1819 * This may be due to IRQ shared with another device, 1820 * or due to sporadic interrupts thrown from our NIC. 1821 */ 1822 if (unlikely(!inta)) { 1823 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1824 /* 1825 * Re-enable interrupts here since we don't 1826 * have anything to service 1827 */ 1828 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1829 _iwl_enable_interrupts(trans); 1830 spin_unlock_bh(&trans_pcie->irq_lock); 1831 lock_map_release(&trans->sync_cmd_lockdep_map); 1832 return IRQ_NONE; 1833 } 1834 1835 if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1836 /* 1837 * Hardware disappeared. It might have 1838 * already raised an interrupt. 1839 */ 1840 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1841 spin_unlock_bh(&trans_pcie->irq_lock); 1842 goto out; 1843 } 1844 1845 /* Ack/clear/reset pending uCode interrupts. 1846 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1847 */ 1848 /* There is a hardware bug in the interrupt mask function that some 1849 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1850 * they are disabled in the CSR_INT_MASK register. Furthermore the 1851 * ICT interrupt handling mechanism has another bug that might cause 1852 * these unmasked interrupts fail to be detected. We workaround the 1853 * hardware bugs here by ACKing all the possible interrupts so that 1854 * interrupt coalescing can still be achieved. 1855 */ 1856 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1857 1858 if (iwl_have_debug_level(IWL_DL_ISR)) 1859 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1860 inta, iwl_read32(trans, CSR_INT_MASK)); 1861 1862 spin_unlock_bh(&trans_pcie->irq_lock); 1863 1864 /* Now service all interrupt bits discovered above. */ 1865 if (inta & CSR_INT_BIT_HW_ERR) { 1866 IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1867 1868 /* Tell the device to stop sending interrupts */ 1869 iwl_disable_interrupts(trans); 1870 1871 isr_stats->hw++; 1872 iwl_pcie_irq_handle_error(trans); 1873 1874 handled |= CSR_INT_BIT_HW_ERR; 1875 1876 goto out; 1877 } 1878 1879 /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1880 if (inta & CSR_INT_BIT_SCD) { 1881 IWL_DEBUG_ISR(trans, 1882 "Scheduler finished to transmit the frame/frames.\n"); 1883 isr_stats->sch++; 1884 } 1885 1886 /* Alive notification via Rx interrupt will do the real work */ 1887 if (inta & CSR_INT_BIT_ALIVE) { 1888 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1889 isr_stats->alive++; 1890 if (trans->trans_cfg->gen2) { 1891 /* 1892 * We can restock, since firmware configured 1893 * the RFH 1894 */ 1895 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1896 } 1897 1898 handled |= CSR_INT_BIT_ALIVE; 1899 } 1900 1901 /* Safely ignore these bits for debug checks below */ 1902 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1903 1904 /* HW RF KILL switch toggled */ 1905 if (inta & CSR_INT_BIT_RF_KILL) { 1906 iwl_pcie_handle_rfkill_irq(trans); 1907 handled |= CSR_INT_BIT_RF_KILL; 1908 } 1909 1910 /* Chip got too hot and stopped itself */ 1911 if (inta & CSR_INT_BIT_CT_KILL) { 1912 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1913 isr_stats->ctkill++; 1914 handled |= CSR_INT_BIT_CT_KILL; 1915 } 1916 1917 /* Error detected by uCode */ 1918 if (inta & CSR_INT_BIT_SW_ERR) { 1919 IWL_ERR(trans, "Microcode SW error detected. " 1920 " Restarting 0x%X.\n", inta); 1921 isr_stats->sw++; 1922 iwl_pcie_irq_handle_error(trans); 1923 handled |= CSR_INT_BIT_SW_ERR; 1924 } 1925 1926 /* uCode wakes up after power-down sleep */ 1927 if (inta & CSR_INT_BIT_WAKEUP) { 1928 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1929 iwl_pcie_rxq_check_wrptr(trans); 1930 iwl_pcie_txq_check_wrptrs(trans); 1931 1932 isr_stats->wakeup++; 1933 1934 handled |= CSR_INT_BIT_WAKEUP; 1935 } 1936 1937 /* All uCode command responses, including Tx command responses, 1938 * Rx "responses" (frame-received notification), and other 1939 * notifications from uCode come through here*/ 1940 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1941 CSR_INT_BIT_RX_PERIODIC)) { 1942 IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1943 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1944 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1945 iwl_write32(trans, CSR_FH_INT_STATUS, 1946 CSR_FH_INT_RX_MASK); 1947 } 1948 if (inta & CSR_INT_BIT_RX_PERIODIC) { 1949 handled |= CSR_INT_BIT_RX_PERIODIC; 1950 iwl_write32(trans, 1951 CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1952 } 1953 /* Sending RX interrupt require many steps to be done in the 1954 * the device: 1955 * 1- write interrupt to current index in ICT table. 1956 * 2- dma RX frame. 1957 * 3- update RX shared data to indicate last write index. 1958 * 4- send interrupt. 1959 * This could lead to RX race, driver could receive RX interrupt 1960 * but the shared data changes does not reflect this; 1961 * periodic interrupt will detect any dangling Rx activity. 1962 */ 1963 1964 /* Disable periodic interrupt; we use it as just a one-shot. */ 1965 iwl_write8(trans, CSR_INT_PERIODIC_REG, 1966 CSR_INT_PERIODIC_DIS); 1967 1968 /* 1969 * Enable periodic interrupt in 8 msec only if we received 1970 * real RX interrupt (instead of just periodic int), to catch 1971 * any dangling Rx interrupt. If it was just the periodic 1972 * interrupt, there was no dangling Rx activity, and no need 1973 * to extend the periodic interrupt; one-shot is enough. 1974 */ 1975 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1976 iwl_write8(trans, CSR_INT_PERIODIC_REG, 1977 CSR_INT_PERIODIC_ENA); 1978 1979 isr_stats->rx++; 1980 1981 local_bh_disable(); 1982 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 1983 polling = true; 1984 __napi_schedule(&trans_pcie->rxq[0].napi); 1985 } 1986 local_bh_enable(); 1987 } 1988 1989 /* This "Tx" DMA channel is used only for loading uCode */ 1990 if (inta & CSR_INT_BIT_FH_TX) { 1991 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1992 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1993 isr_stats->tx++; 1994 handled |= CSR_INT_BIT_FH_TX; 1995 /* Wake up uCode load routine, now that load is complete */ 1996 trans_pcie->ucode_write_complete = true; 1997 wake_up(&trans_pcie->ucode_write_waitq); 1998 } 1999 2000 if (inta & ~handled) { 2001 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 2002 isr_stats->unhandled++; 2003 } 2004 2005 if (inta & ~(trans_pcie->inta_mask)) { 2006 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 2007 inta & ~trans_pcie->inta_mask); 2008 } 2009 2010 if (!polling) { 2011 spin_lock_bh(&trans_pcie->irq_lock); 2012 /* only Re-enable all interrupt if disabled by irq */ 2013 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 2014 _iwl_enable_interrupts(trans); 2015 /* we are loading the firmware, enable FH_TX interrupt only */ 2016 else if (handled & CSR_INT_BIT_FH_TX) 2017 iwl_enable_fw_load_int(trans); 2018 /* Re-enable RF_KILL if it occurred */ 2019 else if (handled & CSR_INT_BIT_RF_KILL) 2020 iwl_enable_rfkill_int(trans); 2021 /* Re-enable the ALIVE / Rx interrupt if it occurred */ 2022 else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX)) 2023 iwl_enable_fw_load_int_ctx_info(trans); 2024 spin_unlock_bh(&trans_pcie->irq_lock); 2025 } 2026 2027 out: 2028 lock_map_release(&trans->sync_cmd_lockdep_map); 2029 return IRQ_HANDLED; 2030 } 2031 2032 /****************************************************************************** 2033 * 2034 * ICT functions 2035 * 2036 ******************************************************************************/ 2037 2038 /* Free dram table */ 2039 void iwl_pcie_free_ict(struct iwl_trans *trans) 2040 { 2041 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2042 2043 if (trans_pcie->ict_tbl) { 2044 dma_free_coherent(trans->dev, ICT_SIZE, 2045 trans_pcie->ict_tbl, 2046 trans_pcie->ict_tbl_dma); 2047 trans_pcie->ict_tbl = NULL; 2048 trans_pcie->ict_tbl_dma = 0; 2049 } 2050 } 2051 2052 /* 2053 * allocate dram shared table, it is an aligned memory 2054 * block of ICT_SIZE. 2055 * also reset all data related to ICT table interrupt. 2056 */ 2057 int iwl_pcie_alloc_ict(struct iwl_trans *trans) 2058 { 2059 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2060 2061 trans_pcie->ict_tbl = 2062 dma_alloc_coherent(trans->dev, ICT_SIZE, 2063 &trans_pcie->ict_tbl_dma, GFP_KERNEL); 2064 if (!trans_pcie->ict_tbl) 2065 return -ENOMEM; 2066 2067 /* just an API sanity check ... it is guaranteed to be aligned */ 2068 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 2069 iwl_pcie_free_ict(trans); 2070 return -EINVAL; 2071 } 2072 2073 return 0; 2074 } 2075 2076 /* Device is going up inform it about using ICT interrupt table, 2077 * also we need to tell the driver to start using ICT interrupt. 2078 */ 2079 void iwl_pcie_reset_ict(struct iwl_trans *trans) 2080 { 2081 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2082 u32 val; 2083 2084 if (!trans_pcie->ict_tbl) 2085 return; 2086 2087 spin_lock_bh(&trans_pcie->irq_lock); 2088 _iwl_disable_interrupts(trans); 2089 2090 memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 2091 2092 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 2093 2094 val |= CSR_DRAM_INT_TBL_ENABLE | 2095 CSR_DRAM_INIT_TBL_WRAP_CHECK | 2096 CSR_DRAM_INIT_TBL_WRITE_POINTER; 2097 2098 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 2099 2100 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 2101 trans_pcie->use_ict = true; 2102 trans_pcie->ict_index = 0; 2103 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 2104 _iwl_enable_interrupts(trans); 2105 spin_unlock_bh(&trans_pcie->irq_lock); 2106 } 2107 2108 /* Device is going down disable ict interrupt usage */ 2109 void iwl_pcie_disable_ict(struct iwl_trans *trans) 2110 { 2111 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2112 2113 spin_lock_bh(&trans_pcie->irq_lock); 2114 trans_pcie->use_ict = false; 2115 spin_unlock_bh(&trans_pcie->irq_lock); 2116 } 2117 2118 irqreturn_t iwl_pcie_isr(int irq, void *data) 2119 { 2120 struct iwl_trans *trans = data; 2121 2122 if (!trans) 2123 return IRQ_NONE; 2124 2125 /* Disable (but don't clear!) interrupts here to avoid 2126 * back-to-back ISRs and sporadic interrupts from our NIC. 2127 * If we have something to service, the tasklet will re-enable ints. 2128 * If we *don't* have something, we'll re-enable before leaving here. 2129 */ 2130 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2131 2132 return IRQ_WAKE_THREAD; 2133 } 2134 2135 irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 2136 { 2137 return IRQ_WAKE_THREAD; 2138 } 2139 2140 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 2141 { 2142 struct msix_entry *entry = dev_id; 2143 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 2144 struct iwl_trans *trans = trans_pcie->trans; 2145 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2146 u32 inta_fh_msk = ~MSIX_FH_INT_CAUSES_DATA_QUEUE; 2147 u32 inta_fh, inta_hw; 2148 bool polling = false; 2149 2150 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 2151 inta_fh_msk |= MSIX_FH_INT_CAUSES_Q0; 2152 2153 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 2154 inta_fh_msk |= MSIX_FH_INT_CAUSES_Q1; 2155 2156 lock_map_acquire(&trans->sync_cmd_lockdep_map); 2157 2158 spin_lock_bh(&trans_pcie->irq_lock); 2159 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 2160 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 2161 /* 2162 * Clear causes registers to avoid being handling the same cause. 2163 */ 2164 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk); 2165 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 2166 spin_unlock_bh(&trans_pcie->irq_lock); 2167 2168 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2169 2170 if (unlikely(!(inta_fh | inta_hw))) { 2171 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 2172 lock_map_release(&trans->sync_cmd_lockdep_map); 2173 return IRQ_NONE; 2174 } 2175 2176 if (iwl_have_debug_level(IWL_DL_ISR)) { 2177 IWL_DEBUG_ISR(trans, 2178 "ISR[%d] inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 2179 entry->entry, inta_fh, trans_pcie->fh_mask, 2180 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 2181 if (inta_fh & ~trans_pcie->fh_mask) 2182 IWL_DEBUG_ISR(trans, 2183 "We got a masked interrupt (0x%08x)\n", 2184 inta_fh & ~trans_pcie->fh_mask); 2185 } 2186 2187 inta_fh &= trans_pcie->fh_mask; 2188 2189 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2190 inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2191 local_bh_disable(); 2192 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 2193 polling = true; 2194 __napi_schedule(&trans_pcie->rxq[0].napi); 2195 } 2196 local_bh_enable(); 2197 } 2198 2199 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2200 inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2201 local_bh_disable(); 2202 if (napi_schedule_prep(&trans_pcie->rxq[1].napi)) { 2203 polling = true; 2204 __napi_schedule(&trans_pcie->rxq[1].napi); 2205 } 2206 local_bh_enable(); 2207 } 2208 2209 /* This "Tx" DMA channel is used only for loading uCode */ 2210 if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 2211 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 2212 isr_stats->tx++; 2213 /* 2214 * Wake up uCode load routine, 2215 * now that load is complete 2216 */ 2217 trans_pcie->ucode_write_complete = true; 2218 wake_up(&trans_pcie->ucode_write_waitq); 2219 } 2220 2221 /* Error detected by uCode */ 2222 if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 2223 (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) { 2224 IWL_ERR(trans, 2225 "Microcode SW error detected. Restarting 0x%X.\n", 2226 inta_fh); 2227 isr_stats->sw++; 2228 iwl_pcie_irq_handle_error(trans); 2229 } 2230 2231 /* After checking FH register check HW register */ 2232 if (iwl_have_debug_level(IWL_DL_ISR)) { 2233 IWL_DEBUG_ISR(trans, 2234 "ISR[%d] inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 2235 entry->entry, inta_hw, trans_pcie->hw_mask, 2236 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 2237 if (inta_hw & ~trans_pcie->hw_mask) 2238 IWL_DEBUG_ISR(trans, 2239 "We got a masked interrupt 0x%08x\n", 2240 inta_hw & ~trans_pcie->hw_mask); 2241 } 2242 2243 inta_hw &= trans_pcie->hw_mask; 2244 2245 /* Alive notification via Rx interrupt will do the real work */ 2246 if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 2247 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 2248 isr_stats->alive++; 2249 if (trans->trans_cfg->gen2) { 2250 /* We can restock, since firmware configured the RFH */ 2251 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2252 } 2253 } 2254 2255 if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 2256 u32 sleep_notif = 2257 le32_to_cpu(trans_pcie->prph_info->sleep_notif); 2258 if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND || 2259 sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) { 2260 IWL_DEBUG_ISR(trans, 2261 "Sx interrupt: sleep notification = 0x%x\n", 2262 sleep_notif); 2263 trans_pcie->sx_complete = true; 2264 wake_up(&trans_pcie->sx_waitq); 2265 } else { 2266 /* uCode wakes up after power-down sleep */ 2267 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 2268 iwl_pcie_rxq_check_wrptr(trans); 2269 iwl_pcie_txq_check_wrptrs(trans); 2270 2271 isr_stats->wakeup++; 2272 } 2273 } 2274 2275 /* Chip got too hot and stopped itself */ 2276 if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 2277 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 2278 isr_stats->ctkill++; 2279 } 2280 2281 /* HW RF KILL switch toggled */ 2282 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 2283 iwl_pcie_handle_rfkill_irq(trans); 2284 2285 if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 2286 IWL_ERR(trans, 2287 "Hardware error detected. Restarting.\n"); 2288 2289 isr_stats->hw++; 2290 trans->dbg.hw_error = true; 2291 iwl_pcie_irq_handle_error(trans); 2292 } 2293 2294 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE) { 2295 IWL_DEBUG_ISR(trans, "Reset flow completed\n"); 2296 trans_pcie->fw_reset_done = true; 2297 wake_up(&trans_pcie->fw_reset_waitq); 2298 } 2299 2300 if (!polling) 2301 iwl_pcie_clear_irq(trans, entry->entry); 2302 2303 lock_map_release(&trans->sync_cmd_lockdep_map); 2304 2305 return IRQ_HANDLED; 2306 } 2307