1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2003-2014, 2018-2020 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/sched.h> 8 #include <linux/wait.h> 9 #include <linux/gfp.h> 10 11 #include "iwl-prph.h" 12 #include "iwl-io.h" 13 #include "internal.h" 14 #include "iwl-op-mode.h" 15 #include "iwl-context-info-gen3.h" 16 17 /****************************************************************************** 18 * 19 * RX path functions 20 * 21 ******************************************************************************/ 22 23 /* 24 * Rx theory of operation 25 * 26 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 27 * each of which point to Receive Buffers to be filled by the NIC. These get 28 * used not only for Rx frames, but for any command response or notification 29 * from the NIC. The driver and NIC manage the Rx buffers by means 30 * of indexes into the circular buffer. 31 * 32 * Rx Queue Indexes 33 * The host/firmware share two index registers for managing the Rx buffers. 34 * 35 * The READ index maps to the first position that the firmware may be writing 36 * to -- the driver can read up to (but not including) this position and get 37 * good data. 38 * The READ index is managed by the firmware once the card is enabled. 39 * 40 * The WRITE index maps to the last position the driver has read from -- the 41 * position preceding WRITE is the last slot the firmware can place a packet. 42 * 43 * The queue is empty (no good data) if WRITE = READ - 1, and is full if 44 * WRITE = READ. 45 * 46 * During initialization, the host sets up the READ queue position to the first 47 * INDEX position, and WRITE to the last (READ - 1 wrapped) 48 * 49 * When the firmware places a packet in a buffer, it will advance the READ index 50 * and fire the RX interrupt. The driver can then query the READ index and 51 * process as many packets as possible, moving the WRITE index forward as it 52 * resets the Rx queue buffers with new memory. 53 * 54 * The management in the driver is as follows: 55 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 56 * When the interrupt handler is called, the request is processed. 57 * The page is either stolen - transferred to the upper layer 58 * or reused - added immediately to the iwl->rxq->rx_free list. 59 * + When the page is stolen - the driver updates the matching queue's used 60 * count, detaches the RBD and transfers it to the queue used list. 61 * When there are two used RBDs - they are transferred to the allocator empty 62 * list. Work is then scheduled for the allocator to start allocating 63 * eight buffers. 64 * When there are another 6 used RBDs - they are transferred to the allocator 65 * empty list and the driver tries to claim the pre-allocated buffers and 66 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 67 * until ready. 68 * When there are 8+ buffers in the free list - either from allocation or from 69 * 8 reused unstolen pages - restock is called to update the FW and indexes. 70 * + In order to make sure the allocator always has RBDs to use for allocation 71 * the allocator has initial pool in the size of num_queues*(8-2) - the 72 * maximum missing RBDs per allocation request (request posted with 2 73 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 74 * The queues supplies the recycle of the rest of the RBDs. 75 * + A received packet is processed and handed to the kernel network stack, 76 * detached from the iwl->rxq. The driver 'processed' index is updated. 77 * + If there are no allocated buffers in iwl->rxq->rx_free, 78 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 79 * If there were enough free buffers and RX_STALLED is set it is cleared. 80 * 81 * 82 * Driver sequence: 83 * 84 * iwl_rxq_alloc() Allocates rx_free 85 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 86 * iwl_pcie_rxq_restock. 87 * Used only during initialization. 88 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 89 * queue, updates firmware pointers, and updates 90 * the WRITE index. 91 * iwl_pcie_rx_allocator() Background work for allocating pages. 92 * 93 * -- enable interrupts -- 94 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 95 * READ INDEX, detaching the SKB from the pool. 96 * Moves the packet buffer from queue to rx_used. 97 * Posts and claims requests to the allocator. 98 * Calls iwl_pcie_rxq_restock to refill any empty 99 * slots. 100 * 101 * RBD life-cycle: 102 * 103 * Init: 104 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 105 * 106 * Regular Receive interrupt: 107 * Page Stolen: 108 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 109 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 110 * Page not Stolen: 111 * rxq.queue -> rxq.rx_free -> rxq.queue 112 * ... 113 * 114 */ 115 116 /* 117 * iwl_rxq_space - Return number of free slots available in queue. 118 */ 119 static int iwl_rxq_space(const struct iwl_rxq *rxq) 120 { 121 /* Make sure rx queue size is a power of 2 */ 122 WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 123 124 /* 125 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 126 * between empty and completely full queues. 127 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 128 * defined for negative dividends. 129 */ 130 return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 131 } 132 133 /* 134 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 135 */ 136 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 137 { 138 return cpu_to_le32((u32)(dma_addr >> 8)); 139 } 140 141 /* 142 * iwl_pcie_rx_stop - stops the Rx DMA 143 */ 144 int iwl_pcie_rx_stop(struct iwl_trans *trans) 145 { 146 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 147 /* TODO: remove this once fw does it */ 148 iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 149 return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3, 150 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 151 } else if (trans->trans_cfg->mq_rx_supported) { 152 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 153 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 154 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 155 } else { 156 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 157 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 158 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 159 1000); 160 } 161 } 162 163 /* 164 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 165 */ 166 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 167 struct iwl_rxq *rxq) 168 { 169 u32 reg; 170 171 lockdep_assert_held(&rxq->lock); 172 173 /* 174 * explicitly wake up the NIC if: 175 * 1. shadow registers aren't enabled 176 * 2. there is a chance that the NIC is asleep 177 */ 178 if (!trans->trans_cfg->base_params->shadow_reg_enable && 179 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 180 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 181 182 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 183 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 184 reg); 185 iwl_set_bit(trans, CSR_GP_CNTRL, 186 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 187 rxq->need_update = true; 188 return; 189 } 190 } 191 192 rxq->write_actual = round_down(rxq->write, 8); 193 if (trans->trans_cfg->mq_rx_supported) 194 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 195 rxq->write_actual); 196 else 197 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 198 } 199 200 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 201 { 202 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 203 int i; 204 205 for (i = 0; i < trans->num_rx_queues; i++) { 206 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 207 208 if (!rxq->need_update) 209 continue; 210 spin_lock(&rxq->lock); 211 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 212 rxq->need_update = false; 213 spin_unlock(&rxq->lock); 214 } 215 } 216 217 static void iwl_pcie_restock_bd(struct iwl_trans *trans, 218 struct iwl_rxq *rxq, 219 struct iwl_rx_mem_buffer *rxb) 220 { 221 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 222 struct iwl_rx_transfer_desc *bd = rxq->bd; 223 224 BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64)); 225 226 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 227 bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 228 } else { 229 __le64 *bd = rxq->bd; 230 231 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 232 } 233 234 IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n", 235 (u32)rxb->vid, rxq->id, rxq->write); 236 } 237 238 /* 239 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 240 */ 241 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 242 struct iwl_rxq *rxq) 243 { 244 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 245 struct iwl_rx_mem_buffer *rxb; 246 247 /* 248 * If the device isn't enabled - no need to try to add buffers... 249 * This can happen when we stop the device and still have an interrupt 250 * pending. We stop the APM before we sync the interrupts because we 251 * have to (see comment there). On the other hand, since the APM is 252 * stopped, we cannot access the HW (in particular not prph). 253 * So don't try to restock if the APM has been already stopped. 254 */ 255 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 256 return; 257 258 spin_lock(&rxq->lock); 259 while (rxq->free_count) { 260 /* Get next free Rx buffer, remove from free list */ 261 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 262 list); 263 list_del(&rxb->list); 264 rxb->invalid = false; 265 /* some low bits are expected to be unset (depending on hw) */ 266 WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask); 267 /* Point to Rx buffer via next RBD in circular buffer */ 268 iwl_pcie_restock_bd(trans, rxq, rxb); 269 rxq->write = (rxq->write + 1) & (rxq->queue_size - 1); 270 rxq->free_count--; 271 } 272 spin_unlock(&rxq->lock); 273 274 /* 275 * If we've added more space for the firmware to place data, tell it. 276 * Increment device's write pointer in multiples of 8. 277 */ 278 if (rxq->write_actual != (rxq->write & ~0x7)) { 279 spin_lock(&rxq->lock); 280 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 281 spin_unlock(&rxq->lock); 282 } 283 } 284 285 /* 286 * iwl_pcie_rxsq_restock - restock implementation for single queue rx 287 */ 288 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 289 struct iwl_rxq *rxq) 290 { 291 struct iwl_rx_mem_buffer *rxb; 292 293 /* 294 * If the device isn't enabled - not need to try to add buffers... 295 * This can happen when we stop the device and still have an interrupt 296 * pending. We stop the APM before we sync the interrupts because we 297 * have to (see comment there). On the other hand, since the APM is 298 * stopped, we cannot access the HW (in particular not prph). 299 * So don't try to restock if the APM has been already stopped. 300 */ 301 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 302 return; 303 304 spin_lock(&rxq->lock); 305 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 306 __le32 *bd = (__le32 *)rxq->bd; 307 /* The overwritten rxb must be a used one */ 308 rxb = rxq->queue[rxq->write]; 309 BUG_ON(rxb && rxb->page); 310 311 /* Get next free Rx buffer, remove from free list */ 312 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 313 list); 314 list_del(&rxb->list); 315 rxb->invalid = false; 316 317 /* Point to Rx buffer via next RBD in circular buffer */ 318 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 319 rxq->queue[rxq->write] = rxb; 320 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 321 rxq->free_count--; 322 } 323 spin_unlock(&rxq->lock); 324 325 /* If we've added more space for the firmware to place data, tell it. 326 * Increment device's write pointer in multiples of 8. */ 327 if (rxq->write_actual != (rxq->write & ~0x7)) { 328 spin_lock(&rxq->lock); 329 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 330 spin_unlock(&rxq->lock); 331 } 332 } 333 334 /* 335 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 336 * 337 * If there are slots in the RX queue that need to be restocked, 338 * and we have free pre-allocated buffers, fill the ranks as much 339 * as we can, pulling from rx_free. 340 * 341 * This moves the 'write' index forward to catch up with 'processed', and 342 * also updates the memory address in the firmware to reference the new 343 * target buffer. 344 */ 345 static 346 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 347 { 348 if (trans->trans_cfg->mq_rx_supported) 349 iwl_pcie_rxmq_restock(trans, rxq); 350 else 351 iwl_pcie_rxsq_restock(trans, rxq); 352 } 353 354 /* 355 * iwl_pcie_rx_alloc_page - allocates and returns a page. 356 * 357 */ 358 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 359 u32 *offset, gfp_t priority) 360 { 361 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 362 unsigned int rbsize = iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 363 unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order; 364 struct page *page; 365 gfp_t gfp_mask = priority; 366 367 if (trans_pcie->rx_page_order > 0) 368 gfp_mask |= __GFP_COMP; 369 370 if (trans_pcie->alloc_page) { 371 spin_lock_bh(&trans_pcie->alloc_page_lock); 372 /* recheck */ 373 if (trans_pcie->alloc_page) { 374 *offset = trans_pcie->alloc_page_used; 375 page = trans_pcie->alloc_page; 376 trans_pcie->alloc_page_used += rbsize; 377 if (trans_pcie->alloc_page_used >= allocsize) 378 trans_pcie->alloc_page = NULL; 379 else 380 get_page(page); 381 spin_unlock_bh(&trans_pcie->alloc_page_lock); 382 return page; 383 } 384 spin_unlock_bh(&trans_pcie->alloc_page_lock); 385 } 386 387 /* Alloc a new receive buffer */ 388 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 389 if (!page) { 390 if (net_ratelimit()) 391 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 392 trans_pcie->rx_page_order); 393 /* 394 * Issue an error if we don't have enough pre-allocated 395 * buffers. 396 */ 397 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 398 IWL_CRIT(trans, 399 "Failed to alloc_pages\n"); 400 return NULL; 401 } 402 403 if (2 * rbsize <= allocsize) { 404 spin_lock_bh(&trans_pcie->alloc_page_lock); 405 if (!trans_pcie->alloc_page) { 406 get_page(page); 407 trans_pcie->alloc_page = page; 408 trans_pcie->alloc_page_used = rbsize; 409 } 410 spin_unlock_bh(&trans_pcie->alloc_page_lock); 411 } 412 413 *offset = 0; 414 return page; 415 } 416 417 /* 418 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 419 * 420 * A used RBD is an Rx buffer that has been given to the stack. To use it again 421 * a page must be allocated and the RBD must point to the page. This function 422 * doesn't change the HW pointer but handles the list of pages that is used by 423 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 424 * allocated buffers. 425 */ 426 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 427 struct iwl_rxq *rxq) 428 { 429 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 430 struct iwl_rx_mem_buffer *rxb; 431 struct page *page; 432 433 while (1) { 434 unsigned int offset; 435 436 spin_lock(&rxq->lock); 437 if (list_empty(&rxq->rx_used)) { 438 spin_unlock(&rxq->lock); 439 return; 440 } 441 spin_unlock(&rxq->lock); 442 443 page = iwl_pcie_rx_alloc_page(trans, &offset, priority); 444 if (!page) 445 return; 446 447 spin_lock(&rxq->lock); 448 449 if (list_empty(&rxq->rx_used)) { 450 spin_unlock(&rxq->lock); 451 __free_pages(page, trans_pcie->rx_page_order); 452 return; 453 } 454 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 455 list); 456 list_del(&rxb->list); 457 spin_unlock(&rxq->lock); 458 459 BUG_ON(rxb->page); 460 rxb->page = page; 461 rxb->offset = offset; 462 /* Get physical address of the RB */ 463 rxb->page_dma = 464 dma_map_page(trans->dev, page, rxb->offset, 465 trans_pcie->rx_buf_bytes, 466 DMA_FROM_DEVICE); 467 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 468 rxb->page = NULL; 469 spin_lock(&rxq->lock); 470 list_add(&rxb->list, &rxq->rx_used); 471 spin_unlock(&rxq->lock); 472 __free_pages(page, trans_pcie->rx_page_order); 473 return; 474 } 475 476 spin_lock(&rxq->lock); 477 478 list_add_tail(&rxb->list, &rxq->rx_free); 479 rxq->free_count++; 480 481 spin_unlock(&rxq->lock); 482 } 483 } 484 485 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 486 { 487 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 488 int i; 489 490 for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) { 491 if (!trans_pcie->rx_pool[i].page) 492 continue; 493 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 494 trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE); 495 __free_pages(trans_pcie->rx_pool[i].page, 496 trans_pcie->rx_page_order); 497 trans_pcie->rx_pool[i].page = NULL; 498 } 499 } 500 501 /* 502 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 503 * 504 * Allocates for each received request 8 pages 505 * Called as a scheduled work item. 506 */ 507 static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 508 { 509 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 510 struct iwl_rb_allocator *rba = &trans_pcie->rba; 511 struct list_head local_empty; 512 int pending = atomic_read(&rba->req_pending); 513 514 IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending); 515 516 /* If we were scheduled - there is at least one request */ 517 spin_lock(&rba->lock); 518 /* swap out the rba->rbd_empty to a local list */ 519 list_replace_init(&rba->rbd_empty, &local_empty); 520 spin_unlock(&rba->lock); 521 522 while (pending) { 523 int i; 524 LIST_HEAD(local_allocated); 525 gfp_t gfp_mask = GFP_KERNEL; 526 527 /* Do not post a warning if there are only a few requests */ 528 if (pending < RX_PENDING_WATERMARK) 529 gfp_mask |= __GFP_NOWARN; 530 531 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 532 struct iwl_rx_mem_buffer *rxb; 533 struct page *page; 534 535 /* List should never be empty - each reused RBD is 536 * returned to the list, and initial pool covers any 537 * possible gap between the time the page is allocated 538 * to the time the RBD is added. 539 */ 540 BUG_ON(list_empty(&local_empty)); 541 /* Get the first rxb from the rbd list */ 542 rxb = list_first_entry(&local_empty, 543 struct iwl_rx_mem_buffer, list); 544 BUG_ON(rxb->page); 545 546 /* Alloc a new receive buffer */ 547 page = iwl_pcie_rx_alloc_page(trans, &rxb->offset, 548 gfp_mask); 549 if (!page) 550 continue; 551 rxb->page = page; 552 553 /* Get physical address of the RB */ 554 rxb->page_dma = dma_map_page(trans->dev, page, 555 rxb->offset, 556 trans_pcie->rx_buf_bytes, 557 DMA_FROM_DEVICE); 558 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 559 rxb->page = NULL; 560 __free_pages(page, trans_pcie->rx_page_order); 561 continue; 562 } 563 564 /* move the allocated entry to the out list */ 565 list_move(&rxb->list, &local_allocated); 566 i++; 567 } 568 569 atomic_dec(&rba->req_pending); 570 pending--; 571 572 if (!pending) { 573 pending = atomic_read(&rba->req_pending); 574 if (pending) 575 IWL_DEBUG_TPT(trans, 576 "Got more pending allocation requests = %d\n", 577 pending); 578 } 579 580 spin_lock(&rba->lock); 581 /* add the allocated rbds to the allocator allocated list */ 582 list_splice_tail(&local_allocated, &rba->rbd_allocated); 583 /* get more empty RBDs for current pending requests */ 584 list_splice_tail_init(&rba->rbd_empty, &local_empty); 585 spin_unlock(&rba->lock); 586 587 atomic_inc(&rba->req_ready); 588 589 } 590 591 spin_lock(&rba->lock); 592 /* return unused rbds to the allocator empty list */ 593 list_splice_tail(&local_empty, &rba->rbd_empty); 594 spin_unlock(&rba->lock); 595 596 IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__); 597 } 598 599 /* 600 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 601 .* 602 .* Called by queue when the queue posted allocation request and 603 * has freed 8 RBDs in order to restock itself. 604 * This function directly moves the allocated RBs to the queue's ownership 605 * and updates the relevant counters. 606 */ 607 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 608 struct iwl_rxq *rxq) 609 { 610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 611 struct iwl_rb_allocator *rba = &trans_pcie->rba; 612 int i; 613 614 lockdep_assert_held(&rxq->lock); 615 616 /* 617 * atomic_dec_if_positive returns req_ready - 1 for any scenario. 618 * If req_ready is 0 atomic_dec_if_positive will return -1 and this 619 * function will return early, as there are no ready requests. 620 * atomic_dec_if_positive will perofrm the *actual* decrement only if 621 * req_ready > 0, i.e. - there are ready requests and the function 622 * hands one request to the caller. 623 */ 624 if (atomic_dec_if_positive(&rba->req_ready) < 0) 625 return; 626 627 spin_lock(&rba->lock); 628 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 629 /* Get next free Rx buffer, remove it from free list */ 630 struct iwl_rx_mem_buffer *rxb = 631 list_first_entry(&rba->rbd_allocated, 632 struct iwl_rx_mem_buffer, list); 633 634 list_move(&rxb->list, &rxq->rx_free); 635 } 636 spin_unlock(&rba->lock); 637 638 rxq->used_count -= RX_CLAIM_REQ_ALLOC; 639 rxq->free_count += RX_CLAIM_REQ_ALLOC; 640 } 641 642 void iwl_pcie_rx_allocator_work(struct work_struct *data) 643 { 644 struct iwl_rb_allocator *rba_p = 645 container_of(data, struct iwl_rb_allocator, rx_alloc); 646 struct iwl_trans_pcie *trans_pcie = 647 container_of(rba_p, struct iwl_trans_pcie, rba); 648 649 iwl_pcie_rx_allocator(trans_pcie->trans); 650 } 651 652 static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td) 653 { 654 struct iwl_rx_transfer_desc *rx_td; 655 656 if (use_rx_td) 657 return sizeof(*rx_td); 658 else 659 return trans->trans_cfg->mq_rx_supported ? sizeof(__le64) : 660 sizeof(__le32); 661 } 662 663 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 664 struct iwl_rxq *rxq) 665 { 666 struct device *dev = trans->dev; 667 bool use_rx_td = (trans->trans_cfg->device_family >= 668 IWL_DEVICE_FAMILY_AX210); 669 int free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 670 671 if (rxq->bd) 672 dma_free_coherent(trans->dev, 673 free_size * rxq->queue_size, 674 rxq->bd, rxq->bd_dma); 675 rxq->bd_dma = 0; 676 rxq->bd = NULL; 677 678 rxq->rb_stts_dma = 0; 679 rxq->rb_stts = NULL; 680 681 if (rxq->used_bd) 682 dma_free_coherent(trans->dev, 683 (use_rx_td ? sizeof(*rxq->cd) : 684 sizeof(__le32)) * rxq->queue_size, 685 rxq->used_bd, rxq->used_bd_dma); 686 rxq->used_bd_dma = 0; 687 rxq->used_bd = NULL; 688 689 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 690 return; 691 692 if (rxq->tr_tail) 693 dma_free_coherent(dev, sizeof(__le16), 694 rxq->tr_tail, rxq->tr_tail_dma); 695 rxq->tr_tail_dma = 0; 696 rxq->tr_tail = NULL; 697 698 if (rxq->cr_tail) 699 dma_free_coherent(dev, sizeof(__le16), 700 rxq->cr_tail, rxq->cr_tail_dma); 701 rxq->cr_tail_dma = 0; 702 rxq->cr_tail = NULL; 703 } 704 705 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 706 struct iwl_rxq *rxq) 707 { 708 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 709 struct device *dev = trans->dev; 710 int i; 711 int free_size; 712 bool use_rx_td = (trans->trans_cfg->device_family >= 713 IWL_DEVICE_FAMILY_AX210); 714 size_t rb_stts_size = use_rx_td ? sizeof(__le16) : 715 sizeof(struct iwl_rb_status); 716 717 spin_lock_init(&rxq->lock); 718 if (trans->trans_cfg->mq_rx_supported) 719 rxq->queue_size = trans->cfg->num_rbds; 720 else 721 rxq->queue_size = RX_QUEUE_SIZE; 722 723 free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 724 725 /* 726 * Allocate the circular buffer of Read Buffer Descriptors 727 * (RBDs) 728 */ 729 rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size, 730 &rxq->bd_dma, GFP_KERNEL); 731 if (!rxq->bd) 732 goto err; 733 734 if (trans->trans_cfg->mq_rx_supported) { 735 rxq->used_bd = dma_alloc_coherent(dev, 736 (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size, 737 &rxq->used_bd_dma, 738 GFP_KERNEL); 739 if (!rxq->used_bd) 740 goto err; 741 } 742 743 rxq->rb_stts = trans_pcie->base_rb_stts + rxq->id * rb_stts_size; 744 rxq->rb_stts_dma = 745 trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size; 746 747 if (!use_rx_td) 748 return 0; 749 750 /* Allocate the driver's pointer to TR tail */ 751 rxq->tr_tail = dma_alloc_coherent(dev, sizeof(__le16), 752 &rxq->tr_tail_dma, GFP_KERNEL); 753 if (!rxq->tr_tail) 754 goto err; 755 756 /* Allocate the driver's pointer to CR tail */ 757 rxq->cr_tail = dma_alloc_coherent(dev, sizeof(__le16), 758 &rxq->cr_tail_dma, GFP_KERNEL); 759 if (!rxq->cr_tail) 760 goto err; 761 762 return 0; 763 764 err: 765 for (i = 0; i < trans->num_rx_queues; i++) { 766 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 767 768 iwl_pcie_free_rxq_dma(trans, rxq); 769 } 770 771 return -ENOMEM; 772 } 773 774 static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 775 { 776 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 777 struct iwl_rb_allocator *rba = &trans_pcie->rba; 778 int i, ret; 779 size_t rb_stts_size = trans->trans_cfg->device_family >= 780 IWL_DEVICE_FAMILY_AX210 ? 781 sizeof(__le16) : sizeof(struct iwl_rb_status); 782 783 if (WARN_ON(trans_pcie->rxq)) 784 return -EINVAL; 785 786 trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 787 GFP_KERNEL); 788 trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 789 sizeof(trans_pcie->rx_pool[0]), 790 GFP_KERNEL); 791 trans_pcie->global_table = 792 kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 793 sizeof(trans_pcie->global_table[0]), 794 GFP_KERNEL); 795 if (!trans_pcie->rxq || !trans_pcie->rx_pool || 796 !trans_pcie->global_table) { 797 ret = -ENOMEM; 798 goto err; 799 } 800 801 spin_lock_init(&rba->lock); 802 803 /* 804 * Allocate the driver's pointer to receive buffer status. 805 * Allocate for all queues continuously (HW requirement). 806 */ 807 trans_pcie->base_rb_stts = 808 dma_alloc_coherent(trans->dev, 809 rb_stts_size * trans->num_rx_queues, 810 &trans_pcie->base_rb_stts_dma, 811 GFP_KERNEL); 812 if (!trans_pcie->base_rb_stts) { 813 ret = -ENOMEM; 814 goto err; 815 } 816 817 for (i = 0; i < trans->num_rx_queues; i++) { 818 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 819 820 rxq->id = i; 821 ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 822 if (ret) 823 goto err; 824 } 825 return 0; 826 827 err: 828 if (trans_pcie->base_rb_stts) { 829 dma_free_coherent(trans->dev, 830 rb_stts_size * trans->num_rx_queues, 831 trans_pcie->base_rb_stts, 832 trans_pcie->base_rb_stts_dma); 833 trans_pcie->base_rb_stts = NULL; 834 trans_pcie->base_rb_stts_dma = 0; 835 } 836 kfree(trans_pcie->rx_pool); 837 kfree(trans_pcie->global_table); 838 kfree(trans_pcie->rxq); 839 840 return ret; 841 } 842 843 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 844 { 845 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 846 u32 rb_size; 847 unsigned long flags; 848 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 849 850 switch (trans_pcie->rx_buf_size) { 851 case IWL_AMSDU_4K: 852 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 853 break; 854 case IWL_AMSDU_8K: 855 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 856 break; 857 case IWL_AMSDU_12K: 858 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 859 break; 860 default: 861 WARN_ON(1); 862 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 863 } 864 865 if (!iwl_trans_grab_nic_access(trans, &flags)) 866 return; 867 868 /* Stop Rx DMA */ 869 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 870 /* reset and flush pointers */ 871 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 872 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 873 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 874 875 /* Reset driver's Rx queue write index */ 876 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 877 878 /* Tell device where to find RBD circular buffer in DRAM */ 879 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 880 (u32)(rxq->bd_dma >> 8)); 881 882 /* Tell device where in DRAM to update its Rx status */ 883 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 884 rxq->rb_stts_dma >> 4); 885 886 /* Enable Rx DMA 887 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 888 * the credit mechanism in 5000 HW RX FIFO 889 * Direct rx interrupts to hosts 890 * Rx buffer size 4 or 8k or 12k 891 * RB timeout 0x10 892 * 256 RBDs 893 */ 894 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 895 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 896 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 897 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 898 rb_size | 899 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 900 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 901 902 iwl_trans_release_nic_access(trans, &flags); 903 904 /* Set interrupt coalescing timer to default (2048 usecs) */ 905 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 906 907 /* W/A for interrupt coalescing bug in 7260 and 3160 */ 908 if (trans->cfg->host_interrupt_operation_mode) 909 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 910 } 911 912 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 913 { 914 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 915 u32 rb_size, enabled = 0; 916 unsigned long flags; 917 int i; 918 919 switch (trans_pcie->rx_buf_size) { 920 case IWL_AMSDU_2K: 921 rb_size = RFH_RXF_DMA_RB_SIZE_2K; 922 break; 923 case IWL_AMSDU_4K: 924 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 925 break; 926 case IWL_AMSDU_8K: 927 rb_size = RFH_RXF_DMA_RB_SIZE_8K; 928 break; 929 case IWL_AMSDU_12K: 930 rb_size = RFH_RXF_DMA_RB_SIZE_12K; 931 break; 932 default: 933 WARN_ON(1); 934 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 935 } 936 937 if (!iwl_trans_grab_nic_access(trans, &flags)) 938 return; 939 940 /* Stop Rx DMA */ 941 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 942 /* disable free amd used rx queue operation */ 943 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 944 945 for (i = 0; i < trans->num_rx_queues; i++) { 946 /* Tell device where to find RBD free table in DRAM */ 947 iwl_write_prph64_no_grab(trans, 948 RFH_Q_FRBDCB_BA_LSB(i), 949 trans_pcie->rxq[i].bd_dma); 950 /* Tell device where to find RBD used table in DRAM */ 951 iwl_write_prph64_no_grab(trans, 952 RFH_Q_URBDCB_BA_LSB(i), 953 trans_pcie->rxq[i].used_bd_dma); 954 /* Tell device where in DRAM to update its Rx status */ 955 iwl_write_prph64_no_grab(trans, 956 RFH_Q_URBD_STTS_WPTR_LSB(i), 957 trans_pcie->rxq[i].rb_stts_dma); 958 /* Reset device indice tables */ 959 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 960 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 961 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 962 963 enabled |= BIT(i) | BIT(i + 16); 964 } 965 966 /* 967 * Enable Rx DMA 968 * Rx buffer size 4 or 8k or 12k 969 * Min RB size 4 or 8 970 * Drop frames that exceed RB size 971 * 512 RBDs 972 */ 973 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 974 RFH_DMA_EN_ENABLE_VAL | rb_size | 975 RFH_RXF_DMA_MIN_RB_4_8 | 976 RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 977 RFH_RXF_DMA_RBDCB_SIZE_512); 978 979 /* 980 * Activate DMA snooping. 981 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 982 * Default queue is 0 983 */ 984 iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 985 RFH_GEN_CFG_RFH_DMA_SNOOP | 986 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 987 RFH_GEN_CFG_SERVICE_DMA_SNOOP | 988 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 989 trans->trans_cfg->integrated ? 990 RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 991 RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 992 /* Enable the relevant rx queues */ 993 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 994 995 iwl_trans_release_nic_access(trans, &flags); 996 997 /* Set interrupt coalescing timer to default (2048 usecs) */ 998 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 999 } 1000 1001 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 1002 { 1003 lockdep_assert_held(&rxq->lock); 1004 1005 INIT_LIST_HEAD(&rxq->rx_free); 1006 INIT_LIST_HEAD(&rxq->rx_used); 1007 rxq->free_count = 0; 1008 rxq->used_count = 0; 1009 } 1010 1011 int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) 1012 { 1013 WARN_ON(1); 1014 return 0; 1015 } 1016 1017 static int _iwl_pcie_rx_init(struct iwl_trans *trans) 1018 { 1019 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1020 struct iwl_rxq *def_rxq; 1021 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1022 int i, err, queue_size, allocator_pool_size, num_alloc; 1023 1024 if (!trans_pcie->rxq) { 1025 err = iwl_pcie_rx_alloc(trans); 1026 if (err) 1027 return err; 1028 } 1029 def_rxq = trans_pcie->rxq; 1030 1031 cancel_work_sync(&rba->rx_alloc); 1032 1033 spin_lock(&rba->lock); 1034 atomic_set(&rba->req_pending, 0); 1035 atomic_set(&rba->req_ready, 0); 1036 INIT_LIST_HEAD(&rba->rbd_allocated); 1037 INIT_LIST_HEAD(&rba->rbd_empty); 1038 spin_unlock(&rba->lock); 1039 1040 /* free all first - we might be reconfigured for a different size */ 1041 iwl_pcie_free_rbs_pool(trans); 1042 1043 for (i = 0; i < RX_QUEUE_SIZE; i++) 1044 def_rxq->queue[i] = NULL; 1045 1046 for (i = 0; i < trans->num_rx_queues; i++) { 1047 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1048 1049 spin_lock(&rxq->lock); 1050 /* 1051 * Set read write pointer to reflect that we have processed 1052 * and used all buffers, but have not restocked the Rx queue 1053 * with fresh buffers 1054 */ 1055 rxq->read = 0; 1056 rxq->write = 0; 1057 rxq->write_actual = 0; 1058 memset(rxq->rb_stts, 0, 1059 (trans->trans_cfg->device_family >= 1060 IWL_DEVICE_FAMILY_AX210) ? 1061 sizeof(__le16) : sizeof(struct iwl_rb_status)); 1062 1063 iwl_pcie_rx_init_rxb_lists(rxq); 1064 1065 if (!rxq->napi.poll) 1066 netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 1067 iwl_pcie_dummy_napi_poll, 64); 1068 1069 spin_unlock(&rxq->lock); 1070 } 1071 1072 /* move the pool to the default queue and allocator ownerships */ 1073 queue_size = trans->trans_cfg->mq_rx_supported ? 1074 trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE; 1075 allocator_pool_size = trans->num_rx_queues * 1076 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 1077 num_alloc = queue_size + allocator_pool_size; 1078 1079 for (i = 0; i < num_alloc; i++) { 1080 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 1081 1082 if (i < allocator_pool_size) 1083 list_add(&rxb->list, &rba->rbd_empty); 1084 else 1085 list_add(&rxb->list, &def_rxq->rx_used); 1086 trans_pcie->global_table[i] = rxb; 1087 rxb->vid = (u16)(i + 1); 1088 rxb->invalid = true; 1089 } 1090 1091 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 1092 1093 return 0; 1094 } 1095 1096 int iwl_pcie_rx_init(struct iwl_trans *trans) 1097 { 1098 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1099 int ret = _iwl_pcie_rx_init(trans); 1100 1101 if (ret) 1102 return ret; 1103 1104 if (trans->trans_cfg->mq_rx_supported) 1105 iwl_pcie_rx_mq_hw_init(trans); 1106 else 1107 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 1108 1109 iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 1110 1111 spin_lock(&trans_pcie->rxq->lock); 1112 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 1113 spin_unlock(&trans_pcie->rxq->lock); 1114 1115 return 0; 1116 } 1117 1118 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1119 { 1120 /* Set interrupt coalescing timer to default (2048 usecs) */ 1121 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1122 1123 /* 1124 * We don't configure the RFH. 1125 * Restock will be done at alive, after firmware configured the RFH. 1126 */ 1127 return _iwl_pcie_rx_init(trans); 1128 } 1129 1130 void iwl_pcie_rx_free(struct iwl_trans *trans) 1131 { 1132 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1133 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1134 int i; 1135 size_t rb_stts_size = trans->trans_cfg->device_family >= 1136 IWL_DEVICE_FAMILY_AX210 ? 1137 sizeof(__le16) : sizeof(struct iwl_rb_status); 1138 1139 /* 1140 * if rxq is NULL, it means that nothing has been allocated, 1141 * exit now 1142 */ 1143 if (!trans_pcie->rxq) { 1144 IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1145 return; 1146 } 1147 1148 cancel_work_sync(&rba->rx_alloc); 1149 1150 iwl_pcie_free_rbs_pool(trans); 1151 1152 if (trans_pcie->base_rb_stts) { 1153 dma_free_coherent(trans->dev, 1154 rb_stts_size * trans->num_rx_queues, 1155 trans_pcie->base_rb_stts, 1156 trans_pcie->base_rb_stts_dma); 1157 trans_pcie->base_rb_stts = NULL; 1158 trans_pcie->base_rb_stts_dma = 0; 1159 } 1160 1161 for (i = 0; i < trans->num_rx_queues; i++) { 1162 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1163 1164 iwl_pcie_free_rxq_dma(trans, rxq); 1165 1166 if (rxq->napi.poll) 1167 netif_napi_del(&rxq->napi); 1168 } 1169 kfree(trans_pcie->rx_pool); 1170 kfree(trans_pcie->global_table); 1171 kfree(trans_pcie->rxq); 1172 1173 if (trans_pcie->alloc_page) 1174 __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order); 1175 } 1176 1177 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq, 1178 struct iwl_rb_allocator *rba) 1179 { 1180 spin_lock(&rba->lock); 1181 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1182 spin_unlock(&rba->lock); 1183 } 1184 1185 /* 1186 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1187 * 1188 * Called when a RBD can be reused. The RBD is transferred to the allocator. 1189 * When there are 2 empty RBDs - a request for allocation is posted 1190 */ 1191 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1192 struct iwl_rx_mem_buffer *rxb, 1193 struct iwl_rxq *rxq, bool emergency) 1194 { 1195 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1196 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1197 1198 /* Move the RBD to the used list, will be moved to allocator in batches 1199 * before claiming or posting a request*/ 1200 list_add_tail(&rxb->list, &rxq->rx_used); 1201 1202 if (unlikely(emergency)) 1203 return; 1204 1205 /* Count the allocator owned RBDs */ 1206 rxq->used_count++; 1207 1208 /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1209 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1210 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1211 * after but we still need to post another request. 1212 */ 1213 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1214 /* Move the 2 RBDs to the allocator ownership. 1215 Allocator has another 6 from pool for the request completion*/ 1216 iwl_pcie_rx_move_to_allocator(rxq, rba); 1217 1218 atomic_inc(&rba->req_pending); 1219 queue_work(rba->alloc_wq, &rba->rx_alloc); 1220 } 1221 } 1222 1223 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 1224 struct iwl_rxq *rxq, 1225 struct iwl_rx_mem_buffer *rxb, 1226 bool emergency, 1227 int i) 1228 { 1229 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1230 struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id]; 1231 bool page_stolen = false; 1232 int max_len = trans_pcie->rx_buf_bytes; 1233 u32 offset = 0; 1234 1235 if (WARN_ON(!rxb)) 1236 return; 1237 1238 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1239 1240 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1241 struct iwl_rx_packet *pkt; 1242 bool reclaim; 1243 int len; 1244 struct iwl_rx_cmd_buffer rxcb = { 1245 ._offset = rxb->offset + offset, 1246 ._rx_page_order = trans_pcie->rx_page_order, 1247 ._page = rxb->page, 1248 ._page_stolen = false, 1249 .truesize = max_len, 1250 }; 1251 1252 pkt = rxb_addr(&rxcb); 1253 1254 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 1255 IWL_DEBUG_RX(trans, 1256 "Q %d: RB end marker at offset %d\n", 1257 rxq->id, offset); 1258 break; 1259 } 1260 1261 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1262 FH_RSCSR_RXQ_POS != rxq->id, 1263 "frame on invalid queue - is on %d and indicates %d\n", 1264 rxq->id, 1265 (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1266 FH_RSCSR_RXQ_POS); 1267 1268 IWL_DEBUG_RX(trans, 1269 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 1270 rxq->id, offset, 1271 iwl_get_cmd_string(trans, 1272 iwl_cmd_id(pkt->hdr.cmd, 1273 pkt->hdr.group_id, 1274 0)), 1275 pkt->hdr.group_id, pkt->hdr.cmd, 1276 le16_to_cpu(pkt->hdr.sequence)); 1277 1278 len = iwl_rx_packet_len(pkt); 1279 len += sizeof(u32); /* account for status word */ 1280 1281 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1282 1283 /* check that what the device tells us made sense */ 1284 if (offset > max_len) 1285 break; 1286 1287 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1288 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1289 1290 /* Reclaim a command buffer only if this packet is a response 1291 * to a (driver-originated) command. 1292 * If the packet (e.g. Rx frame) originated from uCode, 1293 * there is no command buffer to reclaim. 1294 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1295 * but apparently a few don't get set; catch them here. */ 1296 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1297 if (reclaim && !pkt->hdr.group_id) { 1298 int i; 1299 1300 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1301 if (trans_pcie->no_reclaim_cmds[i] == 1302 pkt->hdr.cmd) { 1303 reclaim = false; 1304 break; 1305 } 1306 } 1307 } 1308 1309 if (rxq->id == trans_pcie->def_rx_queue) 1310 iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1311 &rxcb); 1312 else 1313 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1314 &rxcb, rxq->id); 1315 1316 /* 1317 * After here, we should always check rxcb._page_stolen, 1318 * if it is true then one of the handlers took the page. 1319 */ 1320 1321 if (reclaim) { 1322 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1323 int index = SEQ_TO_INDEX(sequence); 1324 int cmd_index = iwl_txq_get_cmd_index(txq, index); 1325 1326 kfree_sensitive(txq->entries[cmd_index].free_buf); 1327 txq->entries[cmd_index].free_buf = NULL; 1328 1329 /* Invoke any callbacks, transfer the buffer to caller, 1330 * and fire off the (possibly) blocking 1331 * iwl_trans_send_cmd() 1332 * as we reclaim the driver command queue */ 1333 if (!rxcb._page_stolen) 1334 iwl_pcie_hcmd_complete(trans, &rxcb); 1335 else 1336 IWL_WARN(trans, "Claim null rxb?\n"); 1337 } 1338 1339 page_stolen |= rxcb._page_stolen; 1340 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1341 break; 1342 } 1343 1344 /* page was stolen from us -- free our reference */ 1345 if (page_stolen) { 1346 __free_pages(rxb->page, trans_pcie->rx_page_order); 1347 rxb->page = NULL; 1348 } 1349 1350 /* Reuse the page if possible. For notification packets and 1351 * SKBs that fail to Rx correctly, add them back into the 1352 * rx_free list for reuse later. */ 1353 if (rxb->page != NULL) { 1354 rxb->page_dma = 1355 dma_map_page(trans->dev, rxb->page, rxb->offset, 1356 trans_pcie->rx_buf_bytes, 1357 DMA_FROM_DEVICE); 1358 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1359 /* 1360 * free the page(s) as well to not break 1361 * the invariant that the items on the used 1362 * list have no page(s) 1363 */ 1364 __free_pages(rxb->page, trans_pcie->rx_page_order); 1365 rxb->page = NULL; 1366 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1367 } else { 1368 list_add_tail(&rxb->list, &rxq->rx_free); 1369 rxq->free_count++; 1370 } 1371 } else 1372 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1373 } 1374 1375 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans, 1376 struct iwl_rxq *rxq, int i, 1377 bool *join) 1378 { 1379 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1380 struct iwl_rx_mem_buffer *rxb; 1381 u16 vid; 1382 1383 BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32); 1384 1385 if (!trans->trans_cfg->mq_rx_supported) { 1386 rxb = rxq->queue[i]; 1387 rxq->queue[i] = NULL; 1388 return rxb; 1389 } 1390 1391 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1392 vid = le16_to_cpu(rxq->cd[i].rbid); 1393 *join = rxq->cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED; 1394 } else { 1395 vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; /* 12-bit VID */ 1396 } 1397 1398 if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs)) 1399 goto out_err; 1400 1401 rxb = trans_pcie->global_table[vid - 1]; 1402 if (rxb->invalid) 1403 goto out_err; 1404 1405 IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid); 1406 1407 rxb->invalid = true; 1408 1409 return rxb; 1410 1411 out_err: 1412 WARN(1, "Invalid rxb from HW %u\n", (u32)vid); 1413 iwl_force_nmi(trans); 1414 return NULL; 1415 } 1416 1417 /* 1418 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1419 */ 1420 static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue) 1421 { 1422 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1423 struct napi_struct *napi; 1424 struct iwl_rxq *rxq; 1425 u32 r, i, count = 0; 1426 bool emergency = false; 1427 1428 if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd)) 1429 return; 1430 1431 rxq = &trans_pcie->rxq[queue]; 1432 1433 restart: 1434 spin_lock(&rxq->lock); 1435 /* uCode's read index (stored in shared DRAM) indicates the last Rx 1436 * buffer that the driver may process (last buffer filled by ucode). */ 1437 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1438 i = rxq->read; 1439 1440 /* W/A 9000 device step A0 wrap-around bug */ 1441 r &= (rxq->queue_size - 1); 1442 1443 /* Rx interrupt, but nothing sent from uCode */ 1444 if (i == r) 1445 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1446 1447 while (i != r) { 1448 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1449 struct iwl_rx_mem_buffer *rxb; 1450 /* number of RBDs still waiting for page allocation */ 1451 u32 rb_pending_alloc = 1452 atomic_read(&trans_pcie->rba.req_pending) * 1453 RX_CLAIM_REQ_ALLOC; 1454 bool join = false; 1455 1456 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 && 1457 !emergency)) { 1458 iwl_pcie_rx_move_to_allocator(rxq, rba); 1459 emergency = true; 1460 IWL_DEBUG_TPT(trans, 1461 "RX path is in emergency. Pending allocations %d\n", 1462 rb_pending_alloc); 1463 } 1464 1465 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 1466 1467 rxb = iwl_pcie_get_rxb(trans, rxq, i, &join); 1468 if (!rxb) 1469 goto out; 1470 1471 if (unlikely(join || rxq->next_rb_is_fragment)) { 1472 rxq->next_rb_is_fragment = join; 1473 /* 1474 * We can only get a multi-RB in the following cases: 1475 * - firmware issue, sending a too big notification 1476 * - sniffer mode with a large A-MSDU 1477 * - large MTU frames (>2k) 1478 * since the multi-RB functionality is limited to newer 1479 * hardware that cannot put multiple entries into a 1480 * single RB. 1481 * 1482 * Right now, the higher layers aren't set up to deal 1483 * with that, so discard all of these. 1484 */ 1485 list_add_tail(&rxb->list, &rxq->rx_free); 1486 rxq->free_count++; 1487 } else { 1488 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i); 1489 } 1490 1491 i = (i + 1) & (rxq->queue_size - 1); 1492 1493 /* 1494 * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1495 * try to claim the pre-allocated buffers from the allocator. 1496 * If not ready - will try to reclaim next time. 1497 * There is no need to reschedule work - allocator exits only 1498 * on success 1499 */ 1500 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1501 iwl_pcie_rx_allocator_get(trans, rxq); 1502 1503 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1504 /* Add the remaining empty RBDs for allocator use */ 1505 iwl_pcie_rx_move_to_allocator(rxq, rba); 1506 } else if (emergency) { 1507 count++; 1508 if (count == 8) { 1509 count = 0; 1510 if (rb_pending_alloc < rxq->queue_size / 3) { 1511 IWL_DEBUG_TPT(trans, 1512 "RX path exited emergency. Pending allocations %d\n", 1513 rb_pending_alloc); 1514 emergency = false; 1515 } 1516 1517 rxq->read = i; 1518 spin_unlock(&rxq->lock); 1519 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1520 iwl_pcie_rxq_restock(trans, rxq); 1521 goto restart; 1522 } 1523 } 1524 } 1525 out: 1526 /* Backtrack one entry */ 1527 rxq->read = i; 1528 /* update cr tail with the rxq read pointer */ 1529 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1530 *rxq->cr_tail = cpu_to_le16(r); 1531 spin_unlock(&rxq->lock); 1532 1533 /* 1534 * handle a case where in emergency there are some unallocated RBDs. 1535 * those RBDs are in the used list, but are not tracked by the queue's 1536 * used_count which counts allocator owned RBDs. 1537 * unallocated emergency RBDs must be allocated on exit, otherwise 1538 * when called again the function may not be in emergency mode and 1539 * they will be handed to the allocator with no tracking in the RBD 1540 * allocator counters, which will lead to them never being claimed back 1541 * by the queue. 1542 * by allocating them here, they are now in the queue free list, and 1543 * will be restocked by the next call of iwl_pcie_rxq_restock. 1544 */ 1545 if (unlikely(emergency && count)) 1546 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1547 1548 napi = &rxq->napi; 1549 if (napi->poll) { 1550 napi_gro_flush(napi, false); 1551 1552 if (napi->rx_count) { 1553 netif_receive_skb_list(&napi->rx_list); 1554 INIT_LIST_HEAD(&napi->rx_list); 1555 napi->rx_count = 0; 1556 } 1557 } 1558 1559 iwl_pcie_rxq_restock(trans, rxq); 1560 } 1561 1562 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 1563 { 1564 u8 queue = entry->entry; 1565 struct msix_entry *entries = entry - queue; 1566 1567 return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 1568 } 1569 1570 /* 1571 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 1572 * This interrupt handler should be used with RSS queue only. 1573 */ 1574 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 1575 { 1576 struct msix_entry *entry = dev_id; 1577 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 1578 struct iwl_trans *trans = trans_pcie->trans; 1579 1580 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1581 1582 if (WARN_ON(entry->entry >= trans->num_rx_queues)) 1583 return IRQ_NONE; 1584 1585 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1586 1587 local_bh_disable(); 1588 iwl_pcie_rx_handle(trans, entry->entry); 1589 local_bh_enable(); 1590 1591 iwl_pcie_clear_irq(trans, entry); 1592 1593 lock_map_release(&trans->sync_cmd_lockdep_map); 1594 1595 return IRQ_HANDLED; 1596 } 1597 1598 /* 1599 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1600 */ 1601 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1602 { 1603 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1604 int i; 1605 1606 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1607 if (trans->cfg->internal_wimax_coex && 1608 !trans->cfg->apmg_not_supported && 1609 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1610 APMS_CLK_VAL_MRB_FUNC_MODE) || 1611 (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1612 APMG_PS_CTRL_VAL_RESET_REQ))) { 1613 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1614 iwl_op_mode_wimax_active(trans->op_mode); 1615 wake_up(&trans_pcie->wait_command_queue); 1616 return; 1617 } 1618 1619 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 1620 if (!trans->txqs.txq[i]) 1621 continue; 1622 del_timer(&trans->txqs.txq[i]->stuck_timer); 1623 } 1624 1625 /* The STATUS_FW_ERROR bit is set in this function. This must happen 1626 * before we wake up the command caller, to ensure a proper cleanup. */ 1627 iwl_trans_fw_error(trans); 1628 1629 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1630 wake_up(&trans_pcie->wait_command_queue); 1631 } 1632 1633 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1634 { 1635 u32 inta; 1636 1637 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1638 1639 trace_iwlwifi_dev_irq(trans->dev); 1640 1641 /* Discover which interrupts are active/pending */ 1642 inta = iwl_read32(trans, CSR_INT); 1643 1644 /* the thread will service interrupts and re-enable them */ 1645 return inta; 1646 } 1647 1648 /* a device (PCI-E) page is 4096 bytes long */ 1649 #define ICT_SHIFT 12 1650 #define ICT_SIZE (1 << ICT_SHIFT) 1651 #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1652 1653 /* interrupt handler using ict table, with this interrupt driver will 1654 * stop using INTA register to get device's interrupt, reading this register 1655 * is expensive, device will write interrupts in ICT dram table, increment 1656 * index then will fire interrupt to driver, driver will OR all ICT table 1657 * entries from current index up to table entry with 0 value. the result is 1658 * the interrupt we need to service, driver will set the entries back to 0 and 1659 * set index. 1660 */ 1661 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1662 { 1663 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1664 u32 inta; 1665 u32 val = 0; 1666 u32 read; 1667 1668 trace_iwlwifi_dev_irq(trans->dev); 1669 1670 /* Ignore interrupt if there's nothing in NIC to service. 1671 * This may be due to IRQ shared with another device, 1672 * or due to sporadic interrupts thrown from our NIC. */ 1673 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1674 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1675 if (!read) 1676 return 0; 1677 1678 /* 1679 * Collect all entries up to the first 0, starting from ict_index; 1680 * note we already read at ict_index. 1681 */ 1682 do { 1683 val |= read; 1684 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1685 trans_pcie->ict_index, read); 1686 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1687 trans_pcie->ict_index = 1688 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1689 1690 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1691 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1692 read); 1693 } while (read); 1694 1695 /* We should not get this value, just ignore it. */ 1696 if (val == 0xffffffff) 1697 val = 0; 1698 1699 /* 1700 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1701 * (bit 15 before shifting it to 31) to clear when using interrupt 1702 * coalescing. fortunately, bits 18 and 19 stay set when this happens 1703 * so we use them to decide on the real state of the Rx bit. 1704 * In order words, bit 15 is set if bit 18 or bit 19 are set. 1705 */ 1706 if (val & 0xC0000) 1707 val |= 0x8000; 1708 1709 inta = (0xff & val) | ((0xff00 & val) << 16); 1710 return inta; 1711 } 1712 1713 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 1714 { 1715 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1716 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1717 bool hw_rfkill, prev, report; 1718 1719 mutex_lock(&trans_pcie->mutex); 1720 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1721 hw_rfkill = iwl_is_rfkill_set(trans); 1722 if (hw_rfkill) { 1723 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1724 set_bit(STATUS_RFKILL_HW, &trans->status); 1725 } 1726 if (trans_pcie->opmode_down) 1727 report = hw_rfkill; 1728 else 1729 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1730 1731 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 1732 hw_rfkill ? "disable radio" : "enable radio"); 1733 1734 isr_stats->rfkill++; 1735 1736 if (prev != report) 1737 iwl_trans_pcie_rf_kill(trans, report); 1738 mutex_unlock(&trans_pcie->mutex); 1739 1740 if (hw_rfkill) { 1741 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 1742 &trans->status)) 1743 IWL_DEBUG_RF_KILL(trans, 1744 "Rfkill while SYNC HCMD in flight\n"); 1745 wake_up(&trans_pcie->wait_command_queue); 1746 } else { 1747 clear_bit(STATUS_RFKILL_HW, &trans->status); 1748 if (trans_pcie->opmode_down) 1749 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1750 } 1751 } 1752 1753 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1754 { 1755 struct iwl_trans *trans = dev_id; 1756 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1757 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1758 u32 inta = 0; 1759 u32 handled = 0; 1760 1761 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1762 1763 spin_lock(&trans_pcie->irq_lock); 1764 1765 /* dram interrupt table not set yet, 1766 * use legacy interrupt. 1767 */ 1768 if (likely(trans_pcie->use_ict)) 1769 inta = iwl_pcie_int_cause_ict(trans); 1770 else 1771 inta = iwl_pcie_int_cause_non_ict(trans); 1772 1773 if (iwl_have_debug_level(IWL_DL_ISR)) { 1774 IWL_DEBUG_ISR(trans, 1775 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1776 inta, trans_pcie->inta_mask, 1777 iwl_read32(trans, CSR_INT_MASK), 1778 iwl_read32(trans, CSR_FH_INT_STATUS)); 1779 if (inta & (~trans_pcie->inta_mask)) 1780 IWL_DEBUG_ISR(trans, 1781 "We got a masked interrupt (0x%08x)\n", 1782 inta & (~trans_pcie->inta_mask)); 1783 } 1784 1785 inta &= trans_pcie->inta_mask; 1786 1787 /* 1788 * Ignore interrupt if there's nothing in NIC to service. 1789 * This may be due to IRQ shared with another device, 1790 * or due to sporadic interrupts thrown from our NIC. 1791 */ 1792 if (unlikely(!inta)) { 1793 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1794 /* 1795 * Re-enable interrupts here since we don't 1796 * have anything to service 1797 */ 1798 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1799 _iwl_enable_interrupts(trans); 1800 spin_unlock(&trans_pcie->irq_lock); 1801 lock_map_release(&trans->sync_cmd_lockdep_map); 1802 return IRQ_NONE; 1803 } 1804 1805 if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1806 /* 1807 * Hardware disappeared. It might have 1808 * already raised an interrupt. 1809 */ 1810 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1811 spin_unlock(&trans_pcie->irq_lock); 1812 goto out; 1813 } 1814 1815 /* Ack/clear/reset pending uCode interrupts. 1816 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1817 */ 1818 /* There is a hardware bug in the interrupt mask function that some 1819 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1820 * they are disabled in the CSR_INT_MASK register. Furthermore the 1821 * ICT interrupt handling mechanism has another bug that might cause 1822 * these unmasked interrupts fail to be detected. We workaround the 1823 * hardware bugs here by ACKing all the possible interrupts so that 1824 * interrupt coalescing can still be achieved. 1825 */ 1826 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1827 1828 if (iwl_have_debug_level(IWL_DL_ISR)) 1829 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1830 inta, iwl_read32(trans, CSR_INT_MASK)); 1831 1832 spin_unlock(&trans_pcie->irq_lock); 1833 1834 /* Now service all interrupt bits discovered above. */ 1835 if (inta & CSR_INT_BIT_HW_ERR) { 1836 IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1837 1838 /* Tell the device to stop sending interrupts */ 1839 iwl_disable_interrupts(trans); 1840 1841 isr_stats->hw++; 1842 iwl_pcie_irq_handle_error(trans); 1843 1844 handled |= CSR_INT_BIT_HW_ERR; 1845 1846 goto out; 1847 } 1848 1849 /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1850 if (inta & CSR_INT_BIT_SCD) { 1851 IWL_DEBUG_ISR(trans, 1852 "Scheduler finished to transmit the frame/frames.\n"); 1853 isr_stats->sch++; 1854 } 1855 1856 /* Alive notification via Rx interrupt will do the real work */ 1857 if (inta & CSR_INT_BIT_ALIVE) { 1858 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1859 isr_stats->alive++; 1860 if (trans->trans_cfg->gen2) { 1861 /* 1862 * We can restock, since firmware configured 1863 * the RFH 1864 */ 1865 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1866 } 1867 1868 handled |= CSR_INT_BIT_ALIVE; 1869 } 1870 1871 /* Safely ignore these bits for debug checks below */ 1872 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1873 1874 /* HW RF KILL switch toggled */ 1875 if (inta & CSR_INT_BIT_RF_KILL) { 1876 iwl_pcie_handle_rfkill_irq(trans); 1877 handled |= CSR_INT_BIT_RF_KILL; 1878 } 1879 1880 /* Chip got too hot and stopped itself */ 1881 if (inta & CSR_INT_BIT_CT_KILL) { 1882 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1883 isr_stats->ctkill++; 1884 handled |= CSR_INT_BIT_CT_KILL; 1885 } 1886 1887 /* Error detected by uCode */ 1888 if (inta & CSR_INT_BIT_SW_ERR) { 1889 IWL_ERR(trans, "Microcode SW error detected. " 1890 " Restarting 0x%X.\n", inta); 1891 isr_stats->sw++; 1892 iwl_pcie_irq_handle_error(trans); 1893 handled |= CSR_INT_BIT_SW_ERR; 1894 } 1895 1896 /* uCode wakes up after power-down sleep */ 1897 if (inta & CSR_INT_BIT_WAKEUP) { 1898 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1899 iwl_pcie_rxq_check_wrptr(trans); 1900 iwl_pcie_txq_check_wrptrs(trans); 1901 1902 isr_stats->wakeup++; 1903 1904 handled |= CSR_INT_BIT_WAKEUP; 1905 } 1906 1907 /* All uCode command responses, including Tx command responses, 1908 * Rx "responses" (frame-received notification), and other 1909 * notifications from uCode come through here*/ 1910 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1911 CSR_INT_BIT_RX_PERIODIC)) { 1912 IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1913 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1914 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1915 iwl_write32(trans, CSR_FH_INT_STATUS, 1916 CSR_FH_INT_RX_MASK); 1917 } 1918 if (inta & CSR_INT_BIT_RX_PERIODIC) { 1919 handled |= CSR_INT_BIT_RX_PERIODIC; 1920 iwl_write32(trans, 1921 CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1922 } 1923 /* Sending RX interrupt require many steps to be done in the 1924 * the device: 1925 * 1- write interrupt to current index in ICT table. 1926 * 2- dma RX frame. 1927 * 3- update RX shared data to indicate last write index. 1928 * 4- send interrupt. 1929 * This could lead to RX race, driver could receive RX interrupt 1930 * but the shared data changes does not reflect this; 1931 * periodic interrupt will detect any dangling Rx activity. 1932 */ 1933 1934 /* Disable periodic interrupt; we use it as just a one-shot. */ 1935 iwl_write8(trans, CSR_INT_PERIODIC_REG, 1936 CSR_INT_PERIODIC_DIS); 1937 1938 /* 1939 * Enable periodic interrupt in 8 msec only if we received 1940 * real RX interrupt (instead of just periodic int), to catch 1941 * any dangling Rx interrupt. If it was just the periodic 1942 * interrupt, there was no dangling Rx activity, and no need 1943 * to extend the periodic interrupt; one-shot is enough. 1944 */ 1945 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1946 iwl_write8(trans, CSR_INT_PERIODIC_REG, 1947 CSR_INT_PERIODIC_ENA); 1948 1949 isr_stats->rx++; 1950 1951 local_bh_disable(); 1952 iwl_pcie_rx_handle(trans, 0); 1953 local_bh_enable(); 1954 } 1955 1956 /* This "Tx" DMA channel is used only for loading uCode */ 1957 if (inta & CSR_INT_BIT_FH_TX) { 1958 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1959 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1960 isr_stats->tx++; 1961 handled |= CSR_INT_BIT_FH_TX; 1962 /* Wake up uCode load routine, now that load is complete */ 1963 trans_pcie->ucode_write_complete = true; 1964 wake_up(&trans_pcie->ucode_write_waitq); 1965 } 1966 1967 if (inta & ~handled) { 1968 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 1969 isr_stats->unhandled++; 1970 } 1971 1972 if (inta & ~(trans_pcie->inta_mask)) { 1973 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 1974 inta & ~trans_pcie->inta_mask); 1975 } 1976 1977 spin_lock(&trans_pcie->irq_lock); 1978 /* only Re-enable all interrupt if disabled by irq */ 1979 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1980 _iwl_enable_interrupts(trans); 1981 /* we are loading the firmware, enable FH_TX interrupt only */ 1982 else if (handled & CSR_INT_BIT_FH_TX) 1983 iwl_enable_fw_load_int(trans); 1984 /* Re-enable RF_KILL if it occurred */ 1985 else if (handled & CSR_INT_BIT_RF_KILL) 1986 iwl_enable_rfkill_int(trans); 1987 /* Re-enable the ALIVE / Rx interrupt if it occurred */ 1988 else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX)) 1989 iwl_enable_fw_load_int_ctx_info(trans); 1990 spin_unlock(&trans_pcie->irq_lock); 1991 1992 out: 1993 lock_map_release(&trans->sync_cmd_lockdep_map); 1994 return IRQ_HANDLED; 1995 } 1996 1997 /****************************************************************************** 1998 * 1999 * ICT functions 2000 * 2001 ******************************************************************************/ 2002 2003 /* Free dram table */ 2004 void iwl_pcie_free_ict(struct iwl_trans *trans) 2005 { 2006 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2007 2008 if (trans_pcie->ict_tbl) { 2009 dma_free_coherent(trans->dev, ICT_SIZE, 2010 trans_pcie->ict_tbl, 2011 trans_pcie->ict_tbl_dma); 2012 trans_pcie->ict_tbl = NULL; 2013 trans_pcie->ict_tbl_dma = 0; 2014 } 2015 } 2016 2017 /* 2018 * allocate dram shared table, it is an aligned memory 2019 * block of ICT_SIZE. 2020 * also reset all data related to ICT table interrupt. 2021 */ 2022 int iwl_pcie_alloc_ict(struct iwl_trans *trans) 2023 { 2024 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2025 2026 trans_pcie->ict_tbl = 2027 dma_alloc_coherent(trans->dev, ICT_SIZE, 2028 &trans_pcie->ict_tbl_dma, GFP_KERNEL); 2029 if (!trans_pcie->ict_tbl) 2030 return -ENOMEM; 2031 2032 /* just an API sanity check ... it is guaranteed to be aligned */ 2033 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 2034 iwl_pcie_free_ict(trans); 2035 return -EINVAL; 2036 } 2037 2038 return 0; 2039 } 2040 2041 /* Device is going up inform it about using ICT interrupt table, 2042 * also we need to tell the driver to start using ICT interrupt. 2043 */ 2044 void iwl_pcie_reset_ict(struct iwl_trans *trans) 2045 { 2046 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2047 u32 val; 2048 2049 if (!trans_pcie->ict_tbl) 2050 return; 2051 2052 spin_lock(&trans_pcie->irq_lock); 2053 _iwl_disable_interrupts(trans); 2054 2055 memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 2056 2057 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 2058 2059 val |= CSR_DRAM_INT_TBL_ENABLE | 2060 CSR_DRAM_INIT_TBL_WRAP_CHECK | 2061 CSR_DRAM_INIT_TBL_WRITE_POINTER; 2062 2063 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 2064 2065 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 2066 trans_pcie->use_ict = true; 2067 trans_pcie->ict_index = 0; 2068 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 2069 _iwl_enable_interrupts(trans); 2070 spin_unlock(&trans_pcie->irq_lock); 2071 } 2072 2073 /* Device is going down disable ict interrupt usage */ 2074 void iwl_pcie_disable_ict(struct iwl_trans *trans) 2075 { 2076 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2077 2078 spin_lock(&trans_pcie->irq_lock); 2079 trans_pcie->use_ict = false; 2080 spin_unlock(&trans_pcie->irq_lock); 2081 } 2082 2083 irqreturn_t iwl_pcie_isr(int irq, void *data) 2084 { 2085 struct iwl_trans *trans = data; 2086 2087 if (!trans) 2088 return IRQ_NONE; 2089 2090 /* Disable (but don't clear!) interrupts here to avoid 2091 * back-to-back ISRs and sporadic interrupts from our NIC. 2092 * If we have something to service, the tasklet will re-enable ints. 2093 * If we *don't* have something, we'll re-enable before leaving here. 2094 */ 2095 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2096 2097 return IRQ_WAKE_THREAD; 2098 } 2099 2100 irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 2101 { 2102 return IRQ_WAKE_THREAD; 2103 } 2104 2105 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 2106 { 2107 struct msix_entry *entry = dev_id; 2108 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 2109 struct iwl_trans *trans = trans_pcie->trans; 2110 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2111 u32 inta_fh, inta_hw; 2112 2113 lock_map_acquire(&trans->sync_cmd_lockdep_map); 2114 2115 spin_lock(&trans_pcie->irq_lock); 2116 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 2117 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 2118 /* 2119 * Clear causes registers to avoid being handling the same cause. 2120 */ 2121 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 2122 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 2123 spin_unlock(&trans_pcie->irq_lock); 2124 2125 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2126 2127 if (unlikely(!(inta_fh | inta_hw))) { 2128 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 2129 lock_map_release(&trans->sync_cmd_lockdep_map); 2130 return IRQ_NONE; 2131 } 2132 2133 if (iwl_have_debug_level(IWL_DL_ISR)) { 2134 IWL_DEBUG_ISR(trans, 2135 "ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 2136 inta_fh, trans_pcie->fh_mask, 2137 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 2138 if (inta_fh & ~trans_pcie->fh_mask) 2139 IWL_DEBUG_ISR(trans, 2140 "We got a masked interrupt (0x%08x)\n", 2141 inta_fh & ~trans_pcie->fh_mask); 2142 } 2143 2144 inta_fh &= trans_pcie->fh_mask; 2145 2146 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2147 inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2148 local_bh_disable(); 2149 iwl_pcie_rx_handle(trans, 0); 2150 local_bh_enable(); 2151 } 2152 2153 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2154 inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2155 local_bh_disable(); 2156 iwl_pcie_rx_handle(trans, 1); 2157 local_bh_enable(); 2158 } 2159 2160 /* This "Tx" DMA channel is used only for loading uCode */ 2161 if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 2162 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 2163 isr_stats->tx++; 2164 /* 2165 * Wake up uCode load routine, 2166 * now that load is complete 2167 */ 2168 trans_pcie->ucode_write_complete = true; 2169 wake_up(&trans_pcie->ucode_write_waitq); 2170 } 2171 2172 /* Error detected by uCode */ 2173 if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 2174 (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) { 2175 IWL_ERR(trans, 2176 "Microcode SW error detected. Restarting 0x%X.\n", 2177 inta_fh); 2178 isr_stats->sw++; 2179 iwl_pcie_irq_handle_error(trans); 2180 } 2181 2182 /* After checking FH register check HW register */ 2183 if (iwl_have_debug_level(IWL_DL_ISR)) { 2184 IWL_DEBUG_ISR(trans, 2185 "ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 2186 inta_hw, trans_pcie->hw_mask, 2187 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 2188 if (inta_hw & ~trans_pcie->hw_mask) 2189 IWL_DEBUG_ISR(trans, 2190 "We got a masked interrupt 0x%08x\n", 2191 inta_hw & ~trans_pcie->hw_mask); 2192 } 2193 2194 inta_hw &= trans_pcie->hw_mask; 2195 2196 /* Alive notification via Rx interrupt will do the real work */ 2197 if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 2198 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 2199 isr_stats->alive++; 2200 if (trans->trans_cfg->gen2) { 2201 /* We can restock, since firmware configured the RFH */ 2202 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2203 } 2204 } 2205 2206 if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 2207 u32 sleep_notif = 2208 le32_to_cpu(trans_pcie->prph_info->sleep_notif); 2209 if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND || 2210 sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) { 2211 IWL_DEBUG_ISR(trans, 2212 "Sx interrupt: sleep notification = 0x%x\n", 2213 sleep_notif); 2214 trans_pcie->sx_complete = true; 2215 wake_up(&trans_pcie->sx_waitq); 2216 } else { 2217 /* uCode wakes up after power-down sleep */ 2218 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 2219 iwl_pcie_rxq_check_wrptr(trans); 2220 iwl_pcie_txq_check_wrptrs(trans); 2221 2222 isr_stats->wakeup++; 2223 } 2224 } 2225 2226 /* Chip got too hot and stopped itself */ 2227 if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 2228 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 2229 isr_stats->ctkill++; 2230 } 2231 2232 /* HW RF KILL switch toggled */ 2233 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 2234 iwl_pcie_handle_rfkill_irq(trans); 2235 2236 if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 2237 IWL_ERR(trans, 2238 "Hardware error detected. Restarting.\n"); 2239 2240 isr_stats->hw++; 2241 trans->dbg.hw_error = true; 2242 iwl_pcie_irq_handle_error(trans); 2243 } 2244 2245 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE) { 2246 IWL_DEBUG_ISR(trans, "Reset flow completed\n"); 2247 trans_pcie->fw_reset_done = true; 2248 wake_up(&trans_pcie->fw_reset_waitq); 2249 } 2250 2251 iwl_pcie_clear_irq(trans, entry); 2252 2253 lock_map_release(&trans->sync_cmd_lockdep_map); 2254 2255 return IRQ_HANDLED; 2256 } 2257