1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2003-2014, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/sched.h> 8 #include <linux/wait.h> 9 #include <linux/gfp.h> 10 11 #include "iwl-prph.h" 12 #include "iwl-io.h" 13 #include "internal.h" 14 #include "iwl-op-mode.h" 15 #include "iwl-context-info-gen3.h" 16 17 /****************************************************************************** 18 * 19 * RX path functions 20 * 21 ******************************************************************************/ 22 23 /* 24 * Rx theory of operation 25 * 26 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 27 * each of which point to Receive Buffers to be filled by the NIC. These get 28 * used not only for Rx frames, but for any command response or notification 29 * from the NIC. The driver and NIC manage the Rx buffers by means 30 * of indexes into the circular buffer. 31 * 32 * Rx Queue Indexes 33 * The host/firmware share two index registers for managing the Rx buffers. 34 * 35 * The READ index maps to the first position that the firmware may be writing 36 * to -- the driver can read up to (but not including) this position and get 37 * good data. 38 * The READ index is managed by the firmware once the card is enabled. 39 * 40 * The WRITE index maps to the last position the driver has read from -- the 41 * position preceding WRITE is the last slot the firmware can place a packet. 42 * 43 * The queue is empty (no good data) if WRITE = READ - 1, and is full if 44 * WRITE = READ. 45 * 46 * During initialization, the host sets up the READ queue position to the first 47 * INDEX position, and WRITE to the last (READ - 1 wrapped) 48 * 49 * When the firmware places a packet in a buffer, it will advance the READ index 50 * and fire the RX interrupt. The driver can then query the READ index and 51 * process as many packets as possible, moving the WRITE index forward as it 52 * resets the Rx queue buffers with new memory. 53 * 54 * The management in the driver is as follows: 55 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 56 * When the interrupt handler is called, the request is processed. 57 * The page is either stolen - transferred to the upper layer 58 * or reused - added immediately to the iwl->rxq->rx_free list. 59 * + When the page is stolen - the driver updates the matching queue's used 60 * count, detaches the RBD and transfers it to the queue used list. 61 * When there are two used RBDs - they are transferred to the allocator empty 62 * list. Work is then scheduled for the allocator to start allocating 63 * eight buffers. 64 * When there are another 6 used RBDs - they are transferred to the allocator 65 * empty list and the driver tries to claim the pre-allocated buffers and 66 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 67 * until ready. 68 * When there are 8+ buffers in the free list - either from allocation or from 69 * 8 reused unstolen pages - restock is called to update the FW and indexes. 70 * + In order to make sure the allocator always has RBDs to use for allocation 71 * the allocator has initial pool in the size of num_queues*(8-2) - the 72 * maximum missing RBDs per allocation request (request posted with 2 73 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 74 * The queues supplies the recycle of the rest of the RBDs. 75 * + A received packet is processed and handed to the kernel network stack, 76 * detached from the iwl->rxq. The driver 'processed' index is updated. 77 * + If there are no allocated buffers in iwl->rxq->rx_free, 78 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 79 * If there were enough free buffers and RX_STALLED is set it is cleared. 80 * 81 * 82 * Driver sequence: 83 * 84 * iwl_rxq_alloc() Allocates rx_free 85 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 86 * iwl_pcie_rxq_restock. 87 * Used only during initialization. 88 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 89 * queue, updates firmware pointers, and updates 90 * the WRITE index. 91 * iwl_pcie_rx_allocator() Background work for allocating pages. 92 * 93 * -- enable interrupts -- 94 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 95 * READ INDEX, detaching the SKB from the pool. 96 * Moves the packet buffer from queue to rx_used. 97 * Posts and claims requests to the allocator. 98 * Calls iwl_pcie_rxq_restock to refill any empty 99 * slots. 100 * 101 * RBD life-cycle: 102 * 103 * Init: 104 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 105 * 106 * Regular Receive interrupt: 107 * Page Stolen: 108 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 109 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 110 * Page not Stolen: 111 * rxq.queue -> rxq.rx_free -> rxq.queue 112 * ... 113 * 114 */ 115 116 /* 117 * iwl_rxq_space - Return number of free slots available in queue. 118 */ 119 static int iwl_rxq_space(const struct iwl_rxq *rxq) 120 { 121 /* Make sure rx queue size is a power of 2 */ 122 WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 123 124 /* 125 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 126 * between empty and completely full queues. 127 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 128 * defined for negative dividends. 129 */ 130 return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 131 } 132 133 /* 134 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 135 */ 136 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 137 { 138 return cpu_to_le32((u32)(dma_addr >> 8)); 139 } 140 141 /* 142 * iwl_pcie_rx_stop - stops the Rx DMA 143 */ 144 int iwl_pcie_rx_stop(struct iwl_trans *trans) 145 { 146 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 147 /* TODO: remove this once fw does it */ 148 iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 149 return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3, 150 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 151 } else if (trans->trans_cfg->mq_rx_supported) { 152 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 153 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 154 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 155 } else { 156 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 157 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 158 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 159 1000); 160 } 161 } 162 163 /* 164 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 165 */ 166 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 167 struct iwl_rxq *rxq) 168 { 169 u32 reg; 170 171 lockdep_assert_held(&rxq->lock); 172 173 /* 174 * explicitly wake up the NIC if: 175 * 1. shadow registers aren't enabled 176 * 2. there is a chance that the NIC is asleep 177 */ 178 if (!trans->trans_cfg->base_params->shadow_reg_enable && 179 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 180 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 181 182 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 183 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 184 reg); 185 iwl_set_bit(trans, CSR_GP_CNTRL, 186 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 187 rxq->need_update = true; 188 return; 189 } 190 } 191 192 rxq->write_actual = round_down(rxq->write, 8); 193 if (!trans->trans_cfg->mq_rx_supported) 194 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 195 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 196 iwl_write32(trans, HBUS_TARG_WRPTR, rxq->write_actual | 197 HBUS_TARG_WRPTR_RX_Q(rxq->id)); 198 else 199 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 200 rxq->write_actual); 201 } 202 203 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 204 { 205 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 206 int i; 207 208 for (i = 0; i < trans->num_rx_queues; i++) { 209 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 210 211 if (!rxq->need_update) 212 continue; 213 spin_lock_bh(&rxq->lock); 214 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 215 rxq->need_update = false; 216 spin_unlock_bh(&rxq->lock); 217 } 218 } 219 220 static void iwl_pcie_restock_bd(struct iwl_trans *trans, 221 struct iwl_rxq *rxq, 222 struct iwl_rx_mem_buffer *rxb) 223 { 224 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 225 struct iwl_rx_transfer_desc *bd = rxq->bd; 226 227 BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64)); 228 229 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 230 bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 231 } else { 232 __le64 *bd = rxq->bd; 233 234 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 235 } 236 237 IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n", 238 (u32)rxb->vid, rxq->id, rxq->write); 239 } 240 241 /* 242 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 243 */ 244 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 245 struct iwl_rxq *rxq) 246 { 247 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 248 struct iwl_rx_mem_buffer *rxb; 249 250 /* 251 * If the device isn't enabled - no need to try to add buffers... 252 * This can happen when we stop the device and still have an interrupt 253 * pending. We stop the APM before we sync the interrupts because we 254 * have to (see comment there). On the other hand, since the APM is 255 * stopped, we cannot access the HW (in particular not prph). 256 * So don't try to restock if the APM has been already stopped. 257 */ 258 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 259 return; 260 261 spin_lock_bh(&rxq->lock); 262 while (rxq->free_count) { 263 /* Get next free Rx buffer, remove from free list */ 264 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 265 list); 266 list_del(&rxb->list); 267 rxb->invalid = false; 268 /* some low bits are expected to be unset (depending on hw) */ 269 WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask); 270 /* Point to Rx buffer via next RBD in circular buffer */ 271 iwl_pcie_restock_bd(trans, rxq, rxb); 272 rxq->write = (rxq->write + 1) & (rxq->queue_size - 1); 273 rxq->free_count--; 274 } 275 spin_unlock_bh(&rxq->lock); 276 277 /* 278 * If we've added more space for the firmware to place data, tell it. 279 * Increment device's write pointer in multiples of 8. 280 */ 281 if (rxq->write_actual != (rxq->write & ~0x7)) { 282 spin_lock_bh(&rxq->lock); 283 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 284 spin_unlock_bh(&rxq->lock); 285 } 286 } 287 288 /* 289 * iwl_pcie_rxsq_restock - restock implementation for single queue rx 290 */ 291 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 292 struct iwl_rxq *rxq) 293 { 294 struct iwl_rx_mem_buffer *rxb; 295 296 /* 297 * If the device isn't enabled - not need to try to add buffers... 298 * This can happen when we stop the device and still have an interrupt 299 * pending. We stop the APM before we sync the interrupts because we 300 * have to (see comment there). On the other hand, since the APM is 301 * stopped, we cannot access the HW (in particular not prph). 302 * So don't try to restock if the APM has been already stopped. 303 */ 304 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 305 return; 306 307 spin_lock_bh(&rxq->lock); 308 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 309 __le32 *bd = (__le32 *)rxq->bd; 310 /* The overwritten rxb must be a used one */ 311 rxb = rxq->queue[rxq->write]; 312 BUG_ON(rxb && rxb->page); 313 314 /* Get next free Rx buffer, remove from free list */ 315 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 316 list); 317 list_del(&rxb->list); 318 rxb->invalid = false; 319 320 /* Point to Rx buffer via next RBD in circular buffer */ 321 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 322 rxq->queue[rxq->write] = rxb; 323 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 324 rxq->free_count--; 325 } 326 spin_unlock_bh(&rxq->lock); 327 328 /* If we've added more space for the firmware to place data, tell it. 329 * Increment device's write pointer in multiples of 8. */ 330 if (rxq->write_actual != (rxq->write & ~0x7)) { 331 spin_lock_bh(&rxq->lock); 332 iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 333 spin_unlock_bh(&rxq->lock); 334 } 335 } 336 337 /* 338 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 339 * 340 * If there are slots in the RX queue that need to be restocked, 341 * and we have free pre-allocated buffers, fill the ranks as much 342 * as we can, pulling from rx_free. 343 * 344 * This moves the 'write' index forward to catch up with 'processed', and 345 * also updates the memory address in the firmware to reference the new 346 * target buffer. 347 */ 348 static 349 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 350 { 351 if (trans->trans_cfg->mq_rx_supported) 352 iwl_pcie_rxmq_restock(trans, rxq); 353 else 354 iwl_pcie_rxsq_restock(trans, rxq); 355 } 356 357 /* 358 * iwl_pcie_rx_alloc_page - allocates and returns a page. 359 * 360 */ 361 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 362 u32 *offset, gfp_t priority) 363 { 364 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 365 unsigned int rbsize = iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 366 unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order; 367 struct page *page; 368 gfp_t gfp_mask = priority; 369 370 if (trans_pcie->rx_page_order > 0) 371 gfp_mask |= __GFP_COMP; 372 373 if (trans_pcie->alloc_page) { 374 spin_lock_bh(&trans_pcie->alloc_page_lock); 375 /* recheck */ 376 if (trans_pcie->alloc_page) { 377 *offset = trans_pcie->alloc_page_used; 378 page = trans_pcie->alloc_page; 379 trans_pcie->alloc_page_used += rbsize; 380 if (trans_pcie->alloc_page_used >= allocsize) 381 trans_pcie->alloc_page = NULL; 382 else 383 get_page(page); 384 spin_unlock_bh(&trans_pcie->alloc_page_lock); 385 return page; 386 } 387 spin_unlock_bh(&trans_pcie->alloc_page_lock); 388 } 389 390 /* Alloc a new receive buffer */ 391 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 392 if (!page) { 393 if (net_ratelimit()) 394 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 395 trans_pcie->rx_page_order); 396 /* 397 * Issue an error if we don't have enough pre-allocated 398 * buffers. 399 */ 400 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 401 IWL_CRIT(trans, 402 "Failed to alloc_pages\n"); 403 return NULL; 404 } 405 406 if (2 * rbsize <= allocsize) { 407 spin_lock_bh(&trans_pcie->alloc_page_lock); 408 if (!trans_pcie->alloc_page) { 409 get_page(page); 410 trans_pcie->alloc_page = page; 411 trans_pcie->alloc_page_used = rbsize; 412 } 413 spin_unlock_bh(&trans_pcie->alloc_page_lock); 414 } 415 416 *offset = 0; 417 return page; 418 } 419 420 /* 421 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 422 * 423 * A used RBD is an Rx buffer that has been given to the stack. To use it again 424 * a page must be allocated and the RBD must point to the page. This function 425 * doesn't change the HW pointer but handles the list of pages that is used by 426 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 427 * allocated buffers. 428 */ 429 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 430 struct iwl_rxq *rxq) 431 { 432 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 433 struct iwl_rx_mem_buffer *rxb; 434 struct page *page; 435 436 while (1) { 437 unsigned int offset; 438 439 spin_lock_bh(&rxq->lock); 440 if (list_empty(&rxq->rx_used)) { 441 spin_unlock_bh(&rxq->lock); 442 return; 443 } 444 spin_unlock_bh(&rxq->lock); 445 446 page = iwl_pcie_rx_alloc_page(trans, &offset, priority); 447 if (!page) 448 return; 449 450 spin_lock_bh(&rxq->lock); 451 452 if (list_empty(&rxq->rx_used)) { 453 spin_unlock_bh(&rxq->lock); 454 __free_pages(page, trans_pcie->rx_page_order); 455 return; 456 } 457 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 458 list); 459 list_del(&rxb->list); 460 spin_unlock_bh(&rxq->lock); 461 462 BUG_ON(rxb->page); 463 rxb->page = page; 464 rxb->offset = offset; 465 /* Get physical address of the RB */ 466 rxb->page_dma = 467 dma_map_page(trans->dev, page, rxb->offset, 468 trans_pcie->rx_buf_bytes, 469 DMA_FROM_DEVICE); 470 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 471 rxb->page = NULL; 472 spin_lock_bh(&rxq->lock); 473 list_add(&rxb->list, &rxq->rx_used); 474 spin_unlock_bh(&rxq->lock); 475 __free_pages(page, trans_pcie->rx_page_order); 476 return; 477 } 478 479 spin_lock_bh(&rxq->lock); 480 481 list_add_tail(&rxb->list, &rxq->rx_free); 482 rxq->free_count++; 483 484 spin_unlock_bh(&rxq->lock); 485 } 486 } 487 488 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 489 { 490 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 491 int i; 492 493 if (!trans_pcie->rx_pool) 494 return; 495 496 for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) { 497 if (!trans_pcie->rx_pool[i].page) 498 continue; 499 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 500 trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE); 501 __free_pages(trans_pcie->rx_pool[i].page, 502 trans_pcie->rx_page_order); 503 trans_pcie->rx_pool[i].page = NULL; 504 } 505 } 506 507 /* 508 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 509 * 510 * Allocates for each received request 8 pages 511 * Called as a scheduled work item. 512 */ 513 static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 514 { 515 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 516 struct iwl_rb_allocator *rba = &trans_pcie->rba; 517 struct list_head local_empty; 518 int pending = atomic_read(&rba->req_pending); 519 520 IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending); 521 522 /* If we were scheduled - there is at least one request */ 523 spin_lock_bh(&rba->lock); 524 /* swap out the rba->rbd_empty to a local list */ 525 list_replace_init(&rba->rbd_empty, &local_empty); 526 spin_unlock_bh(&rba->lock); 527 528 while (pending) { 529 int i; 530 LIST_HEAD(local_allocated); 531 gfp_t gfp_mask = GFP_KERNEL; 532 533 /* Do not post a warning if there are only a few requests */ 534 if (pending < RX_PENDING_WATERMARK) 535 gfp_mask |= __GFP_NOWARN; 536 537 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 538 struct iwl_rx_mem_buffer *rxb; 539 struct page *page; 540 541 /* List should never be empty - each reused RBD is 542 * returned to the list, and initial pool covers any 543 * possible gap between the time the page is allocated 544 * to the time the RBD is added. 545 */ 546 BUG_ON(list_empty(&local_empty)); 547 /* Get the first rxb from the rbd list */ 548 rxb = list_first_entry(&local_empty, 549 struct iwl_rx_mem_buffer, list); 550 BUG_ON(rxb->page); 551 552 /* Alloc a new receive buffer */ 553 page = iwl_pcie_rx_alloc_page(trans, &rxb->offset, 554 gfp_mask); 555 if (!page) 556 continue; 557 rxb->page = page; 558 559 /* Get physical address of the RB */ 560 rxb->page_dma = dma_map_page(trans->dev, page, 561 rxb->offset, 562 trans_pcie->rx_buf_bytes, 563 DMA_FROM_DEVICE); 564 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 565 rxb->page = NULL; 566 __free_pages(page, trans_pcie->rx_page_order); 567 continue; 568 } 569 570 /* move the allocated entry to the out list */ 571 list_move(&rxb->list, &local_allocated); 572 i++; 573 } 574 575 atomic_dec(&rba->req_pending); 576 pending--; 577 578 if (!pending) { 579 pending = atomic_read(&rba->req_pending); 580 if (pending) 581 IWL_DEBUG_TPT(trans, 582 "Got more pending allocation requests = %d\n", 583 pending); 584 } 585 586 spin_lock_bh(&rba->lock); 587 /* add the allocated rbds to the allocator allocated list */ 588 list_splice_tail(&local_allocated, &rba->rbd_allocated); 589 /* get more empty RBDs for current pending requests */ 590 list_splice_tail_init(&rba->rbd_empty, &local_empty); 591 spin_unlock_bh(&rba->lock); 592 593 atomic_inc(&rba->req_ready); 594 595 } 596 597 spin_lock_bh(&rba->lock); 598 /* return unused rbds to the allocator empty list */ 599 list_splice_tail(&local_empty, &rba->rbd_empty); 600 spin_unlock_bh(&rba->lock); 601 602 IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__); 603 } 604 605 /* 606 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 607 .* 608 .* Called by queue when the queue posted allocation request and 609 * has freed 8 RBDs in order to restock itself. 610 * This function directly moves the allocated RBs to the queue's ownership 611 * and updates the relevant counters. 612 */ 613 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 614 struct iwl_rxq *rxq) 615 { 616 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 617 struct iwl_rb_allocator *rba = &trans_pcie->rba; 618 int i; 619 620 lockdep_assert_held(&rxq->lock); 621 622 /* 623 * atomic_dec_if_positive returns req_ready - 1 for any scenario. 624 * If req_ready is 0 atomic_dec_if_positive will return -1 and this 625 * function will return early, as there are no ready requests. 626 * atomic_dec_if_positive will perofrm the *actual* decrement only if 627 * req_ready > 0, i.e. - there are ready requests and the function 628 * hands one request to the caller. 629 */ 630 if (atomic_dec_if_positive(&rba->req_ready) < 0) 631 return; 632 633 spin_lock(&rba->lock); 634 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 635 /* Get next free Rx buffer, remove it from free list */ 636 struct iwl_rx_mem_buffer *rxb = 637 list_first_entry(&rba->rbd_allocated, 638 struct iwl_rx_mem_buffer, list); 639 640 list_move(&rxb->list, &rxq->rx_free); 641 } 642 spin_unlock(&rba->lock); 643 644 rxq->used_count -= RX_CLAIM_REQ_ALLOC; 645 rxq->free_count += RX_CLAIM_REQ_ALLOC; 646 } 647 648 void iwl_pcie_rx_allocator_work(struct work_struct *data) 649 { 650 struct iwl_rb_allocator *rba_p = 651 container_of(data, struct iwl_rb_allocator, rx_alloc); 652 struct iwl_trans_pcie *trans_pcie = 653 container_of(rba_p, struct iwl_trans_pcie, rba); 654 655 iwl_pcie_rx_allocator(trans_pcie->trans); 656 } 657 658 static int iwl_pcie_free_bd_size(struct iwl_trans *trans) 659 { 660 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 661 return sizeof(struct iwl_rx_transfer_desc); 662 663 return trans->trans_cfg->mq_rx_supported ? 664 sizeof(__le64) : sizeof(__le32); 665 } 666 667 static int iwl_pcie_used_bd_size(struct iwl_trans *trans) 668 { 669 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 670 return sizeof(struct iwl_rx_completion_desc_bz); 671 672 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 673 return sizeof(struct iwl_rx_completion_desc); 674 675 return sizeof(__le32); 676 } 677 678 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 679 struct iwl_rxq *rxq) 680 { 681 int free_size = iwl_pcie_free_bd_size(trans); 682 683 if (rxq->bd) 684 dma_free_coherent(trans->dev, 685 free_size * rxq->queue_size, 686 rxq->bd, rxq->bd_dma); 687 rxq->bd_dma = 0; 688 rxq->bd = NULL; 689 690 rxq->rb_stts_dma = 0; 691 rxq->rb_stts = NULL; 692 693 if (rxq->used_bd) 694 dma_free_coherent(trans->dev, 695 iwl_pcie_used_bd_size(trans) * 696 rxq->queue_size, 697 rxq->used_bd, rxq->used_bd_dma); 698 rxq->used_bd_dma = 0; 699 rxq->used_bd = NULL; 700 } 701 702 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 703 struct iwl_rxq *rxq) 704 { 705 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 706 struct device *dev = trans->dev; 707 int i; 708 int free_size; 709 bool use_rx_td = (trans->trans_cfg->device_family >= 710 IWL_DEVICE_FAMILY_AX210); 711 size_t rb_stts_size = use_rx_td ? sizeof(__le16) : 712 sizeof(struct iwl_rb_status); 713 714 spin_lock_init(&rxq->lock); 715 if (trans->trans_cfg->mq_rx_supported) 716 rxq->queue_size = trans->cfg->num_rbds; 717 else 718 rxq->queue_size = RX_QUEUE_SIZE; 719 720 free_size = iwl_pcie_free_bd_size(trans); 721 722 /* 723 * Allocate the circular buffer of Read Buffer Descriptors 724 * (RBDs) 725 */ 726 rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size, 727 &rxq->bd_dma, GFP_KERNEL); 728 if (!rxq->bd) 729 goto err; 730 731 if (trans->trans_cfg->mq_rx_supported) { 732 rxq->used_bd = dma_alloc_coherent(dev, 733 iwl_pcie_used_bd_size(trans) * 734 rxq->queue_size, 735 &rxq->used_bd_dma, 736 GFP_KERNEL); 737 if (!rxq->used_bd) 738 goto err; 739 } 740 741 rxq->rb_stts = (u8 *)trans_pcie->base_rb_stts + rxq->id * rb_stts_size; 742 rxq->rb_stts_dma = 743 trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size; 744 745 return 0; 746 747 err: 748 for (i = 0; i < trans->num_rx_queues; i++) { 749 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 750 751 iwl_pcie_free_rxq_dma(trans, rxq); 752 } 753 754 return -ENOMEM; 755 } 756 757 static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 758 { 759 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 760 struct iwl_rb_allocator *rba = &trans_pcie->rba; 761 int i, ret; 762 size_t rb_stts_size = trans->trans_cfg->device_family >= 763 IWL_DEVICE_FAMILY_AX210 ? 764 sizeof(__le16) : sizeof(struct iwl_rb_status); 765 766 if (WARN_ON(trans_pcie->rxq)) 767 return -EINVAL; 768 769 trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 770 GFP_KERNEL); 771 trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 772 sizeof(trans_pcie->rx_pool[0]), 773 GFP_KERNEL); 774 trans_pcie->global_table = 775 kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 776 sizeof(trans_pcie->global_table[0]), 777 GFP_KERNEL); 778 if (!trans_pcie->rxq || !trans_pcie->rx_pool || 779 !trans_pcie->global_table) { 780 ret = -ENOMEM; 781 goto err; 782 } 783 784 spin_lock_init(&rba->lock); 785 786 /* 787 * Allocate the driver's pointer to receive buffer status. 788 * Allocate for all queues continuously (HW requirement). 789 */ 790 trans_pcie->base_rb_stts = 791 dma_alloc_coherent(trans->dev, 792 rb_stts_size * trans->num_rx_queues, 793 &trans_pcie->base_rb_stts_dma, 794 GFP_KERNEL); 795 if (!trans_pcie->base_rb_stts) { 796 ret = -ENOMEM; 797 goto err; 798 } 799 800 for (i = 0; i < trans->num_rx_queues; i++) { 801 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 802 803 rxq->id = i; 804 ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 805 if (ret) 806 goto err; 807 } 808 return 0; 809 810 err: 811 if (trans_pcie->base_rb_stts) { 812 dma_free_coherent(trans->dev, 813 rb_stts_size * trans->num_rx_queues, 814 trans_pcie->base_rb_stts, 815 trans_pcie->base_rb_stts_dma); 816 trans_pcie->base_rb_stts = NULL; 817 trans_pcie->base_rb_stts_dma = 0; 818 } 819 kfree(trans_pcie->rx_pool); 820 trans_pcie->rx_pool = NULL; 821 kfree(trans_pcie->global_table); 822 trans_pcie->global_table = NULL; 823 kfree(trans_pcie->rxq); 824 trans_pcie->rxq = NULL; 825 826 return ret; 827 } 828 829 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 830 { 831 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 832 u32 rb_size; 833 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 834 835 switch (trans_pcie->rx_buf_size) { 836 case IWL_AMSDU_4K: 837 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 838 break; 839 case IWL_AMSDU_8K: 840 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 841 break; 842 case IWL_AMSDU_12K: 843 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 844 break; 845 default: 846 WARN_ON(1); 847 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 848 } 849 850 if (!iwl_trans_grab_nic_access(trans)) 851 return; 852 853 /* Stop Rx DMA */ 854 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 855 /* reset and flush pointers */ 856 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 857 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 858 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 859 860 /* Reset driver's Rx queue write index */ 861 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 862 863 /* Tell device where to find RBD circular buffer in DRAM */ 864 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 865 (u32)(rxq->bd_dma >> 8)); 866 867 /* Tell device where in DRAM to update its Rx status */ 868 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 869 rxq->rb_stts_dma >> 4); 870 871 /* Enable Rx DMA 872 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 873 * the credit mechanism in 5000 HW RX FIFO 874 * Direct rx interrupts to hosts 875 * Rx buffer size 4 or 8k or 12k 876 * RB timeout 0x10 877 * 256 RBDs 878 */ 879 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 880 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 881 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 882 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 883 rb_size | 884 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 885 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 886 887 iwl_trans_release_nic_access(trans); 888 889 /* Set interrupt coalescing timer to default (2048 usecs) */ 890 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 891 892 /* W/A for interrupt coalescing bug in 7260 and 3160 */ 893 if (trans->cfg->host_interrupt_operation_mode) 894 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 895 } 896 897 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 898 { 899 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 900 u32 rb_size, enabled = 0; 901 int i; 902 903 switch (trans_pcie->rx_buf_size) { 904 case IWL_AMSDU_2K: 905 rb_size = RFH_RXF_DMA_RB_SIZE_2K; 906 break; 907 case IWL_AMSDU_4K: 908 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 909 break; 910 case IWL_AMSDU_8K: 911 rb_size = RFH_RXF_DMA_RB_SIZE_8K; 912 break; 913 case IWL_AMSDU_12K: 914 rb_size = RFH_RXF_DMA_RB_SIZE_12K; 915 break; 916 default: 917 WARN_ON(1); 918 rb_size = RFH_RXF_DMA_RB_SIZE_4K; 919 } 920 921 if (!iwl_trans_grab_nic_access(trans)) 922 return; 923 924 /* Stop Rx DMA */ 925 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 926 /* disable free amd used rx queue operation */ 927 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 928 929 for (i = 0; i < trans->num_rx_queues; i++) { 930 /* Tell device where to find RBD free table in DRAM */ 931 iwl_write_prph64_no_grab(trans, 932 RFH_Q_FRBDCB_BA_LSB(i), 933 trans_pcie->rxq[i].bd_dma); 934 /* Tell device where to find RBD used table in DRAM */ 935 iwl_write_prph64_no_grab(trans, 936 RFH_Q_URBDCB_BA_LSB(i), 937 trans_pcie->rxq[i].used_bd_dma); 938 /* Tell device where in DRAM to update its Rx status */ 939 iwl_write_prph64_no_grab(trans, 940 RFH_Q_URBD_STTS_WPTR_LSB(i), 941 trans_pcie->rxq[i].rb_stts_dma); 942 /* Reset device indice tables */ 943 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 944 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 945 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 946 947 enabled |= BIT(i) | BIT(i + 16); 948 } 949 950 /* 951 * Enable Rx DMA 952 * Rx buffer size 4 or 8k or 12k 953 * Min RB size 4 or 8 954 * Drop frames that exceed RB size 955 * 512 RBDs 956 */ 957 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 958 RFH_DMA_EN_ENABLE_VAL | rb_size | 959 RFH_RXF_DMA_MIN_RB_4_8 | 960 RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 961 RFH_RXF_DMA_RBDCB_SIZE_512); 962 963 /* 964 * Activate DMA snooping. 965 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 966 * Default queue is 0 967 */ 968 iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 969 RFH_GEN_CFG_RFH_DMA_SNOOP | 970 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 971 RFH_GEN_CFG_SERVICE_DMA_SNOOP | 972 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 973 trans->trans_cfg->integrated ? 974 RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 975 RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 976 /* Enable the relevant rx queues */ 977 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 978 979 iwl_trans_release_nic_access(trans); 980 981 /* Set interrupt coalescing timer to default (2048 usecs) */ 982 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 983 } 984 985 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 986 { 987 lockdep_assert_held(&rxq->lock); 988 989 INIT_LIST_HEAD(&rxq->rx_free); 990 INIT_LIST_HEAD(&rxq->rx_used); 991 rxq->free_count = 0; 992 rxq->used_count = 0; 993 } 994 995 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget); 996 997 static int iwl_pcie_napi_poll(struct napi_struct *napi, int budget) 998 { 999 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 1000 struct iwl_trans_pcie *trans_pcie; 1001 struct iwl_trans *trans; 1002 int ret; 1003 1004 trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 1005 trans = trans_pcie->trans; 1006 1007 ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 1008 1009 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", 1010 rxq->id, ret, budget); 1011 1012 if (ret < budget) { 1013 spin_lock(&trans_pcie->irq_lock); 1014 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1015 _iwl_enable_interrupts(trans); 1016 spin_unlock(&trans_pcie->irq_lock); 1017 1018 napi_complete_done(&rxq->napi, ret); 1019 } 1020 1021 return ret; 1022 } 1023 1024 static int iwl_pcie_napi_poll_msix(struct napi_struct *napi, int budget) 1025 { 1026 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 1027 struct iwl_trans_pcie *trans_pcie; 1028 struct iwl_trans *trans; 1029 int ret; 1030 1031 trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 1032 trans = trans_pcie->trans; 1033 1034 ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 1035 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", rxq->id, ret, 1036 budget); 1037 1038 if (ret < budget) { 1039 int irq_line = rxq->id; 1040 1041 /* FIRST_RSS is shared with line 0 */ 1042 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS && 1043 rxq->id == 1) 1044 irq_line = 0; 1045 1046 spin_lock(&trans_pcie->irq_lock); 1047 iwl_pcie_clear_irq(trans, irq_line); 1048 spin_unlock(&trans_pcie->irq_lock); 1049 1050 napi_complete_done(&rxq->napi, ret); 1051 } 1052 1053 return ret; 1054 } 1055 1056 void iwl_pcie_rx_napi_sync(struct iwl_trans *trans) 1057 { 1058 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1059 int i; 1060 1061 if (unlikely(!trans_pcie->rxq)) 1062 return; 1063 1064 for (i = 0; i < trans->num_rx_queues; i++) { 1065 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1066 1067 if (rxq && rxq->napi.poll) 1068 napi_synchronize(&rxq->napi); 1069 } 1070 } 1071 1072 static int _iwl_pcie_rx_init(struct iwl_trans *trans) 1073 { 1074 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1075 struct iwl_rxq *def_rxq; 1076 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1077 int i, err, queue_size, allocator_pool_size, num_alloc; 1078 1079 if (!trans_pcie->rxq) { 1080 err = iwl_pcie_rx_alloc(trans); 1081 if (err) 1082 return err; 1083 } 1084 def_rxq = trans_pcie->rxq; 1085 1086 cancel_work_sync(&rba->rx_alloc); 1087 1088 spin_lock_bh(&rba->lock); 1089 atomic_set(&rba->req_pending, 0); 1090 atomic_set(&rba->req_ready, 0); 1091 INIT_LIST_HEAD(&rba->rbd_allocated); 1092 INIT_LIST_HEAD(&rba->rbd_empty); 1093 spin_unlock_bh(&rba->lock); 1094 1095 /* free all first - we overwrite everything here */ 1096 iwl_pcie_free_rbs_pool(trans); 1097 1098 for (i = 0; i < RX_QUEUE_SIZE; i++) 1099 def_rxq->queue[i] = NULL; 1100 1101 for (i = 0; i < trans->num_rx_queues; i++) { 1102 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1103 1104 spin_lock_bh(&rxq->lock); 1105 /* 1106 * Set read write pointer to reflect that we have processed 1107 * and used all buffers, but have not restocked the Rx queue 1108 * with fresh buffers 1109 */ 1110 rxq->read = 0; 1111 rxq->write = 0; 1112 rxq->write_actual = 0; 1113 memset(rxq->rb_stts, 0, 1114 (trans->trans_cfg->device_family >= 1115 IWL_DEVICE_FAMILY_AX210) ? 1116 sizeof(__le16) : sizeof(struct iwl_rb_status)); 1117 1118 iwl_pcie_rx_init_rxb_lists(rxq); 1119 1120 spin_unlock_bh(&rxq->lock); 1121 1122 if (!rxq->napi.poll) { 1123 int (*poll)(struct napi_struct *, int) = iwl_pcie_napi_poll; 1124 1125 if (trans_pcie->msix_enabled) 1126 poll = iwl_pcie_napi_poll_msix; 1127 1128 netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 1129 poll); 1130 napi_enable(&rxq->napi); 1131 } 1132 1133 } 1134 1135 /* move the pool to the default queue and allocator ownerships */ 1136 queue_size = trans->trans_cfg->mq_rx_supported ? 1137 trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE; 1138 allocator_pool_size = trans->num_rx_queues * 1139 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 1140 num_alloc = queue_size + allocator_pool_size; 1141 1142 for (i = 0; i < num_alloc; i++) { 1143 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 1144 1145 if (i < allocator_pool_size) 1146 list_add(&rxb->list, &rba->rbd_empty); 1147 else 1148 list_add(&rxb->list, &def_rxq->rx_used); 1149 trans_pcie->global_table[i] = rxb; 1150 rxb->vid = (u16)(i + 1); 1151 rxb->invalid = true; 1152 } 1153 1154 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 1155 1156 return 0; 1157 } 1158 1159 int iwl_pcie_rx_init(struct iwl_trans *trans) 1160 { 1161 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1162 int ret = _iwl_pcie_rx_init(trans); 1163 1164 if (ret) 1165 return ret; 1166 1167 if (trans->trans_cfg->mq_rx_supported) 1168 iwl_pcie_rx_mq_hw_init(trans); 1169 else 1170 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 1171 1172 iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 1173 1174 spin_lock_bh(&trans_pcie->rxq->lock); 1175 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 1176 spin_unlock_bh(&trans_pcie->rxq->lock); 1177 1178 return 0; 1179 } 1180 1181 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1182 { 1183 /* Set interrupt coalescing timer to default (2048 usecs) */ 1184 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1185 1186 /* 1187 * We don't configure the RFH. 1188 * Restock will be done at alive, after firmware configured the RFH. 1189 */ 1190 return _iwl_pcie_rx_init(trans); 1191 } 1192 1193 void iwl_pcie_rx_free(struct iwl_trans *trans) 1194 { 1195 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1196 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1197 int i; 1198 size_t rb_stts_size = trans->trans_cfg->device_family >= 1199 IWL_DEVICE_FAMILY_AX210 ? 1200 sizeof(__le16) : sizeof(struct iwl_rb_status); 1201 1202 /* 1203 * if rxq is NULL, it means that nothing has been allocated, 1204 * exit now 1205 */ 1206 if (!trans_pcie->rxq) { 1207 IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1208 return; 1209 } 1210 1211 cancel_work_sync(&rba->rx_alloc); 1212 1213 iwl_pcie_free_rbs_pool(trans); 1214 1215 if (trans_pcie->base_rb_stts) { 1216 dma_free_coherent(trans->dev, 1217 rb_stts_size * trans->num_rx_queues, 1218 trans_pcie->base_rb_stts, 1219 trans_pcie->base_rb_stts_dma); 1220 trans_pcie->base_rb_stts = NULL; 1221 trans_pcie->base_rb_stts_dma = 0; 1222 } 1223 1224 for (i = 0; i < trans->num_rx_queues; i++) { 1225 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1226 1227 iwl_pcie_free_rxq_dma(trans, rxq); 1228 1229 if (rxq->napi.poll) { 1230 napi_disable(&rxq->napi); 1231 netif_napi_del(&rxq->napi); 1232 } 1233 } 1234 kfree(trans_pcie->rx_pool); 1235 kfree(trans_pcie->global_table); 1236 kfree(trans_pcie->rxq); 1237 1238 if (trans_pcie->alloc_page) 1239 __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order); 1240 } 1241 1242 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq, 1243 struct iwl_rb_allocator *rba) 1244 { 1245 spin_lock(&rba->lock); 1246 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1247 spin_unlock(&rba->lock); 1248 } 1249 1250 /* 1251 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1252 * 1253 * Called when a RBD can be reused. The RBD is transferred to the allocator. 1254 * When there are 2 empty RBDs - a request for allocation is posted 1255 */ 1256 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1257 struct iwl_rx_mem_buffer *rxb, 1258 struct iwl_rxq *rxq, bool emergency) 1259 { 1260 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1261 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1262 1263 /* Move the RBD to the used list, will be moved to allocator in batches 1264 * before claiming or posting a request*/ 1265 list_add_tail(&rxb->list, &rxq->rx_used); 1266 1267 if (unlikely(emergency)) 1268 return; 1269 1270 /* Count the allocator owned RBDs */ 1271 rxq->used_count++; 1272 1273 /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1274 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1275 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1276 * after but we still need to post another request. 1277 */ 1278 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1279 /* Move the 2 RBDs to the allocator ownership. 1280 Allocator has another 6 from pool for the request completion*/ 1281 iwl_pcie_rx_move_to_allocator(rxq, rba); 1282 1283 atomic_inc(&rba->req_pending); 1284 queue_work(rba->alloc_wq, &rba->rx_alloc); 1285 } 1286 } 1287 1288 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 1289 struct iwl_rxq *rxq, 1290 struct iwl_rx_mem_buffer *rxb, 1291 bool emergency, 1292 int i) 1293 { 1294 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1295 struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id]; 1296 bool page_stolen = false; 1297 int max_len = trans_pcie->rx_buf_bytes; 1298 u32 offset = 0; 1299 1300 if (WARN_ON(!rxb)) 1301 return; 1302 1303 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1304 1305 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1306 struct iwl_rx_packet *pkt; 1307 bool reclaim; 1308 int len; 1309 struct iwl_rx_cmd_buffer rxcb = { 1310 ._offset = rxb->offset + offset, 1311 ._rx_page_order = trans_pcie->rx_page_order, 1312 ._page = rxb->page, 1313 ._page_stolen = false, 1314 .truesize = max_len, 1315 }; 1316 1317 pkt = rxb_addr(&rxcb); 1318 1319 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 1320 IWL_DEBUG_RX(trans, 1321 "Q %d: RB end marker at offset %d\n", 1322 rxq->id, offset); 1323 break; 1324 } 1325 1326 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1327 FH_RSCSR_RXQ_POS != rxq->id, 1328 "frame on invalid queue - is on %d and indicates %d\n", 1329 rxq->id, 1330 (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1331 FH_RSCSR_RXQ_POS); 1332 1333 IWL_DEBUG_RX(trans, 1334 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 1335 rxq->id, offset, 1336 iwl_get_cmd_string(trans, 1337 WIDE_ID(pkt->hdr.group_id, pkt->hdr.cmd)), 1338 pkt->hdr.group_id, pkt->hdr.cmd, 1339 le16_to_cpu(pkt->hdr.sequence)); 1340 1341 len = iwl_rx_packet_len(pkt); 1342 len += sizeof(u32); /* account for status word */ 1343 1344 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1345 1346 /* check that what the device tells us made sense */ 1347 if (len < sizeof(*pkt) || offset > max_len) 1348 break; 1349 1350 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1351 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1352 1353 /* Reclaim a command buffer only if this packet is a response 1354 * to a (driver-originated) command. 1355 * If the packet (e.g. Rx frame) originated from uCode, 1356 * there is no command buffer to reclaim. 1357 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1358 * but apparently a few don't get set; catch them here. */ 1359 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1360 if (reclaim && !pkt->hdr.group_id) { 1361 int i; 1362 1363 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1364 if (trans_pcie->no_reclaim_cmds[i] == 1365 pkt->hdr.cmd) { 1366 reclaim = false; 1367 break; 1368 } 1369 } 1370 } 1371 1372 if (rxq->id == trans_pcie->def_rx_queue) 1373 iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1374 &rxcb); 1375 else 1376 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1377 &rxcb, rxq->id); 1378 1379 /* 1380 * After here, we should always check rxcb._page_stolen, 1381 * if it is true then one of the handlers took the page. 1382 */ 1383 1384 if (reclaim) { 1385 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1386 int index = SEQ_TO_INDEX(sequence); 1387 int cmd_index = iwl_txq_get_cmd_index(txq, index); 1388 1389 kfree_sensitive(txq->entries[cmd_index].free_buf); 1390 txq->entries[cmd_index].free_buf = NULL; 1391 1392 /* Invoke any callbacks, transfer the buffer to caller, 1393 * and fire off the (possibly) blocking 1394 * iwl_trans_send_cmd() 1395 * as we reclaim the driver command queue */ 1396 if (!rxcb._page_stolen) 1397 iwl_pcie_hcmd_complete(trans, &rxcb); 1398 else 1399 IWL_WARN(trans, "Claim null rxb?\n"); 1400 } 1401 1402 page_stolen |= rxcb._page_stolen; 1403 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1404 break; 1405 } 1406 1407 /* page was stolen from us -- free our reference */ 1408 if (page_stolen) { 1409 __free_pages(rxb->page, trans_pcie->rx_page_order); 1410 rxb->page = NULL; 1411 } 1412 1413 /* Reuse the page if possible. For notification packets and 1414 * SKBs that fail to Rx correctly, add them back into the 1415 * rx_free list for reuse later. */ 1416 if (rxb->page != NULL) { 1417 rxb->page_dma = 1418 dma_map_page(trans->dev, rxb->page, rxb->offset, 1419 trans_pcie->rx_buf_bytes, 1420 DMA_FROM_DEVICE); 1421 if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1422 /* 1423 * free the page(s) as well to not break 1424 * the invariant that the items on the used 1425 * list have no page(s) 1426 */ 1427 __free_pages(rxb->page, trans_pcie->rx_page_order); 1428 rxb->page = NULL; 1429 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1430 } else { 1431 list_add_tail(&rxb->list, &rxq->rx_free); 1432 rxq->free_count++; 1433 } 1434 } else 1435 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1436 } 1437 1438 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans, 1439 struct iwl_rxq *rxq, int i, 1440 bool *join) 1441 { 1442 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1443 struct iwl_rx_mem_buffer *rxb; 1444 u16 vid; 1445 1446 BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32); 1447 BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc_bz) != 4); 1448 1449 if (!trans->trans_cfg->mq_rx_supported) { 1450 rxb = rxq->queue[i]; 1451 rxq->queue[i] = NULL; 1452 return rxb; 1453 } 1454 1455 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1456 struct iwl_rx_completion_desc_bz *cd = rxq->used_bd; 1457 1458 vid = le16_to_cpu(cd[i].rbid); 1459 *join = cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED; 1460 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1461 struct iwl_rx_completion_desc *cd = rxq->used_bd; 1462 1463 vid = le16_to_cpu(cd[i].rbid); 1464 *join = cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED; 1465 } else { 1466 __le32 *cd = rxq->used_bd; 1467 1468 vid = le32_to_cpu(cd[i]) & 0x0FFF; /* 12-bit VID */ 1469 } 1470 1471 if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs)) 1472 goto out_err; 1473 1474 rxb = trans_pcie->global_table[vid - 1]; 1475 if (rxb->invalid) 1476 goto out_err; 1477 1478 IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid); 1479 1480 rxb->invalid = true; 1481 1482 return rxb; 1483 1484 out_err: 1485 WARN(1, "Invalid rxb from HW %u\n", (u32)vid); 1486 iwl_force_nmi(trans); 1487 return NULL; 1488 } 1489 1490 /* 1491 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1492 */ 1493 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget) 1494 { 1495 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1496 struct iwl_rxq *rxq; 1497 u32 r, i, count = 0, handled = 0; 1498 bool emergency = false; 1499 1500 if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd)) 1501 return budget; 1502 1503 rxq = &trans_pcie->rxq[queue]; 1504 1505 restart: 1506 spin_lock(&rxq->lock); 1507 /* uCode's read index (stored in shared DRAM) indicates the last Rx 1508 * buffer that the driver may process (last buffer filled by ucode). */ 1509 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1510 i = rxq->read; 1511 1512 /* W/A 9000 device step A0 wrap-around bug */ 1513 r &= (rxq->queue_size - 1); 1514 1515 /* Rx interrupt, but nothing sent from uCode */ 1516 if (i == r) 1517 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1518 1519 while (i != r && ++handled < budget) { 1520 struct iwl_rb_allocator *rba = &trans_pcie->rba; 1521 struct iwl_rx_mem_buffer *rxb; 1522 /* number of RBDs still waiting for page allocation */ 1523 u32 rb_pending_alloc = 1524 atomic_read(&trans_pcie->rba.req_pending) * 1525 RX_CLAIM_REQ_ALLOC; 1526 bool join = false; 1527 1528 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 && 1529 !emergency)) { 1530 iwl_pcie_rx_move_to_allocator(rxq, rba); 1531 emergency = true; 1532 IWL_DEBUG_TPT(trans, 1533 "RX path is in emergency. Pending allocations %d\n", 1534 rb_pending_alloc); 1535 } 1536 1537 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 1538 1539 rxb = iwl_pcie_get_rxb(trans, rxq, i, &join); 1540 if (!rxb) 1541 goto out; 1542 1543 if (unlikely(join || rxq->next_rb_is_fragment)) { 1544 rxq->next_rb_is_fragment = join; 1545 /* 1546 * We can only get a multi-RB in the following cases: 1547 * - firmware issue, sending a too big notification 1548 * - sniffer mode with a large A-MSDU 1549 * - large MTU frames (>2k) 1550 * since the multi-RB functionality is limited to newer 1551 * hardware that cannot put multiple entries into a 1552 * single RB. 1553 * 1554 * Right now, the higher layers aren't set up to deal 1555 * with that, so discard all of these. 1556 */ 1557 list_add_tail(&rxb->list, &rxq->rx_free); 1558 rxq->free_count++; 1559 } else { 1560 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i); 1561 } 1562 1563 i = (i + 1) & (rxq->queue_size - 1); 1564 1565 /* 1566 * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1567 * try to claim the pre-allocated buffers from the allocator. 1568 * If not ready - will try to reclaim next time. 1569 * There is no need to reschedule work - allocator exits only 1570 * on success 1571 */ 1572 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1573 iwl_pcie_rx_allocator_get(trans, rxq); 1574 1575 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1576 /* Add the remaining empty RBDs for allocator use */ 1577 iwl_pcie_rx_move_to_allocator(rxq, rba); 1578 } else if (emergency) { 1579 count++; 1580 if (count == 8) { 1581 count = 0; 1582 if (rb_pending_alloc < rxq->queue_size / 3) { 1583 IWL_DEBUG_TPT(trans, 1584 "RX path exited emergency. Pending allocations %d\n", 1585 rb_pending_alloc); 1586 emergency = false; 1587 } 1588 1589 rxq->read = i; 1590 spin_unlock(&rxq->lock); 1591 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1592 iwl_pcie_rxq_restock(trans, rxq); 1593 goto restart; 1594 } 1595 } 1596 } 1597 out: 1598 /* Backtrack one entry */ 1599 rxq->read = i; 1600 spin_unlock(&rxq->lock); 1601 1602 /* 1603 * handle a case where in emergency there are some unallocated RBDs. 1604 * those RBDs are in the used list, but are not tracked by the queue's 1605 * used_count which counts allocator owned RBDs. 1606 * unallocated emergency RBDs must be allocated on exit, otherwise 1607 * when called again the function may not be in emergency mode and 1608 * they will be handed to the allocator with no tracking in the RBD 1609 * allocator counters, which will lead to them never being claimed back 1610 * by the queue. 1611 * by allocating them here, they are now in the queue free list, and 1612 * will be restocked by the next call of iwl_pcie_rxq_restock. 1613 */ 1614 if (unlikely(emergency && count)) 1615 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1616 1617 iwl_pcie_rxq_restock(trans, rxq); 1618 1619 return handled; 1620 } 1621 1622 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 1623 { 1624 u8 queue = entry->entry; 1625 struct msix_entry *entries = entry - queue; 1626 1627 return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 1628 } 1629 1630 /* 1631 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 1632 * This interrupt handler should be used with RSS queue only. 1633 */ 1634 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 1635 { 1636 struct msix_entry *entry = dev_id; 1637 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 1638 struct iwl_trans *trans = trans_pcie->trans; 1639 struct iwl_rxq *rxq = &trans_pcie->rxq[entry->entry]; 1640 1641 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1642 1643 if (WARN_ON(entry->entry >= trans->num_rx_queues)) 1644 return IRQ_NONE; 1645 1646 if (!rxq) { 1647 if (net_ratelimit()) 1648 IWL_ERR(trans, 1649 "[%d] Got MSI-X interrupt before we have Rx queues\n", 1650 entry->entry); 1651 return IRQ_NONE; 1652 } 1653 1654 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1655 IWL_DEBUG_ISR(trans, "[%d] Got interrupt\n", entry->entry); 1656 1657 local_bh_disable(); 1658 if (napi_schedule_prep(&rxq->napi)) 1659 __napi_schedule(&rxq->napi); 1660 else 1661 iwl_pcie_clear_irq(trans, entry->entry); 1662 local_bh_enable(); 1663 1664 lock_map_release(&trans->sync_cmd_lockdep_map); 1665 1666 return IRQ_HANDLED; 1667 } 1668 1669 /* 1670 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1671 */ 1672 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1673 { 1674 int i; 1675 1676 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1677 if (trans->cfg->internal_wimax_coex && 1678 !trans->cfg->apmg_not_supported && 1679 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1680 APMS_CLK_VAL_MRB_FUNC_MODE) || 1681 (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1682 APMG_PS_CTRL_VAL_RESET_REQ))) { 1683 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1684 iwl_op_mode_wimax_active(trans->op_mode); 1685 wake_up(&trans->wait_command_queue); 1686 return; 1687 } 1688 1689 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 1690 if (!trans->txqs.txq[i]) 1691 continue; 1692 del_timer(&trans->txqs.txq[i]->stuck_timer); 1693 } 1694 1695 /* The STATUS_FW_ERROR bit is set in this function. This must happen 1696 * before we wake up the command caller, to ensure a proper cleanup. */ 1697 iwl_trans_fw_error(trans, false); 1698 1699 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1700 wake_up(&trans->wait_command_queue); 1701 } 1702 1703 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1704 { 1705 u32 inta; 1706 1707 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1708 1709 trace_iwlwifi_dev_irq(trans->dev); 1710 1711 /* Discover which interrupts are active/pending */ 1712 inta = iwl_read32(trans, CSR_INT); 1713 1714 /* the thread will service interrupts and re-enable them */ 1715 return inta; 1716 } 1717 1718 /* a device (PCI-E) page is 4096 bytes long */ 1719 #define ICT_SHIFT 12 1720 #define ICT_SIZE (1 << ICT_SHIFT) 1721 #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1722 1723 /* interrupt handler using ict table, with this interrupt driver will 1724 * stop using INTA register to get device's interrupt, reading this register 1725 * is expensive, device will write interrupts in ICT dram table, increment 1726 * index then will fire interrupt to driver, driver will OR all ICT table 1727 * entries from current index up to table entry with 0 value. the result is 1728 * the interrupt we need to service, driver will set the entries back to 0 and 1729 * set index. 1730 */ 1731 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1732 { 1733 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1734 u32 inta; 1735 u32 val = 0; 1736 u32 read; 1737 1738 trace_iwlwifi_dev_irq(trans->dev); 1739 1740 /* Ignore interrupt if there's nothing in NIC to service. 1741 * This may be due to IRQ shared with another device, 1742 * or due to sporadic interrupts thrown from our NIC. */ 1743 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1744 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1745 if (!read) 1746 return 0; 1747 1748 /* 1749 * Collect all entries up to the first 0, starting from ict_index; 1750 * note we already read at ict_index. 1751 */ 1752 do { 1753 val |= read; 1754 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1755 trans_pcie->ict_index, read); 1756 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1757 trans_pcie->ict_index = 1758 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1759 1760 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1761 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1762 read); 1763 } while (read); 1764 1765 /* We should not get this value, just ignore it. */ 1766 if (val == 0xffffffff) 1767 val = 0; 1768 1769 /* 1770 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1771 * (bit 15 before shifting it to 31) to clear when using interrupt 1772 * coalescing. fortunately, bits 18 and 19 stay set when this happens 1773 * so we use them to decide on the real state of the Rx bit. 1774 * In order words, bit 15 is set if bit 18 or bit 19 are set. 1775 */ 1776 if (val & 0xC0000) 1777 val |= 0x8000; 1778 1779 inta = (0xff & val) | ((0xff00 & val) << 16); 1780 return inta; 1781 } 1782 1783 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 1784 { 1785 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1786 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1787 bool hw_rfkill, prev, report; 1788 1789 mutex_lock(&trans_pcie->mutex); 1790 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1791 hw_rfkill = iwl_is_rfkill_set(trans); 1792 if (hw_rfkill) { 1793 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1794 set_bit(STATUS_RFKILL_HW, &trans->status); 1795 } 1796 if (trans_pcie->opmode_down) 1797 report = hw_rfkill; 1798 else 1799 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1800 1801 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 1802 hw_rfkill ? "disable radio" : "enable radio"); 1803 1804 isr_stats->rfkill++; 1805 1806 if (prev != report) 1807 iwl_trans_pcie_rf_kill(trans, report); 1808 mutex_unlock(&trans_pcie->mutex); 1809 1810 if (hw_rfkill) { 1811 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 1812 &trans->status)) 1813 IWL_DEBUG_RF_KILL(trans, 1814 "Rfkill while SYNC HCMD in flight\n"); 1815 wake_up(&trans->wait_command_queue); 1816 } else { 1817 clear_bit(STATUS_RFKILL_HW, &trans->status); 1818 if (trans_pcie->opmode_down) 1819 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1820 } 1821 } 1822 1823 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1824 { 1825 struct iwl_trans *trans = dev_id; 1826 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1827 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1828 u32 inta = 0; 1829 u32 handled = 0; 1830 bool polling = false; 1831 1832 lock_map_acquire(&trans->sync_cmd_lockdep_map); 1833 1834 spin_lock_bh(&trans_pcie->irq_lock); 1835 1836 /* dram interrupt table not set yet, 1837 * use legacy interrupt. 1838 */ 1839 if (likely(trans_pcie->use_ict)) 1840 inta = iwl_pcie_int_cause_ict(trans); 1841 else 1842 inta = iwl_pcie_int_cause_non_ict(trans); 1843 1844 if (iwl_have_debug_level(IWL_DL_ISR)) { 1845 IWL_DEBUG_ISR(trans, 1846 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1847 inta, trans_pcie->inta_mask, 1848 iwl_read32(trans, CSR_INT_MASK), 1849 iwl_read32(trans, CSR_FH_INT_STATUS)); 1850 if (inta & (~trans_pcie->inta_mask)) 1851 IWL_DEBUG_ISR(trans, 1852 "We got a masked interrupt (0x%08x)\n", 1853 inta & (~trans_pcie->inta_mask)); 1854 } 1855 1856 inta &= trans_pcie->inta_mask; 1857 1858 /* 1859 * Ignore interrupt if there's nothing in NIC to service. 1860 * This may be due to IRQ shared with another device, 1861 * or due to sporadic interrupts thrown from our NIC. 1862 */ 1863 if (unlikely(!inta)) { 1864 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1865 /* 1866 * Re-enable interrupts here since we don't 1867 * have anything to service 1868 */ 1869 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1870 _iwl_enable_interrupts(trans); 1871 spin_unlock_bh(&trans_pcie->irq_lock); 1872 lock_map_release(&trans->sync_cmd_lockdep_map); 1873 return IRQ_NONE; 1874 } 1875 1876 if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1877 /* 1878 * Hardware disappeared. It might have 1879 * already raised an interrupt. 1880 */ 1881 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1882 spin_unlock_bh(&trans_pcie->irq_lock); 1883 goto out; 1884 } 1885 1886 /* Ack/clear/reset pending uCode interrupts. 1887 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1888 */ 1889 /* There is a hardware bug in the interrupt mask function that some 1890 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1891 * they are disabled in the CSR_INT_MASK register. Furthermore the 1892 * ICT interrupt handling mechanism has another bug that might cause 1893 * these unmasked interrupts fail to be detected. We workaround the 1894 * hardware bugs here by ACKing all the possible interrupts so that 1895 * interrupt coalescing can still be achieved. 1896 */ 1897 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1898 1899 if (iwl_have_debug_level(IWL_DL_ISR)) 1900 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1901 inta, iwl_read32(trans, CSR_INT_MASK)); 1902 1903 spin_unlock_bh(&trans_pcie->irq_lock); 1904 1905 /* Now service all interrupt bits discovered above. */ 1906 if (inta & CSR_INT_BIT_HW_ERR) { 1907 IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1908 1909 /* Tell the device to stop sending interrupts */ 1910 iwl_disable_interrupts(trans); 1911 1912 isr_stats->hw++; 1913 iwl_pcie_irq_handle_error(trans); 1914 1915 handled |= CSR_INT_BIT_HW_ERR; 1916 1917 goto out; 1918 } 1919 1920 /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1921 if (inta & CSR_INT_BIT_SCD) { 1922 IWL_DEBUG_ISR(trans, 1923 "Scheduler finished to transmit the frame/frames.\n"); 1924 isr_stats->sch++; 1925 } 1926 1927 /* Alive notification via Rx interrupt will do the real work */ 1928 if (inta & CSR_INT_BIT_ALIVE) { 1929 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1930 isr_stats->alive++; 1931 if (trans->trans_cfg->gen2) { 1932 /* 1933 * We can restock, since firmware configured 1934 * the RFH 1935 */ 1936 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1937 } 1938 1939 handled |= CSR_INT_BIT_ALIVE; 1940 } 1941 1942 /* Safely ignore these bits for debug checks below */ 1943 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1944 1945 /* HW RF KILL switch toggled */ 1946 if (inta & CSR_INT_BIT_RF_KILL) { 1947 iwl_pcie_handle_rfkill_irq(trans); 1948 handled |= CSR_INT_BIT_RF_KILL; 1949 } 1950 1951 /* Chip got too hot and stopped itself */ 1952 if (inta & CSR_INT_BIT_CT_KILL) { 1953 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1954 isr_stats->ctkill++; 1955 handled |= CSR_INT_BIT_CT_KILL; 1956 } 1957 1958 /* Error detected by uCode */ 1959 if (inta & CSR_INT_BIT_SW_ERR) { 1960 IWL_ERR(trans, "Microcode SW error detected. " 1961 " Restarting 0x%X.\n", inta); 1962 isr_stats->sw++; 1963 iwl_pcie_irq_handle_error(trans); 1964 handled |= CSR_INT_BIT_SW_ERR; 1965 } 1966 1967 /* uCode wakes up after power-down sleep */ 1968 if (inta & CSR_INT_BIT_WAKEUP) { 1969 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1970 iwl_pcie_rxq_check_wrptr(trans); 1971 iwl_pcie_txq_check_wrptrs(trans); 1972 1973 isr_stats->wakeup++; 1974 1975 handled |= CSR_INT_BIT_WAKEUP; 1976 } 1977 1978 /* All uCode command responses, including Tx command responses, 1979 * Rx "responses" (frame-received notification), and other 1980 * notifications from uCode come through here*/ 1981 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1982 CSR_INT_BIT_RX_PERIODIC)) { 1983 IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1984 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1985 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1986 iwl_write32(trans, CSR_FH_INT_STATUS, 1987 CSR_FH_INT_RX_MASK); 1988 } 1989 if (inta & CSR_INT_BIT_RX_PERIODIC) { 1990 handled |= CSR_INT_BIT_RX_PERIODIC; 1991 iwl_write32(trans, 1992 CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1993 } 1994 /* Sending RX interrupt require many steps to be done in the 1995 * device: 1996 * 1- write interrupt to current index in ICT table. 1997 * 2- dma RX frame. 1998 * 3- update RX shared data to indicate last write index. 1999 * 4- send interrupt. 2000 * This could lead to RX race, driver could receive RX interrupt 2001 * but the shared data changes does not reflect this; 2002 * periodic interrupt will detect any dangling Rx activity. 2003 */ 2004 2005 /* Disable periodic interrupt; we use it as just a one-shot. */ 2006 iwl_write8(trans, CSR_INT_PERIODIC_REG, 2007 CSR_INT_PERIODIC_DIS); 2008 2009 /* 2010 * Enable periodic interrupt in 8 msec only if we received 2011 * real RX interrupt (instead of just periodic int), to catch 2012 * any dangling Rx interrupt. If it was just the periodic 2013 * interrupt, there was no dangling Rx activity, and no need 2014 * to extend the periodic interrupt; one-shot is enough. 2015 */ 2016 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 2017 iwl_write8(trans, CSR_INT_PERIODIC_REG, 2018 CSR_INT_PERIODIC_ENA); 2019 2020 isr_stats->rx++; 2021 2022 local_bh_disable(); 2023 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 2024 polling = true; 2025 __napi_schedule(&trans_pcie->rxq[0].napi); 2026 } 2027 local_bh_enable(); 2028 } 2029 2030 /* This "Tx" DMA channel is used only for loading uCode */ 2031 if (inta & CSR_INT_BIT_FH_TX) { 2032 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 2033 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 2034 isr_stats->tx++; 2035 handled |= CSR_INT_BIT_FH_TX; 2036 /* Wake up uCode load routine, now that load is complete */ 2037 trans_pcie->ucode_write_complete = true; 2038 wake_up(&trans_pcie->ucode_write_waitq); 2039 /* Wake up IMR write routine, now that write to SRAM is complete */ 2040 if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2041 trans_pcie->imr_status = IMR_D2S_COMPLETED; 2042 wake_up(&trans_pcie->ucode_write_waitq); 2043 } 2044 } 2045 2046 if (inta & ~handled) { 2047 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 2048 isr_stats->unhandled++; 2049 } 2050 2051 if (inta & ~(trans_pcie->inta_mask)) { 2052 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 2053 inta & ~trans_pcie->inta_mask); 2054 } 2055 2056 if (!polling) { 2057 spin_lock_bh(&trans_pcie->irq_lock); 2058 /* only Re-enable all interrupt if disabled by irq */ 2059 if (test_bit(STATUS_INT_ENABLED, &trans->status)) 2060 _iwl_enable_interrupts(trans); 2061 /* we are loading the firmware, enable FH_TX interrupt only */ 2062 else if (handled & CSR_INT_BIT_FH_TX) 2063 iwl_enable_fw_load_int(trans); 2064 /* Re-enable RF_KILL if it occurred */ 2065 else if (handled & CSR_INT_BIT_RF_KILL) 2066 iwl_enable_rfkill_int(trans); 2067 /* Re-enable the ALIVE / Rx interrupt if it occurred */ 2068 else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX)) 2069 iwl_enable_fw_load_int_ctx_info(trans); 2070 spin_unlock_bh(&trans_pcie->irq_lock); 2071 } 2072 2073 out: 2074 lock_map_release(&trans->sync_cmd_lockdep_map); 2075 return IRQ_HANDLED; 2076 } 2077 2078 /****************************************************************************** 2079 * 2080 * ICT functions 2081 * 2082 ******************************************************************************/ 2083 2084 /* Free dram table */ 2085 void iwl_pcie_free_ict(struct iwl_trans *trans) 2086 { 2087 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2088 2089 if (trans_pcie->ict_tbl) { 2090 dma_free_coherent(trans->dev, ICT_SIZE, 2091 trans_pcie->ict_tbl, 2092 trans_pcie->ict_tbl_dma); 2093 trans_pcie->ict_tbl = NULL; 2094 trans_pcie->ict_tbl_dma = 0; 2095 } 2096 } 2097 2098 /* 2099 * allocate dram shared table, it is an aligned memory 2100 * block of ICT_SIZE. 2101 * also reset all data related to ICT table interrupt. 2102 */ 2103 int iwl_pcie_alloc_ict(struct iwl_trans *trans) 2104 { 2105 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2106 2107 trans_pcie->ict_tbl = 2108 dma_alloc_coherent(trans->dev, ICT_SIZE, 2109 &trans_pcie->ict_tbl_dma, GFP_KERNEL); 2110 if (!trans_pcie->ict_tbl) 2111 return -ENOMEM; 2112 2113 /* just an API sanity check ... it is guaranteed to be aligned */ 2114 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 2115 iwl_pcie_free_ict(trans); 2116 return -EINVAL; 2117 } 2118 2119 return 0; 2120 } 2121 2122 /* Device is going up inform it about using ICT interrupt table, 2123 * also we need to tell the driver to start using ICT interrupt. 2124 */ 2125 void iwl_pcie_reset_ict(struct iwl_trans *trans) 2126 { 2127 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2128 u32 val; 2129 2130 if (!trans_pcie->ict_tbl) 2131 return; 2132 2133 spin_lock_bh(&trans_pcie->irq_lock); 2134 _iwl_disable_interrupts(trans); 2135 2136 memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 2137 2138 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 2139 2140 val |= CSR_DRAM_INT_TBL_ENABLE | 2141 CSR_DRAM_INIT_TBL_WRAP_CHECK | 2142 CSR_DRAM_INIT_TBL_WRITE_POINTER; 2143 2144 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 2145 2146 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 2147 trans_pcie->use_ict = true; 2148 trans_pcie->ict_index = 0; 2149 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 2150 _iwl_enable_interrupts(trans); 2151 spin_unlock_bh(&trans_pcie->irq_lock); 2152 } 2153 2154 /* Device is going down disable ict interrupt usage */ 2155 void iwl_pcie_disable_ict(struct iwl_trans *trans) 2156 { 2157 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2158 2159 spin_lock_bh(&trans_pcie->irq_lock); 2160 trans_pcie->use_ict = false; 2161 spin_unlock_bh(&trans_pcie->irq_lock); 2162 } 2163 2164 irqreturn_t iwl_pcie_isr(int irq, void *data) 2165 { 2166 struct iwl_trans *trans = data; 2167 2168 if (!trans) 2169 return IRQ_NONE; 2170 2171 /* Disable (but don't clear!) interrupts here to avoid 2172 * back-to-back ISRs and sporadic interrupts from our NIC. 2173 * If we have something to service, the tasklet will re-enable ints. 2174 * If we *don't* have something, we'll re-enable before leaving here. 2175 */ 2176 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2177 2178 return IRQ_WAKE_THREAD; 2179 } 2180 2181 irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 2182 { 2183 return IRQ_WAKE_THREAD; 2184 } 2185 2186 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 2187 { 2188 struct msix_entry *entry = dev_id; 2189 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 2190 struct iwl_trans *trans = trans_pcie->trans; 2191 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2192 u32 inta_fh_msk = ~MSIX_FH_INT_CAUSES_DATA_QUEUE; 2193 u32 inta_fh, inta_hw; 2194 bool polling = false; 2195 bool sw_err; 2196 2197 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 2198 inta_fh_msk |= MSIX_FH_INT_CAUSES_Q0; 2199 2200 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 2201 inta_fh_msk |= MSIX_FH_INT_CAUSES_Q1; 2202 2203 lock_map_acquire(&trans->sync_cmd_lockdep_map); 2204 2205 spin_lock_bh(&trans_pcie->irq_lock); 2206 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 2207 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 2208 /* 2209 * Clear causes registers to avoid being handling the same cause. 2210 */ 2211 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk); 2212 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 2213 spin_unlock_bh(&trans_pcie->irq_lock); 2214 2215 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2216 2217 if (unlikely(!(inta_fh | inta_hw))) { 2218 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 2219 lock_map_release(&trans->sync_cmd_lockdep_map); 2220 return IRQ_NONE; 2221 } 2222 2223 if (iwl_have_debug_level(IWL_DL_ISR)) { 2224 IWL_DEBUG_ISR(trans, 2225 "ISR[%d] inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 2226 entry->entry, inta_fh, trans_pcie->fh_mask, 2227 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 2228 if (inta_fh & ~trans_pcie->fh_mask) 2229 IWL_DEBUG_ISR(trans, 2230 "We got a masked interrupt (0x%08x)\n", 2231 inta_fh & ~trans_pcie->fh_mask); 2232 } 2233 2234 inta_fh &= trans_pcie->fh_mask; 2235 2236 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2237 inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2238 local_bh_disable(); 2239 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 2240 polling = true; 2241 __napi_schedule(&trans_pcie->rxq[0].napi); 2242 } 2243 local_bh_enable(); 2244 } 2245 2246 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2247 inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2248 local_bh_disable(); 2249 if (napi_schedule_prep(&trans_pcie->rxq[1].napi)) { 2250 polling = true; 2251 __napi_schedule(&trans_pcie->rxq[1].napi); 2252 } 2253 local_bh_enable(); 2254 } 2255 2256 /* This "Tx" DMA channel is used only for loading uCode */ 2257 if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM && 2258 trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2259 IWL_DEBUG_ISR(trans, "IMR Complete interrupt\n"); 2260 isr_stats->tx++; 2261 2262 /* Wake up IMR routine once write to SRAM is complete */ 2263 if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2264 trans_pcie->imr_status = IMR_D2S_COMPLETED; 2265 wake_up(&trans_pcie->ucode_write_waitq); 2266 } 2267 } else if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 2268 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 2269 isr_stats->tx++; 2270 /* 2271 * Wake up uCode load routine, 2272 * now that load is complete 2273 */ 2274 trans_pcie->ucode_write_complete = true; 2275 wake_up(&trans_pcie->ucode_write_waitq); 2276 2277 /* Wake up IMR routine once write to SRAM is complete */ 2278 if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2279 trans_pcie->imr_status = IMR_D2S_COMPLETED; 2280 wake_up(&trans_pcie->ucode_write_waitq); 2281 } 2282 } 2283 2284 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2285 sw_err = inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 2286 else 2287 sw_err = inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR; 2288 2289 /* Error detected by uCode */ 2290 if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || sw_err) { 2291 IWL_ERR(trans, 2292 "Microcode SW error detected. Restarting 0x%X.\n", 2293 inta_fh); 2294 isr_stats->sw++; 2295 /* during FW reset flow report errors from there */ 2296 if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2297 trans_pcie->imr_status = IMR_D2S_ERROR; 2298 wake_up(&trans_pcie->imr_waitq); 2299 } else if (trans_pcie->fw_reset_state == FW_RESET_REQUESTED) { 2300 trans_pcie->fw_reset_state = FW_RESET_ERROR; 2301 wake_up(&trans_pcie->fw_reset_waitq); 2302 } else { 2303 iwl_pcie_irq_handle_error(trans); 2304 } 2305 } 2306 2307 /* After checking FH register check HW register */ 2308 if (iwl_have_debug_level(IWL_DL_ISR)) { 2309 IWL_DEBUG_ISR(trans, 2310 "ISR[%d] inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 2311 entry->entry, inta_hw, trans_pcie->hw_mask, 2312 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 2313 if (inta_hw & ~trans_pcie->hw_mask) 2314 IWL_DEBUG_ISR(trans, 2315 "We got a masked interrupt 0x%08x\n", 2316 inta_hw & ~trans_pcie->hw_mask); 2317 } 2318 2319 inta_hw &= trans_pcie->hw_mask; 2320 2321 /* Alive notification via Rx interrupt will do the real work */ 2322 if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 2323 IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 2324 isr_stats->alive++; 2325 if (trans->trans_cfg->gen2) { 2326 /* We can restock, since firmware configured the RFH */ 2327 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2328 } 2329 } 2330 2331 /* 2332 * In some rare cases when the HW is in a bad state, we may 2333 * get this interrupt too early, when prph_info is still NULL. 2334 * So make sure that it's not NULL to prevent crashing. 2335 */ 2336 if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP && trans_pcie->prph_info) { 2337 u32 sleep_notif = 2338 le32_to_cpu(trans_pcie->prph_info->sleep_notif); 2339 if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND || 2340 sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) { 2341 IWL_DEBUG_ISR(trans, 2342 "Sx interrupt: sleep notification = 0x%x\n", 2343 sleep_notif); 2344 trans_pcie->sx_complete = true; 2345 wake_up(&trans_pcie->sx_waitq); 2346 } else { 2347 /* uCode wakes up after power-down sleep */ 2348 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 2349 iwl_pcie_rxq_check_wrptr(trans); 2350 iwl_pcie_txq_check_wrptrs(trans); 2351 2352 isr_stats->wakeup++; 2353 } 2354 } 2355 2356 /* Chip got too hot and stopped itself */ 2357 if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 2358 IWL_ERR(trans, "Microcode CT kill error detected.\n"); 2359 isr_stats->ctkill++; 2360 } 2361 2362 /* HW RF KILL switch toggled */ 2363 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 2364 iwl_pcie_handle_rfkill_irq(trans); 2365 2366 if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 2367 IWL_ERR(trans, 2368 "Hardware error detected. Restarting.\n"); 2369 2370 isr_stats->hw++; 2371 trans->dbg.hw_error = true; 2372 iwl_pcie_irq_handle_error(trans); 2373 } 2374 2375 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE) { 2376 IWL_DEBUG_ISR(trans, "Reset flow completed\n"); 2377 trans_pcie->fw_reset_state = FW_RESET_OK; 2378 wake_up(&trans_pcie->fw_reset_waitq); 2379 } 2380 2381 if (!polling) 2382 iwl_pcie_clear_irq(trans, entry->entry); 2383 2384 lock_map_release(&trans->sync_cmd_lockdep_map); 2385 2386 return IRQ_HANDLED; 2387 } 2388