18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 32b616666SMordechay Goodstein * Copyright (C) 2003-2014, 2018-2021 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #include <linux/sched.h> 8e705c121SKalle Valo #include <linux/wait.h> 9e705c121SKalle Valo #include <linux/gfp.h> 10e705c121SKalle Valo 11e705c121SKalle Valo #include "iwl-prph.h" 12e705c121SKalle Valo #include "iwl-io.h" 13e705c121SKalle Valo #include "internal.h" 14e705c121SKalle Valo #include "iwl-op-mode.h" 159b58419eSGolan Ben Ami #include "iwl-context-info-gen3.h" 16e705c121SKalle Valo 17e705c121SKalle Valo /****************************************************************************** 18e705c121SKalle Valo * 19e705c121SKalle Valo * RX path functions 20e705c121SKalle Valo * 21e705c121SKalle Valo ******************************************************************************/ 22e705c121SKalle Valo 23e705c121SKalle Valo /* 24e705c121SKalle Valo * Rx theory of operation 25e705c121SKalle Valo * 26e705c121SKalle Valo * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 27e705c121SKalle Valo * each of which point to Receive Buffers to be filled by the NIC. These get 28e705c121SKalle Valo * used not only for Rx frames, but for any command response or notification 29e705c121SKalle Valo * from the NIC. The driver and NIC manage the Rx buffers by means 30e705c121SKalle Valo * of indexes into the circular buffer. 31e705c121SKalle Valo * 32e705c121SKalle Valo * Rx Queue Indexes 33e705c121SKalle Valo * The host/firmware share two index registers for managing the Rx buffers. 34e705c121SKalle Valo * 35e705c121SKalle Valo * The READ index maps to the first position that the firmware may be writing 36e705c121SKalle Valo * to -- the driver can read up to (but not including) this position and get 37e705c121SKalle Valo * good data. 38e705c121SKalle Valo * The READ index is managed by the firmware once the card is enabled. 39e705c121SKalle Valo * 40e705c121SKalle Valo * The WRITE index maps to the last position the driver has read from -- the 41e705c121SKalle Valo * position preceding WRITE is the last slot the firmware can place a packet. 42e705c121SKalle Valo * 43e705c121SKalle Valo * The queue is empty (no good data) if WRITE = READ - 1, and is full if 44e705c121SKalle Valo * WRITE = READ. 45e705c121SKalle Valo * 46e705c121SKalle Valo * During initialization, the host sets up the READ queue position to the first 47e705c121SKalle Valo * INDEX position, and WRITE to the last (READ - 1 wrapped) 48e705c121SKalle Valo * 49e705c121SKalle Valo * When the firmware places a packet in a buffer, it will advance the READ index 50e705c121SKalle Valo * and fire the RX interrupt. The driver can then query the READ index and 51e705c121SKalle Valo * process as many packets as possible, moving the WRITE index forward as it 52e705c121SKalle Valo * resets the Rx queue buffers with new memory. 53e705c121SKalle Valo * 54e705c121SKalle Valo * The management in the driver is as follows: 55e705c121SKalle Valo * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 56e705c121SKalle Valo * When the interrupt handler is called, the request is processed. 57e705c121SKalle Valo * The page is either stolen - transferred to the upper layer 58e705c121SKalle Valo * or reused - added immediately to the iwl->rxq->rx_free list. 59e705c121SKalle Valo * + When the page is stolen - the driver updates the matching queue's used 60e705c121SKalle Valo * count, detaches the RBD and transfers it to the queue used list. 61e705c121SKalle Valo * When there are two used RBDs - they are transferred to the allocator empty 62e705c121SKalle Valo * list. Work is then scheduled for the allocator to start allocating 63e705c121SKalle Valo * eight buffers. 64e705c121SKalle Valo * When there are another 6 used RBDs - they are transferred to the allocator 65e705c121SKalle Valo * empty list and the driver tries to claim the pre-allocated buffers and 66e705c121SKalle Valo * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 67e705c121SKalle Valo * until ready. 68e705c121SKalle Valo * When there are 8+ buffers in the free list - either from allocation or from 69e705c121SKalle Valo * 8 reused unstolen pages - restock is called to update the FW and indexes. 70e705c121SKalle Valo * + In order to make sure the allocator always has RBDs to use for allocation 71e705c121SKalle Valo * the allocator has initial pool in the size of num_queues*(8-2) - the 72e705c121SKalle Valo * maximum missing RBDs per allocation request (request posted with 2 73e705c121SKalle Valo * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 74e705c121SKalle Valo * The queues supplies the recycle of the rest of the RBDs. 75e705c121SKalle Valo * + A received packet is processed and handed to the kernel network stack, 76e705c121SKalle Valo * detached from the iwl->rxq. The driver 'processed' index is updated. 77e705c121SKalle Valo * + If there are no allocated buffers in iwl->rxq->rx_free, 78e705c121SKalle Valo * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 79e705c121SKalle Valo * If there were enough free buffers and RX_STALLED is set it is cleared. 80e705c121SKalle Valo * 81e705c121SKalle Valo * 82e705c121SKalle Valo * Driver sequence: 83e705c121SKalle Valo * 84e705c121SKalle Valo * iwl_rxq_alloc() Allocates rx_free 85e705c121SKalle Valo * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 86e705c121SKalle Valo * iwl_pcie_rxq_restock. 87e705c121SKalle Valo * Used only during initialization. 88e705c121SKalle Valo * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 89e705c121SKalle Valo * queue, updates firmware pointers, and updates 90e705c121SKalle Valo * the WRITE index. 91e705c121SKalle Valo * iwl_pcie_rx_allocator() Background work for allocating pages. 92e705c121SKalle Valo * 93e705c121SKalle Valo * -- enable interrupts -- 94e705c121SKalle Valo * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 95e705c121SKalle Valo * READ INDEX, detaching the SKB from the pool. 96e705c121SKalle Valo * Moves the packet buffer from queue to rx_used. 97e705c121SKalle Valo * Posts and claims requests to the allocator. 98e705c121SKalle Valo * Calls iwl_pcie_rxq_restock to refill any empty 99e705c121SKalle Valo * slots. 100e705c121SKalle Valo * 101e705c121SKalle Valo * RBD life-cycle: 102e705c121SKalle Valo * 103e705c121SKalle Valo * Init: 104e705c121SKalle Valo * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 105e705c121SKalle Valo * 106e705c121SKalle Valo * Regular Receive interrupt: 107e705c121SKalle Valo * Page Stolen: 108e705c121SKalle Valo * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 109e705c121SKalle Valo * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 110e705c121SKalle Valo * Page not Stolen: 111e705c121SKalle Valo * rxq.queue -> rxq.rx_free -> rxq.queue 112e705c121SKalle Valo * ... 113e705c121SKalle Valo * 114e705c121SKalle Valo */ 115e705c121SKalle Valo 116e705c121SKalle Valo /* 117e705c121SKalle Valo * iwl_rxq_space - Return number of free slots available in queue. 118e705c121SKalle Valo */ 119e705c121SKalle Valo static int iwl_rxq_space(const struct iwl_rxq *rxq) 120e705c121SKalle Valo { 12196a6497bSSara Sharon /* Make sure rx queue size is a power of 2 */ 12296a6497bSSara Sharon WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 123e705c121SKalle Valo 124e705c121SKalle Valo /* 125e705c121SKalle Valo * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 126e705c121SKalle Valo * between empty and completely full queues. 127e705c121SKalle Valo * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 128e705c121SKalle Valo * defined for negative dividends. 129e705c121SKalle Valo */ 13096a6497bSSara Sharon return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 131e705c121SKalle Valo } 132e705c121SKalle Valo 133e705c121SKalle Valo /* 134e705c121SKalle Valo * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 135e705c121SKalle Valo */ 136e705c121SKalle Valo static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 137e705c121SKalle Valo { 138e705c121SKalle Valo return cpu_to_le32((u32)(dma_addr >> 8)); 139e705c121SKalle Valo } 140e705c121SKalle Valo 141e705c121SKalle Valo /* 142e705c121SKalle Valo * iwl_pcie_rx_stop - stops the Rx DMA 143e705c121SKalle Valo */ 144e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans) 145e705c121SKalle Valo { 1463681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1473681021fSJohannes Berg /* TODO: remove this once fw does it */ 148ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 149ea695b7cSShaul Triebitz return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3, 150d0158235SGolan Ben Ami RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 151286ca8ebSLuca Coelho } else if (trans->trans_cfg->mq_rx_supported) { 152d7fdd0e5SSara Sharon iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 153d7fdd0e5SSara Sharon return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 154d7fdd0e5SSara Sharon RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 155d7fdd0e5SSara Sharon } else { 156e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 157e705c121SKalle Valo return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 158d7fdd0e5SSara Sharon FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 159d7fdd0e5SSara Sharon 1000); 160d7fdd0e5SSara Sharon } 161e705c121SKalle Valo } 162e705c121SKalle Valo 163e705c121SKalle Valo /* 164e705c121SKalle Valo * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 165e705c121SKalle Valo */ 16678485054SSara Sharon static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 16778485054SSara Sharon struct iwl_rxq *rxq) 168e705c121SKalle Valo { 169e705c121SKalle Valo u32 reg; 170e705c121SKalle Valo 171e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 172e705c121SKalle Valo 173e705c121SKalle Valo /* 174e705c121SKalle Valo * explicitly wake up the NIC if: 175e705c121SKalle Valo * 1. shadow registers aren't enabled 176e705c121SKalle Valo * 2. there is a chance that the NIC is asleep 177e705c121SKalle Valo */ 178286ca8ebSLuca Coelho if (!trans->trans_cfg->base_params->shadow_reg_enable && 179e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 180e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 181e705c121SKalle Valo 182e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 183e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 184e705c121SKalle Valo reg); 185e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 1866dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 187e705c121SKalle Valo rxq->need_update = true; 188e705c121SKalle Valo return; 189e705c121SKalle Valo } 190e705c121SKalle Valo } 191e705c121SKalle Valo 192e705c121SKalle Valo rxq->write_actual = round_down(rxq->write, 8); 1933681021fSJohannes Berg if (trans->trans_cfg->mq_rx_supported) 1941554ed20SSara Sharon iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 19596a6497bSSara Sharon rxq->write_actual); 1961316d595SSara Sharon else 197e705c121SKalle Valo iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 198e705c121SKalle Valo } 199e705c121SKalle Valo 200e705c121SKalle Valo static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 201e705c121SKalle Valo { 202e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20378485054SSara Sharon int i; 204e705c121SKalle Valo 20578485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 20678485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 207e705c121SKalle Valo 208e705c121SKalle Valo if (!rxq->need_update) 20978485054SSara Sharon continue; 21025edc8f2SJohannes Berg spin_lock_bh(&rxq->lock); 21178485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 212e705c121SKalle Valo rxq->need_update = false; 21325edc8f2SJohannes Berg spin_unlock_bh(&rxq->lock); 214e705c121SKalle Valo } 21578485054SSara Sharon } 216e705c121SKalle Valo 2170307c839SGolan Ben Ami static void iwl_pcie_restock_bd(struct iwl_trans *trans, 2180307c839SGolan Ben Ami struct iwl_rxq *rxq, 2190307c839SGolan Ben Ami struct iwl_rx_mem_buffer *rxb) 2200307c839SGolan Ben Ami { 2213681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 2220307c839SGolan Ben Ami struct iwl_rx_transfer_desc *bd = rxq->bd; 2230307c839SGolan Ben Ami 224f826faaaSJohannes Berg BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64)); 225f826faaaSJohannes Berg 2260307c839SGolan Ben Ami bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 2270307c839SGolan Ben Ami bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 2280307c839SGolan Ben Ami } else { 2290307c839SGolan Ben Ami __le64 *bd = rxq->bd; 2300307c839SGolan Ben Ami 2310307c839SGolan Ben Ami bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 2320307c839SGolan Ben Ami } 23385d78bb1SSara Sharon 23485d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n", 23585d78bb1SSara Sharon (u32)rxb->vid, rxq->id, rxq->write); 2360307c839SGolan Ben Ami } 2370307c839SGolan Ben Ami 238e0e168dcSGregory Greenman /* 2392047fa54SSara Sharon * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 240e0e168dcSGregory Greenman */ 2412047fa54SSara Sharon static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 24296a6497bSSara Sharon struct iwl_rxq *rxq) 24396a6497bSSara Sharon { 244cfdc20efSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 24596a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb; 24696a6497bSSara Sharon 24796a6497bSSara Sharon /* 24896a6497bSSara Sharon * If the device isn't enabled - no need to try to add buffers... 24996a6497bSSara Sharon * This can happen when we stop the device and still have an interrupt 25096a6497bSSara Sharon * pending. We stop the APM before we sync the interrupts because we 25196a6497bSSara Sharon * have to (see comment there). On the other hand, since the APM is 25296a6497bSSara Sharon * stopped, we cannot access the HW (in particular not prph). 25396a6497bSSara Sharon * So don't try to restock if the APM has been already stopped. 25496a6497bSSara Sharon */ 25596a6497bSSara Sharon if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 25696a6497bSSara Sharon return; 25796a6497bSSara Sharon 25825edc8f2SJohannes Berg spin_lock_bh(&rxq->lock); 25996a6497bSSara Sharon while (rxq->free_count) { 26096a6497bSSara Sharon /* Get next free Rx buffer, remove from free list */ 26196a6497bSSara Sharon rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 26296a6497bSSara Sharon list); 26396a6497bSSara Sharon list_del(&rxb->list); 264b1753c62SSara Sharon rxb->invalid = false; 265cfdc20efSJohannes Berg /* some low bits are expected to be unset (depending on hw) */ 266cfdc20efSJohannes Berg WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask); 26796a6497bSSara Sharon /* Point to Rx buffer via next RBD in circular buffer */ 2680307c839SGolan Ben Ami iwl_pcie_restock_bd(trans, rxq, rxb); 2695661925aSJohannes Berg rxq->write = (rxq->write + 1) & (rxq->queue_size - 1); 27096a6497bSSara Sharon rxq->free_count--; 27196a6497bSSara Sharon } 27225edc8f2SJohannes Berg spin_unlock_bh(&rxq->lock); 27396a6497bSSara Sharon 27496a6497bSSara Sharon /* 27596a6497bSSara Sharon * If we've added more space for the firmware to place data, tell it. 27696a6497bSSara Sharon * Increment device's write pointer in multiples of 8. 27796a6497bSSara Sharon */ 27896a6497bSSara Sharon if (rxq->write_actual != (rxq->write & ~0x7)) { 27925edc8f2SJohannes Berg spin_lock_bh(&rxq->lock); 28096a6497bSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 28125edc8f2SJohannes Berg spin_unlock_bh(&rxq->lock); 28296a6497bSSara Sharon } 28396a6497bSSara Sharon } 28496a6497bSSara Sharon 285e705c121SKalle Valo /* 2862047fa54SSara Sharon * iwl_pcie_rxsq_restock - restock implementation for single queue rx 287e705c121SKalle Valo */ 2882047fa54SSara Sharon static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 289e0e168dcSGregory Greenman struct iwl_rxq *rxq) 290e705c121SKalle Valo { 291e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 292e705c121SKalle Valo 293e705c121SKalle Valo /* 294e705c121SKalle Valo * If the device isn't enabled - not need to try to add buffers... 295e705c121SKalle Valo * This can happen when we stop the device and still have an interrupt 296e705c121SKalle Valo * pending. We stop the APM before we sync the interrupts because we 297e705c121SKalle Valo * have to (see comment there). On the other hand, since the APM is 298e705c121SKalle Valo * stopped, we cannot access the HW (in particular not prph). 299e705c121SKalle Valo * So don't try to restock if the APM has been already stopped. 300e705c121SKalle Valo */ 301e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 302e705c121SKalle Valo return; 303e705c121SKalle Valo 30447ef328cSIlan Peer spin_lock_bh(&rxq->lock); 305e705c121SKalle Valo while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 30696a6497bSSara Sharon __le32 *bd = (__le32 *)rxq->bd; 307e705c121SKalle Valo /* The overwritten rxb must be a used one */ 308e705c121SKalle Valo rxb = rxq->queue[rxq->write]; 309e705c121SKalle Valo BUG_ON(rxb && rxb->page); 310e705c121SKalle Valo 311e705c121SKalle Valo /* Get next free Rx buffer, remove from free list */ 312e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 313e705c121SKalle Valo list); 314e705c121SKalle Valo list_del(&rxb->list); 315b1753c62SSara Sharon rxb->invalid = false; 316e705c121SKalle Valo 317e705c121SKalle Valo /* Point to Rx buffer via next RBD in circular buffer */ 31896a6497bSSara Sharon bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 319e705c121SKalle Valo rxq->queue[rxq->write] = rxb; 320e705c121SKalle Valo rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 321e705c121SKalle Valo rxq->free_count--; 322e705c121SKalle Valo } 32347ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 324e705c121SKalle Valo 325e705c121SKalle Valo /* If we've added more space for the firmware to place data, tell it. 326e705c121SKalle Valo * Increment device's write pointer in multiples of 8. */ 327e705c121SKalle Valo if (rxq->write_actual != (rxq->write & ~0x7)) { 32847ef328cSIlan Peer spin_lock_bh(&rxq->lock); 32978485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 33047ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 331e705c121SKalle Valo } 332e705c121SKalle Valo } 333e705c121SKalle Valo 334e705c121SKalle Valo /* 335e0e168dcSGregory Greenman * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 336e0e168dcSGregory Greenman * 337e0e168dcSGregory Greenman * If there are slots in the RX queue that need to be restocked, 338e0e168dcSGregory Greenman * and we have free pre-allocated buffers, fill the ranks as much 339e0e168dcSGregory Greenman * as we can, pulling from rx_free. 340e0e168dcSGregory Greenman * 341e0e168dcSGregory Greenman * This moves the 'write' index forward to catch up with 'processed', and 342e0e168dcSGregory Greenman * also updates the memory address in the firmware to reference the new 343e0e168dcSGregory Greenman * target buffer. 344e0e168dcSGregory Greenman */ 345e0e168dcSGregory Greenman static 346e0e168dcSGregory Greenman void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 347e0e168dcSGregory Greenman { 348286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 3492047fa54SSara Sharon iwl_pcie_rxmq_restock(trans, rxq); 350e0e168dcSGregory Greenman else 3512047fa54SSara Sharon iwl_pcie_rxsq_restock(trans, rxq); 352e0e168dcSGregory Greenman } 353e0e168dcSGregory Greenman 354e0e168dcSGregory Greenman /* 355e705c121SKalle Valo * iwl_pcie_rx_alloc_page - allocates and returns a page. 356e705c121SKalle Valo * 357e705c121SKalle Valo */ 358e705c121SKalle Valo static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 359cfdc20efSJohannes Berg u32 *offset, gfp_t priority) 360e705c121SKalle Valo { 361e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 362cfdc20efSJohannes Berg unsigned int rbsize = iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 363cfdc20efSJohannes Berg unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order; 364e705c121SKalle Valo struct page *page; 365e705c121SKalle Valo gfp_t gfp_mask = priority; 366e705c121SKalle Valo 367e705c121SKalle Valo if (trans_pcie->rx_page_order > 0) 368e705c121SKalle Valo gfp_mask |= __GFP_COMP; 369e705c121SKalle Valo 370cfdc20efSJohannes Berg if (trans_pcie->alloc_page) { 371cfdc20efSJohannes Berg spin_lock_bh(&trans_pcie->alloc_page_lock); 372cfdc20efSJohannes Berg /* recheck */ 373cfdc20efSJohannes Berg if (trans_pcie->alloc_page) { 374cfdc20efSJohannes Berg *offset = trans_pcie->alloc_page_used; 375cfdc20efSJohannes Berg page = trans_pcie->alloc_page; 376cfdc20efSJohannes Berg trans_pcie->alloc_page_used += rbsize; 377cfdc20efSJohannes Berg if (trans_pcie->alloc_page_used >= allocsize) 378cfdc20efSJohannes Berg trans_pcie->alloc_page = NULL; 379cfdc20efSJohannes Berg else 380cfdc20efSJohannes Berg get_page(page); 381cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 382cfdc20efSJohannes Berg return page; 383cfdc20efSJohannes Berg } 384cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 385cfdc20efSJohannes Berg } 386cfdc20efSJohannes Berg 387e705c121SKalle Valo /* Alloc a new receive buffer */ 388e705c121SKalle Valo page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 389e705c121SKalle Valo if (!page) { 390e705c121SKalle Valo if (net_ratelimit()) 391e705c121SKalle Valo IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 392e705c121SKalle Valo trans_pcie->rx_page_order); 39378485054SSara Sharon /* 39478485054SSara Sharon * Issue an error if we don't have enough pre-allocated 39578485054SSara Sharon * buffers. 3961da3823dSLuca Coelho */ 39778485054SSara Sharon if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 398e705c121SKalle Valo IWL_CRIT(trans, 39978485054SSara Sharon "Failed to alloc_pages\n"); 400e705c121SKalle Valo return NULL; 401e705c121SKalle Valo } 402cfdc20efSJohannes Berg 403cfdc20efSJohannes Berg if (2 * rbsize <= allocsize) { 404cfdc20efSJohannes Berg spin_lock_bh(&trans_pcie->alloc_page_lock); 405cfdc20efSJohannes Berg if (!trans_pcie->alloc_page) { 406cfdc20efSJohannes Berg get_page(page); 407cfdc20efSJohannes Berg trans_pcie->alloc_page = page; 408cfdc20efSJohannes Berg trans_pcie->alloc_page_used = rbsize; 409cfdc20efSJohannes Berg } 410cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 411cfdc20efSJohannes Berg } 412cfdc20efSJohannes Berg 413cfdc20efSJohannes Berg *offset = 0; 414e705c121SKalle Valo return page; 415e705c121SKalle Valo } 416e705c121SKalle Valo 417e705c121SKalle Valo /* 418e705c121SKalle Valo * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 419e705c121SKalle Valo * 420e705c121SKalle Valo * A used RBD is an Rx buffer that has been given to the stack. To use it again 421e705c121SKalle Valo * a page must be allocated and the RBD must point to the page. This function 422e705c121SKalle Valo * doesn't change the HW pointer but handles the list of pages that is used by 423e705c121SKalle Valo * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 424e705c121SKalle Valo * allocated buffers. 425e705c121SKalle Valo */ 426ff932f61SGolan Ben Ami void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 42778485054SSara Sharon struct iwl_rxq *rxq) 428e705c121SKalle Valo { 429e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 430e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 431e705c121SKalle Valo struct page *page; 432e705c121SKalle Valo 433e705c121SKalle Valo while (1) { 434cfdc20efSJohannes Berg unsigned int offset; 435cfdc20efSJohannes Berg 43647ef328cSIlan Peer spin_lock_bh(&rxq->lock); 437e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 43847ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 439e705c121SKalle Valo return; 440e705c121SKalle Valo } 44147ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 442e705c121SKalle Valo 443cfdc20efSJohannes Berg page = iwl_pcie_rx_alloc_page(trans, &offset, priority); 444e705c121SKalle Valo if (!page) 445e705c121SKalle Valo return; 446e705c121SKalle Valo 44747ef328cSIlan Peer spin_lock_bh(&rxq->lock); 448e705c121SKalle Valo 449e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 45047ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 451e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 452e705c121SKalle Valo return; 453e705c121SKalle Valo } 454e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 455e705c121SKalle Valo list); 456e705c121SKalle Valo list_del(&rxb->list); 45747ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 458e705c121SKalle Valo 459e705c121SKalle Valo BUG_ON(rxb->page); 460e705c121SKalle Valo rxb->page = page; 461cfdc20efSJohannes Berg rxb->offset = offset; 462e705c121SKalle Valo /* Get physical address of the RB */ 463e705c121SKalle Valo rxb->page_dma = 464cfdc20efSJohannes Berg dma_map_page(trans->dev, page, rxb->offset, 46580084e35SJohannes Berg trans_pcie->rx_buf_bytes, 466e705c121SKalle Valo DMA_FROM_DEVICE); 467e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 468e705c121SKalle Valo rxb->page = NULL; 46947ef328cSIlan Peer spin_lock_bh(&rxq->lock); 470e705c121SKalle Valo list_add(&rxb->list, &rxq->rx_used); 47147ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 472e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 473e705c121SKalle Valo return; 474e705c121SKalle Valo } 475e705c121SKalle Valo 47647ef328cSIlan Peer spin_lock_bh(&rxq->lock); 477e705c121SKalle Valo 478e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 479e705c121SKalle Valo rxq->free_count++; 480e705c121SKalle Valo 48147ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 482e705c121SKalle Valo } 483e705c121SKalle Valo } 484e705c121SKalle Valo 485ff932f61SGolan Ben Ami void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 486e705c121SKalle Valo { 487e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 488e705c121SKalle Valo int i; 489e705c121SKalle Valo 4906ac57200SJohannes Berg if (!trans_pcie->rx_pool) 4916ac57200SJohannes Berg return; 4926ac57200SJohannes Berg 493c042f0c7SJohannes Berg for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) { 49478485054SSara Sharon if (!trans_pcie->rx_pool[i].page) 495e705c121SKalle Valo continue; 49678485054SSara Sharon dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 49780084e35SJohannes Berg trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE); 49878485054SSara Sharon __free_pages(trans_pcie->rx_pool[i].page, 49978485054SSara Sharon trans_pcie->rx_page_order); 50078485054SSara Sharon trans_pcie->rx_pool[i].page = NULL; 501e705c121SKalle Valo } 502e705c121SKalle Valo } 503e705c121SKalle Valo 504e705c121SKalle Valo /* 505e705c121SKalle Valo * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 506e705c121SKalle Valo * 507e705c121SKalle Valo * Allocates for each received request 8 pages 508e705c121SKalle Valo * Called as a scheduled work item. 509e705c121SKalle Valo */ 510e705c121SKalle Valo static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 511e705c121SKalle Valo { 512e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 513e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 514e705c121SKalle Valo struct list_head local_empty; 515c6ac9f9fSSara Sharon int pending = atomic_read(&rba->req_pending); 516e705c121SKalle Valo 5176dcdd165SSara Sharon IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending); 518e705c121SKalle Valo 519e705c121SKalle Valo /* If we were scheduled - there is at least one request */ 52025edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 521e705c121SKalle Valo /* swap out the rba->rbd_empty to a local list */ 522e705c121SKalle Valo list_replace_init(&rba->rbd_empty, &local_empty); 52325edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 524e705c121SKalle Valo 525e705c121SKalle Valo while (pending) { 526e705c121SKalle Valo int i; 5270979a913SJohannes Berg LIST_HEAD(local_allocated); 52878485054SSara Sharon gfp_t gfp_mask = GFP_KERNEL; 52978485054SSara Sharon 53078485054SSara Sharon /* Do not post a warning if there are only a few requests */ 53178485054SSara Sharon if (pending < RX_PENDING_WATERMARK) 53278485054SSara Sharon gfp_mask |= __GFP_NOWARN; 533e705c121SKalle Valo 534e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 535e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 536e705c121SKalle Valo struct page *page; 537e705c121SKalle Valo 538e705c121SKalle Valo /* List should never be empty - each reused RBD is 539e705c121SKalle Valo * returned to the list, and initial pool covers any 540e705c121SKalle Valo * possible gap between the time the page is allocated 541e705c121SKalle Valo * to the time the RBD is added. 542e705c121SKalle Valo */ 543e705c121SKalle Valo BUG_ON(list_empty(&local_empty)); 544e705c121SKalle Valo /* Get the first rxb from the rbd list */ 545e705c121SKalle Valo rxb = list_first_entry(&local_empty, 546e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 547e705c121SKalle Valo BUG_ON(rxb->page); 548e705c121SKalle Valo 549e705c121SKalle Valo /* Alloc a new receive buffer */ 550cfdc20efSJohannes Berg page = iwl_pcie_rx_alloc_page(trans, &rxb->offset, 551cfdc20efSJohannes Berg gfp_mask); 552e705c121SKalle Valo if (!page) 553e705c121SKalle Valo continue; 554e705c121SKalle Valo rxb->page = page; 555e705c121SKalle Valo 556e705c121SKalle Valo /* Get physical address of the RB */ 557cfdc20efSJohannes Berg rxb->page_dma = dma_map_page(trans->dev, page, 558cfdc20efSJohannes Berg rxb->offset, 55980084e35SJohannes Berg trans_pcie->rx_buf_bytes, 560e705c121SKalle Valo DMA_FROM_DEVICE); 561e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 562e705c121SKalle Valo rxb->page = NULL; 563e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 564e705c121SKalle Valo continue; 565e705c121SKalle Valo } 566e705c121SKalle Valo 567e705c121SKalle Valo /* move the allocated entry to the out list */ 568e705c121SKalle Valo list_move(&rxb->list, &local_allocated); 569e705c121SKalle Valo i++; 570e705c121SKalle Valo } 571e705c121SKalle Valo 572c6ac9f9fSSara Sharon atomic_dec(&rba->req_pending); 573e705c121SKalle Valo pending--; 574c6ac9f9fSSara Sharon 575e705c121SKalle Valo if (!pending) { 576c6ac9f9fSSara Sharon pending = atomic_read(&rba->req_pending); 5776dcdd165SSara Sharon if (pending) 5786dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 579c6ac9f9fSSara Sharon "Got more pending allocation requests = %d\n", 580e705c121SKalle Valo pending); 581e705c121SKalle Valo } 582e705c121SKalle Valo 58325edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 584e705c121SKalle Valo /* add the allocated rbds to the allocator allocated list */ 585e705c121SKalle Valo list_splice_tail(&local_allocated, &rba->rbd_allocated); 586e705c121SKalle Valo /* get more empty RBDs for current pending requests */ 587e705c121SKalle Valo list_splice_tail_init(&rba->rbd_empty, &local_empty); 58825edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 589e705c121SKalle Valo 590e705c121SKalle Valo atomic_inc(&rba->req_ready); 591c6ac9f9fSSara Sharon 592e705c121SKalle Valo } 593e705c121SKalle Valo 59425edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 595e705c121SKalle Valo /* return unused rbds to the allocator empty list */ 596e705c121SKalle Valo list_splice_tail(&local_empty, &rba->rbd_empty); 59725edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 598c6ac9f9fSSara Sharon 5996dcdd165SSara Sharon IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__); 600e705c121SKalle Valo } 601e705c121SKalle Valo 602e705c121SKalle Valo /* 603d56daea4SSara Sharon * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 604e705c121SKalle Valo .* 605e705c121SKalle Valo .* Called by queue when the queue posted allocation request and 606e705c121SKalle Valo * has freed 8 RBDs in order to restock itself. 607d56daea4SSara Sharon * This function directly moves the allocated RBs to the queue's ownership 608d56daea4SSara Sharon * and updates the relevant counters. 609e705c121SKalle Valo */ 610d56daea4SSara Sharon static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 611d56daea4SSara Sharon struct iwl_rxq *rxq) 612e705c121SKalle Valo { 613e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 614e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 615e705c121SKalle Valo int i; 616e705c121SKalle Valo 617d56daea4SSara Sharon lockdep_assert_held(&rxq->lock); 618d56daea4SSara Sharon 619e705c121SKalle Valo /* 620e705c121SKalle Valo * atomic_dec_if_positive returns req_ready - 1 for any scenario. 621e705c121SKalle Valo * If req_ready is 0 atomic_dec_if_positive will return -1 and this 622d56daea4SSara Sharon * function will return early, as there are no ready requests. 623e705c121SKalle Valo * atomic_dec_if_positive will perofrm the *actual* decrement only if 624e705c121SKalle Valo * req_ready > 0, i.e. - there are ready requests and the function 625e705c121SKalle Valo * hands one request to the caller. 626e705c121SKalle Valo */ 627e705c121SKalle Valo if (atomic_dec_if_positive(&rba->req_ready) < 0) 628d56daea4SSara Sharon return; 629e705c121SKalle Valo 630e705c121SKalle Valo spin_lock(&rba->lock); 631e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 632e705c121SKalle Valo /* Get next free Rx buffer, remove it from free list */ 633d56daea4SSara Sharon struct iwl_rx_mem_buffer *rxb = 634d56daea4SSara Sharon list_first_entry(&rba->rbd_allocated, 635e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 636d56daea4SSara Sharon 637d56daea4SSara Sharon list_move(&rxb->list, &rxq->rx_free); 638e705c121SKalle Valo } 639e705c121SKalle Valo spin_unlock(&rba->lock); 640e705c121SKalle Valo 641d56daea4SSara Sharon rxq->used_count -= RX_CLAIM_REQ_ALLOC; 642d56daea4SSara Sharon rxq->free_count += RX_CLAIM_REQ_ALLOC; 643e705c121SKalle Valo } 644e705c121SKalle Valo 64510a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data) 646e705c121SKalle Valo { 647e705c121SKalle Valo struct iwl_rb_allocator *rba_p = 648e705c121SKalle Valo container_of(data, struct iwl_rb_allocator, rx_alloc); 649e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 650e705c121SKalle Valo container_of(rba_p, struct iwl_trans_pcie, rba); 651e705c121SKalle Valo 652e705c121SKalle Valo iwl_pcie_rx_allocator(trans_pcie->trans); 653e705c121SKalle Valo } 654e705c121SKalle Valo 6550307c839SGolan Ben Ami static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td) 6560307c839SGolan Ben Ami { 6570307c839SGolan Ben Ami struct iwl_rx_transfer_desc *rx_td; 6580307c839SGolan Ben Ami 6590307c839SGolan Ben Ami if (use_rx_td) 6600307c839SGolan Ben Ami return sizeof(*rx_td); 6610307c839SGolan Ben Ami else 662286ca8ebSLuca Coelho return trans->trans_cfg->mq_rx_supported ? sizeof(__le64) : 6630307c839SGolan Ben Ami sizeof(__le32); 6640307c839SGolan Ben Ami } 6650307c839SGolan Ben Ami 6661b493e30SGolan Ben Ami static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 6671b493e30SGolan Ben Ami struct iwl_rxq *rxq) 6681b493e30SGolan Ben Ami { 669286ca8ebSLuca Coelho bool use_rx_td = (trans->trans_cfg->device_family >= 6703681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210); 6710307c839SGolan Ben Ami int free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 6721b493e30SGolan Ben Ami 6731b493e30SGolan Ben Ami if (rxq->bd) 6740307c839SGolan Ben Ami dma_free_coherent(trans->dev, 6750307c839SGolan Ben Ami free_size * rxq->queue_size, 6761b493e30SGolan Ben Ami rxq->bd, rxq->bd_dma); 6771b493e30SGolan Ben Ami rxq->bd_dma = 0; 6781b493e30SGolan Ben Ami rxq->bd = NULL; 6791b493e30SGolan Ben Ami 6801b493e30SGolan Ben Ami rxq->rb_stts_dma = 0; 6811b493e30SGolan Ben Ami rxq->rb_stts = NULL; 6821b493e30SGolan Ben Ami 6831b493e30SGolan Ben Ami if (rxq->used_bd) 6840307c839SGolan Ben Ami dma_free_coherent(trans->dev, 685b2a58c97SSara Sharon (use_rx_td ? sizeof(*rxq->cd) : 6860307c839SGolan Ben Ami sizeof(__le32)) * rxq->queue_size, 6871b493e30SGolan Ben Ami rxq->used_bd, rxq->used_bd_dma); 6881b493e30SGolan Ben Ami rxq->used_bd_dma = 0; 6891b493e30SGolan Ben Ami rxq->used_bd = NULL; 6901b493e30SGolan Ben Ami } 6911b493e30SGolan Ben Ami 6921b493e30SGolan Ben Ami static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 6931b493e30SGolan Ben Ami struct iwl_rxq *rxq) 694e705c121SKalle Valo { 695e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 696e705c121SKalle Valo struct device *dev = trans->dev; 69778485054SSara Sharon int i; 6980307c839SGolan Ben Ami int free_size; 699286ca8ebSLuca Coelho bool use_rx_td = (trans->trans_cfg->device_family >= 7003681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210); 7016cc6ba3aSTriebitz size_t rb_stts_size = use_rx_td ? sizeof(__le16) : 7026cc6ba3aSTriebitz sizeof(struct iwl_rb_status); 703e705c121SKalle Valo 70478485054SSara Sharon spin_lock_init(&rxq->lock); 705286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 706c042f0c7SJohannes Berg rxq->queue_size = trans->cfg->num_rbds; 70796a6497bSSara Sharon else 70896a6497bSSara Sharon rxq->queue_size = RX_QUEUE_SIZE; 70996a6497bSSara Sharon 7100307c839SGolan Ben Ami free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 7110307c839SGolan Ben Ami 71278485054SSara Sharon /* 71378485054SSara Sharon * Allocate the circular buffer of Read Buffer Descriptors 71478485054SSara Sharon * (RBDs) 71578485054SSara Sharon */ 716750afb08SLuis Chamberlain rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size, 717e705c121SKalle Valo &rxq->bd_dma, GFP_KERNEL); 718e705c121SKalle Valo if (!rxq->bd) 71978485054SSara Sharon goto err; 72078485054SSara Sharon 721286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) { 722750afb08SLuis Chamberlain rxq->used_bd = dma_alloc_coherent(dev, 723750afb08SLuis Chamberlain (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size, 72496a6497bSSara Sharon &rxq->used_bd_dma, 72596a6497bSSara Sharon GFP_KERNEL); 72696a6497bSSara Sharon if (!rxq->used_bd) 72796a6497bSSara Sharon goto err; 72896a6497bSSara Sharon } 729e705c121SKalle Valo 7303827cb59SJohannes Berg rxq->rb_stts = (u8 *)trans_pcie->base_rb_stts + rxq->id * rb_stts_size; 7316cc6ba3aSTriebitz rxq->rb_stts_dma = 7326cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size; 7331b493e30SGolan Ben Ami 734e705c121SKalle Valo return 0; 735e705c121SKalle Valo 73678485054SSara Sharon err: 73778485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 73878485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 73978485054SSara Sharon 7401b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 74178485054SSara Sharon } 74296a6497bSSara Sharon 743e705c121SKalle Valo return -ENOMEM; 744e705c121SKalle Valo } 745e705c121SKalle Valo 746ab393cb1SJohannes Berg static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 7471b493e30SGolan Ben Ami { 7481b493e30SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 7491b493e30SGolan Ben Ami struct iwl_rb_allocator *rba = &trans_pcie->rba; 7501b493e30SGolan Ben Ami int i, ret; 751286ca8ebSLuca Coelho size_t rb_stts_size = trans->trans_cfg->device_family >= 7523681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210 ? 7536cc6ba3aSTriebitz sizeof(__le16) : sizeof(struct iwl_rb_status); 7541b493e30SGolan Ben Ami 7551b493e30SGolan Ben Ami if (WARN_ON(trans_pcie->rxq)) 7561b493e30SGolan Ben Ami return -EINVAL; 7571b493e30SGolan Ben Ami 7581b493e30SGolan Ben Ami trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 7591b493e30SGolan Ben Ami GFP_KERNEL); 760c042f0c7SJohannes Berg trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 761c042f0c7SJohannes Berg sizeof(trans_pcie->rx_pool[0]), 762c042f0c7SJohannes Berg GFP_KERNEL); 763c042f0c7SJohannes Berg trans_pcie->global_table = 764c042f0c7SJohannes Berg kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 765c042f0c7SJohannes Berg sizeof(trans_pcie->global_table[0]), 766c042f0c7SJohannes Berg GFP_KERNEL); 767c042f0c7SJohannes Berg if (!trans_pcie->rxq || !trans_pcie->rx_pool || 768c042f0c7SJohannes Berg !trans_pcie->global_table) { 769c042f0c7SJohannes Berg ret = -ENOMEM; 770c042f0c7SJohannes Berg goto err; 771c042f0c7SJohannes Berg } 7721b493e30SGolan Ben Ami 7731b493e30SGolan Ben Ami spin_lock_init(&rba->lock); 7741b493e30SGolan Ben Ami 7756cc6ba3aSTriebitz /* 7766cc6ba3aSTriebitz * Allocate the driver's pointer to receive buffer status. 7776cc6ba3aSTriebitz * Allocate for all queues continuously (HW requirement). 7786cc6ba3aSTriebitz */ 7796cc6ba3aSTriebitz trans_pcie->base_rb_stts = 7806cc6ba3aSTriebitz dma_alloc_coherent(trans->dev, 7816cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 7826cc6ba3aSTriebitz &trans_pcie->base_rb_stts_dma, 7836cc6ba3aSTriebitz GFP_KERNEL); 7846cc6ba3aSTriebitz if (!trans_pcie->base_rb_stts) { 7856cc6ba3aSTriebitz ret = -ENOMEM; 7866cc6ba3aSTriebitz goto err; 7876cc6ba3aSTriebitz } 7886cc6ba3aSTriebitz 7891b493e30SGolan Ben Ami for (i = 0; i < trans->num_rx_queues; i++) { 7901b493e30SGolan Ben Ami struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 7911b493e30SGolan Ben Ami 7926cc6ba3aSTriebitz rxq->id = i; 7931b493e30SGolan Ben Ami ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 7941b493e30SGolan Ben Ami if (ret) 7956cc6ba3aSTriebitz goto err; 7961b493e30SGolan Ben Ami } 7971b493e30SGolan Ben Ami return 0; 7986cc6ba3aSTriebitz 7996cc6ba3aSTriebitz err: 8006cc6ba3aSTriebitz if (trans_pcie->base_rb_stts) { 8016cc6ba3aSTriebitz dma_free_coherent(trans->dev, 8026cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 8036cc6ba3aSTriebitz trans_pcie->base_rb_stts, 8046cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma); 8056cc6ba3aSTriebitz trans_pcie->base_rb_stts = NULL; 8066cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma = 0; 8076cc6ba3aSTriebitz } 808c042f0c7SJohannes Berg kfree(trans_pcie->rx_pool); 8099cf671d6SEmmanuel Grumbach trans_pcie->rx_pool = NULL; 810c042f0c7SJohannes Berg kfree(trans_pcie->global_table); 8119cf671d6SEmmanuel Grumbach trans_pcie->global_table = NULL; 8126cc6ba3aSTriebitz kfree(trans_pcie->rxq); 8139cf671d6SEmmanuel Grumbach trans_pcie->rxq = NULL; 8146cc6ba3aSTriebitz 8156cc6ba3aSTriebitz return ret; 8161b493e30SGolan Ben Ami } 8171b493e30SGolan Ben Ami 818e705c121SKalle Valo static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 819e705c121SKalle Valo { 820e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 821e705c121SKalle Valo u32 rb_size; 822e705c121SKalle Valo const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 823e705c121SKalle Valo 8246c4fbcbcSEmmanuel Grumbach switch (trans_pcie->rx_buf_size) { 8256c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 826e705c121SKalle Valo rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8276c4fbcbcSEmmanuel Grumbach break; 8286c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 8296c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 8306c4fbcbcSEmmanuel Grumbach break; 8316c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 8326c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 8336c4fbcbcSEmmanuel Grumbach break; 8346c4fbcbcSEmmanuel Grumbach default: 8356c4fbcbcSEmmanuel Grumbach WARN_ON(1); 8366c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8376c4fbcbcSEmmanuel Grumbach } 838e705c121SKalle Valo 8391ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 840dfcfeef9SSara Sharon return; 841dfcfeef9SSara Sharon 842e705c121SKalle Valo /* Stop Rx DMA */ 843dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 844e705c121SKalle Valo /* reset and flush pointers */ 845dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 846dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 847dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 848e705c121SKalle Valo 849e705c121SKalle Valo /* Reset driver's Rx queue write index */ 850dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 851e705c121SKalle Valo 852e705c121SKalle Valo /* Tell device where to find RBD circular buffer in DRAM */ 853dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 854e705c121SKalle Valo (u32)(rxq->bd_dma >> 8)); 855e705c121SKalle Valo 856e705c121SKalle Valo /* Tell device where in DRAM to update its Rx status */ 857dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 858e705c121SKalle Valo rxq->rb_stts_dma >> 4); 859e705c121SKalle Valo 860e705c121SKalle Valo /* Enable Rx DMA 861e705c121SKalle Valo * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 862e705c121SKalle Valo * the credit mechanism in 5000 HW RX FIFO 863e705c121SKalle Valo * Direct rx interrupts to hosts 8646c4fbcbcSEmmanuel Grumbach * Rx buffer size 4 or 8k or 12k 865e705c121SKalle Valo * RB timeout 0x10 866e705c121SKalle Valo * 256 RBDs 867e705c121SKalle Valo */ 868dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 869e705c121SKalle Valo FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 870e705c121SKalle Valo FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 871e705c121SKalle Valo FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 872e705c121SKalle Valo rb_size | 873e705c121SKalle Valo (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 874e705c121SKalle Valo (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 875e705c121SKalle Valo 8761ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 877dfcfeef9SSara Sharon 878e705c121SKalle Valo /* Set interrupt coalescing timer to default (2048 usecs) */ 879e705c121SKalle Valo iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 880e705c121SKalle Valo 881e705c121SKalle Valo /* W/A for interrupt coalescing bug in 7260 and 3160 */ 882e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) 883e705c121SKalle Valo iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 884e705c121SKalle Valo } 885e705c121SKalle Valo 886bce97731SSara Sharon static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 88796a6497bSSara Sharon { 88896a6497bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 88996a6497bSSara Sharon u32 rb_size, enabled = 0; 89096a6497bSSara Sharon int i; 89196a6497bSSara Sharon 89296a6497bSSara Sharon switch (trans_pcie->rx_buf_size) { 8931a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 8941a4968d1SGolan Ben Ami rb_size = RFH_RXF_DMA_RB_SIZE_2K; 8951a4968d1SGolan Ben Ami break; 89696a6497bSSara Sharon case IWL_AMSDU_4K: 89796a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 89896a6497bSSara Sharon break; 89996a6497bSSara Sharon case IWL_AMSDU_8K: 90096a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_8K; 90196a6497bSSara Sharon break; 90296a6497bSSara Sharon case IWL_AMSDU_12K: 90396a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_12K; 90496a6497bSSara Sharon break; 90596a6497bSSara Sharon default: 90696a6497bSSara Sharon WARN_ON(1); 90796a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 90896a6497bSSara Sharon } 90996a6497bSSara Sharon 9101ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 911dfcfeef9SSara Sharon return; 912dfcfeef9SSara Sharon 91396a6497bSSara Sharon /* Stop Rx DMA */ 914dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 91596a6497bSSara Sharon /* disable free amd used rx queue operation */ 916dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 91796a6497bSSara Sharon 91896a6497bSSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 91996a6497bSSara Sharon /* Tell device where to find RBD free table in DRAM */ 92012a17458SSara Sharon iwl_write_prph64_no_grab(trans, 921dfcfeef9SSara Sharon RFH_Q_FRBDCB_BA_LSB(i), 922dfcfeef9SSara Sharon trans_pcie->rxq[i].bd_dma); 92396a6497bSSara Sharon /* Tell device where to find RBD used table in DRAM */ 92412a17458SSara Sharon iwl_write_prph64_no_grab(trans, 925dfcfeef9SSara Sharon RFH_Q_URBDCB_BA_LSB(i), 926dfcfeef9SSara Sharon trans_pcie->rxq[i].used_bd_dma); 92796a6497bSSara Sharon /* Tell device where in DRAM to update its Rx status */ 92812a17458SSara Sharon iwl_write_prph64_no_grab(trans, 929dfcfeef9SSara Sharon RFH_Q_URBD_STTS_WPTR_LSB(i), 930bce97731SSara Sharon trans_pcie->rxq[i].rb_stts_dma); 93196a6497bSSara Sharon /* Reset device indice tables */ 932dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 933dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 934dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 93596a6497bSSara Sharon 93696a6497bSSara Sharon enabled |= BIT(i) | BIT(i + 16); 93796a6497bSSara Sharon } 93896a6497bSSara Sharon 93996a6497bSSara Sharon /* 94096a6497bSSara Sharon * Enable Rx DMA 94196a6497bSSara Sharon * Rx buffer size 4 or 8k or 12k 94296a6497bSSara Sharon * Min RB size 4 or 8 94388076015SSara Sharon * Drop frames that exceed RB size 94496a6497bSSara Sharon * 512 RBDs 94596a6497bSSara Sharon */ 946dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 94763044335SSara Sharon RFH_DMA_EN_ENABLE_VAL | rb_size | 94896a6497bSSara Sharon RFH_RXF_DMA_MIN_RB_4_8 | 94988076015SSara Sharon RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 95096a6497bSSara Sharon RFH_RXF_DMA_RBDCB_SIZE_512); 95196a6497bSSara Sharon 95288076015SSara Sharon /* 95388076015SSara Sharon * Activate DMA snooping. 954b0262f07SSara Sharon * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 95588076015SSara Sharon * Default queue is 0 95688076015SSara Sharon */ 957f3779f47SJohannes Berg iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 958f3779f47SJohannes Berg RFH_GEN_CFG_RFH_DMA_SNOOP | 959f3779f47SJohannes Berg RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 960b0262f07SSara Sharon RFH_GEN_CFG_SERVICE_DMA_SNOOP | 961f3779f47SJohannes Berg RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 9627897dfa2SLuca Coelho trans->trans_cfg->integrated ? 963b0262f07SSara Sharon RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 964f3779f47SJohannes Berg RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 96588076015SSara Sharon /* Enable the relevant rx queues */ 966dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 967dfcfeef9SSara Sharon 9681ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 96996a6497bSSara Sharon 97096a6497bSSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 97196a6497bSSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 97296a6497bSSara Sharon } 97396a6497bSSara Sharon 974ff932f61SGolan Ben Ami void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 975e705c121SKalle Valo { 976e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 977e705c121SKalle Valo 978e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_free); 979e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_used); 980e705c121SKalle Valo rxq->free_count = 0; 981e705c121SKalle Valo rxq->used_count = 0; 982e705c121SKalle Valo } 983e705c121SKalle Valo 98425edc8f2SJohannes Berg static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget); 98525edc8f2SJohannes Berg 98625edc8f2SJohannes Berg static int iwl_pcie_napi_poll(struct napi_struct *napi, int budget) 987bce97731SSara Sharon { 98825edc8f2SJohannes Berg struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 98925edc8f2SJohannes Berg struct iwl_trans_pcie *trans_pcie; 99025edc8f2SJohannes Berg struct iwl_trans *trans; 99125edc8f2SJohannes Berg int ret; 99225edc8f2SJohannes Berg 99325edc8f2SJohannes Berg trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 99425edc8f2SJohannes Berg trans = trans_pcie->trans; 99525edc8f2SJohannes Berg 99625edc8f2SJohannes Berg ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 99725edc8f2SJohannes Berg 9989d401222SMordechay Goodstein IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", 9999d401222SMordechay Goodstein rxq->id, ret, budget); 10009d401222SMordechay Goodstein 100125edc8f2SJohannes Berg if (ret < budget) { 100225edc8f2SJohannes Berg spin_lock(&trans_pcie->irq_lock); 100325edc8f2SJohannes Berg if (test_bit(STATUS_INT_ENABLED, &trans->status)) 100425edc8f2SJohannes Berg _iwl_enable_interrupts(trans); 100525edc8f2SJohannes Berg spin_unlock(&trans_pcie->irq_lock); 100625edc8f2SJohannes Berg 100725edc8f2SJohannes Berg napi_complete_done(&rxq->napi, ret); 100825edc8f2SJohannes Berg } 100925edc8f2SJohannes Berg 101025edc8f2SJohannes Berg return ret; 101125edc8f2SJohannes Berg } 101225edc8f2SJohannes Berg 101325edc8f2SJohannes Berg static int iwl_pcie_napi_poll_msix(struct napi_struct *napi, int budget) 101425edc8f2SJohannes Berg { 101525edc8f2SJohannes Berg struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 101625edc8f2SJohannes Berg struct iwl_trans_pcie *trans_pcie; 101725edc8f2SJohannes Berg struct iwl_trans *trans; 101825edc8f2SJohannes Berg int ret; 101925edc8f2SJohannes Berg 102025edc8f2SJohannes Berg trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 102125edc8f2SJohannes Berg trans = trans_pcie->trans; 102225edc8f2SJohannes Berg 102325edc8f2SJohannes Berg ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 10242b616666SMordechay Goodstein IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", rxq->id, ret, 10252b616666SMordechay Goodstein budget); 102625edc8f2SJohannes Berg 102725edc8f2SJohannes Berg if (ret < budget) { 10282b616666SMordechay Goodstein int irq_line = rxq->id; 10292b616666SMordechay Goodstein 10302b616666SMordechay Goodstein /* FIRST_RSS is shared with line 0 */ 10312b616666SMordechay Goodstein if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS && 10322b616666SMordechay Goodstein rxq->id == 1) 10332b616666SMordechay Goodstein irq_line = 0; 10342b616666SMordechay Goodstein 103525edc8f2SJohannes Berg spin_lock(&trans_pcie->irq_lock); 10362b616666SMordechay Goodstein iwl_pcie_clear_irq(trans, irq_line); 103725edc8f2SJohannes Berg spin_unlock(&trans_pcie->irq_lock); 103825edc8f2SJohannes Berg 103925edc8f2SJohannes Berg napi_complete_done(&rxq->napi, ret); 104025edc8f2SJohannes Berg } 104125edc8f2SJohannes Berg 104225edc8f2SJohannes Berg return ret; 1043bce97731SSara Sharon } 1044bce97731SSara Sharon 1045ab393cb1SJohannes Berg static int _iwl_pcie_rx_init(struct iwl_trans *trans) 1046e705c121SKalle Valo { 1047e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 104878485054SSara Sharon struct iwl_rxq *def_rxq; 1049e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 10507b542436SSara Sharon int i, err, queue_size, allocator_pool_size, num_alloc; 1051e705c121SKalle Valo 105278485054SSara Sharon if (!trans_pcie->rxq) { 1053e705c121SKalle Valo err = iwl_pcie_rx_alloc(trans); 1054e705c121SKalle Valo if (err) 1055e705c121SKalle Valo return err; 1056e705c121SKalle Valo } 105778485054SSara Sharon def_rxq = trans_pcie->rxq; 1058e705c121SKalle Valo 10590f22e400SShaul Triebitz cancel_work_sync(&rba->rx_alloc); 10600f22e400SShaul Triebitz 106125edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 1062e705c121SKalle Valo atomic_set(&rba->req_pending, 0); 1063e705c121SKalle Valo atomic_set(&rba->req_ready, 0); 106496a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_allocated); 106596a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_empty); 106625edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 1067e705c121SKalle Valo 10686ac57200SJohannes Berg /* free all first - we overwrite everything here */ 106978485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1070e705c121SKalle Valo 1071e705c121SKalle Valo for (i = 0; i < RX_QUEUE_SIZE; i++) 107278485054SSara Sharon def_rxq->queue[i] = NULL; 1073e705c121SKalle Valo 107478485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 107578485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1076e705c121SKalle Valo 107747ef328cSIlan Peer spin_lock_bh(&rxq->lock); 107878485054SSara Sharon /* 107978485054SSara Sharon * Set read write pointer to reflect that we have processed 108078485054SSara Sharon * and used all buffers, but have not restocked the Rx queue 108178485054SSara Sharon * with fresh buffers 108278485054SSara Sharon */ 108378485054SSara Sharon rxq->read = 0; 108478485054SSara Sharon rxq->write = 0; 108578485054SSara Sharon rxq->write_actual = 0; 10863681021fSJohannes Berg memset(rxq->rb_stts, 0, 10873681021fSJohannes Berg (trans->trans_cfg->device_family >= 10883681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210) ? 10890307c839SGolan Ben Ami sizeof(__le16) : sizeof(struct iwl_rb_status)); 109078485054SSara Sharon 109178485054SSara Sharon iwl_pcie_rx_init_rxb_lists(rxq); 109278485054SSara Sharon 1093295d4cd8SJiri Kosina spin_unlock_bh(&rxq->lock); 1094295d4cd8SJiri Kosina 109525edc8f2SJohannes Berg if (!rxq->napi.poll) { 109625edc8f2SJohannes Berg int (*poll)(struct napi_struct *, int) = iwl_pcie_napi_poll; 109725edc8f2SJohannes Berg 10982b616666SMordechay Goodstein if (trans_pcie->msix_enabled) 109925edc8f2SJohannes Berg poll = iwl_pcie_napi_poll_msix; 110025edc8f2SJohannes Berg 1101bce97731SSara Sharon netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 110225edc8f2SJohannes Berg poll, NAPI_POLL_WEIGHT); 110325edc8f2SJohannes Berg napi_enable(&rxq->napi); 110425edc8f2SJohannes Berg } 1105bce97731SSara Sharon 110678485054SSara Sharon } 110778485054SSara Sharon 110896a6497bSSara Sharon /* move the pool to the default queue and allocator ownerships */ 1109286ca8ebSLuca Coelho queue_size = trans->trans_cfg->mq_rx_supported ? 1110c042f0c7SJohannes Berg trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE; 111196a6497bSSara Sharon allocator_pool_size = trans->num_rx_queues * 111296a6497bSSara Sharon (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 11137b542436SSara Sharon num_alloc = queue_size + allocator_pool_size; 1114c042f0c7SJohannes Berg 11157b542436SSara Sharon for (i = 0; i < num_alloc; i++) { 111696a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 111796a6497bSSara Sharon 111896a6497bSSara Sharon if (i < allocator_pool_size) 111996a6497bSSara Sharon list_add(&rxb->list, &rba->rbd_empty); 112096a6497bSSara Sharon else 112196a6497bSSara Sharon list_add(&rxb->list, &def_rxq->rx_used); 112296a6497bSSara Sharon trans_pcie->global_table[i] = rxb; 1123e25d65f2SSara Sharon rxb->vid = (u16)(i + 1); 1124b1753c62SSara Sharon rxb->invalid = true; 112596a6497bSSara Sharon } 112678485054SSara Sharon 112778485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 11282047fa54SSara Sharon 1129eda50cdeSSara Sharon return 0; 1130eda50cdeSSara Sharon } 1131eda50cdeSSara Sharon 1132eda50cdeSSara Sharon int iwl_pcie_rx_init(struct iwl_trans *trans) 1133eda50cdeSSara Sharon { 1134eda50cdeSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1135eda50cdeSSara Sharon int ret = _iwl_pcie_rx_init(trans); 1136eda50cdeSSara Sharon 1137eda50cdeSSara Sharon if (ret) 1138eda50cdeSSara Sharon return ret; 1139eda50cdeSSara Sharon 1140286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 1141bce97731SSara Sharon iwl_pcie_rx_mq_hw_init(trans); 11422047fa54SSara Sharon else 1143eda50cdeSSara Sharon iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 11442047fa54SSara Sharon 1145eda50cdeSSara Sharon iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 114678485054SSara Sharon 114747ef328cSIlan Peer spin_lock_bh(&trans_pcie->rxq->lock); 1148eda50cdeSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 114947ef328cSIlan Peer spin_unlock_bh(&trans_pcie->rxq->lock); 1150e705c121SKalle Valo 1151e705c121SKalle Valo return 0; 1152e705c121SKalle Valo } 1153e705c121SKalle Valo 1154eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1155eda50cdeSSara Sharon { 1156e506b481SSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 1157e506b481SSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1158e506b481SSara Sharon 1159eda50cdeSSara Sharon /* 1160eda50cdeSSara Sharon * We don't configure the RFH. 1161eda50cdeSSara Sharon * Restock will be done at alive, after firmware configured the RFH. 1162eda50cdeSSara Sharon */ 1163eda50cdeSSara Sharon return _iwl_pcie_rx_init(trans); 1164eda50cdeSSara Sharon } 1165eda50cdeSSara Sharon 1166e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans) 1167e705c121SKalle Valo { 1168e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1169e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 117078485054SSara Sharon int i; 1171286ca8ebSLuca Coelho size_t rb_stts_size = trans->trans_cfg->device_family >= 11723681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210 ? 11736cc6ba3aSTriebitz sizeof(__le16) : sizeof(struct iwl_rb_status); 1174e705c121SKalle Valo 117578485054SSara Sharon /* 117678485054SSara Sharon * if rxq is NULL, it means that nothing has been allocated, 117778485054SSara Sharon * exit now 117878485054SSara Sharon */ 117978485054SSara Sharon if (!trans_pcie->rxq) { 1180e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1181e705c121SKalle Valo return; 1182e705c121SKalle Valo } 1183e705c121SKalle Valo 1184e705c121SKalle Valo cancel_work_sync(&rba->rx_alloc); 1185e705c121SKalle Valo 118678485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1187e705c121SKalle Valo 11886cc6ba3aSTriebitz if (trans_pcie->base_rb_stts) { 11896cc6ba3aSTriebitz dma_free_coherent(trans->dev, 11906cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 11916cc6ba3aSTriebitz trans_pcie->base_rb_stts, 11926cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma); 11936cc6ba3aSTriebitz trans_pcie->base_rb_stts = NULL; 11946cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma = 0; 11956cc6ba3aSTriebitz } 11966cc6ba3aSTriebitz 119778485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 119878485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 119978485054SSara Sharon 12001b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 1201bce97731SSara Sharon 120225edc8f2SJohannes Berg if (rxq->napi.poll) { 120325edc8f2SJohannes Berg napi_disable(&rxq->napi); 1204bce97731SSara Sharon netif_napi_del(&rxq->napi); 120596a6497bSSara Sharon } 120625edc8f2SJohannes Berg } 1207c042f0c7SJohannes Berg kfree(trans_pcie->rx_pool); 1208c042f0c7SJohannes Berg kfree(trans_pcie->global_table); 120978485054SSara Sharon kfree(trans_pcie->rxq); 1210cfdc20efSJohannes Berg 1211cfdc20efSJohannes Berg if (trans_pcie->alloc_page) 1212cfdc20efSJohannes Berg __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order); 1213e705c121SKalle Valo } 1214e705c121SKalle Valo 1215868a1e86SShaul Triebitz static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq, 1216868a1e86SShaul Triebitz struct iwl_rb_allocator *rba) 1217868a1e86SShaul Triebitz { 1218868a1e86SShaul Triebitz spin_lock(&rba->lock); 1219868a1e86SShaul Triebitz list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1220868a1e86SShaul Triebitz spin_unlock(&rba->lock); 1221868a1e86SShaul Triebitz } 1222868a1e86SShaul Triebitz 1223e705c121SKalle Valo /* 1224e705c121SKalle Valo * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1225e705c121SKalle Valo * 1226e705c121SKalle Valo * Called when a RBD can be reused. The RBD is transferred to the allocator. 1227e705c121SKalle Valo * When there are 2 empty RBDs - a request for allocation is posted 1228e705c121SKalle Valo */ 1229e705c121SKalle Valo static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1230e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 1231e705c121SKalle Valo struct iwl_rxq *rxq, bool emergency) 1232e705c121SKalle Valo { 1233e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1234e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 1235e705c121SKalle Valo 1236e705c121SKalle Valo /* Move the RBD to the used list, will be moved to allocator in batches 1237e705c121SKalle Valo * before claiming or posting a request*/ 1238e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_used); 1239e705c121SKalle Valo 1240e705c121SKalle Valo if (unlikely(emergency)) 1241e705c121SKalle Valo return; 1242e705c121SKalle Valo 1243e705c121SKalle Valo /* Count the allocator owned RBDs */ 1244e705c121SKalle Valo rxq->used_count++; 1245e705c121SKalle Valo 1246e705c121SKalle Valo /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1247e705c121SKalle Valo * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1248e705c121SKalle Valo * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1249e705c121SKalle Valo * after but we still need to post another request. 1250e705c121SKalle Valo */ 1251e705c121SKalle Valo if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1252e705c121SKalle Valo /* Move the 2 RBDs to the allocator ownership. 1253e705c121SKalle Valo Allocator has another 6 from pool for the request completion*/ 1254868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1255e705c121SKalle Valo 1256e705c121SKalle Valo atomic_inc(&rba->req_pending); 1257e705c121SKalle Valo queue_work(rba->alloc_wq, &rba->rx_alloc); 1258e705c121SKalle Valo } 1259e705c121SKalle Valo } 1260e705c121SKalle Valo 1261e705c121SKalle Valo static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 126278485054SSara Sharon struct iwl_rxq *rxq, 1263e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 12647891965dSSara Sharon bool emergency, 12657891965dSSara Sharon int i) 1266e705c121SKalle Valo { 1267e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 12684f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id]; 1269e705c121SKalle Valo bool page_stolen = false; 127080084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 1271e705c121SKalle Valo u32 offset = 0; 1272e705c121SKalle Valo 1273e705c121SKalle Valo if (WARN_ON(!rxb)) 1274e705c121SKalle Valo return; 1275e705c121SKalle Valo 1276e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1277e705c121SKalle Valo 1278e705c121SKalle Valo while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1279e705c121SKalle Valo struct iwl_rx_packet *pkt; 1280e705c121SKalle Valo bool reclaim; 1281e4475583SJohannes Berg int len; 1282e705c121SKalle Valo struct iwl_rx_cmd_buffer rxcb = { 1283cfdc20efSJohannes Berg ._offset = rxb->offset + offset, 1284e705c121SKalle Valo ._rx_page_order = trans_pcie->rx_page_order, 1285e705c121SKalle Valo ._page = rxb->page, 1286e705c121SKalle Valo ._page_stolen = false, 1287e705c121SKalle Valo .truesize = max_len, 1288e705c121SKalle Valo }; 1289e705c121SKalle Valo 1290e705c121SKalle Valo pkt = rxb_addr(&rxcb); 1291e705c121SKalle Valo 12923bfdee76SJohannes Berg if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 12933bfdee76SJohannes Berg IWL_DEBUG_RX(trans, 12943bfdee76SJohannes Berg "Q %d: RB end marker at offset %d\n", 12953bfdee76SJohannes Berg rxq->id, offset); 1296e705c121SKalle Valo break; 12973bfdee76SJohannes Berg } 1298e705c121SKalle Valo 1299a395058eSJohannes Berg WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1300a395058eSJohannes Berg FH_RSCSR_RXQ_POS != rxq->id, 1301a395058eSJohannes Berg "frame on invalid queue - is on %d and indicates %d\n", 1302a395058eSJohannes Berg rxq->id, 1303a395058eSJohannes Berg (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1304a395058eSJohannes Berg FH_RSCSR_RXQ_POS); 1305ab2e696bSSara Sharon 1306e705c121SKalle Valo IWL_DEBUG_RX(trans, 13073bfdee76SJohannes Berg "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 13083bfdee76SJohannes Berg rxq->id, offset, 130939bdb17eSSharon Dvir iwl_get_cmd_string(trans, 1310f0c86427SJohannes Berg WIDE_ID(pkt->hdr.group_id, pkt->hdr.cmd)), 131135177c99SSara Sharon pkt->hdr.group_id, pkt->hdr.cmd, 131235177c99SSara Sharon le16_to_cpu(pkt->hdr.sequence)); 1313e705c121SKalle Valo 1314e705c121SKalle Valo len = iwl_rx_packet_len(pkt); 1315e705c121SKalle Valo len += sizeof(u32); /* account for status word */ 1316df72138dSJohannes Berg 1317df72138dSJohannes Berg offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1318df72138dSJohannes Berg 1319df72138dSJohannes Berg /* check that what the device tells us made sense */ 1320df72138dSJohannes Berg if (offset > max_len) 1321df72138dSJohannes Berg break; 1322df72138dSJohannes Berg 1323e705c121SKalle Valo trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1324e705c121SKalle Valo trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1325e705c121SKalle Valo 1326e705c121SKalle Valo /* Reclaim a command buffer only if this packet is a response 1327e705c121SKalle Valo * to a (driver-originated) command. 1328e705c121SKalle Valo * If the packet (e.g. Rx frame) originated from uCode, 1329e705c121SKalle Valo * there is no command buffer to reclaim. 1330e705c121SKalle Valo * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1331e705c121SKalle Valo * but apparently a few don't get set; catch them here. */ 1332e705c121SKalle Valo reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1333d8a130b0SJohannes Berg if (reclaim && !pkt->hdr.group_id) { 1334e705c121SKalle Valo int i; 1335e705c121SKalle Valo 1336e705c121SKalle Valo for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1337e705c121SKalle Valo if (trans_pcie->no_reclaim_cmds[i] == 1338e705c121SKalle Valo pkt->hdr.cmd) { 1339e705c121SKalle Valo reclaim = false; 1340e705c121SKalle Valo break; 1341e705c121SKalle Valo } 1342e705c121SKalle Valo } 1343e705c121SKalle Valo } 1344e705c121SKalle Valo 13459416560eSGolan Ben Ami if (rxq->id == trans_pcie->def_rx_queue) 1346bce97731SSara Sharon iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1347bce97731SSara Sharon &rxcb); 1348bce97731SSara Sharon else 1349bce97731SSara Sharon iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1350bce97731SSara Sharon &rxcb, rxq->id); 1351e705c121SKalle Valo 1352e705c121SKalle Valo /* 1353e705c121SKalle Valo * After here, we should always check rxcb._page_stolen, 1354e705c121SKalle Valo * if it is true then one of the handlers took the page. 1355e705c121SKalle Valo */ 1356e705c121SKalle Valo 1357e705c121SKalle Valo if (reclaim) { 1358e4475583SJohannes Berg u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1359e4475583SJohannes Berg int index = SEQ_TO_INDEX(sequence); 1360e4475583SJohannes Berg int cmd_index = iwl_txq_get_cmd_index(txq, index); 1361e4475583SJohannes Berg 1362e4475583SJohannes Berg kfree_sensitive(txq->entries[cmd_index].free_buf); 1363e4475583SJohannes Berg txq->entries[cmd_index].free_buf = NULL; 1364e4475583SJohannes Berg 1365e705c121SKalle Valo /* Invoke any callbacks, transfer the buffer to caller, 1366e705c121SKalle Valo * and fire off the (possibly) blocking 1367e705c121SKalle Valo * iwl_trans_send_cmd() 1368e705c121SKalle Valo * as we reclaim the driver command queue */ 1369e705c121SKalle Valo if (!rxcb._page_stolen) 1370e705c121SKalle Valo iwl_pcie_hcmd_complete(trans, &rxcb); 1371e705c121SKalle Valo else 1372e705c121SKalle Valo IWL_WARN(trans, "Claim null rxb?\n"); 1373e705c121SKalle Valo } 1374e705c121SKalle Valo 1375e705c121SKalle Valo page_stolen |= rxcb._page_stolen; 13763681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 13770307c839SGolan Ben Ami break; 1378e705c121SKalle Valo } 1379e705c121SKalle Valo 1380e705c121SKalle Valo /* page was stolen from us -- free our reference */ 1381e705c121SKalle Valo if (page_stolen) { 1382e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1383e705c121SKalle Valo rxb->page = NULL; 1384e705c121SKalle Valo } 1385e705c121SKalle Valo 1386e705c121SKalle Valo /* Reuse the page if possible. For notification packets and 1387e705c121SKalle Valo * SKBs that fail to Rx correctly, add them back into the 1388e705c121SKalle Valo * rx_free list for reuse later. */ 1389e705c121SKalle Valo if (rxb->page != NULL) { 1390e705c121SKalle Valo rxb->page_dma = 1391cfdc20efSJohannes Berg dma_map_page(trans->dev, rxb->page, rxb->offset, 139280084e35SJohannes Berg trans_pcie->rx_buf_bytes, 1393e705c121SKalle Valo DMA_FROM_DEVICE); 1394e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1395e705c121SKalle Valo /* 1396e705c121SKalle Valo * free the page(s) as well to not break 1397e705c121SKalle Valo * the invariant that the items on the used 1398e705c121SKalle Valo * list have no page(s) 1399e705c121SKalle Valo */ 1400e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1401e705c121SKalle Valo rxb->page = NULL; 1402e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1403e705c121SKalle Valo } else { 1404e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 1405e705c121SKalle Valo rxq->free_count++; 1406e705c121SKalle Valo } 1407e705c121SKalle Valo } else 1408e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1409e705c121SKalle Valo } 1410e705c121SKalle Valo 14111b4bbe8bSSara Sharon static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans, 1412b1c860f6SJohannes Berg struct iwl_rxq *rxq, int i, 1413b1c860f6SJohannes Berg bool *join) 14141b4bbe8bSSara Sharon { 14151b4bbe8bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 14161b4bbe8bSSara Sharon struct iwl_rx_mem_buffer *rxb; 14171b4bbe8bSSara Sharon u16 vid; 14181b4bbe8bSSara Sharon 1419f826faaaSJohannes Berg BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32); 1420f826faaaSJohannes Berg 1421286ca8ebSLuca Coelho if (!trans->trans_cfg->mq_rx_supported) { 14221b4bbe8bSSara Sharon rxb = rxq->queue[i]; 14231b4bbe8bSSara Sharon rxq->queue[i] = NULL; 14241b4bbe8bSSara Sharon return rxb; 14251b4bbe8bSSara Sharon } 14261b4bbe8bSSara Sharon 1427b1c860f6SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1428c042f0c7SJohannes Berg vid = le16_to_cpu(rxq->cd[i].rbid); 1429b1c860f6SJohannes Berg *join = rxq->cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED; 1430b1c860f6SJohannes Berg } else { 1431c042f0c7SJohannes Berg vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; /* 12-bit VID */ 1432b1c860f6SJohannes Berg } 14331b4bbe8bSSara Sharon 1434c042f0c7SJohannes Berg if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs)) 14351b4bbe8bSSara Sharon goto out_err; 14361b4bbe8bSSara Sharon 14371b4bbe8bSSara Sharon rxb = trans_pcie->global_table[vid - 1]; 14381b4bbe8bSSara Sharon if (rxb->invalid) 14391b4bbe8bSSara Sharon goto out_err; 14401b4bbe8bSSara Sharon 144185d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid); 144285d78bb1SSara Sharon 14431b4bbe8bSSara Sharon rxb->invalid = true; 14441b4bbe8bSSara Sharon 14451b4bbe8bSSara Sharon return rxb; 14461b4bbe8bSSara Sharon 14471b4bbe8bSSara Sharon out_err: 14481b4bbe8bSSara Sharon WARN(1, "Invalid rxb from HW %u\n", (u32)vid); 14491b4bbe8bSSara Sharon iwl_force_nmi(trans); 14501b4bbe8bSSara Sharon return NULL; 14511b4bbe8bSSara Sharon } 14521b4bbe8bSSara Sharon 1453e705c121SKalle Valo /* 1454e705c121SKalle Valo * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1455e705c121SKalle Valo */ 145625edc8f2SJohannes Berg static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget) 1457e705c121SKalle Valo { 1458e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 145930f24eabSJohannes Berg struct iwl_rxq *rxq; 146025edc8f2SJohannes Berg u32 r, i, count = 0, handled = 0; 1461e705c121SKalle Valo bool emergency = false; 1462e705c121SKalle Valo 146330f24eabSJohannes Berg if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd)) 146425edc8f2SJohannes Berg return budget; 146530f24eabSJohannes Berg 146630f24eabSJohannes Berg rxq = &trans_pcie->rxq[queue]; 146730f24eabSJohannes Berg 1468e705c121SKalle Valo restart: 1469e705c121SKalle Valo spin_lock(&rxq->lock); 1470e705c121SKalle Valo /* uCode's read index (stored in shared DRAM) indicates the last Rx 1471e705c121SKalle Valo * buffer that the driver may process (last buffer filled by ucode). */ 14720307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1473e705c121SKalle Valo i = rxq->read; 1474e705c121SKalle Valo 14755eae443eSSara Sharon /* W/A 9000 device step A0 wrap-around bug */ 14765eae443eSSara Sharon r &= (rxq->queue_size - 1); 14775eae443eSSara Sharon 1478e705c121SKalle Valo /* Rx interrupt, but nothing sent from uCode */ 1479e705c121SKalle Valo if (i == r) 14805eae443eSSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1481e705c121SKalle Valo 148225edc8f2SJohannes Berg while (i != r && ++handled < budget) { 1483868a1e86SShaul Triebitz struct iwl_rb_allocator *rba = &trans_pcie->rba; 1484e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 1485868a1e86SShaul Triebitz /* number of RBDs still waiting for page allocation */ 1486868a1e86SShaul Triebitz u32 rb_pending_alloc = 1487868a1e86SShaul Triebitz atomic_read(&trans_pcie->rba.req_pending) * 1488868a1e86SShaul Triebitz RX_CLAIM_REQ_ALLOC; 1489b1c860f6SJohannes Berg bool join = false; 1490e705c121SKalle Valo 1491868a1e86SShaul Triebitz if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 && 1492868a1e86SShaul Triebitz !emergency)) { 1493868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1494e705c121SKalle Valo emergency = true; 14956dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 14966dcdd165SSara Sharon "RX path is in emergency. Pending allocations %d\n", 14976dcdd165SSara Sharon rb_pending_alloc); 1498868a1e86SShaul Triebitz } 1499e705c121SKalle Valo 150085d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 150185d78bb1SSara Sharon 1502b1c860f6SJohannes Berg rxb = iwl_pcie_get_rxb(trans, rxq, i, &join); 15031b4bbe8bSSara Sharon if (!rxb) 15045eae443eSSara Sharon goto out; 1505e705c121SKalle Valo 1506b1c860f6SJohannes Berg if (unlikely(join || rxq->next_rb_is_fragment)) { 1507b1c860f6SJohannes Berg rxq->next_rb_is_fragment = join; 1508b1c860f6SJohannes Berg /* 1509b1c860f6SJohannes Berg * We can only get a multi-RB in the following cases: 1510b1c860f6SJohannes Berg * - firmware issue, sending a too big notification 1511b1c860f6SJohannes Berg * - sniffer mode with a large A-MSDU 1512b1c860f6SJohannes Berg * - large MTU frames (>2k) 1513b1c860f6SJohannes Berg * since the multi-RB functionality is limited to newer 1514b1c860f6SJohannes Berg * hardware that cannot put multiple entries into a 1515b1c860f6SJohannes Berg * single RB. 1516b1c860f6SJohannes Berg * 1517b1c860f6SJohannes Berg * Right now, the higher layers aren't set up to deal 1518b1c860f6SJohannes Berg * with that, so discard all of these. 1519b1c860f6SJohannes Berg */ 1520b1c860f6SJohannes Berg list_add_tail(&rxb->list, &rxq->rx_free); 1521b1c860f6SJohannes Berg rxq->free_count++; 1522b1c860f6SJohannes Berg } else { 15237891965dSSara Sharon iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i); 1524b1c860f6SJohannes Berg } 1525e705c121SKalle Valo 152696a6497bSSara Sharon i = (i + 1) & (rxq->queue_size - 1); 1527e705c121SKalle Valo 1528d56daea4SSara Sharon /* 1529d56daea4SSara Sharon * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1530d56daea4SSara Sharon * try to claim the pre-allocated buffers from the allocator. 1531d56daea4SSara Sharon * If not ready - will try to reclaim next time. 1532d56daea4SSara Sharon * There is no need to reschedule work - allocator exits only 1533d56daea4SSara Sharon * on success 1534e705c121SKalle Valo */ 1535d56daea4SSara Sharon if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1536d56daea4SSara Sharon iwl_pcie_rx_allocator_get(trans, rxq); 1537e705c121SKalle Valo 1538d56daea4SSara Sharon if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1539d56daea4SSara Sharon /* Add the remaining empty RBDs for allocator use */ 1540868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1541d56daea4SSara Sharon } else if (emergency) { 1542e705c121SKalle Valo count++; 1543e705c121SKalle Valo if (count == 8) { 1544e705c121SKalle Valo count = 0; 15456dcdd165SSara Sharon if (rb_pending_alloc < rxq->queue_size / 3) { 15466dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 15476dcdd165SSara Sharon "RX path exited emergency. Pending allocations %d\n", 15486dcdd165SSara Sharon rb_pending_alloc); 1549e705c121SKalle Valo emergency = false; 15506dcdd165SSara Sharon } 1551e0e168dcSGregory Greenman 1552e705c121SKalle Valo rxq->read = i; 1553e705c121SKalle Valo spin_unlock(&rxq->lock); 1554e0e168dcSGregory Greenman iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 155578485054SSara Sharon iwl_pcie_rxq_restock(trans, rxq); 1556e705c121SKalle Valo goto restart; 1557e705c121SKalle Valo } 1558e705c121SKalle Valo } 1559e0e168dcSGregory Greenman } 15605eae443eSSara Sharon out: 1561e705c121SKalle Valo /* Backtrack one entry */ 1562e705c121SKalle Valo rxq->read = i; 1563e705c121SKalle Valo spin_unlock(&rxq->lock); 1564e705c121SKalle Valo 1565e705c121SKalle Valo /* 1566e705c121SKalle Valo * handle a case where in emergency there are some unallocated RBDs. 1567e705c121SKalle Valo * those RBDs are in the used list, but are not tracked by the queue's 1568e705c121SKalle Valo * used_count which counts allocator owned RBDs. 1569e705c121SKalle Valo * unallocated emergency RBDs must be allocated on exit, otherwise 1570e705c121SKalle Valo * when called again the function may not be in emergency mode and 1571e705c121SKalle Valo * they will be handed to the allocator with no tracking in the RBD 1572e705c121SKalle Valo * allocator counters, which will lead to them never being claimed back 1573e705c121SKalle Valo * by the queue. 1574e705c121SKalle Valo * by allocating them here, they are now in the queue free list, and 1575e705c121SKalle Valo * will be restocked by the next call of iwl_pcie_rxq_restock. 1576e705c121SKalle Valo */ 1577e705c121SKalle Valo if (unlikely(emergency && count)) 157878485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1579e705c121SKalle Valo 1580e0e168dcSGregory Greenman iwl_pcie_rxq_restock(trans, rxq); 158125edc8f2SJohannes Berg 158225edc8f2SJohannes Berg return handled; 1583e705c121SKalle Valo } 1584e705c121SKalle Valo 15852e5d4a8fSHaim Dreyfuss static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 15862e5d4a8fSHaim Dreyfuss { 15872e5d4a8fSHaim Dreyfuss u8 queue = entry->entry; 15882e5d4a8fSHaim Dreyfuss struct msix_entry *entries = entry - queue; 15892e5d4a8fSHaim Dreyfuss 15902e5d4a8fSHaim Dreyfuss return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 15912e5d4a8fSHaim Dreyfuss } 15922e5d4a8fSHaim Dreyfuss 15932e5d4a8fSHaim Dreyfuss /* 15942e5d4a8fSHaim Dreyfuss * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 15952e5d4a8fSHaim Dreyfuss * This interrupt handler should be used with RSS queue only. 15962e5d4a8fSHaim Dreyfuss */ 15972e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 15982e5d4a8fSHaim Dreyfuss { 15992e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 16002e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 16012e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 160225edc8f2SJohannes Berg struct iwl_rxq *rxq = &trans_pcie->rxq[entry->entry]; 16032e5d4a8fSHaim Dreyfuss 1604c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1605c42ff65dSJohannes Berg 16065eae443eSSara Sharon if (WARN_ON(entry->entry >= trans->num_rx_queues)) 16075eae443eSSara Sharon return IRQ_NONE; 16085eae443eSSara Sharon 16099d401222SMordechay Goodstein if (WARN_ONCE(!rxq, 16109d401222SMordechay Goodstein "[%d] Got MSI-X interrupt before we have Rx queues", 16119d401222SMordechay Goodstein entry->entry)) 1612abc599efSEmmanuel Grumbach return IRQ_NONE; 1613abc599efSEmmanuel Grumbach 16142e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 16159d401222SMordechay Goodstein IWL_DEBUG_ISR(trans, "[%d] Got interrupt\n", entry->entry); 16162e5d4a8fSHaim Dreyfuss 16172e5d4a8fSHaim Dreyfuss local_bh_disable(); 161825edc8f2SJohannes Berg if (napi_schedule_prep(&rxq->napi)) 161925edc8f2SJohannes Berg __napi_schedule(&rxq->napi); 162025edc8f2SJohannes Berg else 162125edc8f2SJohannes Berg iwl_pcie_clear_irq(trans, entry->entry); 16222e5d4a8fSHaim Dreyfuss local_bh_enable(); 16232e5d4a8fSHaim Dreyfuss 16242e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 16252e5d4a8fSHaim Dreyfuss 16262e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 16272e5d4a8fSHaim Dreyfuss } 16282e5d4a8fSHaim Dreyfuss 1629e705c121SKalle Valo /* 1630e705c121SKalle Valo * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1631e705c121SKalle Valo */ 1632e705c121SKalle Valo static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1633e705c121SKalle Valo { 1634e705c121SKalle Valo int i; 1635e705c121SKalle Valo 1636e705c121SKalle Valo /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1637e705c121SKalle Valo if (trans->cfg->internal_wimax_coex && 1638e705c121SKalle Valo !trans->cfg->apmg_not_supported && 1639e705c121SKalle Valo (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1640e705c121SKalle Valo APMS_CLK_VAL_MRB_FUNC_MODE) || 1641e705c121SKalle Valo (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1642e705c121SKalle Valo APMG_PS_CTRL_VAL_RESET_REQ))) { 1643e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1644e705c121SKalle Valo iwl_op_mode_wimax_active(trans->op_mode); 164513f028b4SMordechay Goodstein wake_up(&trans->wait_command_queue); 1646e705c121SKalle Valo return; 1647e705c121SKalle Valo } 1648e705c121SKalle Valo 1649286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 16504f4822b7SMordechay Goodstein if (!trans->txqs.txq[i]) 165113a3a390SSara Sharon continue; 16524f4822b7SMordechay Goodstein del_timer(&trans->txqs.txq[i]->stuck_timer); 165313a3a390SSara Sharon } 1654e705c121SKalle Valo 16557d75f32eSEmmanuel Grumbach /* The STATUS_FW_ERROR bit is set in this function. This must happen 16567d75f32eSEmmanuel Grumbach * before we wake up the command caller, to ensure a proper cleanup. */ 1657b8221b0fSJohannes Berg iwl_trans_fw_error(trans, false); 16587d75f32eSEmmanuel Grumbach 1659e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 166013f028b4SMordechay Goodstein wake_up(&trans->wait_command_queue); 1661e705c121SKalle Valo } 1662e705c121SKalle Valo 1663e705c121SKalle Valo static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1664e705c121SKalle Valo { 1665e705c121SKalle Valo u32 inta; 1666e705c121SKalle Valo 1667e705c121SKalle Valo lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1668e705c121SKalle Valo 1669e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1670e705c121SKalle Valo 1671e705c121SKalle Valo /* Discover which interrupts are active/pending */ 1672e705c121SKalle Valo inta = iwl_read32(trans, CSR_INT); 1673e705c121SKalle Valo 1674e705c121SKalle Valo /* the thread will service interrupts and re-enable them */ 1675e705c121SKalle Valo return inta; 1676e705c121SKalle Valo } 1677e705c121SKalle Valo 1678e705c121SKalle Valo /* a device (PCI-E) page is 4096 bytes long */ 1679e705c121SKalle Valo #define ICT_SHIFT 12 1680e705c121SKalle Valo #define ICT_SIZE (1 << ICT_SHIFT) 1681e705c121SKalle Valo #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1682e705c121SKalle Valo 1683e705c121SKalle Valo /* interrupt handler using ict table, with this interrupt driver will 1684e705c121SKalle Valo * stop using INTA register to get device's interrupt, reading this register 1685e705c121SKalle Valo * is expensive, device will write interrupts in ICT dram table, increment 1686e705c121SKalle Valo * index then will fire interrupt to driver, driver will OR all ICT table 1687e705c121SKalle Valo * entries from current index up to table entry with 0 value. the result is 1688e705c121SKalle Valo * the interrupt we need to service, driver will set the entries back to 0 and 1689e705c121SKalle Valo * set index. 1690e705c121SKalle Valo */ 1691e705c121SKalle Valo static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1692e705c121SKalle Valo { 1693e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1694e705c121SKalle Valo u32 inta; 1695e705c121SKalle Valo u32 val = 0; 1696e705c121SKalle Valo u32 read; 1697e705c121SKalle Valo 1698e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1699e705c121SKalle Valo 1700e705c121SKalle Valo /* Ignore interrupt if there's nothing in NIC to service. 1701e705c121SKalle Valo * This may be due to IRQ shared with another device, 1702e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. */ 1703e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1704e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1705e705c121SKalle Valo if (!read) 1706e705c121SKalle Valo return 0; 1707e705c121SKalle Valo 1708e705c121SKalle Valo /* 1709e705c121SKalle Valo * Collect all entries up to the first 0, starting from ict_index; 1710e705c121SKalle Valo * note we already read at ict_index. 1711e705c121SKalle Valo */ 1712e705c121SKalle Valo do { 1713e705c121SKalle Valo val |= read; 1714e705c121SKalle Valo IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1715e705c121SKalle Valo trans_pcie->ict_index, read); 1716e705c121SKalle Valo trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1717e705c121SKalle Valo trans_pcie->ict_index = 1718e705c121SKalle Valo ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1719e705c121SKalle Valo 1720e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1721e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1722e705c121SKalle Valo read); 1723e705c121SKalle Valo } while (read); 1724e705c121SKalle Valo 1725e705c121SKalle Valo /* We should not get this value, just ignore it. */ 1726e705c121SKalle Valo if (val == 0xffffffff) 1727e705c121SKalle Valo val = 0; 1728e705c121SKalle Valo 1729e705c121SKalle Valo /* 1730e705c121SKalle Valo * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1731e705c121SKalle Valo * (bit 15 before shifting it to 31) to clear when using interrupt 1732e705c121SKalle Valo * coalescing. fortunately, bits 18 and 19 stay set when this happens 1733e705c121SKalle Valo * so we use them to decide on the real state of the Rx bit. 1734e705c121SKalle Valo * In order words, bit 15 is set if bit 18 or bit 19 are set. 1735e705c121SKalle Valo */ 1736e705c121SKalle Valo if (val & 0xC0000) 1737e705c121SKalle Valo val |= 0x8000; 1738e705c121SKalle Valo 1739e705c121SKalle Valo inta = (0xff & val) | ((0xff00 & val) << 16); 1740e705c121SKalle Valo return inta; 1741e705c121SKalle Valo } 1742e705c121SKalle Valo 1743fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 17443a6e168bSJohannes Berg { 17453a6e168bSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17463a6e168bSJohannes Berg struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1747326477e4SJohannes Berg bool hw_rfkill, prev, report; 17483a6e168bSJohannes Berg 17493a6e168bSJohannes Berg mutex_lock(&trans_pcie->mutex); 1750326477e4SJohannes Berg prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 17513a6e168bSJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1752326477e4SJohannes Berg if (hw_rfkill) { 1753326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1754326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1755326477e4SJohannes Berg } 1756326477e4SJohannes Berg if (trans_pcie->opmode_down) 1757326477e4SJohannes Berg report = hw_rfkill; 1758326477e4SJohannes Berg else 1759326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 17603a6e168bSJohannes Berg 17613a6e168bSJohannes Berg IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 17623a6e168bSJohannes Berg hw_rfkill ? "disable radio" : "enable radio"); 17633a6e168bSJohannes Berg 17643a6e168bSJohannes Berg isr_stats->rfkill++; 17653a6e168bSJohannes Berg 1766326477e4SJohannes Berg if (prev != report) 1767326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 17683a6e168bSJohannes Berg mutex_unlock(&trans_pcie->mutex); 17693a6e168bSJohannes Berg 17703a6e168bSJohannes Berg if (hw_rfkill) { 17713a6e168bSJohannes Berg if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 17723a6e168bSJohannes Berg &trans->status)) 17733a6e168bSJohannes Berg IWL_DEBUG_RF_KILL(trans, 17743a6e168bSJohannes Berg "Rfkill while SYNC HCMD in flight\n"); 177513f028b4SMordechay Goodstein wake_up(&trans->wait_command_queue); 17763a6e168bSJohannes Berg } else { 1777326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1778326477e4SJohannes Berg if (trans_pcie->opmode_down) 1779326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 17803a6e168bSJohannes Berg } 17813a6e168bSJohannes Berg } 17823a6e168bSJohannes Berg 1783e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1784e705c121SKalle Valo { 1785e705c121SKalle Valo struct iwl_trans *trans = dev_id; 1786e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1787e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1788e705c121SKalle Valo u32 inta = 0; 1789e705c121SKalle Valo u32 handled = 0; 179025edc8f2SJohannes Berg bool polling = false; 1791e705c121SKalle Valo 1792e705c121SKalle Valo lock_map_acquire(&trans->sync_cmd_lockdep_map); 1793e705c121SKalle Valo 179425edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 1795e705c121SKalle Valo 1796e705c121SKalle Valo /* dram interrupt table not set yet, 1797e705c121SKalle Valo * use legacy interrupt. 1798e705c121SKalle Valo */ 1799e705c121SKalle Valo if (likely(trans_pcie->use_ict)) 1800e705c121SKalle Valo inta = iwl_pcie_int_cause_ict(trans); 1801e705c121SKalle Valo else 1802e705c121SKalle Valo inta = iwl_pcie_int_cause_non_ict(trans); 1803e705c121SKalle Valo 1804e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1805e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1806e705c121SKalle Valo "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1807e705c121SKalle Valo inta, trans_pcie->inta_mask, 1808e705c121SKalle Valo iwl_read32(trans, CSR_INT_MASK), 1809e705c121SKalle Valo iwl_read32(trans, CSR_FH_INT_STATUS)); 1810e705c121SKalle Valo if (inta & (~trans_pcie->inta_mask)) 1811e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1812e705c121SKalle Valo "We got a masked interrupt (0x%08x)\n", 1813e705c121SKalle Valo inta & (~trans_pcie->inta_mask)); 1814e705c121SKalle Valo } 1815e705c121SKalle Valo 1816e705c121SKalle Valo inta &= trans_pcie->inta_mask; 1817e705c121SKalle Valo 1818e705c121SKalle Valo /* 1819e705c121SKalle Valo * Ignore interrupt if there's nothing in NIC to service. 1820e705c121SKalle Valo * This may be due to IRQ shared with another device, 1821e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. 1822e705c121SKalle Valo */ 1823e705c121SKalle Valo if (unlikely(!inta)) { 1824e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1825e705c121SKalle Valo /* 1826e705c121SKalle Valo * Re-enable interrupts here since we don't 1827e705c121SKalle Valo * have anything to service 1828e705c121SKalle Valo */ 1829e705c121SKalle Valo if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1830f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 183125edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 1832e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1833e705c121SKalle Valo return IRQ_NONE; 1834e705c121SKalle Valo } 1835e705c121SKalle Valo 1836e705c121SKalle Valo if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1837e705c121SKalle Valo /* 1838e705c121SKalle Valo * Hardware disappeared. It might have 1839e705c121SKalle Valo * already raised an interrupt. 1840e705c121SKalle Valo */ 1841e705c121SKalle Valo IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 184225edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 1843e705c121SKalle Valo goto out; 1844e705c121SKalle Valo } 1845e705c121SKalle Valo 1846e705c121SKalle Valo /* Ack/clear/reset pending uCode interrupts. 1847e705c121SKalle Valo * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1848e705c121SKalle Valo */ 1849e705c121SKalle Valo /* There is a hardware bug in the interrupt mask function that some 1850e705c121SKalle Valo * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1851e705c121SKalle Valo * they are disabled in the CSR_INT_MASK register. Furthermore the 1852e705c121SKalle Valo * ICT interrupt handling mechanism has another bug that might cause 1853e705c121SKalle Valo * these unmasked interrupts fail to be detected. We workaround the 1854e705c121SKalle Valo * hardware bugs here by ACKing all the possible interrupts so that 1855e705c121SKalle Valo * interrupt coalescing can still be achieved. 1856e705c121SKalle Valo */ 1857e705c121SKalle Valo iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1858e705c121SKalle Valo 1859e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) 1860e705c121SKalle Valo IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1861e705c121SKalle Valo inta, iwl_read32(trans, CSR_INT_MASK)); 1862e705c121SKalle Valo 186325edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 1864e705c121SKalle Valo 1865e705c121SKalle Valo /* Now service all interrupt bits discovered above. */ 1866e705c121SKalle Valo if (inta & CSR_INT_BIT_HW_ERR) { 1867e705c121SKalle Valo IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1868e705c121SKalle Valo 1869e705c121SKalle Valo /* Tell the device to stop sending interrupts */ 1870e705c121SKalle Valo iwl_disable_interrupts(trans); 1871e705c121SKalle Valo 1872e705c121SKalle Valo isr_stats->hw++; 1873e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1874e705c121SKalle Valo 1875e705c121SKalle Valo handled |= CSR_INT_BIT_HW_ERR; 1876e705c121SKalle Valo 1877e705c121SKalle Valo goto out; 1878e705c121SKalle Valo } 1879e705c121SKalle Valo 1880e705c121SKalle Valo /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1881e705c121SKalle Valo if (inta & CSR_INT_BIT_SCD) { 1882e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1883e705c121SKalle Valo "Scheduler finished to transmit the frame/frames.\n"); 1884e705c121SKalle Valo isr_stats->sch++; 1885e705c121SKalle Valo } 1886e705c121SKalle Valo 1887e705c121SKalle Valo /* Alive notification via Rx interrupt will do the real work */ 1888e705c121SKalle Valo if (inta & CSR_INT_BIT_ALIVE) { 1889e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1890e705c121SKalle Valo isr_stats->alive++; 1891286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) { 1892eda50cdeSSara Sharon /* 1893eda50cdeSSara Sharon * We can restock, since firmware configured 1894eda50cdeSSara Sharon * the RFH 1895eda50cdeSSara Sharon */ 1896eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1897eda50cdeSSara Sharon } 1898ed3e4c6dSEmmanuel Grumbach 1899ed3e4c6dSEmmanuel Grumbach handled |= CSR_INT_BIT_ALIVE; 1900e705c121SKalle Valo } 1901e705c121SKalle Valo 1902e705c121SKalle Valo /* Safely ignore these bits for debug checks below */ 1903e705c121SKalle Valo inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1904e705c121SKalle Valo 1905e705c121SKalle Valo /* HW RF KILL switch toggled */ 1906e705c121SKalle Valo if (inta & CSR_INT_BIT_RF_KILL) { 19073a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 1908e705c121SKalle Valo handled |= CSR_INT_BIT_RF_KILL; 1909e705c121SKalle Valo } 1910e705c121SKalle Valo 1911e705c121SKalle Valo /* Chip got too hot and stopped itself */ 1912e705c121SKalle Valo if (inta & CSR_INT_BIT_CT_KILL) { 1913e705c121SKalle Valo IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1914e705c121SKalle Valo isr_stats->ctkill++; 1915e705c121SKalle Valo handled |= CSR_INT_BIT_CT_KILL; 1916e705c121SKalle Valo } 1917e705c121SKalle Valo 1918e705c121SKalle Valo /* Error detected by uCode */ 1919e705c121SKalle Valo if (inta & CSR_INT_BIT_SW_ERR) { 1920e705c121SKalle Valo IWL_ERR(trans, "Microcode SW error detected. " 1921e705c121SKalle Valo " Restarting 0x%X.\n", inta); 1922e705c121SKalle Valo isr_stats->sw++; 1923e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1924e705c121SKalle Valo handled |= CSR_INT_BIT_SW_ERR; 1925e705c121SKalle Valo } 1926e705c121SKalle Valo 1927e705c121SKalle Valo /* uCode wakes up after power-down sleep */ 1928e705c121SKalle Valo if (inta & CSR_INT_BIT_WAKEUP) { 1929e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1930e705c121SKalle Valo iwl_pcie_rxq_check_wrptr(trans); 1931e705c121SKalle Valo iwl_pcie_txq_check_wrptrs(trans); 1932e705c121SKalle Valo 1933e705c121SKalle Valo isr_stats->wakeup++; 1934e705c121SKalle Valo 1935e705c121SKalle Valo handled |= CSR_INT_BIT_WAKEUP; 1936e705c121SKalle Valo } 1937e705c121SKalle Valo 1938e705c121SKalle Valo /* All uCode command responses, including Tx command responses, 1939e705c121SKalle Valo * Rx "responses" (frame-received notification), and other 1940e705c121SKalle Valo * notifications from uCode come through here*/ 1941e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1942e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC)) { 1943e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1944e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1945e705c121SKalle Valo handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1946e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 1947e705c121SKalle Valo CSR_FH_INT_RX_MASK); 1948e705c121SKalle Valo } 1949e705c121SKalle Valo if (inta & CSR_INT_BIT_RX_PERIODIC) { 1950e705c121SKalle Valo handled |= CSR_INT_BIT_RX_PERIODIC; 1951e705c121SKalle Valo iwl_write32(trans, 1952e705c121SKalle Valo CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1953e705c121SKalle Valo } 1954e705c121SKalle Valo /* Sending RX interrupt require many steps to be done in the 1955e705c121SKalle Valo * the device: 1956e705c121SKalle Valo * 1- write interrupt to current index in ICT table. 1957e705c121SKalle Valo * 2- dma RX frame. 1958e705c121SKalle Valo * 3- update RX shared data to indicate last write index. 1959e705c121SKalle Valo * 4- send interrupt. 1960e705c121SKalle Valo * This could lead to RX race, driver could receive RX interrupt 1961e705c121SKalle Valo * but the shared data changes does not reflect this; 1962e705c121SKalle Valo * periodic interrupt will detect any dangling Rx activity. 1963e705c121SKalle Valo */ 1964e705c121SKalle Valo 1965e705c121SKalle Valo /* Disable periodic interrupt; we use it as just a one-shot. */ 1966e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1967e705c121SKalle Valo CSR_INT_PERIODIC_DIS); 1968e705c121SKalle Valo 1969e705c121SKalle Valo /* 1970e705c121SKalle Valo * Enable periodic interrupt in 8 msec only if we received 1971e705c121SKalle Valo * real RX interrupt (instead of just periodic int), to catch 1972e705c121SKalle Valo * any dangling Rx interrupt. If it was just the periodic 1973e705c121SKalle Valo * interrupt, there was no dangling Rx activity, and no need 1974e705c121SKalle Valo * to extend the periodic interrupt; one-shot is enough. 1975e705c121SKalle Valo */ 1976e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1977e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1978e705c121SKalle Valo CSR_INT_PERIODIC_ENA); 1979e705c121SKalle Valo 1980e705c121SKalle Valo isr_stats->rx++; 1981e705c121SKalle Valo 1982e705c121SKalle Valo local_bh_disable(); 198325edc8f2SJohannes Berg if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 198425edc8f2SJohannes Berg polling = true; 198525edc8f2SJohannes Berg __napi_schedule(&trans_pcie->rxq[0].napi); 198625edc8f2SJohannes Berg } 1987e705c121SKalle Valo local_bh_enable(); 1988e705c121SKalle Valo } 1989e705c121SKalle Valo 1990e705c121SKalle Valo /* This "Tx" DMA channel is used only for loading uCode */ 1991e705c121SKalle Valo if (inta & CSR_INT_BIT_FH_TX) { 1992e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1993e705c121SKalle Valo IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1994e705c121SKalle Valo isr_stats->tx++; 1995e705c121SKalle Valo handled |= CSR_INT_BIT_FH_TX; 1996e705c121SKalle Valo /* Wake up uCode load routine, now that load is complete */ 1997e705c121SKalle Valo trans_pcie->ucode_write_complete = true; 1998e705c121SKalle Valo wake_up(&trans_pcie->ucode_write_waitq); 1999*c0941aceSMukesh Sisodiya /* Wake up IMR write routine, now that write to SRAM is complete */ 2000*c0941aceSMukesh Sisodiya if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2001*c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_COMPLETED; 2002*c0941aceSMukesh Sisodiya wake_up(&trans_pcie->ucode_write_waitq); 2003*c0941aceSMukesh Sisodiya } 2004e705c121SKalle Valo } 2005e705c121SKalle Valo 2006e705c121SKalle Valo if (inta & ~handled) { 2007e705c121SKalle Valo IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 2008e705c121SKalle Valo isr_stats->unhandled++; 2009e705c121SKalle Valo } 2010e705c121SKalle Valo 2011e705c121SKalle Valo if (inta & ~(trans_pcie->inta_mask)) { 2012e705c121SKalle Valo IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 2013e705c121SKalle Valo inta & ~trans_pcie->inta_mask); 2014e705c121SKalle Valo } 2015e705c121SKalle Valo 201625edc8f2SJohannes Berg if (!polling) { 201725edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 2018a6bd005fSEmmanuel Grumbach /* only Re-enable all interrupt if disabled by irq */ 2019f16c3ebfSEmmanuel Grumbach if (test_bit(STATUS_INT_ENABLED, &trans->status)) 2020f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 2021f16c3ebfSEmmanuel Grumbach /* we are loading the firmware, enable FH_TX interrupt only */ 2022f16c3ebfSEmmanuel Grumbach else if (handled & CSR_INT_BIT_FH_TX) 2023f16c3ebfSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 2024e705c121SKalle Valo /* Re-enable RF_KILL if it occurred */ 2025e705c121SKalle Valo else if (handled & CSR_INT_BIT_RF_KILL) 2026e705c121SKalle Valo iwl_enable_rfkill_int(trans); 2027ed3e4c6dSEmmanuel Grumbach /* Re-enable the ALIVE / Rx interrupt if it occurred */ 2028ed3e4c6dSEmmanuel Grumbach else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX)) 2029ed3e4c6dSEmmanuel Grumbach iwl_enable_fw_load_int_ctx_info(trans); 203025edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 203125edc8f2SJohannes Berg } 2032e705c121SKalle Valo 2033e705c121SKalle Valo out: 2034e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 2035e705c121SKalle Valo return IRQ_HANDLED; 2036e705c121SKalle Valo } 2037e705c121SKalle Valo 2038e705c121SKalle Valo /****************************************************************************** 2039e705c121SKalle Valo * 2040e705c121SKalle Valo * ICT functions 2041e705c121SKalle Valo * 2042e705c121SKalle Valo ******************************************************************************/ 2043e705c121SKalle Valo 2044e705c121SKalle Valo /* Free dram table */ 2045e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans) 2046e705c121SKalle Valo { 2047e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2048e705c121SKalle Valo 2049e705c121SKalle Valo if (trans_pcie->ict_tbl) { 2050e705c121SKalle Valo dma_free_coherent(trans->dev, ICT_SIZE, 2051e705c121SKalle Valo trans_pcie->ict_tbl, 2052e705c121SKalle Valo trans_pcie->ict_tbl_dma); 2053e705c121SKalle Valo trans_pcie->ict_tbl = NULL; 2054e705c121SKalle Valo trans_pcie->ict_tbl_dma = 0; 2055e705c121SKalle Valo } 2056e705c121SKalle Valo } 2057e705c121SKalle Valo 2058e705c121SKalle Valo /* 2059e705c121SKalle Valo * allocate dram shared table, it is an aligned memory 2060e705c121SKalle Valo * block of ICT_SIZE. 2061e705c121SKalle Valo * also reset all data related to ICT table interrupt. 2062e705c121SKalle Valo */ 2063e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans) 2064e705c121SKalle Valo { 2065e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2066e705c121SKalle Valo 2067e705c121SKalle Valo trans_pcie->ict_tbl = 2068750afb08SLuis Chamberlain dma_alloc_coherent(trans->dev, ICT_SIZE, 2069750afb08SLuis Chamberlain &trans_pcie->ict_tbl_dma, GFP_KERNEL); 2070e705c121SKalle Valo if (!trans_pcie->ict_tbl) 2071e705c121SKalle Valo return -ENOMEM; 2072e705c121SKalle Valo 2073e705c121SKalle Valo /* just an API sanity check ... it is guaranteed to be aligned */ 2074e705c121SKalle Valo if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 2075e705c121SKalle Valo iwl_pcie_free_ict(trans); 2076e705c121SKalle Valo return -EINVAL; 2077e705c121SKalle Valo } 2078e705c121SKalle Valo 2079e705c121SKalle Valo return 0; 2080e705c121SKalle Valo } 2081e705c121SKalle Valo 2082e705c121SKalle Valo /* Device is going up inform it about using ICT interrupt table, 2083e705c121SKalle Valo * also we need to tell the driver to start using ICT interrupt. 2084e705c121SKalle Valo */ 2085e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans) 2086e705c121SKalle Valo { 2087e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2088e705c121SKalle Valo u32 val; 2089e705c121SKalle Valo 2090e705c121SKalle Valo if (!trans_pcie->ict_tbl) 2091e705c121SKalle Valo return; 2092e705c121SKalle Valo 209325edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 2094f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 2095e705c121SKalle Valo 2096e705c121SKalle Valo memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 2097e705c121SKalle Valo 2098e705c121SKalle Valo val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 2099e705c121SKalle Valo 2100e705c121SKalle Valo val |= CSR_DRAM_INT_TBL_ENABLE | 2101e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRAP_CHECK | 2102e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRITE_POINTER; 2103e705c121SKalle Valo 2104e705c121SKalle Valo IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 2105e705c121SKalle Valo 2106e705c121SKalle Valo iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 2107e705c121SKalle Valo trans_pcie->use_ict = true; 2108e705c121SKalle Valo trans_pcie->ict_index = 0; 2109e705c121SKalle Valo iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 2110f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 211125edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 2112e705c121SKalle Valo } 2113e705c121SKalle Valo 2114e705c121SKalle Valo /* Device is going down disable ict interrupt usage */ 2115e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans) 2116e705c121SKalle Valo { 2117e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2118e705c121SKalle Valo 211925edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 2120e705c121SKalle Valo trans_pcie->use_ict = false; 212125edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 2122e705c121SKalle Valo } 2123e705c121SKalle Valo 2124e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data) 2125e705c121SKalle Valo { 2126e705c121SKalle Valo struct iwl_trans *trans = data; 2127e705c121SKalle Valo 2128e705c121SKalle Valo if (!trans) 2129e705c121SKalle Valo return IRQ_NONE; 2130e705c121SKalle Valo 2131e705c121SKalle Valo /* Disable (but don't clear!) interrupts here to avoid 2132e705c121SKalle Valo * back-to-back ISRs and sporadic interrupts from our NIC. 2133e705c121SKalle Valo * If we have something to service, the tasklet will re-enable ints. 2134e705c121SKalle Valo * If we *don't* have something, we'll re-enable before leaving here. 2135e705c121SKalle Valo */ 2136e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2137e705c121SKalle Valo 2138e705c121SKalle Valo return IRQ_WAKE_THREAD; 2139e705c121SKalle Valo } 21402e5d4a8fSHaim Dreyfuss 21412e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 21422e5d4a8fSHaim Dreyfuss { 21432e5d4a8fSHaim Dreyfuss return IRQ_WAKE_THREAD; 21442e5d4a8fSHaim Dreyfuss } 21452e5d4a8fSHaim Dreyfuss 21462e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 21472e5d4a8fSHaim Dreyfuss { 21482e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 21492e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 21502e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 215146167a8fSColin Ian King struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2152d4626f91SMordechay Goodstein u32 inta_fh_msk = ~MSIX_FH_INT_CAUSES_DATA_QUEUE; 21532e5d4a8fSHaim Dreyfuss u32 inta_fh, inta_hw; 215425edc8f2SJohannes Berg bool polling = false; 2155571836a0SMike Golant bool sw_err; 21562e5d4a8fSHaim Dreyfuss 2157d4626f91SMordechay Goodstein if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 2158d4626f91SMordechay Goodstein inta_fh_msk |= MSIX_FH_INT_CAUSES_Q0; 2159d4626f91SMordechay Goodstein 2160d4626f91SMordechay Goodstein if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 2161d4626f91SMordechay Goodstein inta_fh_msk |= MSIX_FH_INT_CAUSES_Q1; 2162d4626f91SMordechay Goodstein 21632e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 21642e5d4a8fSHaim Dreyfuss 216525edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 21667ef3dd26SHaim Dreyfuss inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 21677ef3dd26SHaim Dreyfuss inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 21682e5d4a8fSHaim Dreyfuss /* 21692e5d4a8fSHaim Dreyfuss * Clear causes registers to avoid being handling the same cause. 21702e5d4a8fSHaim Dreyfuss */ 2171d4626f91SMordechay Goodstein iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk); 21727ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 217325edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 21742e5d4a8fSHaim Dreyfuss 2175c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2176c42ff65dSJohannes Berg 21772e5d4a8fSHaim Dreyfuss if (unlikely(!(inta_fh | inta_hw))) { 21782e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 21792e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 21802e5d4a8fSHaim Dreyfuss return IRQ_NONE; 21812e5d4a8fSHaim Dreyfuss } 21822e5d4a8fSHaim Dreyfuss 21833b57a10cSEmmanuel Grumbach if (iwl_have_debug_level(IWL_DL_ISR)) { 21843b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 21859d401222SMordechay Goodstein "ISR[%d] inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 21869d401222SMordechay Goodstein entry->entry, inta_fh, trans_pcie->fh_mask, 21872e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 21883b57a10cSEmmanuel Grumbach if (inta_fh & ~trans_pcie->fh_mask) 21893b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 21903b57a10cSEmmanuel Grumbach "We got a masked interrupt (0x%08x)\n", 21913b57a10cSEmmanuel Grumbach inta_fh & ~trans_pcie->fh_mask); 21923b57a10cSEmmanuel Grumbach } 21933b57a10cSEmmanuel Grumbach 21943b57a10cSEmmanuel Grumbach inta_fh &= trans_pcie->fh_mask; 21952e5d4a8fSHaim Dreyfuss 2196496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2197496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2198496d83caSHaim Dreyfuss local_bh_disable(); 219925edc8f2SJohannes Berg if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 220025edc8f2SJohannes Berg polling = true; 220125edc8f2SJohannes Berg __napi_schedule(&trans_pcie->rxq[0].napi); 220225edc8f2SJohannes Berg } 2203496d83caSHaim Dreyfuss local_bh_enable(); 2204496d83caSHaim Dreyfuss } 2205496d83caSHaim Dreyfuss 2206496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2207496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2208496d83caSHaim Dreyfuss local_bh_disable(); 220925edc8f2SJohannes Berg if (napi_schedule_prep(&trans_pcie->rxq[1].napi)) { 221025edc8f2SJohannes Berg polling = true; 221125edc8f2SJohannes Berg __napi_schedule(&trans_pcie->rxq[1].napi); 221225edc8f2SJohannes Berg } 2213496d83caSHaim Dreyfuss local_bh_enable(); 2214496d83caSHaim Dreyfuss } 2215496d83caSHaim Dreyfuss 22162e5d4a8fSHaim Dreyfuss /* This "Tx" DMA channel is used only for loading uCode */ 2217*c0941aceSMukesh Sisodiya if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM && 2218*c0941aceSMukesh Sisodiya trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2219*c0941aceSMukesh Sisodiya IWL_DEBUG_ISR(trans, "IMR Complete interrupt\n"); 2220*c0941aceSMukesh Sisodiya isr_stats->tx++; 2221*c0941aceSMukesh Sisodiya 2222*c0941aceSMukesh Sisodiya /* Wake up IMR routine once write to SRAM is complete */ 2223*c0941aceSMukesh Sisodiya if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2224*c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_COMPLETED; 2225*c0941aceSMukesh Sisodiya wake_up(&trans_pcie->ucode_write_waitq); 2226*c0941aceSMukesh Sisodiya } 2227*c0941aceSMukesh Sisodiya } else if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 22282e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 22292e5d4a8fSHaim Dreyfuss isr_stats->tx++; 22302e5d4a8fSHaim Dreyfuss /* 22312e5d4a8fSHaim Dreyfuss * Wake up uCode load routine, 22322e5d4a8fSHaim Dreyfuss * now that load is complete 22332e5d4a8fSHaim Dreyfuss */ 22342e5d4a8fSHaim Dreyfuss trans_pcie->ucode_write_complete = true; 22352e5d4a8fSHaim Dreyfuss wake_up(&trans_pcie->ucode_write_waitq); 2236*c0941aceSMukesh Sisodiya 2237*c0941aceSMukesh Sisodiya /* Wake up IMR routine once write to SRAM is complete */ 2238*c0941aceSMukesh Sisodiya if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2239*c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_COMPLETED; 2240*c0941aceSMukesh Sisodiya wake_up(&trans_pcie->ucode_write_waitq); 2241*c0941aceSMukesh Sisodiya } 22422e5d4a8fSHaim Dreyfuss } 22432e5d4a8fSHaim Dreyfuss 2244571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2245571836a0SMike Golant sw_err = inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 2246571836a0SMike Golant else 2247571836a0SMike Golant sw_err = inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR; 2248571836a0SMike Golant 22492e5d4a8fSHaim Dreyfuss /* Error detected by uCode */ 2250571836a0SMike Golant if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || sw_err) { 22512e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 22522e5d4a8fSHaim Dreyfuss "Microcode SW error detected. Restarting 0x%X.\n", 22532e5d4a8fSHaim Dreyfuss inta_fh); 22542e5d4a8fSHaim Dreyfuss isr_stats->sw++; 2255e63aafeaSJohannes Berg /* during FW reset flow report errors from there */ 2256*c0941aceSMukesh Sisodiya if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2257*c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_ERROR; 2258*c0941aceSMukesh Sisodiya wake_up(&trans_pcie->imr_waitq); 2259*c0941aceSMukesh Sisodiya } else if (trans_pcie->fw_reset_state == FW_RESET_REQUESTED) { 2260e63aafeaSJohannes Berg trans_pcie->fw_reset_state = FW_RESET_ERROR; 2261e63aafeaSJohannes Berg wake_up(&trans_pcie->fw_reset_waitq); 2262e63aafeaSJohannes Berg } else { 22632e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 22642e5d4a8fSHaim Dreyfuss } 2265e63aafeaSJohannes Berg } 22662e5d4a8fSHaim Dreyfuss 22672e5d4a8fSHaim Dreyfuss /* After checking FH register check HW register */ 22683b57a10cSEmmanuel Grumbach if (iwl_have_debug_level(IWL_DL_ISR)) { 22692e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, 22709d401222SMordechay Goodstein "ISR[%d] inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 22719d401222SMordechay Goodstein entry->entry, inta_hw, trans_pcie->hw_mask, 22722e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 22733b57a10cSEmmanuel Grumbach if (inta_hw & ~trans_pcie->hw_mask) 22743b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 22753b57a10cSEmmanuel Grumbach "We got a masked interrupt 0x%08x\n", 22763b57a10cSEmmanuel Grumbach inta_hw & ~trans_pcie->hw_mask); 22773b57a10cSEmmanuel Grumbach } 22783b57a10cSEmmanuel Grumbach 22793b57a10cSEmmanuel Grumbach inta_hw &= trans_pcie->hw_mask; 22802e5d4a8fSHaim Dreyfuss 22812e5d4a8fSHaim Dreyfuss /* Alive notification via Rx interrupt will do the real work */ 22822e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 22832e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 22842e5d4a8fSHaim Dreyfuss isr_stats->alive++; 2285286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) { 2286eda50cdeSSara Sharon /* We can restock, since firmware configured the RFH */ 2287eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2288eda50cdeSSara Sharon } 22892e5d4a8fSHaim Dreyfuss } 22902e5d4a8fSHaim Dreyfuss 2291459fc0f2SLuca Coelho /* 2292459fc0f2SLuca Coelho * In some rare cases when the HW is in a bad state, we may 2293459fc0f2SLuca Coelho * get this interrupt too early, when prph_info is still NULL. 2294459fc0f2SLuca Coelho * So make sure that it's not NULL to prevent crashing. 2295459fc0f2SLuca Coelho */ 2296459fc0f2SLuca Coelho if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP && trans_pcie->prph_info) { 2297e5f3f215SHaim Dreyfuss u32 sleep_notif = 2298e5f3f215SHaim Dreyfuss le32_to_cpu(trans_pcie->prph_info->sleep_notif); 2299e5f3f215SHaim Dreyfuss if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND || 2300e5f3f215SHaim Dreyfuss sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) { 2301e5f3f215SHaim Dreyfuss IWL_DEBUG_ISR(trans, 2302e5f3f215SHaim Dreyfuss "Sx interrupt: sleep notification = 0x%x\n", 2303e5f3f215SHaim Dreyfuss sleep_notif); 2304e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = true; 2305e5f3f215SHaim Dreyfuss wake_up(&trans_pcie->sx_waitq); 2306e5f3f215SHaim Dreyfuss } else { 23072e5d4a8fSHaim Dreyfuss /* uCode wakes up after power-down sleep */ 23082e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 23092e5d4a8fSHaim Dreyfuss iwl_pcie_rxq_check_wrptr(trans); 23102e5d4a8fSHaim Dreyfuss iwl_pcie_txq_check_wrptrs(trans); 23112e5d4a8fSHaim Dreyfuss 23122e5d4a8fSHaim Dreyfuss isr_stats->wakeup++; 23132e5d4a8fSHaim Dreyfuss } 2314e5f3f215SHaim Dreyfuss } 23152e5d4a8fSHaim Dreyfuss 23162e5d4a8fSHaim Dreyfuss /* Chip got too hot and stopped itself */ 23172e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 23182e5d4a8fSHaim Dreyfuss IWL_ERR(trans, "Microcode CT kill error detected.\n"); 23192e5d4a8fSHaim Dreyfuss isr_stats->ctkill++; 23202e5d4a8fSHaim Dreyfuss } 23212e5d4a8fSHaim Dreyfuss 23222e5d4a8fSHaim Dreyfuss /* HW RF KILL switch toggled */ 23233a6e168bSJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 23243a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 23252e5d4a8fSHaim Dreyfuss 23262e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 23272e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 23282e5d4a8fSHaim Dreyfuss "Hardware error detected. Restarting.\n"); 23292e5d4a8fSHaim Dreyfuss 23302e5d4a8fSHaim Dreyfuss isr_stats->hw++; 233191c28b83SShahar S Matityahu trans->dbg.hw_error = true; 23322e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 23332e5d4a8fSHaim Dreyfuss } 23342e5d4a8fSHaim Dreyfuss 2335906d4eb8SJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE) { 2336906d4eb8SJohannes Berg IWL_DEBUG_ISR(trans, "Reset flow completed\n"); 2337e63aafeaSJohannes Berg trans_pcie->fw_reset_state = FW_RESET_OK; 2338906d4eb8SJohannes Berg wake_up(&trans_pcie->fw_reset_waitq); 2339906d4eb8SJohannes Berg } 2340906d4eb8SJohannes Berg 234125edc8f2SJohannes Berg if (!polling) 234225edc8f2SJohannes Berg iwl_pcie_clear_irq(trans, entry->entry); 23432e5d4a8fSHaim Dreyfuss 23442e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 23452e5d4a8fSHaim Dreyfuss 23462e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 23472e5d4a8fSHaim Dreyfuss } 2348