1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3cefec29eSJohannes Berg * This file is provided under a dual BSD/GPLv2 license. When using or 4cefec29eSJohannes Berg * redistributing this file, you may do so under either license. 5cefec29eSJohannes Berg * 6cefec29eSJohannes Berg * GPL LICENSE SUMMARY 7cefec29eSJohannes Berg * 8e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 14e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 18e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20e705c121SKalle Valo * more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 23cefec29eSJohannes Berg * file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26d01c5366SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29cefec29eSJohannes Berg * BSD LICENSE 30cefec29eSJohannes Berg * 31cefec29eSJohannes Berg * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 32cefec29eSJohannes Berg * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33cefec29eSJohannes Berg * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 35cefec29eSJohannes Berg * All rights reserved. 36cefec29eSJohannes Berg * 37cefec29eSJohannes Berg * Redistribution and use in source and binary forms, with or without 38cefec29eSJohannes Berg * modification, are permitted provided that the following conditions 39cefec29eSJohannes Berg * are met: 40cefec29eSJohannes Berg * 41cefec29eSJohannes Berg * * Redistributions of source code must retain the above copyright 42cefec29eSJohannes Berg * notice, this list of conditions and the following disclaimer. 43cefec29eSJohannes Berg * * Redistributions in binary form must reproduce the above copyright 44cefec29eSJohannes Berg * notice, this list of conditions and the following disclaimer in 45cefec29eSJohannes Berg * the documentation and/or other materials provided with the 46cefec29eSJohannes Berg * distribution. 47cefec29eSJohannes Berg * * Neither the name Intel Corporation nor the names of its 48cefec29eSJohannes Berg * contributors may be used to endorse or promote products derived 49cefec29eSJohannes Berg * from this software without specific prior written permission. 50cefec29eSJohannes Berg * 51cefec29eSJohannes Berg * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52cefec29eSJohannes Berg * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53cefec29eSJohannes Berg * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54cefec29eSJohannes Berg * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55cefec29eSJohannes Berg * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56cefec29eSJohannes Berg * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57cefec29eSJohannes Berg * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58cefec29eSJohannes Berg * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59cefec29eSJohannes Berg * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60cefec29eSJohannes Berg * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61cefec29eSJohannes Berg * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62cefec29eSJohannes Berg * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #include <linux/sched.h> 65e705c121SKalle Valo #include <linux/wait.h> 66e705c121SKalle Valo #include <linux/gfp.h> 67e705c121SKalle Valo 68e705c121SKalle Valo #include "iwl-prph.h" 69e705c121SKalle Valo #include "iwl-io.h" 70e705c121SKalle Valo #include "internal.h" 71e705c121SKalle Valo #include "iwl-op-mode.h" 729b58419eSGolan Ben Ami #include "iwl-context-info-gen3.h" 73e705c121SKalle Valo 74e705c121SKalle Valo /****************************************************************************** 75e705c121SKalle Valo * 76e705c121SKalle Valo * RX path functions 77e705c121SKalle Valo * 78e705c121SKalle Valo ******************************************************************************/ 79e705c121SKalle Valo 80e705c121SKalle Valo /* 81e705c121SKalle Valo * Rx theory of operation 82e705c121SKalle Valo * 83e705c121SKalle Valo * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 84e705c121SKalle Valo * each of which point to Receive Buffers to be filled by the NIC. These get 85e705c121SKalle Valo * used not only for Rx frames, but for any command response or notification 86e705c121SKalle Valo * from the NIC. The driver and NIC manage the Rx buffers by means 87e705c121SKalle Valo * of indexes into the circular buffer. 88e705c121SKalle Valo * 89e705c121SKalle Valo * Rx Queue Indexes 90e705c121SKalle Valo * The host/firmware share two index registers for managing the Rx buffers. 91e705c121SKalle Valo * 92e705c121SKalle Valo * The READ index maps to the first position that the firmware may be writing 93e705c121SKalle Valo * to -- the driver can read up to (but not including) this position and get 94e705c121SKalle Valo * good data. 95e705c121SKalle Valo * The READ index is managed by the firmware once the card is enabled. 96e705c121SKalle Valo * 97e705c121SKalle Valo * The WRITE index maps to the last position the driver has read from -- the 98e705c121SKalle Valo * position preceding WRITE is the last slot the firmware can place a packet. 99e705c121SKalle Valo * 100e705c121SKalle Valo * The queue is empty (no good data) if WRITE = READ - 1, and is full if 101e705c121SKalle Valo * WRITE = READ. 102e705c121SKalle Valo * 103e705c121SKalle Valo * During initialization, the host sets up the READ queue position to the first 104e705c121SKalle Valo * INDEX position, and WRITE to the last (READ - 1 wrapped) 105e705c121SKalle Valo * 106e705c121SKalle Valo * When the firmware places a packet in a buffer, it will advance the READ index 107e705c121SKalle Valo * and fire the RX interrupt. The driver can then query the READ index and 108e705c121SKalle Valo * process as many packets as possible, moving the WRITE index forward as it 109e705c121SKalle Valo * resets the Rx queue buffers with new memory. 110e705c121SKalle Valo * 111e705c121SKalle Valo * The management in the driver is as follows: 112e705c121SKalle Valo * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 113e705c121SKalle Valo * When the interrupt handler is called, the request is processed. 114e705c121SKalle Valo * The page is either stolen - transferred to the upper layer 115e705c121SKalle Valo * or reused - added immediately to the iwl->rxq->rx_free list. 116e705c121SKalle Valo * + When the page is stolen - the driver updates the matching queue's used 117e705c121SKalle Valo * count, detaches the RBD and transfers it to the queue used list. 118e705c121SKalle Valo * When there are two used RBDs - they are transferred to the allocator empty 119e705c121SKalle Valo * list. Work is then scheduled for the allocator to start allocating 120e705c121SKalle Valo * eight buffers. 121e705c121SKalle Valo * When there are another 6 used RBDs - they are transferred to the allocator 122e705c121SKalle Valo * empty list and the driver tries to claim the pre-allocated buffers and 123e705c121SKalle Valo * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 124e705c121SKalle Valo * until ready. 125e705c121SKalle Valo * When there are 8+ buffers in the free list - either from allocation or from 126e705c121SKalle Valo * 8 reused unstolen pages - restock is called to update the FW and indexes. 127e705c121SKalle Valo * + In order to make sure the allocator always has RBDs to use for allocation 128e705c121SKalle Valo * the allocator has initial pool in the size of num_queues*(8-2) - the 129e705c121SKalle Valo * maximum missing RBDs per allocation request (request posted with 2 130e705c121SKalle Valo * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 131e705c121SKalle Valo * The queues supplies the recycle of the rest of the RBDs. 132e705c121SKalle Valo * + A received packet is processed and handed to the kernel network stack, 133e705c121SKalle Valo * detached from the iwl->rxq. The driver 'processed' index is updated. 134e705c121SKalle Valo * + If there are no allocated buffers in iwl->rxq->rx_free, 135e705c121SKalle Valo * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 136e705c121SKalle Valo * If there were enough free buffers and RX_STALLED is set it is cleared. 137e705c121SKalle Valo * 138e705c121SKalle Valo * 139e705c121SKalle Valo * Driver sequence: 140e705c121SKalle Valo * 141e705c121SKalle Valo * iwl_rxq_alloc() Allocates rx_free 142e705c121SKalle Valo * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 143e705c121SKalle Valo * iwl_pcie_rxq_restock. 144e705c121SKalle Valo * Used only during initialization. 145e705c121SKalle Valo * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 146e705c121SKalle Valo * queue, updates firmware pointers, and updates 147e705c121SKalle Valo * the WRITE index. 148e705c121SKalle Valo * iwl_pcie_rx_allocator() Background work for allocating pages. 149e705c121SKalle Valo * 150e705c121SKalle Valo * -- enable interrupts -- 151e705c121SKalle Valo * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 152e705c121SKalle Valo * READ INDEX, detaching the SKB from the pool. 153e705c121SKalle Valo * Moves the packet buffer from queue to rx_used. 154e705c121SKalle Valo * Posts and claims requests to the allocator. 155e705c121SKalle Valo * Calls iwl_pcie_rxq_restock to refill any empty 156e705c121SKalle Valo * slots. 157e705c121SKalle Valo * 158e705c121SKalle Valo * RBD life-cycle: 159e705c121SKalle Valo * 160e705c121SKalle Valo * Init: 161e705c121SKalle Valo * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 162e705c121SKalle Valo * 163e705c121SKalle Valo * Regular Receive interrupt: 164e705c121SKalle Valo * Page Stolen: 165e705c121SKalle Valo * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 166e705c121SKalle Valo * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 167e705c121SKalle Valo * Page not Stolen: 168e705c121SKalle Valo * rxq.queue -> rxq.rx_free -> rxq.queue 169e705c121SKalle Valo * ... 170e705c121SKalle Valo * 171e705c121SKalle Valo */ 172e705c121SKalle Valo 173e705c121SKalle Valo /* 174e705c121SKalle Valo * iwl_rxq_space - Return number of free slots available in queue. 175e705c121SKalle Valo */ 176e705c121SKalle Valo static int iwl_rxq_space(const struct iwl_rxq *rxq) 177e705c121SKalle Valo { 17896a6497bSSara Sharon /* Make sure rx queue size is a power of 2 */ 17996a6497bSSara Sharon WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 180e705c121SKalle Valo 181e705c121SKalle Valo /* 182e705c121SKalle Valo * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 183e705c121SKalle Valo * between empty and completely full queues. 184e705c121SKalle Valo * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 185e705c121SKalle Valo * defined for negative dividends. 186e705c121SKalle Valo */ 18796a6497bSSara Sharon return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 188e705c121SKalle Valo } 189e705c121SKalle Valo 190e705c121SKalle Valo /* 191e705c121SKalle Valo * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 192e705c121SKalle Valo */ 193e705c121SKalle Valo static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 194e705c121SKalle Valo { 195e705c121SKalle Valo return cpu_to_le32((u32)(dma_addr >> 8)); 196e705c121SKalle Valo } 197e705c121SKalle Valo 198e705c121SKalle Valo /* 199e705c121SKalle Valo * iwl_pcie_rx_stop - stops the Rx DMA 200e705c121SKalle Valo */ 201e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans) 202e705c121SKalle Valo { 2033681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 2043681021fSJohannes Berg /* TODO: remove this once fw does it */ 205ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 206ea695b7cSShaul Triebitz return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3, 207d0158235SGolan Ben Ami RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 208286ca8ebSLuca Coelho } else if (trans->trans_cfg->mq_rx_supported) { 209d7fdd0e5SSara Sharon iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 210d7fdd0e5SSara Sharon return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 211d7fdd0e5SSara Sharon RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 212d7fdd0e5SSara Sharon } else { 213e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 214e705c121SKalle Valo return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 215d7fdd0e5SSara Sharon FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 216d7fdd0e5SSara Sharon 1000); 217d7fdd0e5SSara Sharon } 218e705c121SKalle Valo } 219e705c121SKalle Valo 220e705c121SKalle Valo /* 221e705c121SKalle Valo * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 222e705c121SKalle Valo */ 22378485054SSara Sharon static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 22478485054SSara Sharon struct iwl_rxq *rxq) 225e705c121SKalle Valo { 226e705c121SKalle Valo u32 reg; 227e705c121SKalle Valo 228e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 229e705c121SKalle Valo 230e705c121SKalle Valo /* 231e705c121SKalle Valo * explicitly wake up the NIC if: 232e705c121SKalle Valo * 1. shadow registers aren't enabled 233e705c121SKalle Valo * 2. there is a chance that the NIC is asleep 234e705c121SKalle Valo */ 235286ca8ebSLuca Coelho if (!trans->trans_cfg->base_params->shadow_reg_enable && 236e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 237e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 238e705c121SKalle Valo 239e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 240e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 241e705c121SKalle Valo reg); 242e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 2436dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 244e705c121SKalle Valo rxq->need_update = true; 245e705c121SKalle Valo return; 246e705c121SKalle Valo } 247e705c121SKalle Valo } 248e705c121SKalle Valo 249e705c121SKalle Valo rxq->write_actual = round_down(rxq->write, 8); 2503681021fSJohannes Berg if (trans->trans_cfg->mq_rx_supported) 2511554ed20SSara Sharon iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 25296a6497bSSara Sharon rxq->write_actual); 2531316d595SSara Sharon else 254e705c121SKalle Valo iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 255e705c121SKalle Valo } 256e705c121SKalle Valo 257e705c121SKalle Valo static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 258e705c121SKalle Valo { 259e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 26078485054SSara Sharon int i; 261e705c121SKalle Valo 26278485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 26378485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 264e705c121SKalle Valo 265e705c121SKalle Valo if (!rxq->need_update) 26678485054SSara Sharon continue; 26778485054SSara Sharon spin_lock(&rxq->lock); 26878485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 269e705c121SKalle Valo rxq->need_update = false; 270e705c121SKalle Valo spin_unlock(&rxq->lock); 271e705c121SKalle Valo } 27278485054SSara Sharon } 273e705c121SKalle Valo 2740307c839SGolan Ben Ami static void iwl_pcie_restock_bd(struct iwl_trans *trans, 2750307c839SGolan Ben Ami struct iwl_rxq *rxq, 2760307c839SGolan Ben Ami struct iwl_rx_mem_buffer *rxb) 2770307c839SGolan Ben Ami { 2783681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 2790307c839SGolan Ben Ami struct iwl_rx_transfer_desc *bd = rxq->bd; 2800307c839SGolan Ben Ami 281f826faaaSJohannes Berg BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64)); 282f826faaaSJohannes Berg 2830307c839SGolan Ben Ami bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 2840307c839SGolan Ben Ami bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 2850307c839SGolan Ben Ami } else { 2860307c839SGolan Ben Ami __le64 *bd = rxq->bd; 2870307c839SGolan Ben Ami 2880307c839SGolan Ben Ami bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 2890307c839SGolan Ben Ami } 29085d78bb1SSara Sharon 29185d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n", 29285d78bb1SSara Sharon (u32)rxb->vid, rxq->id, rxq->write); 2930307c839SGolan Ben Ami } 2940307c839SGolan Ben Ami 295e0e168dcSGregory Greenman /* 2962047fa54SSara Sharon * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 297e0e168dcSGregory Greenman */ 2982047fa54SSara Sharon static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 29996a6497bSSara Sharon struct iwl_rxq *rxq) 30096a6497bSSara Sharon { 301cfdc20efSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 30296a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb; 30396a6497bSSara Sharon 30496a6497bSSara Sharon /* 30596a6497bSSara Sharon * If the device isn't enabled - no need to try to add buffers... 30696a6497bSSara Sharon * This can happen when we stop the device and still have an interrupt 30796a6497bSSara Sharon * pending. We stop the APM before we sync the interrupts because we 30896a6497bSSara Sharon * have to (see comment there). On the other hand, since the APM is 30996a6497bSSara Sharon * stopped, we cannot access the HW (in particular not prph). 31096a6497bSSara Sharon * So don't try to restock if the APM has been already stopped. 31196a6497bSSara Sharon */ 31296a6497bSSara Sharon if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 31396a6497bSSara Sharon return; 31496a6497bSSara Sharon 31596a6497bSSara Sharon spin_lock(&rxq->lock); 31696a6497bSSara Sharon while (rxq->free_count) { 31796a6497bSSara Sharon /* Get next free Rx buffer, remove from free list */ 31896a6497bSSara Sharon rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 31996a6497bSSara Sharon list); 32096a6497bSSara Sharon list_del(&rxb->list); 321b1753c62SSara Sharon rxb->invalid = false; 322cfdc20efSJohannes Berg /* some low bits are expected to be unset (depending on hw) */ 323cfdc20efSJohannes Berg WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask); 32496a6497bSSara Sharon /* Point to Rx buffer via next RBD in circular buffer */ 3250307c839SGolan Ben Ami iwl_pcie_restock_bd(trans, rxq, rxb); 3265661925aSJohannes Berg rxq->write = (rxq->write + 1) & (rxq->queue_size - 1); 32796a6497bSSara Sharon rxq->free_count--; 32896a6497bSSara Sharon } 32996a6497bSSara Sharon spin_unlock(&rxq->lock); 33096a6497bSSara Sharon 33196a6497bSSara Sharon /* 33296a6497bSSara Sharon * If we've added more space for the firmware to place data, tell it. 33396a6497bSSara Sharon * Increment device's write pointer in multiples of 8. 33496a6497bSSara Sharon */ 33596a6497bSSara Sharon if (rxq->write_actual != (rxq->write & ~0x7)) { 33696a6497bSSara Sharon spin_lock(&rxq->lock); 33796a6497bSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 33896a6497bSSara Sharon spin_unlock(&rxq->lock); 33996a6497bSSara Sharon } 34096a6497bSSara Sharon } 34196a6497bSSara Sharon 342e705c121SKalle Valo /* 3432047fa54SSara Sharon * iwl_pcie_rxsq_restock - restock implementation for single queue rx 344e705c121SKalle Valo */ 3452047fa54SSara Sharon static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 346e0e168dcSGregory Greenman struct iwl_rxq *rxq) 347e705c121SKalle Valo { 348e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 349e705c121SKalle Valo 350e705c121SKalle Valo /* 351e705c121SKalle Valo * If the device isn't enabled - not need to try to add buffers... 352e705c121SKalle Valo * This can happen when we stop the device and still have an interrupt 353e705c121SKalle Valo * pending. We stop the APM before we sync the interrupts because we 354e705c121SKalle Valo * have to (see comment there). On the other hand, since the APM is 355e705c121SKalle Valo * stopped, we cannot access the HW (in particular not prph). 356e705c121SKalle Valo * So don't try to restock if the APM has been already stopped. 357e705c121SKalle Valo */ 358e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 359e705c121SKalle Valo return; 360e705c121SKalle Valo 361e705c121SKalle Valo spin_lock(&rxq->lock); 362e705c121SKalle Valo while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 36396a6497bSSara Sharon __le32 *bd = (__le32 *)rxq->bd; 364e705c121SKalle Valo /* The overwritten rxb must be a used one */ 365e705c121SKalle Valo rxb = rxq->queue[rxq->write]; 366e705c121SKalle Valo BUG_ON(rxb && rxb->page); 367e705c121SKalle Valo 368e705c121SKalle Valo /* Get next free Rx buffer, remove from free list */ 369e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 370e705c121SKalle Valo list); 371e705c121SKalle Valo list_del(&rxb->list); 372b1753c62SSara Sharon rxb->invalid = false; 373e705c121SKalle Valo 374e705c121SKalle Valo /* Point to Rx buffer via next RBD in circular buffer */ 37596a6497bSSara Sharon bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 376e705c121SKalle Valo rxq->queue[rxq->write] = rxb; 377e705c121SKalle Valo rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 378e705c121SKalle Valo rxq->free_count--; 379e705c121SKalle Valo } 380e705c121SKalle Valo spin_unlock(&rxq->lock); 381e705c121SKalle Valo 382e705c121SKalle Valo /* If we've added more space for the firmware to place data, tell it. 383e705c121SKalle Valo * Increment device's write pointer in multiples of 8. */ 384e705c121SKalle Valo if (rxq->write_actual != (rxq->write & ~0x7)) { 385e705c121SKalle Valo spin_lock(&rxq->lock); 38678485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 387e705c121SKalle Valo spin_unlock(&rxq->lock); 388e705c121SKalle Valo } 389e705c121SKalle Valo } 390e705c121SKalle Valo 391e705c121SKalle Valo /* 392e0e168dcSGregory Greenman * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 393e0e168dcSGregory Greenman * 394e0e168dcSGregory Greenman * If there are slots in the RX queue that need to be restocked, 395e0e168dcSGregory Greenman * and we have free pre-allocated buffers, fill the ranks as much 396e0e168dcSGregory Greenman * as we can, pulling from rx_free. 397e0e168dcSGregory Greenman * 398e0e168dcSGregory Greenman * This moves the 'write' index forward to catch up with 'processed', and 399e0e168dcSGregory Greenman * also updates the memory address in the firmware to reference the new 400e0e168dcSGregory Greenman * target buffer. 401e0e168dcSGregory Greenman */ 402e0e168dcSGregory Greenman static 403e0e168dcSGregory Greenman void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 404e0e168dcSGregory Greenman { 405286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 4062047fa54SSara Sharon iwl_pcie_rxmq_restock(trans, rxq); 407e0e168dcSGregory Greenman else 4082047fa54SSara Sharon iwl_pcie_rxsq_restock(trans, rxq); 409e0e168dcSGregory Greenman } 410e0e168dcSGregory Greenman 411e0e168dcSGregory Greenman /* 412e705c121SKalle Valo * iwl_pcie_rx_alloc_page - allocates and returns a page. 413e705c121SKalle Valo * 414e705c121SKalle Valo */ 415e705c121SKalle Valo static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 416cfdc20efSJohannes Berg u32 *offset, gfp_t priority) 417e705c121SKalle Valo { 418e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 419cfdc20efSJohannes Berg unsigned int rbsize = iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 420cfdc20efSJohannes Berg unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order; 421e705c121SKalle Valo struct page *page; 422e705c121SKalle Valo gfp_t gfp_mask = priority; 423e705c121SKalle Valo 424e705c121SKalle Valo if (trans_pcie->rx_page_order > 0) 425e705c121SKalle Valo gfp_mask |= __GFP_COMP; 426e705c121SKalle Valo 427cfdc20efSJohannes Berg if (trans_pcie->alloc_page) { 428cfdc20efSJohannes Berg spin_lock_bh(&trans_pcie->alloc_page_lock); 429cfdc20efSJohannes Berg /* recheck */ 430cfdc20efSJohannes Berg if (trans_pcie->alloc_page) { 431cfdc20efSJohannes Berg *offset = trans_pcie->alloc_page_used; 432cfdc20efSJohannes Berg page = trans_pcie->alloc_page; 433cfdc20efSJohannes Berg trans_pcie->alloc_page_used += rbsize; 434cfdc20efSJohannes Berg if (trans_pcie->alloc_page_used >= allocsize) 435cfdc20efSJohannes Berg trans_pcie->alloc_page = NULL; 436cfdc20efSJohannes Berg else 437cfdc20efSJohannes Berg get_page(page); 438cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 439cfdc20efSJohannes Berg return page; 440cfdc20efSJohannes Berg } 441cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 442cfdc20efSJohannes Berg } 443cfdc20efSJohannes Berg 444e705c121SKalle Valo /* Alloc a new receive buffer */ 445e705c121SKalle Valo page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 446e705c121SKalle Valo if (!page) { 447e705c121SKalle Valo if (net_ratelimit()) 448e705c121SKalle Valo IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 449e705c121SKalle Valo trans_pcie->rx_page_order); 45078485054SSara Sharon /* 45178485054SSara Sharon * Issue an error if we don't have enough pre-allocated 45278485054SSara Sharon * buffers. 4531da3823dSLuca Coelho */ 45478485054SSara Sharon if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 455e705c121SKalle Valo IWL_CRIT(trans, 45678485054SSara Sharon "Failed to alloc_pages\n"); 457e705c121SKalle Valo return NULL; 458e705c121SKalle Valo } 459cfdc20efSJohannes Berg 460cfdc20efSJohannes Berg if (2 * rbsize <= allocsize) { 461cfdc20efSJohannes Berg spin_lock_bh(&trans_pcie->alloc_page_lock); 462cfdc20efSJohannes Berg if (!trans_pcie->alloc_page) { 463cfdc20efSJohannes Berg get_page(page); 464cfdc20efSJohannes Berg trans_pcie->alloc_page = page; 465cfdc20efSJohannes Berg trans_pcie->alloc_page_used = rbsize; 466cfdc20efSJohannes Berg } 467cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 468cfdc20efSJohannes Berg } 469cfdc20efSJohannes Berg 470cfdc20efSJohannes Berg *offset = 0; 471e705c121SKalle Valo return page; 472e705c121SKalle Valo } 473e705c121SKalle Valo 474e705c121SKalle Valo /* 475e705c121SKalle Valo * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 476e705c121SKalle Valo * 477e705c121SKalle Valo * A used RBD is an Rx buffer that has been given to the stack. To use it again 478e705c121SKalle Valo * a page must be allocated and the RBD must point to the page. This function 479e705c121SKalle Valo * doesn't change the HW pointer but handles the list of pages that is used by 480e705c121SKalle Valo * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 481e705c121SKalle Valo * allocated buffers. 482e705c121SKalle Valo */ 483ff932f61SGolan Ben Ami void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 48478485054SSara Sharon struct iwl_rxq *rxq) 485e705c121SKalle Valo { 486e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 487e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 488e705c121SKalle Valo struct page *page; 489e705c121SKalle Valo 490e705c121SKalle Valo while (1) { 491cfdc20efSJohannes Berg unsigned int offset; 492cfdc20efSJohannes Berg 493e705c121SKalle Valo spin_lock(&rxq->lock); 494e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 495e705c121SKalle Valo spin_unlock(&rxq->lock); 496e705c121SKalle Valo return; 497e705c121SKalle Valo } 498e705c121SKalle Valo spin_unlock(&rxq->lock); 499e705c121SKalle Valo 500cfdc20efSJohannes Berg page = iwl_pcie_rx_alloc_page(trans, &offset, priority); 501e705c121SKalle Valo if (!page) 502e705c121SKalle Valo return; 503e705c121SKalle Valo 504e705c121SKalle Valo spin_lock(&rxq->lock); 505e705c121SKalle Valo 506e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 507e705c121SKalle Valo spin_unlock(&rxq->lock); 508e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 509e705c121SKalle Valo return; 510e705c121SKalle Valo } 511e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 512e705c121SKalle Valo list); 513e705c121SKalle Valo list_del(&rxb->list); 514e705c121SKalle Valo spin_unlock(&rxq->lock); 515e705c121SKalle Valo 516e705c121SKalle Valo BUG_ON(rxb->page); 517e705c121SKalle Valo rxb->page = page; 518cfdc20efSJohannes Berg rxb->offset = offset; 519e705c121SKalle Valo /* Get physical address of the RB */ 520e705c121SKalle Valo rxb->page_dma = 521cfdc20efSJohannes Berg dma_map_page(trans->dev, page, rxb->offset, 52280084e35SJohannes Berg trans_pcie->rx_buf_bytes, 523e705c121SKalle Valo DMA_FROM_DEVICE); 524e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 525e705c121SKalle Valo rxb->page = NULL; 526e705c121SKalle Valo spin_lock(&rxq->lock); 527e705c121SKalle Valo list_add(&rxb->list, &rxq->rx_used); 528e705c121SKalle Valo spin_unlock(&rxq->lock); 529e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 530e705c121SKalle Valo return; 531e705c121SKalle Valo } 532e705c121SKalle Valo 533e705c121SKalle Valo spin_lock(&rxq->lock); 534e705c121SKalle Valo 535e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 536e705c121SKalle Valo rxq->free_count++; 537e705c121SKalle Valo 538e705c121SKalle Valo spin_unlock(&rxq->lock); 539e705c121SKalle Valo } 540e705c121SKalle Valo } 541e705c121SKalle Valo 542ff932f61SGolan Ben Ami void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 543e705c121SKalle Valo { 544e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 545e705c121SKalle Valo int i; 546e705c121SKalle Valo 547c042f0c7SJohannes Berg for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) { 54878485054SSara Sharon if (!trans_pcie->rx_pool[i].page) 549e705c121SKalle Valo continue; 55078485054SSara Sharon dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 55180084e35SJohannes Berg trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE); 55278485054SSara Sharon __free_pages(trans_pcie->rx_pool[i].page, 55378485054SSara Sharon trans_pcie->rx_page_order); 55478485054SSara Sharon trans_pcie->rx_pool[i].page = NULL; 555e705c121SKalle Valo } 556e705c121SKalle Valo } 557e705c121SKalle Valo 558e705c121SKalle Valo /* 559e705c121SKalle Valo * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 560e705c121SKalle Valo * 561e705c121SKalle Valo * Allocates for each received request 8 pages 562e705c121SKalle Valo * Called as a scheduled work item. 563e705c121SKalle Valo */ 564e705c121SKalle Valo static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 565e705c121SKalle Valo { 566e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 567e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 568e705c121SKalle Valo struct list_head local_empty; 569c6ac9f9fSSara Sharon int pending = atomic_read(&rba->req_pending); 570e705c121SKalle Valo 5716dcdd165SSara Sharon IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending); 572e705c121SKalle Valo 573e705c121SKalle Valo /* If we were scheduled - there is at least one request */ 574e705c121SKalle Valo spin_lock(&rba->lock); 575e705c121SKalle Valo /* swap out the rba->rbd_empty to a local list */ 576e705c121SKalle Valo list_replace_init(&rba->rbd_empty, &local_empty); 577e705c121SKalle Valo spin_unlock(&rba->lock); 578e705c121SKalle Valo 579e705c121SKalle Valo while (pending) { 580e705c121SKalle Valo int i; 5810979a913SJohannes Berg LIST_HEAD(local_allocated); 58278485054SSara Sharon gfp_t gfp_mask = GFP_KERNEL; 58378485054SSara Sharon 58478485054SSara Sharon /* Do not post a warning if there are only a few requests */ 58578485054SSara Sharon if (pending < RX_PENDING_WATERMARK) 58678485054SSara Sharon gfp_mask |= __GFP_NOWARN; 587e705c121SKalle Valo 588e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 589e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 590e705c121SKalle Valo struct page *page; 591e705c121SKalle Valo 592e705c121SKalle Valo /* List should never be empty - each reused RBD is 593e705c121SKalle Valo * returned to the list, and initial pool covers any 594e705c121SKalle Valo * possible gap between the time the page is allocated 595e705c121SKalle Valo * to the time the RBD is added. 596e705c121SKalle Valo */ 597e705c121SKalle Valo BUG_ON(list_empty(&local_empty)); 598e705c121SKalle Valo /* Get the first rxb from the rbd list */ 599e705c121SKalle Valo rxb = list_first_entry(&local_empty, 600e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 601e705c121SKalle Valo BUG_ON(rxb->page); 602e705c121SKalle Valo 603e705c121SKalle Valo /* Alloc a new receive buffer */ 604cfdc20efSJohannes Berg page = iwl_pcie_rx_alloc_page(trans, &rxb->offset, 605cfdc20efSJohannes Berg gfp_mask); 606e705c121SKalle Valo if (!page) 607e705c121SKalle Valo continue; 608e705c121SKalle Valo rxb->page = page; 609e705c121SKalle Valo 610e705c121SKalle Valo /* Get physical address of the RB */ 611cfdc20efSJohannes Berg rxb->page_dma = dma_map_page(trans->dev, page, 612cfdc20efSJohannes Berg rxb->offset, 61380084e35SJohannes Berg trans_pcie->rx_buf_bytes, 614e705c121SKalle Valo DMA_FROM_DEVICE); 615e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 616e705c121SKalle Valo rxb->page = NULL; 617e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 618e705c121SKalle Valo continue; 619e705c121SKalle Valo } 620e705c121SKalle Valo 621e705c121SKalle Valo /* move the allocated entry to the out list */ 622e705c121SKalle Valo list_move(&rxb->list, &local_allocated); 623e705c121SKalle Valo i++; 624e705c121SKalle Valo } 625e705c121SKalle Valo 626c6ac9f9fSSara Sharon atomic_dec(&rba->req_pending); 627e705c121SKalle Valo pending--; 628c6ac9f9fSSara Sharon 629e705c121SKalle Valo if (!pending) { 630c6ac9f9fSSara Sharon pending = atomic_read(&rba->req_pending); 6316dcdd165SSara Sharon if (pending) 6326dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 633c6ac9f9fSSara Sharon "Got more pending allocation requests = %d\n", 634e705c121SKalle Valo pending); 635e705c121SKalle Valo } 636e705c121SKalle Valo 637e705c121SKalle Valo spin_lock(&rba->lock); 638e705c121SKalle Valo /* add the allocated rbds to the allocator allocated list */ 639e705c121SKalle Valo list_splice_tail(&local_allocated, &rba->rbd_allocated); 640e705c121SKalle Valo /* get more empty RBDs for current pending requests */ 641e705c121SKalle Valo list_splice_tail_init(&rba->rbd_empty, &local_empty); 642e705c121SKalle Valo spin_unlock(&rba->lock); 643e705c121SKalle Valo 644e705c121SKalle Valo atomic_inc(&rba->req_ready); 645c6ac9f9fSSara Sharon 646e705c121SKalle Valo } 647e705c121SKalle Valo 648e705c121SKalle Valo spin_lock(&rba->lock); 649e705c121SKalle Valo /* return unused rbds to the allocator empty list */ 650e705c121SKalle Valo list_splice_tail(&local_empty, &rba->rbd_empty); 651e705c121SKalle Valo spin_unlock(&rba->lock); 652c6ac9f9fSSara Sharon 6536dcdd165SSara Sharon IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__); 654e705c121SKalle Valo } 655e705c121SKalle Valo 656e705c121SKalle Valo /* 657d56daea4SSara Sharon * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 658e705c121SKalle Valo .* 659e705c121SKalle Valo .* Called by queue when the queue posted allocation request and 660e705c121SKalle Valo * has freed 8 RBDs in order to restock itself. 661d56daea4SSara Sharon * This function directly moves the allocated RBs to the queue's ownership 662d56daea4SSara Sharon * and updates the relevant counters. 663e705c121SKalle Valo */ 664d56daea4SSara Sharon static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 665d56daea4SSara Sharon struct iwl_rxq *rxq) 666e705c121SKalle Valo { 667e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 668e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 669e705c121SKalle Valo int i; 670e705c121SKalle Valo 671d56daea4SSara Sharon lockdep_assert_held(&rxq->lock); 672d56daea4SSara Sharon 673e705c121SKalle Valo /* 674e705c121SKalle Valo * atomic_dec_if_positive returns req_ready - 1 for any scenario. 675e705c121SKalle Valo * If req_ready is 0 atomic_dec_if_positive will return -1 and this 676d56daea4SSara Sharon * function will return early, as there are no ready requests. 677e705c121SKalle Valo * atomic_dec_if_positive will perofrm the *actual* decrement only if 678e705c121SKalle Valo * req_ready > 0, i.e. - there are ready requests and the function 679e705c121SKalle Valo * hands one request to the caller. 680e705c121SKalle Valo */ 681e705c121SKalle Valo if (atomic_dec_if_positive(&rba->req_ready) < 0) 682d56daea4SSara Sharon return; 683e705c121SKalle Valo 684e705c121SKalle Valo spin_lock(&rba->lock); 685e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 686e705c121SKalle Valo /* Get next free Rx buffer, remove it from free list */ 687d56daea4SSara Sharon struct iwl_rx_mem_buffer *rxb = 688d56daea4SSara Sharon list_first_entry(&rba->rbd_allocated, 689e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 690d56daea4SSara Sharon 691d56daea4SSara Sharon list_move(&rxb->list, &rxq->rx_free); 692e705c121SKalle Valo } 693e705c121SKalle Valo spin_unlock(&rba->lock); 694e705c121SKalle Valo 695d56daea4SSara Sharon rxq->used_count -= RX_CLAIM_REQ_ALLOC; 696d56daea4SSara Sharon rxq->free_count += RX_CLAIM_REQ_ALLOC; 697e705c121SKalle Valo } 698e705c121SKalle Valo 69910a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data) 700e705c121SKalle Valo { 701e705c121SKalle Valo struct iwl_rb_allocator *rba_p = 702e705c121SKalle Valo container_of(data, struct iwl_rb_allocator, rx_alloc); 703e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 704e705c121SKalle Valo container_of(rba_p, struct iwl_trans_pcie, rba); 705e705c121SKalle Valo 706e705c121SKalle Valo iwl_pcie_rx_allocator(trans_pcie->trans); 707e705c121SKalle Valo } 708e705c121SKalle Valo 7090307c839SGolan Ben Ami static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td) 7100307c839SGolan Ben Ami { 7110307c839SGolan Ben Ami struct iwl_rx_transfer_desc *rx_td; 7120307c839SGolan Ben Ami 7130307c839SGolan Ben Ami if (use_rx_td) 7140307c839SGolan Ben Ami return sizeof(*rx_td); 7150307c839SGolan Ben Ami else 716286ca8ebSLuca Coelho return trans->trans_cfg->mq_rx_supported ? sizeof(__le64) : 7170307c839SGolan Ben Ami sizeof(__le32); 7180307c839SGolan Ben Ami } 7190307c839SGolan Ben Ami 7201b493e30SGolan Ben Ami static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 7211b493e30SGolan Ben Ami struct iwl_rxq *rxq) 7221b493e30SGolan Ben Ami { 7231b493e30SGolan Ben Ami struct device *dev = trans->dev; 724286ca8ebSLuca Coelho bool use_rx_td = (trans->trans_cfg->device_family >= 7253681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210); 7260307c839SGolan Ben Ami int free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 7271b493e30SGolan Ben Ami 7281b493e30SGolan Ben Ami if (rxq->bd) 7290307c839SGolan Ben Ami dma_free_coherent(trans->dev, 7300307c839SGolan Ben Ami free_size * rxq->queue_size, 7311b493e30SGolan Ben Ami rxq->bd, rxq->bd_dma); 7321b493e30SGolan Ben Ami rxq->bd_dma = 0; 7331b493e30SGolan Ben Ami rxq->bd = NULL; 7341b493e30SGolan Ben Ami 7351b493e30SGolan Ben Ami rxq->rb_stts_dma = 0; 7361b493e30SGolan Ben Ami rxq->rb_stts = NULL; 7371b493e30SGolan Ben Ami 7381b493e30SGolan Ben Ami if (rxq->used_bd) 7390307c839SGolan Ben Ami dma_free_coherent(trans->dev, 740b2a58c97SSara Sharon (use_rx_td ? sizeof(*rxq->cd) : 7410307c839SGolan Ben Ami sizeof(__le32)) * rxq->queue_size, 7421b493e30SGolan Ben Ami rxq->used_bd, rxq->used_bd_dma); 7431b493e30SGolan Ben Ami rxq->used_bd_dma = 0; 7441b493e30SGolan Ben Ami rxq->used_bd = NULL; 7451b493e30SGolan Ben Ami 7463681021fSJohannes Berg if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 7471b493e30SGolan Ben Ami return; 7481b493e30SGolan Ben Ami 7491b493e30SGolan Ben Ami if (rxq->tr_tail) 7501b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 7511b493e30SGolan Ben Ami rxq->tr_tail, rxq->tr_tail_dma); 7521b493e30SGolan Ben Ami rxq->tr_tail_dma = 0; 7531b493e30SGolan Ben Ami rxq->tr_tail = NULL; 7541b493e30SGolan Ben Ami 7551b493e30SGolan Ben Ami if (rxq->cr_tail) 7561b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 7571b493e30SGolan Ben Ami rxq->cr_tail, rxq->cr_tail_dma); 7581b493e30SGolan Ben Ami rxq->cr_tail_dma = 0; 7591b493e30SGolan Ben Ami rxq->cr_tail = NULL; 7601b493e30SGolan Ben Ami } 7611b493e30SGolan Ben Ami 7621b493e30SGolan Ben Ami static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 7631b493e30SGolan Ben Ami struct iwl_rxq *rxq) 764e705c121SKalle Valo { 765e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 766e705c121SKalle Valo struct device *dev = trans->dev; 76778485054SSara Sharon int i; 7680307c839SGolan Ben Ami int free_size; 769286ca8ebSLuca Coelho bool use_rx_td = (trans->trans_cfg->device_family >= 7703681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210); 7716cc6ba3aSTriebitz size_t rb_stts_size = use_rx_td ? sizeof(__le16) : 7726cc6ba3aSTriebitz sizeof(struct iwl_rb_status); 773e705c121SKalle Valo 77478485054SSara Sharon spin_lock_init(&rxq->lock); 775286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 776c042f0c7SJohannes Berg rxq->queue_size = trans->cfg->num_rbds; 77796a6497bSSara Sharon else 77896a6497bSSara Sharon rxq->queue_size = RX_QUEUE_SIZE; 77996a6497bSSara Sharon 7800307c839SGolan Ben Ami free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 7810307c839SGolan Ben Ami 78278485054SSara Sharon /* 78378485054SSara Sharon * Allocate the circular buffer of Read Buffer Descriptors 78478485054SSara Sharon * (RBDs) 78578485054SSara Sharon */ 786750afb08SLuis Chamberlain rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size, 787e705c121SKalle Valo &rxq->bd_dma, GFP_KERNEL); 788e705c121SKalle Valo if (!rxq->bd) 78978485054SSara Sharon goto err; 79078485054SSara Sharon 791286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) { 792750afb08SLuis Chamberlain rxq->used_bd = dma_alloc_coherent(dev, 793750afb08SLuis Chamberlain (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size, 79496a6497bSSara Sharon &rxq->used_bd_dma, 79596a6497bSSara Sharon GFP_KERNEL); 79696a6497bSSara Sharon if (!rxq->used_bd) 79796a6497bSSara Sharon goto err; 79896a6497bSSara Sharon } 799e705c121SKalle Valo 8006cc6ba3aSTriebitz rxq->rb_stts = trans_pcie->base_rb_stts + rxq->id * rb_stts_size; 8016cc6ba3aSTriebitz rxq->rb_stts_dma = 8026cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size; 8031b493e30SGolan Ben Ami 8040307c839SGolan Ben Ami if (!use_rx_td) 8051b493e30SGolan Ben Ami return 0; 8061b493e30SGolan Ben Ami 8071b493e30SGolan Ben Ami /* Allocate the driver's pointer to TR tail */ 808750afb08SLuis Chamberlain rxq->tr_tail = dma_alloc_coherent(dev, sizeof(__le16), 809750afb08SLuis Chamberlain &rxq->tr_tail_dma, GFP_KERNEL); 8101b493e30SGolan Ben Ami if (!rxq->tr_tail) 8111b493e30SGolan Ben Ami goto err; 8121b493e30SGolan Ben Ami 8131b493e30SGolan Ben Ami /* Allocate the driver's pointer to CR tail */ 814750afb08SLuis Chamberlain rxq->cr_tail = dma_alloc_coherent(dev, sizeof(__le16), 815750afb08SLuis Chamberlain &rxq->cr_tail_dma, GFP_KERNEL); 8161b493e30SGolan Ben Ami if (!rxq->cr_tail) 8171b493e30SGolan Ben Ami goto err; 8181b493e30SGolan Ben Ami 819e705c121SKalle Valo return 0; 820e705c121SKalle Valo 82178485054SSara Sharon err: 82278485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 82378485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 82478485054SSara Sharon 8251b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 82678485054SSara Sharon } 82796a6497bSSara Sharon 828e705c121SKalle Valo return -ENOMEM; 829e705c121SKalle Valo } 830e705c121SKalle Valo 831ab393cb1SJohannes Berg static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 8321b493e30SGolan Ben Ami { 8331b493e30SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 8341b493e30SGolan Ben Ami struct iwl_rb_allocator *rba = &trans_pcie->rba; 8351b493e30SGolan Ben Ami int i, ret; 836286ca8ebSLuca Coelho size_t rb_stts_size = trans->trans_cfg->device_family >= 8373681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210 ? 8386cc6ba3aSTriebitz sizeof(__le16) : sizeof(struct iwl_rb_status); 8391b493e30SGolan Ben Ami 8401b493e30SGolan Ben Ami if (WARN_ON(trans_pcie->rxq)) 8411b493e30SGolan Ben Ami return -EINVAL; 8421b493e30SGolan Ben Ami 8431b493e30SGolan Ben Ami trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 8441b493e30SGolan Ben Ami GFP_KERNEL); 845c042f0c7SJohannes Berg trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 846c042f0c7SJohannes Berg sizeof(trans_pcie->rx_pool[0]), 847c042f0c7SJohannes Berg GFP_KERNEL); 848c042f0c7SJohannes Berg trans_pcie->global_table = 849c042f0c7SJohannes Berg kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 850c042f0c7SJohannes Berg sizeof(trans_pcie->global_table[0]), 851c042f0c7SJohannes Berg GFP_KERNEL); 852c042f0c7SJohannes Berg if (!trans_pcie->rxq || !trans_pcie->rx_pool || 853c042f0c7SJohannes Berg !trans_pcie->global_table) { 854c042f0c7SJohannes Berg ret = -ENOMEM; 855c042f0c7SJohannes Berg goto err; 856c042f0c7SJohannes Berg } 8571b493e30SGolan Ben Ami 8581b493e30SGolan Ben Ami spin_lock_init(&rba->lock); 8591b493e30SGolan Ben Ami 8606cc6ba3aSTriebitz /* 8616cc6ba3aSTriebitz * Allocate the driver's pointer to receive buffer status. 8626cc6ba3aSTriebitz * Allocate for all queues continuously (HW requirement). 8636cc6ba3aSTriebitz */ 8646cc6ba3aSTriebitz trans_pcie->base_rb_stts = 8656cc6ba3aSTriebitz dma_alloc_coherent(trans->dev, 8666cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 8676cc6ba3aSTriebitz &trans_pcie->base_rb_stts_dma, 8686cc6ba3aSTriebitz GFP_KERNEL); 8696cc6ba3aSTriebitz if (!trans_pcie->base_rb_stts) { 8706cc6ba3aSTriebitz ret = -ENOMEM; 8716cc6ba3aSTriebitz goto err; 8726cc6ba3aSTriebitz } 8736cc6ba3aSTriebitz 8741b493e30SGolan Ben Ami for (i = 0; i < trans->num_rx_queues; i++) { 8751b493e30SGolan Ben Ami struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 8761b493e30SGolan Ben Ami 8776cc6ba3aSTriebitz rxq->id = i; 8781b493e30SGolan Ben Ami ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 8791b493e30SGolan Ben Ami if (ret) 8806cc6ba3aSTriebitz goto err; 8811b493e30SGolan Ben Ami } 8821b493e30SGolan Ben Ami return 0; 8836cc6ba3aSTriebitz 8846cc6ba3aSTriebitz err: 8856cc6ba3aSTriebitz if (trans_pcie->base_rb_stts) { 8866cc6ba3aSTriebitz dma_free_coherent(trans->dev, 8876cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 8886cc6ba3aSTriebitz trans_pcie->base_rb_stts, 8896cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma); 8906cc6ba3aSTriebitz trans_pcie->base_rb_stts = NULL; 8916cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma = 0; 8926cc6ba3aSTriebitz } 893c042f0c7SJohannes Berg kfree(trans_pcie->rx_pool); 894c042f0c7SJohannes Berg kfree(trans_pcie->global_table); 8956cc6ba3aSTriebitz kfree(trans_pcie->rxq); 8966cc6ba3aSTriebitz 8976cc6ba3aSTriebitz return ret; 8981b493e30SGolan Ben Ami } 8991b493e30SGolan Ben Ami 900e705c121SKalle Valo static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 901e705c121SKalle Valo { 902e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 903e705c121SKalle Valo u32 rb_size; 904dfcfeef9SSara Sharon unsigned long flags; 905e705c121SKalle Valo const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 906e705c121SKalle Valo 9076c4fbcbcSEmmanuel Grumbach switch (trans_pcie->rx_buf_size) { 9086c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 909e705c121SKalle Valo rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 9106c4fbcbcSEmmanuel Grumbach break; 9116c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 9126c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 9136c4fbcbcSEmmanuel Grumbach break; 9146c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 9156c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 9166c4fbcbcSEmmanuel Grumbach break; 9176c4fbcbcSEmmanuel Grumbach default: 9186c4fbcbcSEmmanuel Grumbach WARN_ON(1); 9196c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 9206c4fbcbcSEmmanuel Grumbach } 921e705c121SKalle Valo 922dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 923dfcfeef9SSara Sharon return; 924dfcfeef9SSara Sharon 925e705c121SKalle Valo /* Stop Rx DMA */ 926dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 927e705c121SKalle Valo /* reset and flush pointers */ 928dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 929dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 930dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 931e705c121SKalle Valo 932e705c121SKalle Valo /* Reset driver's Rx queue write index */ 933dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 934e705c121SKalle Valo 935e705c121SKalle Valo /* Tell device where to find RBD circular buffer in DRAM */ 936dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 937e705c121SKalle Valo (u32)(rxq->bd_dma >> 8)); 938e705c121SKalle Valo 939e705c121SKalle Valo /* Tell device where in DRAM to update its Rx status */ 940dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 941e705c121SKalle Valo rxq->rb_stts_dma >> 4); 942e705c121SKalle Valo 943e705c121SKalle Valo /* Enable Rx DMA 944e705c121SKalle Valo * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 945e705c121SKalle Valo * the credit mechanism in 5000 HW RX FIFO 946e705c121SKalle Valo * Direct rx interrupts to hosts 9476c4fbcbcSEmmanuel Grumbach * Rx buffer size 4 or 8k or 12k 948e705c121SKalle Valo * RB timeout 0x10 949e705c121SKalle Valo * 256 RBDs 950e705c121SKalle Valo */ 951dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 952e705c121SKalle Valo FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 953e705c121SKalle Valo FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 954e705c121SKalle Valo FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 955e705c121SKalle Valo rb_size | 956e705c121SKalle Valo (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 957e705c121SKalle Valo (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 958e705c121SKalle Valo 959dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 960dfcfeef9SSara Sharon 961e705c121SKalle Valo /* Set interrupt coalescing timer to default (2048 usecs) */ 962e705c121SKalle Valo iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 963e705c121SKalle Valo 964e705c121SKalle Valo /* W/A for interrupt coalescing bug in 7260 and 3160 */ 965e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) 966e705c121SKalle Valo iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 967e705c121SKalle Valo } 968e705c121SKalle Valo 969bce97731SSara Sharon static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 97096a6497bSSara Sharon { 97196a6497bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 97296a6497bSSara Sharon u32 rb_size, enabled = 0; 973dfcfeef9SSara Sharon unsigned long flags; 97496a6497bSSara Sharon int i; 97596a6497bSSara Sharon 97696a6497bSSara Sharon switch (trans_pcie->rx_buf_size) { 9771a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 9781a4968d1SGolan Ben Ami rb_size = RFH_RXF_DMA_RB_SIZE_2K; 9791a4968d1SGolan Ben Ami break; 98096a6497bSSara Sharon case IWL_AMSDU_4K: 98196a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 98296a6497bSSara Sharon break; 98396a6497bSSara Sharon case IWL_AMSDU_8K: 98496a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_8K; 98596a6497bSSara Sharon break; 98696a6497bSSara Sharon case IWL_AMSDU_12K: 98796a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_12K; 98896a6497bSSara Sharon break; 98996a6497bSSara Sharon default: 99096a6497bSSara Sharon WARN_ON(1); 99196a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 99296a6497bSSara Sharon } 99396a6497bSSara Sharon 994dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 995dfcfeef9SSara Sharon return; 996dfcfeef9SSara Sharon 99796a6497bSSara Sharon /* Stop Rx DMA */ 998dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 99996a6497bSSara Sharon /* disable free amd used rx queue operation */ 1000dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 100196a6497bSSara Sharon 100296a6497bSSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 100396a6497bSSara Sharon /* Tell device where to find RBD free table in DRAM */ 100412a17458SSara Sharon iwl_write_prph64_no_grab(trans, 1005dfcfeef9SSara Sharon RFH_Q_FRBDCB_BA_LSB(i), 1006dfcfeef9SSara Sharon trans_pcie->rxq[i].bd_dma); 100796a6497bSSara Sharon /* Tell device where to find RBD used table in DRAM */ 100812a17458SSara Sharon iwl_write_prph64_no_grab(trans, 1009dfcfeef9SSara Sharon RFH_Q_URBDCB_BA_LSB(i), 1010dfcfeef9SSara Sharon trans_pcie->rxq[i].used_bd_dma); 101196a6497bSSara Sharon /* Tell device where in DRAM to update its Rx status */ 101212a17458SSara Sharon iwl_write_prph64_no_grab(trans, 1013dfcfeef9SSara Sharon RFH_Q_URBD_STTS_WPTR_LSB(i), 1014bce97731SSara Sharon trans_pcie->rxq[i].rb_stts_dma); 101596a6497bSSara Sharon /* Reset device indice tables */ 1016dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 1017dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 1018dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 101996a6497bSSara Sharon 102096a6497bSSara Sharon enabled |= BIT(i) | BIT(i + 16); 102196a6497bSSara Sharon } 102296a6497bSSara Sharon 102396a6497bSSara Sharon /* 102496a6497bSSara Sharon * Enable Rx DMA 102596a6497bSSara Sharon * Rx buffer size 4 or 8k or 12k 102696a6497bSSara Sharon * Min RB size 4 or 8 102788076015SSara Sharon * Drop frames that exceed RB size 102896a6497bSSara Sharon * 512 RBDs 102996a6497bSSara Sharon */ 1030dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 103163044335SSara Sharon RFH_DMA_EN_ENABLE_VAL | rb_size | 103296a6497bSSara Sharon RFH_RXF_DMA_MIN_RB_4_8 | 103388076015SSara Sharon RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 103496a6497bSSara Sharon RFH_RXF_DMA_RBDCB_SIZE_512); 103596a6497bSSara Sharon 103688076015SSara Sharon /* 103788076015SSara Sharon * Activate DMA snooping. 1038b0262f07SSara Sharon * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 103988076015SSara Sharon * Default queue is 0 104088076015SSara Sharon */ 1041f3779f47SJohannes Berg iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 1042f3779f47SJohannes Berg RFH_GEN_CFG_RFH_DMA_SNOOP | 1043f3779f47SJohannes Berg RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 1044b0262f07SSara Sharon RFH_GEN_CFG_SERVICE_DMA_SNOOP | 1045f3779f47SJohannes Berg RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 10467897dfa2SLuca Coelho trans->trans_cfg->integrated ? 1047b0262f07SSara Sharon RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 1048f3779f47SJohannes Berg RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 104988076015SSara Sharon /* Enable the relevant rx queues */ 1050dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 1051dfcfeef9SSara Sharon 1052dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 105396a6497bSSara Sharon 105496a6497bSSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 105596a6497bSSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 105696a6497bSSara Sharon } 105796a6497bSSara Sharon 1058ff932f61SGolan Ben Ami void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 1059e705c121SKalle Valo { 1060e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 1061e705c121SKalle Valo 1062e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_free); 1063e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_used); 1064e705c121SKalle Valo rxq->free_count = 0; 1065e705c121SKalle Valo rxq->used_count = 0; 1066e705c121SKalle Valo } 1067e705c121SKalle Valo 1068ff932f61SGolan Ben Ami int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) 1069bce97731SSara Sharon { 1070bce97731SSara Sharon WARN_ON(1); 1071bce97731SSara Sharon return 0; 1072bce97731SSara Sharon } 1073bce97731SSara Sharon 1074ab393cb1SJohannes Berg static int _iwl_pcie_rx_init(struct iwl_trans *trans) 1075e705c121SKalle Valo { 1076e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 107778485054SSara Sharon struct iwl_rxq *def_rxq; 1078e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 10797b542436SSara Sharon int i, err, queue_size, allocator_pool_size, num_alloc; 1080e705c121SKalle Valo 108178485054SSara Sharon if (!trans_pcie->rxq) { 1082e705c121SKalle Valo err = iwl_pcie_rx_alloc(trans); 1083e705c121SKalle Valo if (err) 1084e705c121SKalle Valo return err; 1085e705c121SKalle Valo } 108678485054SSara Sharon def_rxq = trans_pcie->rxq; 1087e705c121SKalle Valo 10880f22e400SShaul Triebitz cancel_work_sync(&rba->rx_alloc); 10890f22e400SShaul Triebitz 1090e705c121SKalle Valo spin_lock(&rba->lock); 1091e705c121SKalle Valo atomic_set(&rba->req_pending, 0); 1092e705c121SKalle Valo atomic_set(&rba->req_ready, 0); 109396a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_allocated); 109496a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_empty); 1095e705c121SKalle Valo spin_unlock(&rba->lock); 1096e705c121SKalle Valo 1097e705c121SKalle Valo /* free all first - we might be reconfigured for a different size */ 109878485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1099e705c121SKalle Valo 1100e705c121SKalle Valo for (i = 0; i < RX_QUEUE_SIZE; i++) 110178485054SSara Sharon def_rxq->queue[i] = NULL; 1102e705c121SKalle Valo 110378485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 110478485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1105e705c121SKalle Valo 1106e705c121SKalle Valo spin_lock(&rxq->lock); 110778485054SSara Sharon /* 110878485054SSara Sharon * Set read write pointer to reflect that we have processed 110978485054SSara Sharon * and used all buffers, but have not restocked the Rx queue 111078485054SSara Sharon * with fresh buffers 111178485054SSara Sharon */ 111278485054SSara Sharon rxq->read = 0; 111378485054SSara Sharon rxq->write = 0; 111478485054SSara Sharon rxq->write_actual = 0; 11153681021fSJohannes Berg memset(rxq->rb_stts, 0, 11163681021fSJohannes Berg (trans->trans_cfg->device_family >= 11173681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210) ? 11180307c839SGolan Ben Ami sizeof(__le16) : sizeof(struct iwl_rb_status)); 111978485054SSara Sharon 112078485054SSara Sharon iwl_pcie_rx_init_rxb_lists(rxq); 112178485054SSara Sharon 1122bce97731SSara Sharon if (!rxq->napi.poll) 1123bce97731SSara Sharon netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 1124bce97731SSara Sharon iwl_pcie_dummy_napi_poll, 64); 1125bce97731SSara Sharon 1126e705c121SKalle Valo spin_unlock(&rxq->lock); 112778485054SSara Sharon } 112878485054SSara Sharon 112996a6497bSSara Sharon /* move the pool to the default queue and allocator ownerships */ 1130286ca8ebSLuca Coelho queue_size = trans->trans_cfg->mq_rx_supported ? 1131c042f0c7SJohannes Berg trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE; 113296a6497bSSara Sharon allocator_pool_size = trans->num_rx_queues * 113396a6497bSSara Sharon (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 11347b542436SSara Sharon num_alloc = queue_size + allocator_pool_size; 1135c042f0c7SJohannes Berg 11367b542436SSara Sharon for (i = 0; i < num_alloc; i++) { 113796a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 113896a6497bSSara Sharon 113996a6497bSSara Sharon if (i < allocator_pool_size) 114096a6497bSSara Sharon list_add(&rxb->list, &rba->rbd_empty); 114196a6497bSSara Sharon else 114296a6497bSSara Sharon list_add(&rxb->list, &def_rxq->rx_used); 114396a6497bSSara Sharon trans_pcie->global_table[i] = rxb; 1144e25d65f2SSara Sharon rxb->vid = (u16)(i + 1); 1145b1753c62SSara Sharon rxb->invalid = true; 114696a6497bSSara Sharon } 114778485054SSara Sharon 114878485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 11492047fa54SSara Sharon 1150eda50cdeSSara Sharon return 0; 1151eda50cdeSSara Sharon } 1152eda50cdeSSara Sharon 1153eda50cdeSSara Sharon int iwl_pcie_rx_init(struct iwl_trans *trans) 1154eda50cdeSSara Sharon { 1155eda50cdeSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1156eda50cdeSSara Sharon int ret = _iwl_pcie_rx_init(trans); 1157eda50cdeSSara Sharon 1158eda50cdeSSara Sharon if (ret) 1159eda50cdeSSara Sharon return ret; 1160eda50cdeSSara Sharon 1161286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 1162bce97731SSara Sharon iwl_pcie_rx_mq_hw_init(trans); 11632047fa54SSara Sharon else 1164eda50cdeSSara Sharon iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 11652047fa54SSara Sharon 1166eda50cdeSSara Sharon iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 116778485054SSara Sharon 1168eda50cdeSSara Sharon spin_lock(&trans_pcie->rxq->lock); 1169eda50cdeSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 1170eda50cdeSSara Sharon spin_unlock(&trans_pcie->rxq->lock); 1171e705c121SKalle Valo 1172e705c121SKalle Valo return 0; 1173e705c121SKalle Valo } 1174e705c121SKalle Valo 1175eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1176eda50cdeSSara Sharon { 1177e506b481SSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 1178e506b481SSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1179e506b481SSara Sharon 1180eda50cdeSSara Sharon /* 1181eda50cdeSSara Sharon * We don't configure the RFH. 1182eda50cdeSSara Sharon * Restock will be done at alive, after firmware configured the RFH. 1183eda50cdeSSara Sharon */ 1184eda50cdeSSara Sharon return _iwl_pcie_rx_init(trans); 1185eda50cdeSSara Sharon } 1186eda50cdeSSara Sharon 1187e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans) 1188e705c121SKalle Valo { 1189e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1190e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 119178485054SSara Sharon int i; 1192286ca8ebSLuca Coelho size_t rb_stts_size = trans->trans_cfg->device_family >= 11933681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210 ? 11946cc6ba3aSTriebitz sizeof(__le16) : sizeof(struct iwl_rb_status); 1195e705c121SKalle Valo 119678485054SSara Sharon /* 119778485054SSara Sharon * if rxq is NULL, it means that nothing has been allocated, 119878485054SSara Sharon * exit now 119978485054SSara Sharon */ 120078485054SSara Sharon if (!trans_pcie->rxq) { 1201e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1202e705c121SKalle Valo return; 1203e705c121SKalle Valo } 1204e705c121SKalle Valo 1205e705c121SKalle Valo cancel_work_sync(&rba->rx_alloc); 1206e705c121SKalle Valo 120778485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1208e705c121SKalle Valo 12096cc6ba3aSTriebitz if (trans_pcie->base_rb_stts) { 12106cc6ba3aSTriebitz dma_free_coherent(trans->dev, 12116cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 12126cc6ba3aSTriebitz trans_pcie->base_rb_stts, 12136cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma); 12146cc6ba3aSTriebitz trans_pcie->base_rb_stts = NULL; 12156cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma = 0; 12166cc6ba3aSTriebitz } 12176cc6ba3aSTriebitz 121878485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 121978485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 122078485054SSara Sharon 12211b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 1222bce97731SSara Sharon 1223bce97731SSara Sharon if (rxq->napi.poll) 1224bce97731SSara Sharon netif_napi_del(&rxq->napi); 122596a6497bSSara Sharon } 1226c042f0c7SJohannes Berg kfree(trans_pcie->rx_pool); 1227c042f0c7SJohannes Berg kfree(trans_pcie->global_table); 122878485054SSara Sharon kfree(trans_pcie->rxq); 1229cfdc20efSJohannes Berg 1230cfdc20efSJohannes Berg if (trans_pcie->alloc_page) 1231cfdc20efSJohannes Berg __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order); 1232e705c121SKalle Valo } 1233e705c121SKalle Valo 1234868a1e86SShaul Triebitz static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq, 1235868a1e86SShaul Triebitz struct iwl_rb_allocator *rba) 1236868a1e86SShaul Triebitz { 1237868a1e86SShaul Triebitz spin_lock(&rba->lock); 1238868a1e86SShaul Triebitz list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1239868a1e86SShaul Triebitz spin_unlock(&rba->lock); 1240868a1e86SShaul Triebitz } 1241868a1e86SShaul Triebitz 1242e705c121SKalle Valo /* 1243e705c121SKalle Valo * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1244e705c121SKalle Valo * 1245e705c121SKalle Valo * Called when a RBD can be reused. The RBD is transferred to the allocator. 1246e705c121SKalle Valo * When there are 2 empty RBDs - a request for allocation is posted 1247e705c121SKalle Valo */ 1248e705c121SKalle Valo static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1249e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 1250e705c121SKalle Valo struct iwl_rxq *rxq, bool emergency) 1251e705c121SKalle Valo { 1252e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1253e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 1254e705c121SKalle Valo 1255e705c121SKalle Valo /* Move the RBD to the used list, will be moved to allocator in batches 1256e705c121SKalle Valo * before claiming or posting a request*/ 1257e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_used); 1258e705c121SKalle Valo 1259e705c121SKalle Valo if (unlikely(emergency)) 1260e705c121SKalle Valo return; 1261e705c121SKalle Valo 1262e705c121SKalle Valo /* Count the allocator owned RBDs */ 1263e705c121SKalle Valo rxq->used_count++; 1264e705c121SKalle Valo 1265e705c121SKalle Valo /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1266e705c121SKalle Valo * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1267e705c121SKalle Valo * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1268e705c121SKalle Valo * after but we still need to post another request. 1269e705c121SKalle Valo */ 1270e705c121SKalle Valo if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1271e705c121SKalle Valo /* Move the 2 RBDs to the allocator ownership. 1272e705c121SKalle Valo Allocator has another 6 from pool for the request completion*/ 1273868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1274e705c121SKalle Valo 1275e705c121SKalle Valo atomic_inc(&rba->req_pending); 1276e705c121SKalle Valo queue_work(rba->alloc_wq, &rba->rx_alloc); 1277e705c121SKalle Valo } 1278e705c121SKalle Valo } 1279e705c121SKalle Valo 1280e705c121SKalle Valo static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 128178485054SSara Sharon struct iwl_rxq *rxq, 1282e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 12837891965dSSara Sharon bool emergency, 12847891965dSSara Sharon int i) 1285e705c121SKalle Valo { 1286e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1287b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1288e705c121SKalle Valo bool page_stolen = false; 128980084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 1290e705c121SKalle Valo u32 offset = 0; 1291e705c121SKalle Valo 1292e705c121SKalle Valo if (WARN_ON(!rxb)) 1293e705c121SKalle Valo return; 1294e705c121SKalle Valo 1295e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1296e705c121SKalle Valo 1297e705c121SKalle Valo while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1298e705c121SKalle Valo struct iwl_rx_packet *pkt; 1299e705c121SKalle Valo u16 sequence; 1300e705c121SKalle Valo bool reclaim; 1301e705c121SKalle Valo int index, cmd_index, len; 1302e705c121SKalle Valo struct iwl_rx_cmd_buffer rxcb = { 1303cfdc20efSJohannes Berg ._offset = rxb->offset + offset, 1304e705c121SKalle Valo ._rx_page_order = trans_pcie->rx_page_order, 1305e705c121SKalle Valo ._page = rxb->page, 1306e705c121SKalle Valo ._page_stolen = false, 1307e705c121SKalle Valo .truesize = max_len, 1308e705c121SKalle Valo }; 1309e705c121SKalle Valo 1310e705c121SKalle Valo pkt = rxb_addr(&rxcb); 1311e705c121SKalle Valo 13123bfdee76SJohannes Berg if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 13133bfdee76SJohannes Berg IWL_DEBUG_RX(trans, 13143bfdee76SJohannes Berg "Q %d: RB end marker at offset %d\n", 13153bfdee76SJohannes Berg rxq->id, offset); 1316e705c121SKalle Valo break; 13173bfdee76SJohannes Berg } 1318e705c121SKalle Valo 1319a395058eSJohannes Berg WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1320a395058eSJohannes Berg FH_RSCSR_RXQ_POS != rxq->id, 1321a395058eSJohannes Berg "frame on invalid queue - is on %d and indicates %d\n", 1322a395058eSJohannes Berg rxq->id, 1323a395058eSJohannes Berg (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1324a395058eSJohannes Berg FH_RSCSR_RXQ_POS); 1325ab2e696bSSara Sharon 1326e705c121SKalle Valo IWL_DEBUG_RX(trans, 13273bfdee76SJohannes Berg "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 13283bfdee76SJohannes Berg rxq->id, offset, 132939bdb17eSSharon Dvir iwl_get_cmd_string(trans, 133039bdb17eSSharon Dvir iwl_cmd_id(pkt->hdr.cmd, 133139bdb17eSSharon Dvir pkt->hdr.group_id, 133239bdb17eSSharon Dvir 0)), 133335177c99SSara Sharon pkt->hdr.group_id, pkt->hdr.cmd, 133435177c99SSara Sharon le16_to_cpu(pkt->hdr.sequence)); 1335e705c121SKalle Valo 1336e705c121SKalle Valo len = iwl_rx_packet_len(pkt); 1337e705c121SKalle Valo len += sizeof(u32); /* account for status word */ 1338e705c121SKalle Valo trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1339e705c121SKalle Valo trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1340e705c121SKalle Valo 1341e705c121SKalle Valo /* Reclaim a command buffer only if this packet is a response 1342e705c121SKalle Valo * to a (driver-originated) command. 1343e705c121SKalle Valo * If the packet (e.g. Rx frame) originated from uCode, 1344e705c121SKalle Valo * there is no command buffer to reclaim. 1345e705c121SKalle Valo * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1346e705c121SKalle Valo * but apparently a few don't get set; catch them here. */ 1347e705c121SKalle Valo reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1348d8a130b0SJohannes Berg if (reclaim && !pkt->hdr.group_id) { 1349e705c121SKalle Valo int i; 1350e705c121SKalle Valo 1351e705c121SKalle Valo for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1352e705c121SKalle Valo if (trans_pcie->no_reclaim_cmds[i] == 1353e705c121SKalle Valo pkt->hdr.cmd) { 1354e705c121SKalle Valo reclaim = false; 1355e705c121SKalle Valo break; 1356e705c121SKalle Valo } 1357e705c121SKalle Valo } 1358e705c121SKalle Valo } 1359e705c121SKalle Valo 1360e705c121SKalle Valo sequence = le16_to_cpu(pkt->hdr.sequence); 1361e705c121SKalle Valo index = SEQ_TO_INDEX(sequence); 13624ecab561SEmmanuel Grumbach cmd_index = iwl_pcie_get_cmd_index(txq, index); 1363e705c121SKalle Valo 13649416560eSGolan Ben Ami if (rxq->id == trans_pcie->def_rx_queue) 1365bce97731SSara Sharon iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1366bce97731SSara Sharon &rxcb); 1367bce97731SSara Sharon else 1368bce97731SSara Sharon iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1369bce97731SSara Sharon &rxcb, rxq->id); 1370e705c121SKalle Valo 1371e705c121SKalle Valo if (reclaim) { 1372e705c121SKalle Valo kzfree(txq->entries[cmd_index].free_buf); 1373e705c121SKalle Valo txq->entries[cmd_index].free_buf = NULL; 1374e705c121SKalle Valo } 1375e705c121SKalle Valo 1376e705c121SKalle Valo /* 1377e705c121SKalle Valo * After here, we should always check rxcb._page_stolen, 1378e705c121SKalle Valo * if it is true then one of the handlers took the page. 1379e705c121SKalle Valo */ 1380e705c121SKalle Valo 1381e705c121SKalle Valo if (reclaim) { 1382e705c121SKalle Valo /* Invoke any callbacks, transfer the buffer to caller, 1383e705c121SKalle Valo * and fire off the (possibly) blocking 1384e705c121SKalle Valo * iwl_trans_send_cmd() 1385e705c121SKalle Valo * as we reclaim the driver command queue */ 1386e705c121SKalle Valo if (!rxcb._page_stolen) 1387e705c121SKalle Valo iwl_pcie_hcmd_complete(trans, &rxcb); 1388e705c121SKalle Valo else 1389e705c121SKalle Valo IWL_WARN(trans, "Claim null rxb?\n"); 1390e705c121SKalle Valo } 1391e705c121SKalle Valo 1392e705c121SKalle Valo page_stolen |= rxcb._page_stolen; 13933681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 13940307c839SGolan Ben Ami break; 1395e705c121SKalle Valo offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1396e705c121SKalle Valo } 1397e705c121SKalle Valo 1398e705c121SKalle Valo /* page was stolen from us -- free our reference */ 1399e705c121SKalle Valo if (page_stolen) { 1400e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1401e705c121SKalle Valo rxb->page = NULL; 1402e705c121SKalle Valo } 1403e705c121SKalle Valo 1404e705c121SKalle Valo /* Reuse the page if possible. For notification packets and 1405e705c121SKalle Valo * SKBs that fail to Rx correctly, add them back into the 1406e705c121SKalle Valo * rx_free list for reuse later. */ 1407e705c121SKalle Valo if (rxb->page != NULL) { 1408e705c121SKalle Valo rxb->page_dma = 1409cfdc20efSJohannes Berg dma_map_page(trans->dev, rxb->page, rxb->offset, 141080084e35SJohannes Berg trans_pcie->rx_buf_bytes, 1411e705c121SKalle Valo DMA_FROM_DEVICE); 1412e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1413e705c121SKalle Valo /* 1414e705c121SKalle Valo * free the page(s) as well to not break 1415e705c121SKalle Valo * the invariant that the items on the used 1416e705c121SKalle Valo * list have no page(s) 1417e705c121SKalle Valo */ 1418e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1419e705c121SKalle Valo rxb->page = NULL; 1420e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1421e705c121SKalle Valo } else { 1422e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 1423e705c121SKalle Valo rxq->free_count++; 1424e705c121SKalle Valo } 1425e705c121SKalle Valo } else 1426e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1427e705c121SKalle Valo } 1428e705c121SKalle Valo 14291b4bbe8bSSara Sharon static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans, 1430b1c860f6SJohannes Berg struct iwl_rxq *rxq, int i, 1431b1c860f6SJohannes Berg bool *join) 14321b4bbe8bSSara Sharon { 14331b4bbe8bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 14341b4bbe8bSSara Sharon struct iwl_rx_mem_buffer *rxb; 14351b4bbe8bSSara Sharon u16 vid; 14361b4bbe8bSSara Sharon 1437f826faaaSJohannes Berg BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32); 1438f826faaaSJohannes Berg 1439286ca8ebSLuca Coelho if (!trans->trans_cfg->mq_rx_supported) { 14401b4bbe8bSSara Sharon rxb = rxq->queue[i]; 14411b4bbe8bSSara Sharon rxq->queue[i] = NULL; 14421b4bbe8bSSara Sharon return rxb; 14431b4bbe8bSSara Sharon } 14441b4bbe8bSSara Sharon 1445b1c860f6SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1446c042f0c7SJohannes Berg vid = le16_to_cpu(rxq->cd[i].rbid); 1447b1c860f6SJohannes Berg *join = rxq->cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED; 1448b1c860f6SJohannes Berg } else { 1449c042f0c7SJohannes Berg vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; /* 12-bit VID */ 1450b1c860f6SJohannes Berg } 14511b4bbe8bSSara Sharon 1452c042f0c7SJohannes Berg if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs)) 14531b4bbe8bSSara Sharon goto out_err; 14541b4bbe8bSSara Sharon 14551b4bbe8bSSara Sharon rxb = trans_pcie->global_table[vid - 1]; 14561b4bbe8bSSara Sharon if (rxb->invalid) 14571b4bbe8bSSara Sharon goto out_err; 14581b4bbe8bSSara Sharon 145985d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid); 146085d78bb1SSara Sharon 14611b4bbe8bSSara Sharon rxb->invalid = true; 14621b4bbe8bSSara Sharon 14631b4bbe8bSSara Sharon return rxb; 14641b4bbe8bSSara Sharon 14651b4bbe8bSSara Sharon out_err: 14661b4bbe8bSSara Sharon WARN(1, "Invalid rxb from HW %u\n", (u32)vid); 14671b4bbe8bSSara Sharon iwl_force_nmi(trans); 14681b4bbe8bSSara Sharon return NULL; 14691b4bbe8bSSara Sharon } 14701b4bbe8bSSara Sharon 1471e705c121SKalle Valo /* 1472e705c121SKalle Valo * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1473e705c121SKalle Valo */ 14742e5d4a8fSHaim Dreyfuss static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue) 1475e705c121SKalle Valo { 1476e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1477b167191eSAlexander Lobakin struct napi_struct *napi; 147830f24eabSJohannes Berg struct iwl_rxq *rxq; 1479d56daea4SSara Sharon u32 r, i, count = 0; 1480e705c121SKalle Valo bool emergency = false; 1481e705c121SKalle Valo 148230f24eabSJohannes Berg if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd)) 148330f24eabSJohannes Berg return; 148430f24eabSJohannes Berg 148530f24eabSJohannes Berg rxq = &trans_pcie->rxq[queue]; 148630f24eabSJohannes Berg 1487e705c121SKalle Valo restart: 1488e705c121SKalle Valo spin_lock(&rxq->lock); 1489e705c121SKalle Valo /* uCode's read index (stored in shared DRAM) indicates the last Rx 1490e705c121SKalle Valo * buffer that the driver may process (last buffer filled by ucode). */ 14910307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1492e705c121SKalle Valo i = rxq->read; 1493e705c121SKalle Valo 14945eae443eSSara Sharon /* W/A 9000 device step A0 wrap-around bug */ 14955eae443eSSara Sharon r &= (rxq->queue_size - 1); 14965eae443eSSara Sharon 1497e705c121SKalle Valo /* Rx interrupt, but nothing sent from uCode */ 1498e705c121SKalle Valo if (i == r) 14995eae443eSSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1500e705c121SKalle Valo 1501e705c121SKalle Valo while (i != r) { 1502868a1e86SShaul Triebitz struct iwl_rb_allocator *rba = &trans_pcie->rba; 1503e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 1504868a1e86SShaul Triebitz /* number of RBDs still waiting for page allocation */ 1505868a1e86SShaul Triebitz u32 rb_pending_alloc = 1506868a1e86SShaul Triebitz atomic_read(&trans_pcie->rba.req_pending) * 1507868a1e86SShaul Triebitz RX_CLAIM_REQ_ALLOC; 1508b1c860f6SJohannes Berg bool join = false; 1509e705c121SKalle Valo 1510868a1e86SShaul Triebitz if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 && 1511868a1e86SShaul Triebitz !emergency)) { 1512868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1513e705c121SKalle Valo emergency = true; 15146dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 15156dcdd165SSara Sharon "RX path is in emergency. Pending allocations %d\n", 15166dcdd165SSara Sharon rb_pending_alloc); 1517868a1e86SShaul Triebitz } 1518e705c121SKalle Valo 151985d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 152085d78bb1SSara Sharon 1521b1c860f6SJohannes Berg rxb = iwl_pcie_get_rxb(trans, rxq, i, &join); 15221b4bbe8bSSara Sharon if (!rxb) 15235eae443eSSara Sharon goto out; 1524e705c121SKalle Valo 1525b1c860f6SJohannes Berg if (unlikely(join || rxq->next_rb_is_fragment)) { 1526b1c860f6SJohannes Berg rxq->next_rb_is_fragment = join; 1527b1c860f6SJohannes Berg /* 1528b1c860f6SJohannes Berg * We can only get a multi-RB in the following cases: 1529b1c860f6SJohannes Berg * - firmware issue, sending a too big notification 1530b1c860f6SJohannes Berg * - sniffer mode with a large A-MSDU 1531b1c860f6SJohannes Berg * - large MTU frames (>2k) 1532b1c860f6SJohannes Berg * since the multi-RB functionality is limited to newer 1533b1c860f6SJohannes Berg * hardware that cannot put multiple entries into a 1534b1c860f6SJohannes Berg * single RB. 1535b1c860f6SJohannes Berg * 1536b1c860f6SJohannes Berg * Right now, the higher layers aren't set up to deal 1537b1c860f6SJohannes Berg * with that, so discard all of these. 1538b1c860f6SJohannes Berg */ 1539b1c860f6SJohannes Berg list_add_tail(&rxb->list, &rxq->rx_free); 1540b1c860f6SJohannes Berg rxq->free_count++; 1541b1c860f6SJohannes Berg } else { 15427891965dSSara Sharon iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i); 1543b1c860f6SJohannes Berg } 1544e705c121SKalle Valo 154596a6497bSSara Sharon i = (i + 1) & (rxq->queue_size - 1); 1546e705c121SKalle Valo 1547d56daea4SSara Sharon /* 1548d56daea4SSara Sharon * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1549d56daea4SSara Sharon * try to claim the pre-allocated buffers from the allocator. 1550d56daea4SSara Sharon * If not ready - will try to reclaim next time. 1551d56daea4SSara Sharon * There is no need to reschedule work - allocator exits only 1552d56daea4SSara Sharon * on success 1553e705c121SKalle Valo */ 1554d56daea4SSara Sharon if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1555d56daea4SSara Sharon iwl_pcie_rx_allocator_get(trans, rxq); 1556e705c121SKalle Valo 1557d56daea4SSara Sharon if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1558d56daea4SSara Sharon /* Add the remaining empty RBDs for allocator use */ 1559868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1560d56daea4SSara Sharon } else if (emergency) { 1561e705c121SKalle Valo count++; 1562e705c121SKalle Valo if (count == 8) { 1563e705c121SKalle Valo count = 0; 15646dcdd165SSara Sharon if (rb_pending_alloc < rxq->queue_size / 3) { 15656dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 15666dcdd165SSara Sharon "RX path exited emergency. Pending allocations %d\n", 15676dcdd165SSara Sharon rb_pending_alloc); 1568e705c121SKalle Valo emergency = false; 15696dcdd165SSara Sharon } 1570e0e168dcSGregory Greenman 1571e705c121SKalle Valo rxq->read = i; 1572e705c121SKalle Valo spin_unlock(&rxq->lock); 1573e0e168dcSGregory Greenman iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 157478485054SSara Sharon iwl_pcie_rxq_restock(trans, rxq); 1575e705c121SKalle Valo goto restart; 1576e705c121SKalle Valo } 1577e705c121SKalle Valo } 1578e0e168dcSGregory Greenman } 15795eae443eSSara Sharon out: 1580e705c121SKalle Valo /* Backtrack one entry */ 1581e705c121SKalle Valo rxq->read = i; 15820307c839SGolan Ben Ami /* update cr tail with the rxq read pointer */ 15833681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 15840307c839SGolan Ben Ami *rxq->cr_tail = cpu_to_le16(r); 1585e705c121SKalle Valo spin_unlock(&rxq->lock); 1586e705c121SKalle Valo 1587e705c121SKalle Valo /* 1588e705c121SKalle Valo * handle a case where in emergency there are some unallocated RBDs. 1589e705c121SKalle Valo * those RBDs are in the used list, but are not tracked by the queue's 1590e705c121SKalle Valo * used_count which counts allocator owned RBDs. 1591e705c121SKalle Valo * unallocated emergency RBDs must be allocated on exit, otherwise 1592e705c121SKalle Valo * when called again the function may not be in emergency mode and 1593e705c121SKalle Valo * they will be handed to the allocator with no tracking in the RBD 1594e705c121SKalle Valo * allocator counters, which will lead to them never being claimed back 1595e705c121SKalle Valo * by the queue. 1596e705c121SKalle Valo * by allocating them here, they are now in the queue free list, and 1597e705c121SKalle Valo * will be restocked by the next call of iwl_pcie_rxq_restock. 1598e705c121SKalle Valo */ 1599e705c121SKalle Valo if (unlikely(emergency && count)) 160078485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1601e705c121SKalle Valo 1602b167191eSAlexander Lobakin napi = &rxq->napi; 1603b167191eSAlexander Lobakin if (napi->poll) { 1604c8079432SMaxim Mikityanskiy napi_gro_flush(napi, false); 1605c8079432SMaxim Mikityanskiy 1606b167191eSAlexander Lobakin if (napi->rx_count) { 1607b167191eSAlexander Lobakin netif_receive_skb_list(&napi->rx_list); 1608b167191eSAlexander Lobakin INIT_LIST_HEAD(&napi->rx_list); 1609b167191eSAlexander Lobakin napi->rx_count = 0; 1610b167191eSAlexander Lobakin } 1611b167191eSAlexander Lobakin } 1612e0e168dcSGregory Greenman 1613e0e168dcSGregory Greenman iwl_pcie_rxq_restock(trans, rxq); 1614e705c121SKalle Valo } 1615e705c121SKalle Valo 16162e5d4a8fSHaim Dreyfuss static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 16172e5d4a8fSHaim Dreyfuss { 16182e5d4a8fSHaim Dreyfuss u8 queue = entry->entry; 16192e5d4a8fSHaim Dreyfuss struct msix_entry *entries = entry - queue; 16202e5d4a8fSHaim Dreyfuss 16212e5d4a8fSHaim Dreyfuss return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 16222e5d4a8fSHaim Dreyfuss } 16232e5d4a8fSHaim Dreyfuss 16242e5d4a8fSHaim Dreyfuss /* 16252e5d4a8fSHaim Dreyfuss * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 16262e5d4a8fSHaim Dreyfuss * This interrupt handler should be used with RSS queue only. 16272e5d4a8fSHaim Dreyfuss */ 16282e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 16292e5d4a8fSHaim Dreyfuss { 16302e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 16312e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 16322e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 16332e5d4a8fSHaim Dreyfuss 1634c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1635c42ff65dSJohannes Berg 16365eae443eSSara Sharon if (WARN_ON(entry->entry >= trans->num_rx_queues)) 16375eae443eSSara Sharon return IRQ_NONE; 16385eae443eSSara Sharon 16392e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 16402e5d4a8fSHaim Dreyfuss 16412e5d4a8fSHaim Dreyfuss local_bh_disable(); 16422e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, entry->entry); 16432e5d4a8fSHaim Dreyfuss local_bh_enable(); 16442e5d4a8fSHaim Dreyfuss 16452e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 16462e5d4a8fSHaim Dreyfuss 16472e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 16482e5d4a8fSHaim Dreyfuss 16492e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 16502e5d4a8fSHaim Dreyfuss } 16512e5d4a8fSHaim Dreyfuss 1652e705c121SKalle Valo /* 1653e705c121SKalle Valo * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1654e705c121SKalle Valo */ 1655e705c121SKalle Valo static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1656e705c121SKalle Valo { 1657e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1658e705c121SKalle Valo int i; 1659e705c121SKalle Valo 1660e705c121SKalle Valo /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1661e705c121SKalle Valo if (trans->cfg->internal_wimax_coex && 1662e705c121SKalle Valo !trans->cfg->apmg_not_supported && 1663e705c121SKalle Valo (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1664e705c121SKalle Valo APMS_CLK_VAL_MRB_FUNC_MODE) || 1665e705c121SKalle Valo (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1666e705c121SKalle Valo APMG_PS_CTRL_VAL_RESET_REQ))) { 1667e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1668e705c121SKalle Valo iwl_op_mode_wimax_active(trans->op_mode); 1669e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1670e705c121SKalle Valo return; 1671e705c121SKalle Valo } 1672e705c121SKalle Valo 1673286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 167413a3a390SSara Sharon if (!trans_pcie->txq[i]) 167513a3a390SSara Sharon continue; 1676b2a3b1c1SSara Sharon del_timer(&trans_pcie->txq[i]->stuck_timer); 167713a3a390SSara Sharon } 1678e705c121SKalle Valo 16797d75f32eSEmmanuel Grumbach /* The STATUS_FW_ERROR bit is set in this function. This must happen 16807d75f32eSEmmanuel Grumbach * before we wake up the command caller, to ensure a proper cleanup. */ 16817d75f32eSEmmanuel Grumbach iwl_trans_fw_error(trans); 16827d75f32eSEmmanuel Grumbach 1683e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1684e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1685e705c121SKalle Valo } 1686e705c121SKalle Valo 1687e705c121SKalle Valo static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1688e705c121SKalle Valo { 1689e705c121SKalle Valo u32 inta; 1690e705c121SKalle Valo 1691e705c121SKalle Valo lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1692e705c121SKalle Valo 1693e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1694e705c121SKalle Valo 1695e705c121SKalle Valo /* Discover which interrupts are active/pending */ 1696e705c121SKalle Valo inta = iwl_read32(trans, CSR_INT); 1697e705c121SKalle Valo 1698e705c121SKalle Valo /* the thread will service interrupts and re-enable them */ 1699e705c121SKalle Valo return inta; 1700e705c121SKalle Valo } 1701e705c121SKalle Valo 1702e705c121SKalle Valo /* a device (PCI-E) page is 4096 bytes long */ 1703e705c121SKalle Valo #define ICT_SHIFT 12 1704e705c121SKalle Valo #define ICT_SIZE (1 << ICT_SHIFT) 1705e705c121SKalle Valo #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1706e705c121SKalle Valo 1707e705c121SKalle Valo /* interrupt handler using ict table, with this interrupt driver will 1708e705c121SKalle Valo * stop using INTA register to get device's interrupt, reading this register 1709e705c121SKalle Valo * is expensive, device will write interrupts in ICT dram table, increment 1710e705c121SKalle Valo * index then will fire interrupt to driver, driver will OR all ICT table 1711e705c121SKalle Valo * entries from current index up to table entry with 0 value. the result is 1712e705c121SKalle Valo * the interrupt we need to service, driver will set the entries back to 0 and 1713e705c121SKalle Valo * set index. 1714e705c121SKalle Valo */ 1715e705c121SKalle Valo static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1716e705c121SKalle Valo { 1717e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1718e705c121SKalle Valo u32 inta; 1719e705c121SKalle Valo u32 val = 0; 1720e705c121SKalle Valo u32 read; 1721e705c121SKalle Valo 1722e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1723e705c121SKalle Valo 1724e705c121SKalle Valo /* Ignore interrupt if there's nothing in NIC to service. 1725e705c121SKalle Valo * This may be due to IRQ shared with another device, 1726e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. */ 1727e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1728e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1729e705c121SKalle Valo if (!read) 1730e705c121SKalle Valo return 0; 1731e705c121SKalle Valo 1732e705c121SKalle Valo /* 1733e705c121SKalle Valo * Collect all entries up to the first 0, starting from ict_index; 1734e705c121SKalle Valo * note we already read at ict_index. 1735e705c121SKalle Valo */ 1736e705c121SKalle Valo do { 1737e705c121SKalle Valo val |= read; 1738e705c121SKalle Valo IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1739e705c121SKalle Valo trans_pcie->ict_index, read); 1740e705c121SKalle Valo trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1741e705c121SKalle Valo trans_pcie->ict_index = 1742e705c121SKalle Valo ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1743e705c121SKalle Valo 1744e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1745e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1746e705c121SKalle Valo read); 1747e705c121SKalle Valo } while (read); 1748e705c121SKalle Valo 1749e705c121SKalle Valo /* We should not get this value, just ignore it. */ 1750e705c121SKalle Valo if (val == 0xffffffff) 1751e705c121SKalle Valo val = 0; 1752e705c121SKalle Valo 1753e705c121SKalle Valo /* 1754e705c121SKalle Valo * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1755e705c121SKalle Valo * (bit 15 before shifting it to 31) to clear when using interrupt 1756e705c121SKalle Valo * coalescing. fortunately, bits 18 and 19 stay set when this happens 1757e705c121SKalle Valo * so we use them to decide on the real state of the Rx bit. 1758e705c121SKalle Valo * In order words, bit 15 is set if bit 18 or bit 19 are set. 1759e705c121SKalle Valo */ 1760e705c121SKalle Valo if (val & 0xC0000) 1761e705c121SKalle Valo val |= 0x8000; 1762e705c121SKalle Valo 1763e705c121SKalle Valo inta = (0xff & val) | ((0xff00 & val) << 16); 1764e705c121SKalle Valo return inta; 1765e705c121SKalle Valo } 1766e705c121SKalle Valo 1767fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 17683a6e168bSJohannes Berg { 17693a6e168bSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17703a6e168bSJohannes Berg struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1771326477e4SJohannes Berg bool hw_rfkill, prev, report; 17723a6e168bSJohannes Berg 17733a6e168bSJohannes Berg mutex_lock(&trans_pcie->mutex); 1774326477e4SJohannes Berg prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 17753a6e168bSJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1776326477e4SJohannes Berg if (hw_rfkill) { 1777326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1778326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1779326477e4SJohannes Berg } 1780326477e4SJohannes Berg if (trans_pcie->opmode_down) 1781326477e4SJohannes Berg report = hw_rfkill; 1782326477e4SJohannes Berg else 1783326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 17843a6e168bSJohannes Berg 17853a6e168bSJohannes Berg IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 17863a6e168bSJohannes Berg hw_rfkill ? "disable radio" : "enable radio"); 17873a6e168bSJohannes Berg 17883a6e168bSJohannes Berg isr_stats->rfkill++; 17893a6e168bSJohannes Berg 1790326477e4SJohannes Berg if (prev != report) 1791326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 17923a6e168bSJohannes Berg mutex_unlock(&trans_pcie->mutex); 17933a6e168bSJohannes Berg 17943a6e168bSJohannes Berg if (hw_rfkill) { 17953a6e168bSJohannes Berg if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 17963a6e168bSJohannes Berg &trans->status)) 17973a6e168bSJohannes Berg IWL_DEBUG_RF_KILL(trans, 17983a6e168bSJohannes Berg "Rfkill while SYNC HCMD in flight\n"); 17993a6e168bSJohannes Berg wake_up(&trans_pcie->wait_command_queue); 18003a6e168bSJohannes Berg } else { 1801326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1802326477e4SJohannes Berg if (trans_pcie->opmode_down) 1803326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 18043a6e168bSJohannes Berg } 18053a6e168bSJohannes Berg } 18063a6e168bSJohannes Berg 1807e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1808e705c121SKalle Valo { 1809e705c121SKalle Valo struct iwl_trans *trans = dev_id; 1810e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1811e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1812e705c121SKalle Valo u32 inta = 0; 1813e705c121SKalle Valo u32 handled = 0; 1814e705c121SKalle Valo 1815e705c121SKalle Valo lock_map_acquire(&trans->sync_cmd_lockdep_map); 1816e705c121SKalle Valo 1817e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1818e705c121SKalle Valo 1819e705c121SKalle Valo /* dram interrupt table not set yet, 1820e705c121SKalle Valo * use legacy interrupt. 1821e705c121SKalle Valo */ 1822e705c121SKalle Valo if (likely(trans_pcie->use_ict)) 1823e705c121SKalle Valo inta = iwl_pcie_int_cause_ict(trans); 1824e705c121SKalle Valo else 1825e705c121SKalle Valo inta = iwl_pcie_int_cause_non_ict(trans); 1826e705c121SKalle Valo 1827e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1828e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1829e705c121SKalle Valo "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1830e705c121SKalle Valo inta, trans_pcie->inta_mask, 1831e705c121SKalle Valo iwl_read32(trans, CSR_INT_MASK), 1832e705c121SKalle Valo iwl_read32(trans, CSR_FH_INT_STATUS)); 1833e705c121SKalle Valo if (inta & (~trans_pcie->inta_mask)) 1834e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1835e705c121SKalle Valo "We got a masked interrupt (0x%08x)\n", 1836e705c121SKalle Valo inta & (~trans_pcie->inta_mask)); 1837e705c121SKalle Valo } 1838e705c121SKalle Valo 1839e705c121SKalle Valo inta &= trans_pcie->inta_mask; 1840e705c121SKalle Valo 1841e705c121SKalle Valo /* 1842e705c121SKalle Valo * Ignore interrupt if there's nothing in NIC to service. 1843e705c121SKalle Valo * This may be due to IRQ shared with another device, 1844e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. 1845e705c121SKalle Valo */ 1846e705c121SKalle Valo if (unlikely(!inta)) { 1847e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1848e705c121SKalle Valo /* 1849e705c121SKalle Valo * Re-enable interrupts here since we don't 1850e705c121SKalle Valo * have anything to service 1851e705c121SKalle Valo */ 1852e705c121SKalle Valo if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1853f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 1854e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1855e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1856e705c121SKalle Valo return IRQ_NONE; 1857e705c121SKalle Valo } 1858e705c121SKalle Valo 1859e705c121SKalle Valo if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1860e705c121SKalle Valo /* 1861e705c121SKalle Valo * Hardware disappeared. It might have 1862e705c121SKalle Valo * already raised an interrupt. 1863e705c121SKalle Valo */ 1864e705c121SKalle Valo IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1865e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1866e705c121SKalle Valo goto out; 1867e705c121SKalle Valo } 1868e705c121SKalle Valo 1869e705c121SKalle Valo /* Ack/clear/reset pending uCode interrupts. 1870e705c121SKalle Valo * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1871e705c121SKalle Valo */ 1872e705c121SKalle Valo /* There is a hardware bug in the interrupt mask function that some 1873e705c121SKalle Valo * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1874e705c121SKalle Valo * they are disabled in the CSR_INT_MASK register. Furthermore the 1875e705c121SKalle Valo * ICT interrupt handling mechanism has another bug that might cause 1876e705c121SKalle Valo * these unmasked interrupts fail to be detected. We workaround the 1877e705c121SKalle Valo * hardware bugs here by ACKing all the possible interrupts so that 1878e705c121SKalle Valo * interrupt coalescing can still be achieved. 1879e705c121SKalle Valo */ 1880e705c121SKalle Valo iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1881e705c121SKalle Valo 1882e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) 1883e705c121SKalle Valo IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1884e705c121SKalle Valo inta, iwl_read32(trans, CSR_INT_MASK)); 1885e705c121SKalle Valo 1886e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1887e705c121SKalle Valo 1888e705c121SKalle Valo /* Now service all interrupt bits discovered above. */ 1889e705c121SKalle Valo if (inta & CSR_INT_BIT_HW_ERR) { 1890e705c121SKalle Valo IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1891e705c121SKalle Valo 1892e705c121SKalle Valo /* Tell the device to stop sending interrupts */ 1893e705c121SKalle Valo iwl_disable_interrupts(trans); 1894e705c121SKalle Valo 1895e705c121SKalle Valo isr_stats->hw++; 1896e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1897e705c121SKalle Valo 1898e705c121SKalle Valo handled |= CSR_INT_BIT_HW_ERR; 1899e705c121SKalle Valo 1900e705c121SKalle Valo goto out; 1901e705c121SKalle Valo } 1902e705c121SKalle Valo 1903e705c121SKalle Valo /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1904e705c121SKalle Valo if (inta & CSR_INT_BIT_SCD) { 1905e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1906e705c121SKalle Valo "Scheduler finished to transmit the frame/frames.\n"); 1907e705c121SKalle Valo isr_stats->sch++; 1908e705c121SKalle Valo } 1909e705c121SKalle Valo 1910e705c121SKalle Valo /* Alive notification via Rx interrupt will do the real work */ 1911e705c121SKalle Valo if (inta & CSR_INT_BIT_ALIVE) { 1912e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1913e705c121SKalle Valo isr_stats->alive++; 1914286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) { 1915eda50cdeSSara Sharon /* 1916eda50cdeSSara Sharon * We can restock, since firmware configured 1917eda50cdeSSara Sharon * the RFH 1918eda50cdeSSara Sharon */ 1919eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1920eda50cdeSSara Sharon } 1921ed3e4c6dSEmmanuel Grumbach 1922ed3e4c6dSEmmanuel Grumbach handled |= CSR_INT_BIT_ALIVE; 1923e705c121SKalle Valo } 1924e705c121SKalle Valo 1925e705c121SKalle Valo /* Safely ignore these bits for debug checks below */ 1926e705c121SKalle Valo inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1927e705c121SKalle Valo 1928e705c121SKalle Valo /* HW RF KILL switch toggled */ 1929e705c121SKalle Valo if (inta & CSR_INT_BIT_RF_KILL) { 19303a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 1931e705c121SKalle Valo handled |= CSR_INT_BIT_RF_KILL; 1932e705c121SKalle Valo } 1933e705c121SKalle Valo 1934e705c121SKalle Valo /* Chip got too hot and stopped itself */ 1935e705c121SKalle Valo if (inta & CSR_INT_BIT_CT_KILL) { 1936e705c121SKalle Valo IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1937e705c121SKalle Valo isr_stats->ctkill++; 1938e705c121SKalle Valo handled |= CSR_INT_BIT_CT_KILL; 1939e705c121SKalle Valo } 1940e705c121SKalle Valo 1941e705c121SKalle Valo /* Error detected by uCode */ 1942e705c121SKalle Valo if (inta & CSR_INT_BIT_SW_ERR) { 1943e705c121SKalle Valo IWL_ERR(trans, "Microcode SW error detected. " 1944e705c121SKalle Valo " Restarting 0x%X.\n", inta); 1945e705c121SKalle Valo isr_stats->sw++; 1946e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1947e705c121SKalle Valo handled |= CSR_INT_BIT_SW_ERR; 1948e705c121SKalle Valo } 1949e705c121SKalle Valo 1950e705c121SKalle Valo /* uCode wakes up after power-down sleep */ 1951e705c121SKalle Valo if (inta & CSR_INT_BIT_WAKEUP) { 1952e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1953e705c121SKalle Valo iwl_pcie_rxq_check_wrptr(trans); 1954e705c121SKalle Valo iwl_pcie_txq_check_wrptrs(trans); 1955e705c121SKalle Valo 1956e705c121SKalle Valo isr_stats->wakeup++; 1957e705c121SKalle Valo 1958e705c121SKalle Valo handled |= CSR_INT_BIT_WAKEUP; 1959e705c121SKalle Valo } 1960e705c121SKalle Valo 1961e705c121SKalle Valo /* All uCode command responses, including Tx command responses, 1962e705c121SKalle Valo * Rx "responses" (frame-received notification), and other 1963e705c121SKalle Valo * notifications from uCode come through here*/ 1964e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1965e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC)) { 1966e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1967e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1968e705c121SKalle Valo handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1969e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 1970e705c121SKalle Valo CSR_FH_INT_RX_MASK); 1971e705c121SKalle Valo } 1972e705c121SKalle Valo if (inta & CSR_INT_BIT_RX_PERIODIC) { 1973e705c121SKalle Valo handled |= CSR_INT_BIT_RX_PERIODIC; 1974e705c121SKalle Valo iwl_write32(trans, 1975e705c121SKalle Valo CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1976e705c121SKalle Valo } 1977e705c121SKalle Valo /* Sending RX interrupt require many steps to be done in the 1978e705c121SKalle Valo * the device: 1979e705c121SKalle Valo * 1- write interrupt to current index in ICT table. 1980e705c121SKalle Valo * 2- dma RX frame. 1981e705c121SKalle Valo * 3- update RX shared data to indicate last write index. 1982e705c121SKalle Valo * 4- send interrupt. 1983e705c121SKalle Valo * This could lead to RX race, driver could receive RX interrupt 1984e705c121SKalle Valo * but the shared data changes does not reflect this; 1985e705c121SKalle Valo * periodic interrupt will detect any dangling Rx activity. 1986e705c121SKalle Valo */ 1987e705c121SKalle Valo 1988e705c121SKalle Valo /* Disable periodic interrupt; we use it as just a one-shot. */ 1989e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1990e705c121SKalle Valo CSR_INT_PERIODIC_DIS); 1991e705c121SKalle Valo 1992e705c121SKalle Valo /* 1993e705c121SKalle Valo * Enable periodic interrupt in 8 msec only if we received 1994e705c121SKalle Valo * real RX interrupt (instead of just periodic int), to catch 1995e705c121SKalle Valo * any dangling Rx interrupt. If it was just the periodic 1996e705c121SKalle Valo * interrupt, there was no dangling Rx activity, and no need 1997e705c121SKalle Valo * to extend the periodic interrupt; one-shot is enough. 1998e705c121SKalle Valo */ 1999e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 2000e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 2001e705c121SKalle Valo CSR_INT_PERIODIC_ENA); 2002e705c121SKalle Valo 2003e705c121SKalle Valo isr_stats->rx++; 2004e705c121SKalle Valo 2005e705c121SKalle Valo local_bh_disable(); 20062e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, 0); 2007e705c121SKalle Valo local_bh_enable(); 2008e705c121SKalle Valo } 2009e705c121SKalle Valo 2010e705c121SKalle Valo /* This "Tx" DMA channel is used only for loading uCode */ 2011e705c121SKalle Valo if (inta & CSR_INT_BIT_FH_TX) { 2012e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 2013e705c121SKalle Valo IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 2014e705c121SKalle Valo isr_stats->tx++; 2015e705c121SKalle Valo handled |= CSR_INT_BIT_FH_TX; 2016e705c121SKalle Valo /* Wake up uCode load routine, now that load is complete */ 2017e705c121SKalle Valo trans_pcie->ucode_write_complete = true; 2018e705c121SKalle Valo wake_up(&trans_pcie->ucode_write_waitq); 2019e705c121SKalle Valo } 2020e705c121SKalle Valo 2021e705c121SKalle Valo if (inta & ~handled) { 2022e705c121SKalle Valo IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 2023e705c121SKalle Valo isr_stats->unhandled++; 2024e705c121SKalle Valo } 2025e705c121SKalle Valo 2026e705c121SKalle Valo if (inta & ~(trans_pcie->inta_mask)) { 2027e705c121SKalle Valo IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 2028e705c121SKalle Valo inta & ~trans_pcie->inta_mask); 2029e705c121SKalle Valo } 2030e705c121SKalle Valo 2031f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 2032a6bd005fSEmmanuel Grumbach /* only Re-enable all interrupt if disabled by irq */ 2033f16c3ebfSEmmanuel Grumbach if (test_bit(STATUS_INT_ENABLED, &trans->status)) 2034f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 2035f16c3ebfSEmmanuel Grumbach /* we are loading the firmware, enable FH_TX interrupt only */ 2036f16c3ebfSEmmanuel Grumbach else if (handled & CSR_INT_BIT_FH_TX) 2037f16c3ebfSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 2038e705c121SKalle Valo /* Re-enable RF_KILL if it occurred */ 2039e705c121SKalle Valo else if (handled & CSR_INT_BIT_RF_KILL) 2040e705c121SKalle Valo iwl_enable_rfkill_int(trans); 2041ed3e4c6dSEmmanuel Grumbach /* Re-enable the ALIVE / Rx interrupt if it occurred */ 2042ed3e4c6dSEmmanuel Grumbach else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX)) 2043ed3e4c6dSEmmanuel Grumbach iwl_enable_fw_load_int_ctx_info(trans); 2044f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 2045e705c121SKalle Valo 2046e705c121SKalle Valo out: 2047e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 2048e705c121SKalle Valo return IRQ_HANDLED; 2049e705c121SKalle Valo } 2050e705c121SKalle Valo 2051e705c121SKalle Valo /****************************************************************************** 2052e705c121SKalle Valo * 2053e705c121SKalle Valo * ICT functions 2054e705c121SKalle Valo * 2055e705c121SKalle Valo ******************************************************************************/ 2056e705c121SKalle Valo 2057e705c121SKalle Valo /* Free dram table */ 2058e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans) 2059e705c121SKalle Valo { 2060e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2061e705c121SKalle Valo 2062e705c121SKalle Valo if (trans_pcie->ict_tbl) { 2063e705c121SKalle Valo dma_free_coherent(trans->dev, ICT_SIZE, 2064e705c121SKalle Valo trans_pcie->ict_tbl, 2065e705c121SKalle Valo trans_pcie->ict_tbl_dma); 2066e705c121SKalle Valo trans_pcie->ict_tbl = NULL; 2067e705c121SKalle Valo trans_pcie->ict_tbl_dma = 0; 2068e705c121SKalle Valo } 2069e705c121SKalle Valo } 2070e705c121SKalle Valo 2071e705c121SKalle Valo /* 2072e705c121SKalle Valo * allocate dram shared table, it is an aligned memory 2073e705c121SKalle Valo * block of ICT_SIZE. 2074e705c121SKalle Valo * also reset all data related to ICT table interrupt. 2075e705c121SKalle Valo */ 2076e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans) 2077e705c121SKalle Valo { 2078e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2079e705c121SKalle Valo 2080e705c121SKalle Valo trans_pcie->ict_tbl = 2081750afb08SLuis Chamberlain dma_alloc_coherent(trans->dev, ICT_SIZE, 2082750afb08SLuis Chamberlain &trans_pcie->ict_tbl_dma, GFP_KERNEL); 2083e705c121SKalle Valo if (!trans_pcie->ict_tbl) 2084e705c121SKalle Valo return -ENOMEM; 2085e705c121SKalle Valo 2086e705c121SKalle Valo /* just an API sanity check ... it is guaranteed to be aligned */ 2087e705c121SKalle Valo if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 2088e705c121SKalle Valo iwl_pcie_free_ict(trans); 2089e705c121SKalle Valo return -EINVAL; 2090e705c121SKalle Valo } 2091e705c121SKalle Valo 2092e705c121SKalle Valo return 0; 2093e705c121SKalle Valo } 2094e705c121SKalle Valo 2095e705c121SKalle Valo /* Device is going up inform it about using ICT interrupt table, 2096e705c121SKalle Valo * also we need to tell the driver to start using ICT interrupt. 2097e705c121SKalle Valo */ 2098e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans) 2099e705c121SKalle Valo { 2100e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2101e705c121SKalle Valo u32 val; 2102e705c121SKalle Valo 2103e705c121SKalle Valo if (!trans_pcie->ict_tbl) 2104e705c121SKalle Valo return; 2105e705c121SKalle Valo 2106e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 2107f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 2108e705c121SKalle Valo 2109e705c121SKalle Valo memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 2110e705c121SKalle Valo 2111e705c121SKalle Valo val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 2112e705c121SKalle Valo 2113e705c121SKalle Valo val |= CSR_DRAM_INT_TBL_ENABLE | 2114e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRAP_CHECK | 2115e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRITE_POINTER; 2116e705c121SKalle Valo 2117e705c121SKalle Valo IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 2118e705c121SKalle Valo 2119e705c121SKalle Valo iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 2120e705c121SKalle Valo trans_pcie->use_ict = true; 2121e705c121SKalle Valo trans_pcie->ict_index = 0; 2122e705c121SKalle Valo iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 2123f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 2124e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 2125e705c121SKalle Valo } 2126e705c121SKalle Valo 2127e705c121SKalle Valo /* Device is going down disable ict interrupt usage */ 2128e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans) 2129e705c121SKalle Valo { 2130e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2131e705c121SKalle Valo 2132e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 2133e705c121SKalle Valo trans_pcie->use_ict = false; 2134e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 2135e705c121SKalle Valo } 2136e705c121SKalle Valo 2137e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data) 2138e705c121SKalle Valo { 2139e705c121SKalle Valo struct iwl_trans *trans = data; 2140e705c121SKalle Valo 2141e705c121SKalle Valo if (!trans) 2142e705c121SKalle Valo return IRQ_NONE; 2143e705c121SKalle Valo 2144e705c121SKalle Valo /* Disable (but don't clear!) interrupts here to avoid 2145e705c121SKalle Valo * back-to-back ISRs and sporadic interrupts from our NIC. 2146e705c121SKalle Valo * If we have something to service, the tasklet will re-enable ints. 2147e705c121SKalle Valo * If we *don't* have something, we'll re-enable before leaving here. 2148e705c121SKalle Valo */ 2149e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2150e705c121SKalle Valo 2151e705c121SKalle Valo return IRQ_WAKE_THREAD; 2152e705c121SKalle Valo } 21532e5d4a8fSHaim Dreyfuss 21542e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 21552e5d4a8fSHaim Dreyfuss { 21562e5d4a8fSHaim Dreyfuss return IRQ_WAKE_THREAD; 21572e5d4a8fSHaim Dreyfuss } 21582e5d4a8fSHaim Dreyfuss 21592e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 21602e5d4a8fSHaim Dreyfuss { 21612e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 21622e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 21632e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 216446167a8fSColin Ian King struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 21652e5d4a8fSHaim Dreyfuss u32 inta_fh, inta_hw; 21662e5d4a8fSHaim Dreyfuss 21672e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 21682e5d4a8fSHaim Dreyfuss 21692e5d4a8fSHaim Dreyfuss spin_lock(&trans_pcie->irq_lock); 21707ef3dd26SHaim Dreyfuss inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 21717ef3dd26SHaim Dreyfuss inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 21722e5d4a8fSHaim Dreyfuss /* 21732e5d4a8fSHaim Dreyfuss * Clear causes registers to avoid being handling the same cause. 21742e5d4a8fSHaim Dreyfuss */ 21757ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 21767ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 21772e5d4a8fSHaim Dreyfuss spin_unlock(&trans_pcie->irq_lock); 21782e5d4a8fSHaim Dreyfuss 2179c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2180c42ff65dSJohannes Berg 21812e5d4a8fSHaim Dreyfuss if (unlikely(!(inta_fh | inta_hw))) { 21822e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 21832e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 21842e5d4a8fSHaim Dreyfuss return IRQ_NONE; 21852e5d4a8fSHaim Dreyfuss } 21862e5d4a8fSHaim Dreyfuss 21873b57a10cSEmmanuel Grumbach if (iwl_have_debug_level(IWL_DL_ISR)) { 21883b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 21893b57a10cSEmmanuel Grumbach "ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 21903b57a10cSEmmanuel Grumbach inta_fh, trans_pcie->fh_mask, 21912e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 21923b57a10cSEmmanuel Grumbach if (inta_fh & ~trans_pcie->fh_mask) 21933b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 21943b57a10cSEmmanuel Grumbach "We got a masked interrupt (0x%08x)\n", 21953b57a10cSEmmanuel Grumbach inta_fh & ~trans_pcie->fh_mask); 21963b57a10cSEmmanuel Grumbach } 21973b57a10cSEmmanuel Grumbach 21983b57a10cSEmmanuel Grumbach inta_fh &= trans_pcie->fh_mask; 21992e5d4a8fSHaim Dreyfuss 2200496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2201496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2202496d83caSHaim Dreyfuss local_bh_disable(); 2203496d83caSHaim Dreyfuss iwl_pcie_rx_handle(trans, 0); 2204496d83caSHaim Dreyfuss local_bh_enable(); 2205496d83caSHaim Dreyfuss } 2206496d83caSHaim Dreyfuss 2207496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2208496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2209496d83caSHaim Dreyfuss local_bh_disable(); 2210496d83caSHaim Dreyfuss iwl_pcie_rx_handle(trans, 1); 2211496d83caSHaim Dreyfuss local_bh_enable(); 2212496d83caSHaim Dreyfuss } 2213496d83caSHaim Dreyfuss 22142e5d4a8fSHaim Dreyfuss /* This "Tx" DMA channel is used only for loading uCode */ 22152e5d4a8fSHaim Dreyfuss if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 22162e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 22172e5d4a8fSHaim Dreyfuss isr_stats->tx++; 22182e5d4a8fSHaim Dreyfuss /* 22192e5d4a8fSHaim Dreyfuss * Wake up uCode load routine, 22202e5d4a8fSHaim Dreyfuss * now that load is complete 22212e5d4a8fSHaim Dreyfuss */ 22222e5d4a8fSHaim Dreyfuss trans_pcie->ucode_write_complete = true; 22232e5d4a8fSHaim Dreyfuss wake_up(&trans_pcie->ucode_write_waitq); 22242e5d4a8fSHaim Dreyfuss } 22252e5d4a8fSHaim Dreyfuss 22262e5d4a8fSHaim Dreyfuss /* Error detected by uCode */ 22272e5d4a8fSHaim Dreyfuss if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 22283681021fSJohannes Berg (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) { 22292e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 22302e5d4a8fSHaim Dreyfuss "Microcode SW error detected. Restarting 0x%X.\n", 22312e5d4a8fSHaim Dreyfuss inta_fh); 22322e5d4a8fSHaim Dreyfuss isr_stats->sw++; 22332e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 22342e5d4a8fSHaim Dreyfuss } 22352e5d4a8fSHaim Dreyfuss 22362e5d4a8fSHaim Dreyfuss /* After checking FH register check HW register */ 22373b57a10cSEmmanuel Grumbach if (iwl_have_debug_level(IWL_DL_ISR)) { 22382e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, 22393b57a10cSEmmanuel Grumbach "ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 22403b57a10cSEmmanuel Grumbach inta_hw, trans_pcie->hw_mask, 22412e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 22423b57a10cSEmmanuel Grumbach if (inta_hw & ~trans_pcie->hw_mask) 22433b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 22443b57a10cSEmmanuel Grumbach "We got a masked interrupt 0x%08x\n", 22453b57a10cSEmmanuel Grumbach inta_hw & ~trans_pcie->hw_mask); 22463b57a10cSEmmanuel Grumbach } 22473b57a10cSEmmanuel Grumbach 22483b57a10cSEmmanuel Grumbach inta_hw &= trans_pcie->hw_mask; 22492e5d4a8fSHaim Dreyfuss 22502e5d4a8fSHaim Dreyfuss /* Alive notification via Rx interrupt will do the real work */ 22512e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 22522e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 22532e5d4a8fSHaim Dreyfuss isr_stats->alive++; 2254286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) { 2255eda50cdeSSara Sharon /* We can restock, since firmware configured the RFH */ 2256eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2257eda50cdeSSara Sharon } 22582e5d4a8fSHaim Dreyfuss } 22592e5d4a8fSHaim Dreyfuss 22603681021fSJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 2261e5f3f215SHaim Dreyfuss u32 sleep_notif = 2262e5f3f215SHaim Dreyfuss le32_to_cpu(trans_pcie->prph_info->sleep_notif); 2263e5f3f215SHaim Dreyfuss if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND || 2264e5f3f215SHaim Dreyfuss sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) { 2265e5f3f215SHaim Dreyfuss IWL_DEBUG_ISR(trans, 2266e5f3f215SHaim Dreyfuss "Sx interrupt: sleep notification = 0x%x\n", 2267e5f3f215SHaim Dreyfuss sleep_notif); 2268e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = true; 2269e5f3f215SHaim Dreyfuss wake_up(&trans_pcie->sx_waitq); 2270e5f3f215SHaim Dreyfuss } else { 22712e5d4a8fSHaim Dreyfuss /* uCode wakes up after power-down sleep */ 22722e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 22732e5d4a8fSHaim Dreyfuss iwl_pcie_rxq_check_wrptr(trans); 22742e5d4a8fSHaim Dreyfuss iwl_pcie_txq_check_wrptrs(trans); 22752e5d4a8fSHaim Dreyfuss 22762e5d4a8fSHaim Dreyfuss isr_stats->wakeup++; 22772e5d4a8fSHaim Dreyfuss } 2278e5f3f215SHaim Dreyfuss } 22792e5d4a8fSHaim Dreyfuss 2280ff911dcaSShaul Triebitz if (inta_hw & MSIX_HW_INT_CAUSES_REG_IML) { 2281ff911dcaSShaul Triebitz /* Reflect IML transfer status */ 2282ff911dcaSShaul Triebitz int res = iwl_read32(trans, CSR_IML_RESP_ADDR); 2283ff911dcaSShaul Triebitz 2284ff911dcaSShaul Triebitz IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res); 2285ff911dcaSShaul Triebitz if (res == IWL_IMAGE_RESP_FAIL) { 2286ff911dcaSShaul Triebitz isr_stats->sw++; 2287ff911dcaSShaul Triebitz iwl_pcie_irq_handle_error(trans); 2288ff911dcaSShaul Triebitz } 2289ff911dcaSShaul Triebitz } 2290ff911dcaSShaul Triebitz 22912e5d4a8fSHaim Dreyfuss /* Chip got too hot and stopped itself */ 22922e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 22932e5d4a8fSHaim Dreyfuss IWL_ERR(trans, "Microcode CT kill error detected.\n"); 22942e5d4a8fSHaim Dreyfuss isr_stats->ctkill++; 22952e5d4a8fSHaim Dreyfuss } 22962e5d4a8fSHaim Dreyfuss 22972e5d4a8fSHaim Dreyfuss /* HW RF KILL switch toggled */ 22983a6e168bSJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 22993a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 23002e5d4a8fSHaim Dreyfuss 23012e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 23022e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 23032e5d4a8fSHaim Dreyfuss "Hardware error detected. Restarting.\n"); 23042e5d4a8fSHaim Dreyfuss 23052e5d4a8fSHaim Dreyfuss isr_stats->hw++; 230691c28b83SShahar S Matityahu trans->dbg.hw_error = true; 23072e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 23082e5d4a8fSHaim Dreyfuss } 23092e5d4a8fSHaim Dreyfuss 23102e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 23112e5d4a8fSHaim Dreyfuss 23122e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 23132e5d4a8fSHaim Dreyfuss 23142e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 23152e5d4a8fSHaim Dreyfuss } 2316