1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 4e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 7e705c121SKalle Valo * 8e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 9e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 10e705c121SKalle Valo * 11e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 12e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 13e705c121SKalle Valo * published by the Free Software Foundation. 14e705c121SKalle Valo * 15e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 16e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18e705c121SKalle Valo * more details. 19e705c121SKalle Valo * 20e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 219b58419eSGolan Ben Ami * this program. 22e705c121SKalle Valo * 23e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 24e705c121SKalle Valo * file called LICENSE. 25e705c121SKalle Valo * 26e705c121SKalle Valo * Contact Information: 27d01c5366SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 28e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29e705c121SKalle Valo * 30e705c121SKalle Valo *****************************************************************************/ 31e705c121SKalle Valo #include <linux/sched.h> 32e705c121SKalle Valo #include <linux/wait.h> 33e705c121SKalle Valo #include <linux/gfp.h> 34e705c121SKalle Valo 35e705c121SKalle Valo #include "iwl-prph.h" 36e705c121SKalle Valo #include "iwl-io.h" 37e705c121SKalle Valo #include "internal.h" 38e705c121SKalle Valo #include "iwl-op-mode.h" 399b58419eSGolan Ben Ami #include "iwl-context-info-gen3.h" 40e705c121SKalle Valo 41e705c121SKalle Valo /****************************************************************************** 42e705c121SKalle Valo * 43e705c121SKalle Valo * RX path functions 44e705c121SKalle Valo * 45e705c121SKalle Valo ******************************************************************************/ 46e705c121SKalle Valo 47e705c121SKalle Valo /* 48e705c121SKalle Valo * Rx theory of operation 49e705c121SKalle Valo * 50e705c121SKalle Valo * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 51e705c121SKalle Valo * each of which point to Receive Buffers to be filled by the NIC. These get 52e705c121SKalle Valo * used not only for Rx frames, but for any command response or notification 53e705c121SKalle Valo * from the NIC. The driver and NIC manage the Rx buffers by means 54e705c121SKalle Valo * of indexes into the circular buffer. 55e705c121SKalle Valo * 56e705c121SKalle Valo * Rx Queue Indexes 57e705c121SKalle Valo * The host/firmware share two index registers for managing the Rx buffers. 58e705c121SKalle Valo * 59e705c121SKalle Valo * The READ index maps to the first position that the firmware may be writing 60e705c121SKalle Valo * to -- the driver can read up to (but not including) this position and get 61e705c121SKalle Valo * good data. 62e705c121SKalle Valo * The READ index is managed by the firmware once the card is enabled. 63e705c121SKalle Valo * 64e705c121SKalle Valo * The WRITE index maps to the last position the driver has read from -- the 65e705c121SKalle Valo * position preceding WRITE is the last slot the firmware can place a packet. 66e705c121SKalle Valo * 67e705c121SKalle Valo * The queue is empty (no good data) if WRITE = READ - 1, and is full if 68e705c121SKalle Valo * WRITE = READ. 69e705c121SKalle Valo * 70e705c121SKalle Valo * During initialization, the host sets up the READ queue position to the first 71e705c121SKalle Valo * INDEX position, and WRITE to the last (READ - 1 wrapped) 72e705c121SKalle Valo * 73e705c121SKalle Valo * When the firmware places a packet in a buffer, it will advance the READ index 74e705c121SKalle Valo * and fire the RX interrupt. The driver can then query the READ index and 75e705c121SKalle Valo * process as many packets as possible, moving the WRITE index forward as it 76e705c121SKalle Valo * resets the Rx queue buffers with new memory. 77e705c121SKalle Valo * 78e705c121SKalle Valo * The management in the driver is as follows: 79e705c121SKalle Valo * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 80e705c121SKalle Valo * When the interrupt handler is called, the request is processed. 81e705c121SKalle Valo * The page is either stolen - transferred to the upper layer 82e705c121SKalle Valo * or reused - added immediately to the iwl->rxq->rx_free list. 83e705c121SKalle Valo * + When the page is stolen - the driver updates the matching queue's used 84e705c121SKalle Valo * count, detaches the RBD and transfers it to the queue used list. 85e705c121SKalle Valo * When there are two used RBDs - they are transferred to the allocator empty 86e705c121SKalle Valo * list. Work is then scheduled for the allocator to start allocating 87e705c121SKalle Valo * eight buffers. 88e705c121SKalle Valo * When there are another 6 used RBDs - they are transferred to the allocator 89e705c121SKalle Valo * empty list and the driver tries to claim the pre-allocated buffers and 90e705c121SKalle Valo * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 91e705c121SKalle Valo * until ready. 92e705c121SKalle Valo * When there are 8+ buffers in the free list - either from allocation or from 93e705c121SKalle Valo * 8 reused unstolen pages - restock is called to update the FW and indexes. 94e705c121SKalle Valo * + In order to make sure the allocator always has RBDs to use for allocation 95e705c121SKalle Valo * the allocator has initial pool in the size of num_queues*(8-2) - the 96e705c121SKalle Valo * maximum missing RBDs per allocation request (request posted with 2 97e705c121SKalle Valo * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 98e705c121SKalle Valo * The queues supplies the recycle of the rest of the RBDs. 99e705c121SKalle Valo * + A received packet is processed and handed to the kernel network stack, 100e705c121SKalle Valo * detached from the iwl->rxq. The driver 'processed' index is updated. 101e705c121SKalle Valo * + If there are no allocated buffers in iwl->rxq->rx_free, 102e705c121SKalle Valo * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 103e705c121SKalle Valo * If there were enough free buffers and RX_STALLED is set it is cleared. 104e705c121SKalle Valo * 105e705c121SKalle Valo * 106e705c121SKalle Valo * Driver sequence: 107e705c121SKalle Valo * 108e705c121SKalle Valo * iwl_rxq_alloc() Allocates rx_free 109e705c121SKalle Valo * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 110e705c121SKalle Valo * iwl_pcie_rxq_restock. 111e705c121SKalle Valo * Used only during initialization. 112e705c121SKalle Valo * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 113e705c121SKalle Valo * queue, updates firmware pointers, and updates 114e705c121SKalle Valo * the WRITE index. 115e705c121SKalle Valo * iwl_pcie_rx_allocator() Background work for allocating pages. 116e705c121SKalle Valo * 117e705c121SKalle Valo * -- enable interrupts -- 118e705c121SKalle Valo * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 119e705c121SKalle Valo * READ INDEX, detaching the SKB from the pool. 120e705c121SKalle Valo * Moves the packet buffer from queue to rx_used. 121e705c121SKalle Valo * Posts and claims requests to the allocator. 122e705c121SKalle Valo * Calls iwl_pcie_rxq_restock to refill any empty 123e705c121SKalle Valo * slots. 124e705c121SKalle Valo * 125e705c121SKalle Valo * RBD life-cycle: 126e705c121SKalle Valo * 127e705c121SKalle Valo * Init: 128e705c121SKalle Valo * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 129e705c121SKalle Valo * 130e705c121SKalle Valo * Regular Receive interrupt: 131e705c121SKalle Valo * Page Stolen: 132e705c121SKalle Valo * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 133e705c121SKalle Valo * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 134e705c121SKalle Valo * Page not Stolen: 135e705c121SKalle Valo * rxq.queue -> rxq.rx_free -> rxq.queue 136e705c121SKalle Valo * ... 137e705c121SKalle Valo * 138e705c121SKalle Valo */ 139e705c121SKalle Valo 140e705c121SKalle Valo /* 141e705c121SKalle Valo * iwl_rxq_space - Return number of free slots available in queue. 142e705c121SKalle Valo */ 143e705c121SKalle Valo static int iwl_rxq_space(const struct iwl_rxq *rxq) 144e705c121SKalle Valo { 14596a6497bSSara Sharon /* Make sure rx queue size is a power of 2 */ 14696a6497bSSara Sharon WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 147e705c121SKalle Valo 148e705c121SKalle Valo /* 149e705c121SKalle Valo * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 150e705c121SKalle Valo * between empty and completely full queues. 151e705c121SKalle Valo * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 152e705c121SKalle Valo * defined for negative dividends. 153e705c121SKalle Valo */ 15496a6497bSSara Sharon return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 155e705c121SKalle Valo } 156e705c121SKalle Valo 157e705c121SKalle Valo /* 158e705c121SKalle Valo * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 159e705c121SKalle Valo */ 160e705c121SKalle Valo static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 161e705c121SKalle Valo { 162e705c121SKalle Valo return cpu_to_le32((u32)(dma_addr >> 8)); 163e705c121SKalle Valo } 164e705c121SKalle Valo 165e705c121SKalle Valo /* 166e705c121SKalle Valo * iwl_pcie_rx_stop - stops the Rx DMA 167e705c121SKalle Valo */ 168e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans) 169e705c121SKalle Valo { 170d7fdd0e5SSara Sharon if (trans->cfg->mq_rx_supported) { 171d7fdd0e5SSara Sharon iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 172d7fdd0e5SSara Sharon return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 173d7fdd0e5SSara Sharon RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 174d7fdd0e5SSara Sharon } else { 175e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 176e705c121SKalle Valo return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 177d7fdd0e5SSara Sharon FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 178d7fdd0e5SSara Sharon 1000); 179d7fdd0e5SSara Sharon } 180e705c121SKalle Valo } 181e705c121SKalle Valo 182e705c121SKalle Valo /* 183e705c121SKalle Valo * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 184e705c121SKalle Valo */ 18578485054SSara Sharon static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 18678485054SSara Sharon struct iwl_rxq *rxq) 187e705c121SKalle Valo { 188e705c121SKalle Valo u32 reg; 189e705c121SKalle Valo 190e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 191e705c121SKalle Valo 192e705c121SKalle Valo /* 193e705c121SKalle Valo * explicitly wake up the NIC if: 194e705c121SKalle Valo * 1. shadow registers aren't enabled 195e705c121SKalle Valo * 2. there is a chance that the NIC is asleep 196e705c121SKalle Valo */ 197e705c121SKalle Valo if (!trans->cfg->base_params->shadow_reg_enable && 198e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 199e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 200e705c121SKalle Valo 201e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 202e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 203e705c121SKalle Valo reg); 204e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 205a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 206e705c121SKalle Valo rxq->need_update = true; 207e705c121SKalle Valo return; 208e705c121SKalle Valo } 209e705c121SKalle Valo } 210e705c121SKalle Valo 211e705c121SKalle Valo rxq->write_actual = round_down(rxq->write, 8); 2121b493e30SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 2131b493e30SGolan Ben Ami iwl_write32(trans, HBUS_TARG_WRPTR, 2141b493e30SGolan Ben Ami (rxq->write_actual | 2151b493e30SGolan Ben Ami ((FIRST_RX_QUEUE + rxq->id) << 16))); 2161b493e30SGolan Ben Ami else if (trans->cfg->mq_rx_supported) 2171554ed20SSara Sharon iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 21896a6497bSSara Sharon rxq->write_actual); 2191316d595SSara Sharon else 220e705c121SKalle Valo iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 221e705c121SKalle Valo } 222e705c121SKalle Valo 223e705c121SKalle Valo static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 224e705c121SKalle Valo { 225e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 22678485054SSara Sharon int i; 227e705c121SKalle Valo 22878485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 22978485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 230e705c121SKalle Valo 231e705c121SKalle Valo if (!rxq->need_update) 23278485054SSara Sharon continue; 23378485054SSara Sharon spin_lock(&rxq->lock); 23478485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 235e705c121SKalle Valo rxq->need_update = false; 236e705c121SKalle Valo spin_unlock(&rxq->lock); 237e705c121SKalle Valo } 23878485054SSara Sharon } 239e705c121SKalle Valo 240e0e168dcSGregory Greenman /* 2412047fa54SSara Sharon * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 242e0e168dcSGregory Greenman */ 2432047fa54SSara Sharon static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 24496a6497bSSara Sharon struct iwl_rxq *rxq) 24596a6497bSSara Sharon { 24696a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb; 24796a6497bSSara Sharon 24896a6497bSSara Sharon /* 24996a6497bSSara Sharon * If the device isn't enabled - no need to try to add buffers... 25096a6497bSSara Sharon * This can happen when we stop the device and still have an interrupt 25196a6497bSSara Sharon * pending. We stop the APM before we sync the interrupts because we 25296a6497bSSara Sharon * have to (see comment there). On the other hand, since the APM is 25396a6497bSSara Sharon * stopped, we cannot access the HW (in particular not prph). 25496a6497bSSara Sharon * So don't try to restock if the APM has been already stopped. 25596a6497bSSara Sharon */ 25696a6497bSSara Sharon if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 25796a6497bSSara Sharon return; 25896a6497bSSara Sharon 25996a6497bSSara Sharon spin_lock(&rxq->lock); 26096a6497bSSara Sharon while (rxq->free_count) { 26196a6497bSSara Sharon __le64 *bd = (__le64 *)rxq->bd; 26296a6497bSSara Sharon 26396a6497bSSara Sharon /* Get next free Rx buffer, remove from free list */ 26496a6497bSSara Sharon rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 26596a6497bSSara Sharon list); 26696a6497bSSara Sharon list_del(&rxb->list); 267b1753c62SSara Sharon rxb->invalid = false; 26896a6497bSSara Sharon /* 12 first bits are expected to be empty */ 26996a6497bSSara Sharon WARN_ON(rxb->page_dma & DMA_BIT_MASK(12)); 27096a6497bSSara Sharon /* Point to Rx buffer via next RBD in circular buffer */ 27196a6497bSSara Sharon bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 27296a6497bSSara Sharon rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK; 27396a6497bSSara Sharon rxq->free_count--; 27496a6497bSSara Sharon } 27596a6497bSSara Sharon spin_unlock(&rxq->lock); 27696a6497bSSara Sharon 27796a6497bSSara Sharon /* 27896a6497bSSara Sharon * If we've added more space for the firmware to place data, tell it. 27996a6497bSSara Sharon * Increment device's write pointer in multiples of 8. 28096a6497bSSara Sharon */ 28196a6497bSSara Sharon if (rxq->write_actual != (rxq->write & ~0x7)) { 28296a6497bSSara Sharon spin_lock(&rxq->lock); 28396a6497bSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 28496a6497bSSara Sharon spin_unlock(&rxq->lock); 28596a6497bSSara Sharon } 28696a6497bSSara Sharon } 28796a6497bSSara Sharon 288e705c121SKalle Valo /* 2892047fa54SSara Sharon * iwl_pcie_rxsq_restock - restock implementation for single queue rx 290e705c121SKalle Valo */ 2912047fa54SSara Sharon static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 292e0e168dcSGregory Greenman struct iwl_rxq *rxq) 293e705c121SKalle Valo { 294e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 295e705c121SKalle Valo 296e705c121SKalle Valo /* 297e705c121SKalle Valo * If the device isn't enabled - not need to try to add buffers... 298e705c121SKalle Valo * This can happen when we stop the device and still have an interrupt 299e705c121SKalle Valo * pending. We stop the APM before we sync the interrupts because we 300e705c121SKalle Valo * have to (see comment there). On the other hand, since the APM is 301e705c121SKalle Valo * stopped, we cannot access the HW (in particular not prph). 302e705c121SKalle Valo * So don't try to restock if the APM has been already stopped. 303e705c121SKalle Valo */ 304e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 305e705c121SKalle Valo return; 306e705c121SKalle Valo 307e705c121SKalle Valo spin_lock(&rxq->lock); 308e705c121SKalle Valo while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 30996a6497bSSara Sharon __le32 *bd = (__le32 *)rxq->bd; 310e705c121SKalle Valo /* The overwritten rxb must be a used one */ 311e705c121SKalle Valo rxb = rxq->queue[rxq->write]; 312e705c121SKalle Valo BUG_ON(rxb && rxb->page); 313e705c121SKalle Valo 314e705c121SKalle Valo /* Get next free Rx buffer, remove from free list */ 315e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 316e705c121SKalle Valo list); 317e705c121SKalle Valo list_del(&rxb->list); 318b1753c62SSara Sharon rxb->invalid = false; 319e705c121SKalle Valo 320e705c121SKalle Valo /* Point to Rx buffer via next RBD in circular buffer */ 32196a6497bSSara Sharon bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 322e705c121SKalle Valo rxq->queue[rxq->write] = rxb; 323e705c121SKalle Valo rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 324e705c121SKalle Valo rxq->free_count--; 325e705c121SKalle Valo } 326e705c121SKalle Valo spin_unlock(&rxq->lock); 327e705c121SKalle Valo 328e705c121SKalle Valo /* If we've added more space for the firmware to place data, tell it. 329e705c121SKalle Valo * Increment device's write pointer in multiples of 8. */ 330e705c121SKalle Valo if (rxq->write_actual != (rxq->write & ~0x7)) { 331e705c121SKalle Valo spin_lock(&rxq->lock); 33278485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 333e705c121SKalle Valo spin_unlock(&rxq->lock); 334e705c121SKalle Valo } 335e705c121SKalle Valo } 336e705c121SKalle Valo 337e705c121SKalle Valo /* 338e0e168dcSGregory Greenman * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 339e0e168dcSGregory Greenman * 340e0e168dcSGregory Greenman * If there are slots in the RX queue that need to be restocked, 341e0e168dcSGregory Greenman * and we have free pre-allocated buffers, fill the ranks as much 342e0e168dcSGregory Greenman * as we can, pulling from rx_free. 343e0e168dcSGregory Greenman * 344e0e168dcSGregory Greenman * This moves the 'write' index forward to catch up with 'processed', and 345e0e168dcSGregory Greenman * also updates the memory address in the firmware to reference the new 346e0e168dcSGregory Greenman * target buffer. 347e0e168dcSGregory Greenman */ 348e0e168dcSGregory Greenman static 349e0e168dcSGregory Greenman void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 350e0e168dcSGregory Greenman { 351e0e168dcSGregory Greenman if (trans->cfg->mq_rx_supported) 3522047fa54SSara Sharon iwl_pcie_rxmq_restock(trans, rxq); 353e0e168dcSGregory Greenman else 3542047fa54SSara Sharon iwl_pcie_rxsq_restock(trans, rxq); 355e0e168dcSGregory Greenman } 356e0e168dcSGregory Greenman 357e0e168dcSGregory Greenman /* 358e705c121SKalle Valo * iwl_pcie_rx_alloc_page - allocates and returns a page. 359e705c121SKalle Valo * 360e705c121SKalle Valo */ 361e705c121SKalle Valo static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 362e705c121SKalle Valo gfp_t priority) 363e705c121SKalle Valo { 364e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 365e705c121SKalle Valo struct page *page; 366e705c121SKalle Valo gfp_t gfp_mask = priority; 367e705c121SKalle Valo 368e705c121SKalle Valo if (trans_pcie->rx_page_order > 0) 369e705c121SKalle Valo gfp_mask |= __GFP_COMP; 370e705c121SKalle Valo 371e705c121SKalle Valo /* Alloc a new receive buffer */ 372e705c121SKalle Valo page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 373e705c121SKalle Valo if (!page) { 374e705c121SKalle Valo if (net_ratelimit()) 375e705c121SKalle Valo IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 376e705c121SKalle Valo trans_pcie->rx_page_order); 37778485054SSara Sharon /* 37878485054SSara Sharon * Issue an error if we don't have enough pre-allocated 37978485054SSara Sharon * buffers. 380e705c121SKalle Valo ` */ 38178485054SSara Sharon if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 382e705c121SKalle Valo IWL_CRIT(trans, 38378485054SSara Sharon "Failed to alloc_pages\n"); 384e705c121SKalle Valo return NULL; 385e705c121SKalle Valo } 386e705c121SKalle Valo return page; 387e705c121SKalle Valo } 388e705c121SKalle Valo 389e705c121SKalle Valo /* 390e705c121SKalle Valo * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 391e705c121SKalle Valo * 392e705c121SKalle Valo * A used RBD is an Rx buffer that has been given to the stack. To use it again 393e705c121SKalle Valo * a page must be allocated and the RBD must point to the page. This function 394e705c121SKalle Valo * doesn't change the HW pointer but handles the list of pages that is used by 395e705c121SKalle Valo * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 396e705c121SKalle Valo * allocated buffers. 397e705c121SKalle Valo */ 39878485054SSara Sharon static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 39978485054SSara Sharon struct iwl_rxq *rxq) 400e705c121SKalle Valo { 401e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 402e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 403e705c121SKalle Valo struct page *page; 404e705c121SKalle Valo 405e705c121SKalle Valo while (1) { 406e705c121SKalle Valo spin_lock(&rxq->lock); 407e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 408e705c121SKalle Valo spin_unlock(&rxq->lock); 409e705c121SKalle Valo return; 410e705c121SKalle Valo } 411e705c121SKalle Valo spin_unlock(&rxq->lock); 412e705c121SKalle Valo 413e705c121SKalle Valo /* Alloc a new receive buffer */ 414e705c121SKalle Valo page = iwl_pcie_rx_alloc_page(trans, priority); 415e705c121SKalle Valo if (!page) 416e705c121SKalle Valo return; 417e705c121SKalle Valo 418e705c121SKalle Valo spin_lock(&rxq->lock); 419e705c121SKalle Valo 420e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 421e705c121SKalle Valo spin_unlock(&rxq->lock); 422e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 423e705c121SKalle Valo return; 424e705c121SKalle Valo } 425e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 426e705c121SKalle Valo list); 427e705c121SKalle Valo list_del(&rxb->list); 428e705c121SKalle Valo spin_unlock(&rxq->lock); 429e705c121SKalle Valo 430e705c121SKalle Valo BUG_ON(rxb->page); 431e705c121SKalle Valo rxb->page = page; 432e705c121SKalle Valo /* Get physical address of the RB */ 433e705c121SKalle Valo rxb->page_dma = 434e705c121SKalle Valo dma_map_page(trans->dev, page, 0, 435e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 436e705c121SKalle Valo DMA_FROM_DEVICE); 437e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 438e705c121SKalle Valo rxb->page = NULL; 439e705c121SKalle Valo spin_lock(&rxq->lock); 440e705c121SKalle Valo list_add(&rxb->list, &rxq->rx_used); 441e705c121SKalle Valo spin_unlock(&rxq->lock); 442e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 443e705c121SKalle Valo return; 444e705c121SKalle Valo } 445e705c121SKalle Valo 446e705c121SKalle Valo spin_lock(&rxq->lock); 447e705c121SKalle Valo 448e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 449e705c121SKalle Valo rxq->free_count++; 450e705c121SKalle Valo 451e705c121SKalle Valo spin_unlock(&rxq->lock); 452e705c121SKalle Valo } 453e705c121SKalle Valo } 454e705c121SKalle Valo 45578485054SSara Sharon static void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 456e705c121SKalle Valo { 457e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 458e705c121SKalle Valo int i; 459e705c121SKalle Valo 4607b542436SSara Sharon for (i = 0; i < RX_POOL_SIZE; i++) { 46178485054SSara Sharon if (!trans_pcie->rx_pool[i].page) 462e705c121SKalle Valo continue; 46378485054SSara Sharon dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 464e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 465e705c121SKalle Valo DMA_FROM_DEVICE); 46678485054SSara Sharon __free_pages(trans_pcie->rx_pool[i].page, 46778485054SSara Sharon trans_pcie->rx_page_order); 46878485054SSara Sharon trans_pcie->rx_pool[i].page = NULL; 469e705c121SKalle Valo } 470e705c121SKalle Valo } 471e705c121SKalle Valo 472e705c121SKalle Valo /* 473e705c121SKalle Valo * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 474e705c121SKalle Valo * 475e705c121SKalle Valo * Allocates for each received request 8 pages 476e705c121SKalle Valo * Called as a scheduled work item. 477e705c121SKalle Valo */ 478e705c121SKalle Valo static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 479e705c121SKalle Valo { 480e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 481e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 482e705c121SKalle Valo struct list_head local_empty; 483e705c121SKalle Valo int pending = atomic_xchg(&rba->req_pending, 0); 484e705c121SKalle Valo 485e705c121SKalle Valo IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending); 486e705c121SKalle Valo 487e705c121SKalle Valo /* If we were scheduled - there is at least one request */ 488e705c121SKalle Valo spin_lock(&rba->lock); 489e705c121SKalle Valo /* swap out the rba->rbd_empty to a local list */ 490e705c121SKalle Valo list_replace_init(&rba->rbd_empty, &local_empty); 491e705c121SKalle Valo spin_unlock(&rba->lock); 492e705c121SKalle Valo 493e705c121SKalle Valo while (pending) { 494e705c121SKalle Valo int i; 4950979a913SJohannes Berg LIST_HEAD(local_allocated); 49678485054SSara Sharon gfp_t gfp_mask = GFP_KERNEL; 49778485054SSara Sharon 49878485054SSara Sharon /* Do not post a warning if there are only a few requests */ 49978485054SSara Sharon if (pending < RX_PENDING_WATERMARK) 50078485054SSara Sharon gfp_mask |= __GFP_NOWARN; 501e705c121SKalle Valo 502e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 503e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 504e705c121SKalle Valo struct page *page; 505e705c121SKalle Valo 506e705c121SKalle Valo /* List should never be empty - each reused RBD is 507e705c121SKalle Valo * returned to the list, and initial pool covers any 508e705c121SKalle Valo * possible gap between the time the page is allocated 509e705c121SKalle Valo * to the time the RBD is added. 510e705c121SKalle Valo */ 511e705c121SKalle Valo BUG_ON(list_empty(&local_empty)); 512e705c121SKalle Valo /* Get the first rxb from the rbd list */ 513e705c121SKalle Valo rxb = list_first_entry(&local_empty, 514e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 515e705c121SKalle Valo BUG_ON(rxb->page); 516e705c121SKalle Valo 517e705c121SKalle Valo /* Alloc a new receive buffer */ 51878485054SSara Sharon page = iwl_pcie_rx_alloc_page(trans, gfp_mask); 519e705c121SKalle Valo if (!page) 520e705c121SKalle Valo continue; 521e705c121SKalle Valo rxb->page = page; 522e705c121SKalle Valo 523e705c121SKalle Valo /* Get physical address of the RB */ 524e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, page, 0, 525e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 526e705c121SKalle Valo DMA_FROM_DEVICE); 527e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 528e705c121SKalle Valo rxb->page = NULL; 529e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 530e705c121SKalle Valo continue; 531e705c121SKalle Valo } 532e705c121SKalle Valo 533e705c121SKalle Valo /* move the allocated entry to the out list */ 534e705c121SKalle Valo list_move(&rxb->list, &local_allocated); 535e705c121SKalle Valo i++; 536e705c121SKalle Valo } 537e705c121SKalle Valo 538e705c121SKalle Valo pending--; 539e705c121SKalle Valo if (!pending) { 540e705c121SKalle Valo pending = atomic_xchg(&rba->req_pending, 0); 541e705c121SKalle Valo IWL_DEBUG_RX(trans, 542e705c121SKalle Valo "Pending allocation requests = %d\n", 543e705c121SKalle Valo pending); 544e705c121SKalle Valo } 545e705c121SKalle Valo 546e705c121SKalle Valo spin_lock(&rba->lock); 547e705c121SKalle Valo /* add the allocated rbds to the allocator allocated list */ 548e705c121SKalle Valo list_splice_tail(&local_allocated, &rba->rbd_allocated); 549e705c121SKalle Valo /* get more empty RBDs for current pending requests */ 550e705c121SKalle Valo list_splice_tail_init(&rba->rbd_empty, &local_empty); 551e705c121SKalle Valo spin_unlock(&rba->lock); 552e705c121SKalle Valo 553e705c121SKalle Valo atomic_inc(&rba->req_ready); 554e705c121SKalle Valo } 555e705c121SKalle Valo 556e705c121SKalle Valo spin_lock(&rba->lock); 557e705c121SKalle Valo /* return unused rbds to the allocator empty list */ 558e705c121SKalle Valo list_splice_tail(&local_empty, &rba->rbd_empty); 559e705c121SKalle Valo spin_unlock(&rba->lock); 560e705c121SKalle Valo } 561e705c121SKalle Valo 562e705c121SKalle Valo /* 563d56daea4SSara Sharon * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 564e705c121SKalle Valo .* 565e705c121SKalle Valo .* Called by queue when the queue posted allocation request and 566e705c121SKalle Valo * has freed 8 RBDs in order to restock itself. 567d56daea4SSara Sharon * This function directly moves the allocated RBs to the queue's ownership 568d56daea4SSara Sharon * and updates the relevant counters. 569e705c121SKalle Valo */ 570d56daea4SSara Sharon static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 571d56daea4SSara Sharon struct iwl_rxq *rxq) 572e705c121SKalle Valo { 573e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 574e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 575e705c121SKalle Valo int i; 576e705c121SKalle Valo 577d56daea4SSara Sharon lockdep_assert_held(&rxq->lock); 578d56daea4SSara Sharon 579e705c121SKalle Valo /* 580e705c121SKalle Valo * atomic_dec_if_positive returns req_ready - 1 for any scenario. 581e705c121SKalle Valo * If req_ready is 0 atomic_dec_if_positive will return -1 and this 582d56daea4SSara Sharon * function will return early, as there are no ready requests. 583e705c121SKalle Valo * atomic_dec_if_positive will perofrm the *actual* decrement only if 584e705c121SKalle Valo * req_ready > 0, i.e. - there are ready requests and the function 585e705c121SKalle Valo * hands one request to the caller. 586e705c121SKalle Valo */ 587e705c121SKalle Valo if (atomic_dec_if_positive(&rba->req_ready) < 0) 588d56daea4SSara Sharon return; 589e705c121SKalle Valo 590e705c121SKalle Valo spin_lock(&rba->lock); 591e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 592e705c121SKalle Valo /* Get next free Rx buffer, remove it from free list */ 593d56daea4SSara Sharon struct iwl_rx_mem_buffer *rxb = 594d56daea4SSara Sharon list_first_entry(&rba->rbd_allocated, 595e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 596d56daea4SSara Sharon 597d56daea4SSara Sharon list_move(&rxb->list, &rxq->rx_free); 598e705c121SKalle Valo } 599e705c121SKalle Valo spin_unlock(&rba->lock); 600e705c121SKalle Valo 601d56daea4SSara Sharon rxq->used_count -= RX_CLAIM_REQ_ALLOC; 602d56daea4SSara Sharon rxq->free_count += RX_CLAIM_REQ_ALLOC; 603e705c121SKalle Valo } 604e705c121SKalle Valo 60510a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data) 606e705c121SKalle Valo { 607e705c121SKalle Valo struct iwl_rb_allocator *rba_p = 608e705c121SKalle Valo container_of(data, struct iwl_rb_allocator, rx_alloc); 609e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 610e705c121SKalle Valo container_of(rba_p, struct iwl_trans_pcie, rba); 611e705c121SKalle Valo 612e705c121SKalle Valo iwl_pcie_rx_allocator(trans_pcie->trans); 613e705c121SKalle Valo } 614e705c121SKalle Valo 6151b493e30SGolan Ben Ami static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 6161b493e30SGolan Ben Ami struct iwl_rxq *rxq) 6171b493e30SGolan Ben Ami { 6181b493e30SGolan Ben Ami struct device *dev = trans->dev; 6191b493e30SGolan Ben Ami int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) : 6201b493e30SGolan Ben Ami sizeof(__le32); 6211b493e30SGolan Ben Ami 6221b493e30SGolan Ben Ami if (rxq->bd) 6231b493e30SGolan Ben Ami dma_free_coherent(dev, free_size * rxq->queue_size, 6241b493e30SGolan Ben Ami rxq->bd, rxq->bd_dma); 6251b493e30SGolan Ben Ami rxq->bd_dma = 0; 6261b493e30SGolan Ben Ami rxq->bd = NULL; 6271b493e30SGolan Ben Ami 6281b493e30SGolan Ben Ami if (rxq->rb_stts) 6291b493e30SGolan Ben Ami dma_free_coherent(trans->dev, 6301b493e30SGolan Ben Ami sizeof(struct iwl_rb_status), 6311b493e30SGolan Ben Ami rxq->rb_stts, rxq->rb_stts_dma); 6321b493e30SGolan Ben Ami rxq->rb_stts_dma = 0; 6331b493e30SGolan Ben Ami rxq->rb_stts = NULL; 6341b493e30SGolan Ben Ami 6351b493e30SGolan Ben Ami if (rxq->used_bd) 6361b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le32) * rxq->queue_size, 6371b493e30SGolan Ben Ami rxq->used_bd, rxq->used_bd_dma); 6381b493e30SGolan Ben Ami rxq->used_bd_dma = 0; 6391b493e30SGolan Ben Ami rxq->used_bd = NULL; 6401b493e30SGolan Ben Ami 6411b493e30SGolan Ben Ami if (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) 6421b493e30SGolan Ben Ami return; 6431b493e30SGolan Ben Ami 6441b493e30SGolan Ben Ami if (rxq->tr_tail) 6451b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 6461b493e30SGolan Ben Ami rxq->tr_tail, rxq->tr_tail_dma); 6471b493e30SGolan Ben Ami rxq->tr_tail_dma = 0; 6481b493e30SGolan Ben Ami rxq->tr_tail = NULL; 6491b493e30SGolan Ben Ami 6501b493e30SGolan Ben Ami if (rxq->cr_tail) 6511b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 6521b493e30SGolan Ben Ami rxq->cr_tail, rxq->cr_tail_dma); 6531b493e30SGolan Ben Ami rxq->cr_tail_dma = 0; 6541b493e30SGolan Ben Ami rxq->cr_tail = NULL; 6551b493e30SGolan Ben Ami } 6561b493e30SGolan Ben Ami 6571b493e30SGolan Ben Ami static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 6581b493e30SGolan Ben Ami struct iwl_rxq *rxq) 659e705c121SKalle Valo { 660e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 661e705c121SKalle Valo struct device *dev = trans->dev; 66278485054SSara Sharon int i; 66396a6497bSSara Sharon int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) : 66496a6497bSSara Sharon sizeof(__le32); 665e705c121SKalle Valo 66678485054SSara Sharon spin_lock_init(&rxq->lock); 66796a6497bSSara Sharon if (trans->cfg->mq_rx_supported) 66896a6497bSSara Sharon rxq->queue_size = MQ_RX_TABLE_SIZE; 66996a6497bSSara Sharon else 67096a6497bSSara Sharon rxq->queue_size = RX_QUEUE_SIZE; 67196a6497bSSara Sharon 67278485054SSara Sharon /* 67378485054SSara Sharon * Allocate the circular buffer of Read Buffer Descriptors 67478485054SSara Sharon * (RBDs) 67578485054SSara Sharon */ 67678485054SSara Sharon rxq->bd = dma_zalloc_coherent(dev, 67796a6497bSSara Sharon free_size * rxq->queue_size, 678e705c121SKalle Valo &rxq->bd_dma, GFP_KERNEL); 679e705c121SKalle Valo if (!rxq->bd) 68078485054SSara Sharon goto err; 68178485054SSara Sharon 68296a6497bSSara Sharon if (trans->cfg->mq_rx_supported) { 68396a6497bSSara Sharon rxq->used_bd = dma_zalloc_coherent(dev, 68496a6497bSSara Sharon sizeof(__le32) * 68596a6497bSSara Sharon rxq->queue_size, 68696a6497bSSara Sharon &rxq->used_bd_dma, 68796a6497bSSara Sharon GFP_KERNEL); 68896a6497bSSara Sharon if (!rxq->used_bd) 68996a6497bSSara Sharon goto err; 69096a6497bSSara Sharon } 691e705c121SKalle Valo 692e705c121SKalle Valo /* Allocate the driver's pointer to receive buffer status */ 693e705c121SKalle Valo rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts), 69478485054SSara Sharon &rxq->rb_stts_dma, 69578485054SSara Sharon GFP_KERNEL); 696e705c121SKalle Valo if (!rxq->rb_stts) 69778485054SSara Sharon goto err; 6981b493e30SGolan Ben Ami 6991b493e30SGolan Ben Ami if (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) 7001b493e30SGolan Ben Ami return 0; 7011b493e30SGolan Ben Ami 7021b493e30SGolan Ben Ami /* Allocate the driver's pointer to TR tail */ 7031b493e30SGolan Ben Ami rxq->tr_tail = dma_zalloc_coherent(dev, sizeof(__le16), 7041b493e30SGolan Ben Ami &rxq->tr_tail_dma, 7051b493e30SGolan Ben Ami GFP_KERNEL); 7061b493e30SGolan Ben Ami if (!rxq->tr_tail) 7071b493e30SGolan Ben Ami goto err; 7081b493e30SGolan Ben Ami 7091b493e30SGolan Ben Ami /* Allocate the driver's pointer to CR tail */ 7101b493e30SGolan Ben Ami rxq->cr_tail = dma_zalloc_coherent(dev, sizeof(__le16), 7111b493e30SGolan Ben Ami &rxq->cr_tail_dma, 7121b493e30SGolan Ben Ami GFP_KERNEL); 7131b493e30SGolan Ben Ami if (!rxq->cr_tail) 7141b493e30SGolan Ben Ami goto err; 7151b493e30SGolan Ben Ami 716e705c121SKalle Valo return 0; 717e705c121SKalle Valo 71878485054SSara Sharon err: 71978485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 72078485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 72178485054SSara Sharon 7221b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 72378485054SSara Sharon } 72478485054SSara Sharon kfree(trans_pcie->rxq); 72596a6497bSSara Sharon 726e705c121SKalle Valo return -ENOMEM; 727e705c121SKalle Valo } 728e705c121SKalle Valo 7291b493e30SGolan Ben Ami static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 7301b493e30SGolan Ben Ami { 7311b493e30SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 7321b493e30SGolan Ben Ami struct iwl_rb_allocator *rba = &trans_pcie->rba; 7331b493e30SGolan Ben Ami int i, ret; 7341b493e30SGolan Ben Ami 7351b493e30SGolan Ben Ami if (WARN_ON(trans_pcie->rxq)) 7361b493e30SGolan Ben Ami return -EINVAL; 7371b493e30SGolan Ben Ami 7381b493e30SGolan Ben Ami trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 7391b493e30SGolan Ben Ami GFP_KERNEL); 7401b493e30SGolan Ben Ami if (!trans_pcie->rxq) 7411b493e30SGolan Ben Ami return -EINVAL; 7421b493e30SGolan Ben Ami 7431b493e30SGolan Ben Ami spin_lock_init(&rba->lock); 7441b493e30SGolan Ben Ami 7451b493e30SGolan Ben Ami for (i = 0; i < trans->num_rx_queues; i++) { 7461b493e30SGolan Ben Ami struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 7471b493e30SGolan Ben Ami 7481b493e30SGolan Ben Ami ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 7491b493e30SGolan Ben Ami if (ret) 7501b493e30SGolan Ben Ami return ret; 7511b493e30SGolan Ben Ami } 7521b493e30SGolan Ben Ami return 0; 7531b493e30SGolan Ben Ami } 7541b493e30SGolan Ben Ami 755e705c121SKalle Valo static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 756e705c121SKalle Valo { 757e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 758e705c121SKalle Valo u32 rb_size; 759dfcfeef9SSara Sharon unsigned long flags; 760e705c121SKalle Valo const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 761e705c121SKalle Valo 7626c4fbcbcSEmmanuel Grumbach switch (trans_pcie->rx_buf_size) { 7636c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 764e705c121SKalle Valo rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 7656c4fbcbcSEmmanuel Grumbach break; 7666c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 7676c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 7686c4fbcbcSEmmanuel Grumbach break; 7696c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 7706c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 7716c4fbcbcSEmmanuel Grumbach break; 7726c4fbcbcSEmmanuel Grumbach default: 7736c4fbcbcSEmmanuel Grumbach WARN_ON(1); 7746c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 7756c4fbcbcSEmmanuel Grumbach } 776e705c121SKalle Valo 777dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 778dfcfeef9SSara Sharon return; 779dfcfeef9SSara Sharon 780e705c121SKalle Valo /* Stop Rx DMA */ 781dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 782e705c121SKalle Valo /* reset and flush pointers */ 783dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 784dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 785dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 786e705c121SKalle Valo 787e705c121SKalle Valo /* Reset driver's Rx queue write index */ 788dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 789e705c121SKalle Valo 790e705c121SKalle Valo /* Tell device where to find RBD circular buffer in DRAM */ 791dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 792e705c121SKalle Valo (u32)(rxq->bd_dma >> 8)); 793e705c121SKalle Valo 794e705c121SKalle Valo /* Tell device where in DRAM to update its Rx status */ 795dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 796e705c121SKalle Valo rxq->rb_stts_dma >> 4); 797e705c121SKalle Valo 798e705c121SKalle Valo /* Enable Rx DMA 799e705c121SKalle Valo * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 800e705c121SKalle Valo * the credit mechanism in 5000 HW RX FIFO 801e705c121SKalle Valo * Direct rx interrupts to hosts 8026c4fbcbcSEmmanuel Grumbach * Rx buffer size 4 or 8k or 12k 803e705c121SKalle Valo * RB timeout 0x10 804e705c121SKalle Valo * 256 RBDs 805e705c121SKalle Valo */ 806dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 807e705c121SKalle Valo FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 808e705c121SKalle Valo FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 809e705c121SKalle Valo FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 810e705c121SKalle Valo rb_size | 811e705c121SKalle Valo (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 812e705c121SKalle Valo (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 813e705c121SKalle Valo 814dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 815dfcfeef9SSara Sharon 816e705c121SKalle Valo /* Set interrupt coalescing timer to default (2048 usecs) */ 817e705c121SKalle Valo iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 818e705c121SKalle Valo 819e705c121SKalle Valo /* W/A for interrupt coalescing bug in 7260 and 3160 */ 820e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) 821e705c121SKalle Valo iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 822e705c121SKalle Valo } 823e705c121SKalle Valo 8241316d595SSara Sharon void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable) 8251316d595SSara Sharon { 826565291c6SJohannes Berg if (trans->cfg->device_family != IWL_DEVICE_FAMILY_9000) 827565291c6SJohannes Berg return; 828565291c6SJohannes Berg 829565291c6SJohannes Berg if (CSR_HW_REV_STEP(trans->hw_rev) != SILICON_A_STEP) 830565291c6SJohannes Berg return; 831565291c6SJohannes Berg 832565291c6SJohannes Berg if (!trans->cfg->integrated) 833565291c6SJohannes Berg return; 834565291c6SJohannes Berg 8351316d595SSara Sharon /* 8361316d595SSara Sharon * Turn on the chicken-bits that cause MAC wakeup for RX-related 8371316d595SSara Sharon * values. 8381316d595SSara Sharon * This costs some power, but needed for W/A 9000 integrated A-step 8391316d595SSara Sharon * bug where shadow registers are not in the retention list and their 8401316d595SSara Sharon * value is lost when NIC powers down 8411316d595SSara Sharon */ 8421316d595SSara Sharon iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 8431316d595SSara Sharon CSR_MAC_SHADOW_REG_CTRL_RX_WAKE); 8441316d595SSara Sharon iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTL2, 8451316d595SSara Sharon CSR_MAC_SHADOW_REG_CTL2_RX_WAKE); 8461316d595SSara Sharon } 8471316d595SSara Sharon 848bce97731SSara Sharon static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 84996a6497bSSara Sharon { 85096a6497bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 85196a6497bSSara Sharon u32 rb_size, enabled = 0; 852dfcfeef9SSara Sharon unsigned long flags; 85396a6497bSSara Sharon int i; 85496a6497bSSara Sharon 85596a6497bSSara Sharon switch (trans_pcie->rx_buf_size) { 85696a6497bSSara Sharon case IWL_AMSDU_4K: 85796a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 85896a6497bSSara Sharon break; 85996a6497bSSara Sharon case IWL_AMSDU_8K: 86096a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_8K; 86196a6497bSSara Sharon break; 86296a6497bSSara Sharon case IWL_AMSDU_12K: 86396a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_12K; 86496a6497bSSara Sharon break; 86596a6497bSSara Sharon default: 86696a6497bSSara Sharon WARN_ON(1); 86796a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 86896a6497bSSara Sharon } 86996a6497bSSara Sharon 870dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 871dfcfeef9SSara Sharon return; 872dfcfeef9SSara Sharon 87396a6497bSSara Sharon /* Stop Rx DMA */ 874dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 87596a6497bSSara Sharon /* disable free amd used rx queue operation */ 876dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 87796a6497bSSara Sharon 87896a6497bSSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 87996a6497bSSara Sharon /* Tell device where to find RBD free table in DRAM */ 88012a17458SSara Sharon iwl_write_prph64_no_grab(trans, 881dfcfeef9SSara Sharon RFH_Q_FRBDCB_BA_LSB(i), 882dfcfeef9SSara Sharon trans_pcie->rxq[i].bd_dma); 88396a6497bSSara Sharon /* Tell device where to find RBD used table in DRAM */ 88412a17458SSara Sharon iwl_write_prph64_no_grab(trans, 885dfcfeef9SSara Sharon RFH_Q_URBDCB_BA_LSB(i), 886dfcfeef9SSara Sharon trans_pcie->rxq[i].used_bd_dma); 88796a6497bSSara Sharon /* Tell device where in DRAM to update its Rx status */ 88812a17458SSara Sharon iwl_write_prph64_no_grab(trans, 889dfcfeef9SSara Sharon RFH_Q_URBD_STTS_WPTR_LSB(i), 890bce97731SSara Sharon trans_pcie->rxq[i].rb_stts_dma); 89196a6497bSSara Sharon /* Reset device indice tables */ 892dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 893dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 894dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 89596a6497bSSara Sharon 89696a6497bSSara Sharon enabled |= BIT(i) | BIT(i + 16); 89796a6497bSSara Sharon } 89896a6497bSSara Sharon 89996a6497bSSara Sharon /* 90096a6497bSSara Sharon * Enable Rx DMA 90196a6497bSSara Sharon * Rx buffer size 4 or 8k or 12k 90296a6497bSSara Sharon * Min RB size 4 or 8 90388076015SSara Sharon * Drop frames that exceed RB size 90496a6497bSSara Sharon * 512 RBDs 90596a6497bSSara Sharon */ 906dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 90763044335SSara Sharon RFH_DMA_EN_ENABLE_VAL | rb_size | 90896a6497bSSara Sharon RFH_RXF_DMA_MIN_RB_4_8 | 90988076015SSara Sharon RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 91096a6497bSSara Sharon RFH_RXF_DMA_RBDCB_SIZE_512); 91196a6497bSSara Sharon 91288076015SSara Sharon /* 91388076015SSara Sharon * Activate DMA snooping. 914b0262f07SSara Sharon * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 91588076015SSara Sharon * Default queue is 0 91688076015SSara Sharon */ 917f3779f47SJohannes Berg iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 918f3779f47SJohannes Berg RFH_GEN_CFG_RFH_DMA_SNOOP | 919f3779f47SJohannes Berg RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 920b0262f07SSara Sharon RFH_GEN_CFG_SERVICE_DMA_SNOOP | 921f3779f47SJohannes Berg RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 922f3779f47SJohannes Berg trans->cfg->integrated ? 923b0262f07SSara Sharon RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 924f3779f47SJohannes Berg RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 92588076015SSara Sharon /* Enable the relevant rx queues */ 926dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 927dfcfeef9SSara Sharon 928dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 92996a6497bSSara Sharon 93096a6497bSSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 93196a6497bSSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 9321316d595SSara Sharon 9331316d595SSara Sharon iwl_pcie_enable_rx_wake(trans, true); 93496a6497bSSara Sharon } 93596a6497bSSara Sharon 936e705c121SKalle Valo static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 937e705c121SKalle Valo { 938e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 939e705c121SKalle Valo 940e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_free); 941e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_used); 942e705c121SKalle Valo rxq->free_count = 0; 943e705c121SKalle Valo rxq->used_count = 0; 944e705c121SKalle Valo } 945e705c121SKalle Valo 946bce97731SSara Sharon static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) 947bce97731SSara Sharon { 948bce97731SSara Sharon WARN_ON(1); 949bce97731SSara Sharon return 0; 950bce97731SSara Sharon } 951bce97731SSara Sharon 952eda50cdeSSara Sharon static int _iwl_pcie_rx_init(struct iwl_trans *trans) 953e705c121SKalle Valo { 954e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 95578485054SSara Sharon struct iwl_rxq *def_rxq; 956e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 9577b542436SSara Sharon int i, err, queue_size, allocator_pool_size, num_alloc; 958e705c121SKalle Valo 95978485054SSara Sharon if (!trans_pcie->rxq) { 960e705c121SKalle Valo err = iwl_pcie_rx_alloc(trans); 961e705c121SKalle Valo if (err) 962e705c121SKalle Valo return err; 963e705c121SKalle Valo } 96478485054SSara Sharon def_rxq = trans_pcie->rxq; 965e705c121SKalle Valo 9660f22e400SShaul Triebitz cancel_work_sync(&rba->rx_alloc); 9670f22e400SShaul Triebitz 968e705c121SKalle Valo spin_lock(&rba->lock); 969e705c121SKalle Valo atomic_set(&rba->req_pending, 0); 970e705c121SKalle Valo atomic_set(&rba->req_ready, 0); 97196a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_allocated); 97296a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_empty); 973e705c121SKalle Valo spin_unlock(&rba->lock); 974e705c121SKalle Valo 975e705c121SKalle Valo /* free all first - we might be reconfigured for a different size */ 97678485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 977e705c121SKalle Valo 978e705c121SKalle Valo for (i = 0; i < RX_QUEUE_SIZE; i++) 97978485054SSara Sharon def_rxq->queue[i] = NULL; 980e705c121SKalle Valo 98178485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 98278485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 983e705c121SKalle Valo 98496a6497bSSara Sharon rxq->id = i; 98596a6497bSSara Sharon 986e705c121SKalle Valo spin_lock(&rxq->lock); 98778485054SSara Sharon /* 98878485054SSara Sharon * Set read write pointer to reflect that we have processed 98978485054SSara Sharon * and used all buffers, but have not restocked the Rx queue 99078485054SSara Sharon * with fresh buffers 99178485054SSara Sharon */ 99278485054SSara Sharon rxq->read = 0; 99378485054SSara Sharon rxq->write = 0; 99478485054SSara Sharon rxq->write_actual = 0; 99578485054SSara Sharon memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts)); 99678485054SSara Sharon 99778485054SSara Sharon iwl_pcie_rx_init_rxb_lists(rxq); 99878485054SSara Sharon 999bce97731SSara Sharon if (!rxq->napi.poll) 1000bce97731SSara Sharon netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 1001bce97731SSara Sharon iwl_pcie_dummy_napi_poll, 64); 1002bce97731SSara Sharon 1003e705c121SKalle Valo spin_unlock(&rxq->lock); 100478485054SSara Sharon } 100578485054SSara Sharon 100696a6497bSSara Sharon /* move the pool to the default queue and allocator ownerships */ 10077b542436SSara Sharon queue_size = trans->cfg->mq_rx_supported ? 10087b542436SSara Sharon MQ_RX_NUM_RBDS : RX_QUEUE_SIZE; 100996a6497bSSara Sharon allocator_pool_size = trans->num_rx_queues * 101096a6497bSSara Sharon (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 10117b542436SSara Sharon num_alloc = queue_size + allocator_pool_size; 101243146925SSara Sharon BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) != 101343146925SSara Sharon ARRAY_SIZE(trans_pcie->rx_pool)); 10147b542436SSara Sharon for (i = 0; i < num_alloc; i++) { 101596a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 101696a6497bSSara Sharon 101796a6497bSSara Sharon if (i < allocator_pool_size) 101896a6497bSSara Sharon list_add(&rxb->list, &rba->rbd_empty); 101996a6497bSSara Sharon else 102096a6497bSSara Sharon list_add(&rxb->list, &def_rxq->rx_used); 102196a6497bSSara Sharon trans_pcie->global_table[i] = rxb; 1022e25d65f2SSara Sharon rxb->vid = (u16)(i + 1); 1023b1753c62SSara Sharon rxb->invalid = true; 102496a6497bSSara Sharon } 102578485054SSara Sharon 102678485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 10272047fa54SSara Sharon 1028eda50cdeSSara Sharon return 0; 1029eda50cdeSSara Sharon } 1030eda50cdeSSara Sharon 1031eda50cdeSSara Sharon int iwl_pcie_rx_init(struct iwl_trans *trans) 1032eda50cdeSSara Sharon { 1033eda50cdeSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1034eda50cdeSSara Sharon int ret = _iwl_pcie_rx_init(trans); 1035eda50cdeSSara Sharon 1036eda50cdeSSara Sharon if (ret) 1037eda50cdeSSara Sharon return ret; 1038eda50cdeSSara Sharon 10392047fa54SSara Sharon if (trans->cfg->mq_rx_supported) 1040bce97731SSara Sharon iwl_pcie_rx_mq_hw_init(trans); 10412047fa54SSara Sharon else 1042eda50cdeSSara Sharon iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 10432047fa54SSara Sharon 1044eda50cdeSSara Sharon iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 104578485054SSara Sharon 1046eda50cdeSSara Sharon spin_lock(&trans_pcie->rxq->lock); 1047eda50cdeSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 1048eda50cdeSSara Sharon spin_unlock(&trans_pcie->rxq->lock); 1049e705c121SKalle Valo 1050e705c121SKalle Valo return 0; 1051e705c121SKalle Valo } 1052e705c121SKalle Valo 1053eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1054eda50cdeSSara Sharon { 1055eda50cdeSSara Sharon /* 1056eda50cdeSSara Sharon * We don't configure the RFH. 1057eda50cdeSSara Sharon * Restock will be done at alive, after firmware configured the RFH. 1058eda50cdeSSara Sharon */ 1059eda50cdeSSara Sharon return _iwl_pcie_rx_init(trans); 1060eda50cdeSSara Sharon } 1061eda50cdeSSara Sharon 1062e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans) 1063e705c121SKalle Valo { 1064e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1065e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 106678485054SSara Sharon int i; 1067e705c121SKalle Valo 106878485054SSara Sharon /* 106978485054SSara Sharon * if rxq is NULL, it means that nothing has been allocated, 107078485054SSara Sharon * exit now 107178485054SSara Sharon */ 107278485054SSara Sharon if (!trans_pcie->rxq) { 1073e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1074e705c121SKalle Valo return; 1075e705c121SKalle Valo } 1076e705c121SKalle Valo 1077e705c121SKalle Valo cancel_work_sync(&rba->rx_alloc); 1078e705c121SKalle Valo 107978485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1080e705c121SKalle Valo 108178485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 108278485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 108378485054SSara Sharon 10841b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 1085bce97731SSara Sharon 1086bce97731SSara Sharon if (rxq->napi.poll) 1087bce97731SSara Sharon netif_napi_del(&rxq->napi); 108896a6497bSSara Sharon } 108978485054SSara Sharon kfree(trans_pcie->rxq); 1090e705c121SKalle Valo } 1091e705c121SKalle Valo 1092e705c121SKalle Valo /* 1093e705c121SKalle Valo * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1094e705c121SKalle Valo * 1095e705c121SKalle Valo * Called when a RBD can be reused. The RBD is transferred to the allocator. 1096e705c121SKalle Valo * When there are 2 empty RBDs - a request for allocation is posted 1097e705c121SKalle Valo */ 1098e705c121SKalle Valo static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1099e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 1100e705c121SKalle Valo struct iwl_rxq *rxq, bool emergency) 1101e705c121SKalle Valo { 1102e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1103e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 1104e705c121SKalle Valo 1105e705c121SKalle Valo /* Move the RBD to the used list, will be moved to allocator in batches 1106e705c121SKalle Valo * before claiming or posting a request*/ 1107e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_used); 1108e705c121SKalle Valo 1109e705c121SKalle Valo if (unlikely(emergency)) 1110e705c121SKalle Valo return; 1111e705c121SKalle Valo 1112e705c121SKalle Valo /* Count the allocator owned RBDs */ 1113e705c121SKalle Valo rxq->used_count++; 1114e705c121SKalle Valo 1115e705c121SKalle Valo /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1116e705c121SKalle Valo * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1117e705c121SKalle Valo * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1118e705c121SKalle Valo * after but we still need to post another request. 1119e705c121SKalle Valo */ 1120e705c121SKalle Valo if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1121e705c121SKalle Valo /* Move the 2 RBDs to the allocator ownership. 1122e705c121SKalle Valo Allocator has another 6 from pool for the request completion*/ 1123e705c121SKalle Valo spin_lock(&rba->lock); 1124e705c121SKalle Valo list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1125e705c121SKalle Valo spin_unlock(&rba->lock); 1126e705c121SKalle Valo 1127e705c121SKalle Valo atomic_inc(&rba->req_pending); 1128e705c121SKalle Valo queue_work(rba->alloc_wq, &rba->rx_alloc); 1129e705c121SKalle Valo } 1130e705c121SKalle Valo } 1131e705c121SKalle Valo 1132e705c121SKalle Valo static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 113378485054SSara Sharon struct iwl_rxq *rxq, 1134e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 1135e705c121SKalle Valo bool emergency) 1136e705c121SKalle Valo { 1137e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1138b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1139e705c121SKalle Valo bool page_stolen = false; 1140e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 1141e705c121SKalle Valo u32 offset = 0; 1142e705c121SKalle Valo 1143e705c121SKalle Valo if (WARN_ON(!rxb)) 1144e705c121SKalle Valo return; 1145e705c121SKalle Valo 1146e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1147e705c121SKalle Valo 1148e705c121SKalle Valo while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1149e705c121SKalle Valo struct iwl_rx_packet *pkt; 1150e705c121SKalle Valo u16 sequence; 1151e705c121SKalle Valo bool reclaim; 1152e705c121SKalle Valo int index, cmd_index, len; 1153e705c121SKalle Valo struct iwl_rx_cmd_buffer rxcb = { 1154e705c121SKalle Valo ._offset = offset, 1155e705c121SKalle Valo ._rx_page_order = trans_pcie->rx_page_order, 1156e705c121SKalle Valo ._page = rxb->page, 1157e705c121SKalle Valo ._page_stolen = false, 1158e705c121SKalle Valo .truesize = max_len, 1159e705c121SKalle Valo }; 1160e705c121SKalle Valo 1161e705c121SKalle Valo pkt = rxb_addr(&rxcb); 1162e705c121SKalle Valo 11633bfdee76SJohannes Berg if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 11643bfdee76SJohannes Berg IWL_DEBUG_RX(trans, 11653bfdee76SJohannes Berg "Q %d: RB end marker at offset %d\n", 11663bfdee76SJohannes Berg rxq->id, offset); 1167e705c121SKalle Valo break; 11683bfdee76SJohannes Berg } 1169e705c121SKalle Valo 1170a395058eSJohannes Berg WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1171a395058eSJohannes Berg FH_RSCSR_RXQ_POS != rxq->id, 1172a395058eSJohannes Berg "frame on invalid queue - is on %d and indicates %d\n", 1173a395058eSJohannes Berg rxq->id, 1174a395058eSJohannes Berg (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1175a395058eSJohannes Berg FH_RSCSR_RXQ_POS); 1176ab2e696bSSara Sharon 1177e705c121SKalle Valo IWL_DEBUG_RX(trans, 11783bfdee76SJohannes Berg "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 11793bfdee76SJohannes Berg rxq->id, offset, 118039bdb17eSSharon Dvir iwl_get_cmd_string(trans, 118139bdb17eSSharon Dvir iwl_cmd_id(pkt->hdr.cmd, 118239bdb17eSSharon Dvir pkt->hdr.group_id, 118339bdb17eSSharon Dvir 0)), 118435177c99SSara Sharon pkt->hdr.group_id, pkt->hdr.cmd, 118535177c99SSara Sharon le16_to_cpu(pkt->hdr.sequence)); 1186e705c121SKalle Valo 1187e705c121SKalle Valo len = iwl_rx_packet_len(pkt); 1188e705c121SKalle Valo len += sizeof(u32); /* account for status word */ 1189e705c121SKalle Valo trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1190e705c121SKalle Valo trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1191e705c121SKalle Valo 1192e705c121SKalle Valo /* Reclaim a command buffer only if this packet is a response 1193e705c121SKalle Valo * to a (driver-originated) command. 1194e705c121SKalle Valo * If the packet (e.g. Rx frame) originated from uCode, 1195e705c121SKalle Valo * there is no command buffer to reclaim. 1196e705c121SKalle Valo * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1197e705c121SKalle Valo * but apparently a few don't get set; catch them here. */ 1198e705c121SKalle Valo reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1199d8a130b0SJohannes Berg if (reclaim && !pkt->hdr.group_id) { 1200e705c121SKalle Valo int i; 1201e705c121SKalle Valo 1202e705c121SKalle Valo for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1203e705c121SKalle Valo if (trans_pcie->no_reclaim_cmds[i] == 1204e705c121SKalle Valo pkt->hdr.cmd) { 1205e705c121SKalle Valo reclaim = false; 1206e705c121SKalle Valo break; 1207e705c121SKalle Valo } 1208e705c121SKalle Valo } 1209e705c121SKalle Valo } 1210e705c121SKalle Valo 1211e705c121SKalle Valo sequence = le16_to_cpu(pkt->hdr.sequence); 1212e705c121SKalle Valo index = SEQ_TO_INDEX(sequence); 12134ecab561SEmmanuel Grumbach cmd_index = iwl_pcie_get_cmd_index(txq, index); 1214e705c121SKalle Valo 1215bce97731SSara Sharon if (rxq->id == 0) 1216bce97731SSara Sharon iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1217bce97731SSara Sharon &rxcb); 1218bce97731SSara Sharon else 1219bce97731SSara Sharon iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1220bce97731SSara Sharon &rxcb, rxq->id); 1221e705c121SKalle Valo 1222e705c121SKalle Valo if (reclaim) { 1223e705c121SKalle Valo kzfree(txq->entries[cmd_index].free_buf); 1224e705c121SKalle Valo txq->entries[cmd_index].free_buf = NULL; 1225e705c121SKalle Valo } 1226e705c121SKalle Valo 1227e705c121SKalle Valo /* 1228e705c121SKalle Valo * After here, we should always check rxcb._page_stolen, 1229e705c121SKalle Valo * if it is true then one of the handlers took the page. 1230e705c121SKalle Valo */ 1231e705c121SKalle Valo 1232e705c121SKalle Valo if (reclaim) { 1233e705c121SKalle Valo /* Invoke any callbacks, transfer the buffer to caller, 1234e705c121SKalle Valo * and fire off the (possibly) blocking 1235e705c121SKalle Valo * iwl_trans_send_cmd() 1236e705c121SKalle Valo * as we reclaim the driver command queue */ 1237e705c121SKalle Valo if (!rxcb._page_stolen) 1238e705c121SKalle Valo iwl_pcie_hcmd_complete(trans, &rxcb); 1239e705c121SKalle Valo else 1240e705c121SKalle Valo IWL_WARN(trans, "Claim null rxb?\n"); 1241e705c121SKalle Valo } 1242e705c121SKalle Valo 1243e705c121SKalle Valo page_stolen |= rxcb._page_stolen; 1244e705c121SKalle Valo offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1245e705c121SKalle Valo } 1246e705c121SKalle Valo 1247e705c121SKalle Valo /* page was stolen from us -- free our reference */ 1248e705c121SKalle Valo if (page_stolen) { 1249e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1250e705c121SKalle Valo rxb->page = NULL; 1251e705c121SKalle Valo } 1252e705c121SKalle Valo 1253e705c121SKalle Valo /* Reuse the page if possible. For notification packets and 1254e705c121SKalle Valo * SKBs that fail to Rx correctly, add them back into the 1255e705c121SKalle Valo * rx_free list for reuse later. */ 1256e705c121SKalle Valo if (rxb->page != NULL) { 1257e705c121SKalle Valo rxb->page_dma = 1258e705c121SKalle Valo dma_map_page(trans->dev, rxb->page, 0, 1259e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 1260e705c121SKalle Valo DMA_FROM_DEVICE); 1261e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1262e705c121SKalle Valo /* 1263e705c121SKalle Valo * free the page(s) as well to not break 1264e705c121SKalle Valo * the invariant that the items on the used 1265e705c121SKalle Valo * list have no page(s) 1266e705c121SKalle Valo */ 1267e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1268e705c121SKalle Valo rxb->page = NULL; 1269e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1270e705c121SKalle Valo } else { 1271e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 1272e705c121SKalle Valo rxq->free_count++; 1273e705c121SKalle Valo } 1274e705c121SKalle Valo } else 1275e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1276e705c121SKalle Valo } 1277e705c121SKalle Valo 1278e705c121SKalle Valo /* 1279e705c121SKalle Valo * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1280e705c121SKalle Valo */ 12812e5d4a8fSHaim Dreyfuss static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue) 1282e705c121SKalle Valo { 1283e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 12842e5d4a8fSHaim Dreyfuss struct iwl_rxq *rxq = &trans_pcie->rxq[queue]; 1285d56daea4SSara Sharon u32 r, i, count = 0; 1286e705c121SKalle Valo bool emergency = false; 1287e705c121SKalle Valo 1288e705c121SKalle Valo restart: 1289e705c121SKalle Valo spin_lock(&rxq->lock); 1290e705c121SKalle Valo /* uCode's read index (stored in shared DRAM) indicates the last Rx 1291e705c121SKalle Valo * buffer that the driver may process (last buffer filled by ucode). */ 12926aa7de05SMark Rutland r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 1293e705c121SKalle Valo i = rxq->read; 1294e705c121SKalle Valo 12955eae443eSSara Sharon /* W/A 9000 device step A0 wrap-around bug */ 12965eae443eSSara Sharon r &= (rxq->queue_size - 1); 12975eae443eSSara Sharon 1298e705c121SKalle Valo /* Rx interrupt, but nothing sent from uCode */ 1299e705c121SKalle Valo if (i == r) 13005eae443eSSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1301e705c121SKalle Valo 1302e705c121SKalle Valo while (i != r) { 1303e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 1304e705c121SKalle Valo 130596a6497bSSara Sharon if (unlikely(rxq->used_count == rxq->queue_size / 2)) 1306e705c121SKalle Valo emergency = true; 1307e705c121SKalle Valo 130896a6497bSSara Sharon if (trans->cfg->mq_rx_supported) { 130996a6497bSSara Sharon /* 131096a6497bSSara Sharon * used_bd is a 32 bit but only 12 are used to retrieve 131196a6497bSSara Sharon * the vid 131296a6497bSSara Sharon */ 13135eae443eSSara Sharon u16 vid = le32_to_cpu(rxq->used_bd[i]) & 0x0FFF; 131496a6497bSSara Sharon 1315e25d65f2SSara Sharon if (WARN(!vid || 1316e25d65f2SSara Sharon vid > ARRAY_SIZE(trans_pcie->global_table), 1317e25d65f2SSara Sharon "Invalid rxb index from HW %u\n", (u32)vid)) { 1318e25d65f2SSara Sharon iwl_force_nmi(trans); 13195eae443eSSara Sharon goto out; 1320e25d65f2SSara Sharon } 1321e25d65f2SSara Sharon rxb = trans_pcie->global_table[vid - 1]; 1322b1753c62SSara Sharon if (WARN(rxb->invalid, 1323b1753c62SSara Sharon "Invalid rxb from HW %u\n", (u32)vid)) { 1324b1753c62SSara Sharon iwl_force_nmi(trans); 1325b1753c62SSara Sharon goto out; 1326b1753c62SSara Sharon } 1327b1753c62SSara Sharon rxb->invalid = true; 132896a6497bSSara Sharon } else { 1329e705c121SKalle Valo rxb = rxq->queue[i]; 1330e705c121SKalle Valo rxq->queue[i] = NULL; 133196a6497bSSara Sharon } 1332e705c121SKalle Valo 13335eae443eSSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 133478485054SSara Sharon iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency); 1335e705c121SKalle Valo 133696a6497bSSara Sharon i = (i + 1) & (rxq->queue_size - 1); 1337e705c121SKalle Valo 1338d56daea4SSara Sharon /* 1339d56daea4SSara Sharon * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1340d56daea4SSara Sharon * try to claim the pre-allocated buffers from the allocator. 1341d56daea4SSara Sharon * If not ready - will try to reclaim next time. 1342d56daea4SSara Sharon * There is no need to reschedule work - allocator exits only 1343d56daea4SSara Sharon * on success 1344e705c121SKalle Valo */ 1345d56daea4SSara Sharon if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1346d56daea4SSara Sharon iwl_pcie_rx_allocator_get(trans, rxq); 1347e705c121SKalle Valo 1348d56daea4SSara Sharon if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1349d56daea4SSara Sharon struct iwl_rb_allocator *rba = &trans_pcie->rba; 1350d56daea4SSara Sharon 1351d56daea4SSara Sharon /* Add the remaining empty RBDs for allocator use */ 1352d56daea4SSara Sharon spin_lock(&rba->lock); 1353d56daea4SSara Sharon list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1354d56daea4SSara Sharon spin_unlock(&rba->lock); 1355d56daea4SSara Sharon } else if (emergency) { 1356e705c121SKalle Valo count++; 1357e705c121SKalle Valo if (count == 8) { 1358e705c121SKalle Valo count = 0; 135996a6497bSSara Sharon if (rxq->used_count < rxq->queue_size / 3) 1360e705c121SKalle Valo emergency = false; 1361e0e168dcSGregory Greenman 1362e705c121SKalle Valo rxq->read = i; 1363e705c121SKalle Valo spin_unlock(&rxq->lock); 1364e0e168dcSGregory Greenman iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 136578485054SSara Sharon iwl_pcie_rxq_restock(trans, rxq); 1366e705c121SKalle Valo goto restart; 1367e705c121SKalle Valo } 1368e705c121SKalle Valo } 1369e0e168dcSGregory Greenman } 13705eae443eSSara Sharon out: 1371e705c121SKalle Valo /* Backtrack one entry */ 1372e705c121SKalle Valo rxq->read = i; 1373e705c121SKalle Valo spin_unlock(&rxq->lock); 1374e705c121SKalle Valo 1375e705c121SKalle Valo /* 1376e705c121SKalle Valo * handle a case where in emergency there are some unallocated RBDs. 1377e705c121SKalle Valo * those RBDs are in the used list, but are not tracked by the queue's 1378e705c121SKalle Valo * used_count which counts allocator owned RBDs. 1379e705c121SKalle Valo * unallocated emergency RBDs must be allocated on exit, otherwise 1380e705c121SKalle Valo * when called again the function may not be in emergency mode and 1381e705c121SKalle Valo * they will be handed to the allocator with no tracking in the RBD 1382e705c121SKalle Valo * allocator counters, which will lead to them never being claimed back 1383e705c121SKalle Valo * by the queue. 1384e705c121SKalle Valo * by allocating them here, they are now in the queue free list, and 1385e705c121SKalle Valo * will be restocked by the next call of iwl_pcie_rxq_restock. 1386e705c121SKalle Valo */ 1387e705c121SKalle Valo if (unlikely(emergency && count)) 138878485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1389e705c121SKalle Valo 1390bce97731SSara Sharon if (rxq->napi.poll) 1391bce97731SSara Sharon napi_gro_flush(&rxq->napi, false); 1392e0e168dcSGregory Greenman 1393e0e168dcSGregory Greenman iwl_pcie_rxq_restock(trans, rxq); 1394e705c121SKalle Valo } 1395e705c121SKalle Valo 13962e5d4a8fSHaim Dreyfuss static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 13972e5d4a8fSHaim Dreyfuss { 13982e5d4a8fSHaim Dreyfuss u8 queue = entry->entry; 13992e5d4a8fSHaim Dreyfuss struct msix_entry *entries = entry - queue; 14002e5d4a8fSHaim Dreyfuss 14012e5d4a8fSHaim Dreyfuss return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 14022e5d4a8fSHaim Dreyfuss } 14032e5d4a8fSHaim Dreyfuss 14042e5d4a8fSHaim Dreyfuss static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 14052e5d4a8fSHaim Dreyfuss struct msix_entry *entry) 14062e5d4a8fSHaim Dreyfuss { 14072e5d4a8fSHaim Dreyfuss /* 14082e5d4a8fSHaim Dreyfuss * Before sending the interrupt the HW disables it to prevent 14092e5d4a8fSHaim Dreyfuss * a nested interrupt. This is done by writing 1 to the corresponding 14102e5d4a8fSHaim Dreyfuss * bit in the mask register. After handling the interrupt, it should be 14112e5d4a8fSHaim Dreyfuss * re-enabled by clearing this bit. This register is defined as 14122e5d4a8fSHaim Dreyfuss * write 1 clear (W1C) register, meaning that it's being clear 14132e5d4a8fSHaim Dreyfuss * by writing 1 to the bit. 14142e5d4a8fSHaim Dreyfuss */ 14157ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 14162e5d4a8fSHaim Dreyfuss } 14172e5d4a8fSHaim Dreyfuss 14182e5d4a8fSHaim Dreyfuss /* 14192e5d4a8fSHaim Dreyfuss * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 14202e5d4a8fSHaim Dreyfuss * This interrupt handler should be used with RSS queue only. 14212e5d4a8fSHaim Dreyfuss */ 14222e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 14232e5d4a8fSHaim Dreyfuss { 14242e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 14252e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 14262e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 14272e5d4a8fSHaim Dreyfuss 1428c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1429c42ff65dSJohannes Berg 14305eae443eSSara Sharon if (WARN_ON(entry->entry >= trans->num_rx_queues)) 14315eae443eSSara Sharon return IRQ_NONE; 14325eae443eSSara Sharon 14332e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 14342e5d4a8fSHaim Dreyfuss 14352e5d4a8fSHaim Dreyfuss local_bh_disable(); 14362e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, entry->entry); 14372e5d4a8fSHaim Dreyfuss local_bh_enable(); 14382e5d4a8fSHaim Dreyfuss 14392e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 14402e5d4a8fSHaim Dreyfuss 14412e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 14422e5d4a8fSHaim Dreyfuss 14432e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 14442e5d4a8fSHaim Dreyfuss } 14452e5d4a8fSHaim Dreyfuss 1446e705c121SKalle Valo /* 1447e705c121SKalle Valo * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1448e705c121SKalle Valo */ 1449e705c121SKalle Valo static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1450e705c121SKalle Valo { 1451e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1452e705c121SKalle Valo int i; 1453e705c121SKalle Valo 1454e705c121SKalle Valo /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1455e705c121SKalle Valo if (trans->cfg->internal_wimax_coex && 1456e705c121SKalle Valo !trans->cfg->apmg_not_supported && 1457e705c121SKalle Valo (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1458e705c121SKalle Valo APMS_CLK_VAL_MRB_FUNC_MODE) || 1459e705c121SKalle Valo (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1460e705c121SKalle Valo APMG_PS_CTRL_VAL_RESET_REQ))) { 1461e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1462e705c121SKalle Valo iwl_op_mode_wimax_active(trans->op_mode); 1463e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1464e705c121SKalle Valo return; 1465e705c121SKalle Valo } 1466e705c121SKalle Valo 146713a3a390SSara Sharon for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 146813a3a390SSara Sharon if (!trans_pcie->txq[i]) 146913a3a390SSara Sharon continue; 1470b2a3b1c1SSara Sharon del_timer(&trans_pcie->txq[i]->stuck_timer); 147113a3a390SSara Sharon } 1472e705c121SKalle Valo 14737d75f32eSEmmanuel Grumbach /* The STATUS_FW_ERROR bit is set in this function. This must happen 14747d75f32eSEmmanuel Grumbach * before we wake up the command caller, to ensure a proper cleanup. */ 14757d75f32eSEmmanuel Grumbach iwl_trans_fw_error(trans); 14767d75f32eSEmmanuel Grumbach 1477e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1478e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1479e705c121SKalle Valo } 1480e705c121SKalle Valo 1481e705c121SKalle Valo static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1482e705c121SKalle Valo { 1483e705c121SKalle Valo u32 inta; 1484e705c121SKalle Valo 1485e705c121SKalle Valo lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1486e705c121SKalle Valo 1487e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1488e705c121SKalle Valo 1489e705c121SKalle Valo /* Discover which interrupts are active/pending */ 1490e705c121SKalle Valo inta = iwl_read32(trans, CSR_INT); 1491e705c121SKalle Valo 1492e705c121SKalle Valo /* the thread will service interrupts and re-enable them */ 1493e705c121SKalle Valo return inta; 1494e705c121SKalle Valo } 1495e705c121SKalle Valo 1496e705c121SKalle Valo /* a device (PCI-E) page is 4096 bytes long */ 1497e705c121SKalle Valo #define ICT_SHIFT 12 1498e705c121SKalle Valo #define ICT_SIZE (1 << ICT_SHIFT) 1499e705c121SKalle Valo #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1500e705c121SKalle Valo 1501e705c121SKalle Valo /* interrupt handler using ict table, with this interrupt driver will 1502e705c121SKalle Valo * stop using INTA register to get device's interrupt, reading this register 1503e705c121SKalle Valo * is expensive, device will write interrupts in ICT dram table, increment 1504e705c121SKalle Valo * index then will fire interrupt to driver, driver will OR all ICT table 1505e705c121SKalle Valo * entries from current index up to table entry with 0 value. the result is 1506e705c121SKalle Valo * the interrupt we need to service, driver will set the entries back to 0 and 1507e705c121SKalle Valo * set index. 1508e705c121SKalle Valo */ 1509e705c121SKalle Valo static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1510e705c121SKalle Valo { 1511e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1512e705c121SKalle Valo u32 inta; 1513e705c121SKalle Valo u32 val = 0; 1514e705c121SKalle Valo u32 read; 1515e705c121SKalle Valo 1516e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1517e705c121SKalle Valo 1518e705c121SKalle Valo /* Ignore interrupt if there's nothing in NIC to service. 1519e705c121SKalle Valo * This may be due to IRQ shared with another device, 1520e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. */ 1521e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1522e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1523e705c121SKalle Valo if (!read) 1524e705c121SKalle Valo return 0; 1525e705c121SKalle Valo 1526e705c121SKalle Valo /* 1527e705c121SKalle Valo * Collect all entries up to the first 0, starting from ict_index; 1528e705c121SKalle Valo * note we already read at ict_index. 1529e705c121SKalle Valo */ 1530e705c121SKalle Valo do { 1531e705c121SKalle Valo val |= read; 1532e705c121SKalle Valo IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1533e705c121SKalle Valo trans_pcie->ict_index, read); 1534e705c121SKalle Valo trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1535e705c121SKalle Valo trans_pcie->ict_index = 1536e705c121SKalle Valo ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1537e705c121SKalle Valo 1538e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1539e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1540e705c121SKalle Valo read); 1541e705c121SKalle Valo } while (read); 1542e705c121SKalle Valo 1543e705c121SKalle Valo /* We should not get this value, just ignore it. */ 1544e705c121SKalle Valo if (val == 0xffffffff) 1545e705c121SKalle Valo val = 0; 1546e705c121SKalle Valo 1547e705c121SKalle Valo /* 1548e705c121SKalle Valo * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1549e705c121SKalle Valo * (bit 15 before shifting it to 31) to clear when using interrupt 1550e705c121SKalle Valo * coalescing. fortunately, bits 18 and 19 stay set when this happens 1551e705c121SKalle Valo * so we use them to decide on the real state of the Rx bit. 1552e705c121SKalle Valo * In order words, bit 15 is set if bit 18 or bit 19 are set. 1553e705c121SKalle Valo */ 1554e705c121SKalle Valo if (val & 0xC0000) 1555e705c121SKalle Valo val |= 0x8000; 1556e705c121SKalle Valo 1557e705c121SKalle Valo inta = (0xff & val) | ((0xff00 & val) << 16); 1558e705c121SKalle Valo return inta; 1559e705c121SKalle Valo } 1560e705c121SKalle Valo 1561fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 15623a6e168bSJohannes Berg { 15633a6e168bSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 15643a6e168bSJohannes Berg struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1565326477e4SJohannes Berg bool hw_rfkill, prev, report; 15663a6e168bSJohannes Berg 15673a6e168bSJohannes Berg mutex_lock(&trans_pcie->mutex); 1568326477e4SJohannes Berg prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 15693a6e168bSJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1570326477e4SJohannes Berg if (hw_rfkill) { 1571326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1572326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1573326477e4SJohannes Berg } 1574326477e4SJohannes Berg if (trans_pcie->opmode_down) 1575326477e4SJohannes Berg report = hw_rfkill; 1576326477e4SJohannes Berg else 1577326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 15783a6e168bSJohannes Berg 15793a6e168bSJohannes Berg IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 15803a6e168bSJohannes Berg hw_rfkill ? "disable radio" : "enable radio"); 15813a6e168bSJohannes Berg 15823a6e168bSJohannes Berg isr_stats->rfkill++; 15833a6e168bSJohannes Berg 1584326477e4SJohannes Berg if (prev != report) 1585326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 15863a6e168bSJohannes Berg mutex_unlock(&trans_pcie->mutex); 15873a6e168bSJohannes Berg 15883a6e168bSJohannes Berg if (hw_rfkill) { 15893a6e168bSJohannes Berg if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 15903a6e168bSJohannes Berg &trans->status)) 15913a6e168bSJohannes Berg IWL_DEBUG_RF_KILL(trans, 15923a6e168bSJohannes Berg "Rfkill while SYNC HCMD in flight\n"); 15933a6e168bSJohannes Berg wake_up(&trans_pcie->wait_command_queue); 15943a6e168bSJohannes Berg } else { 1595326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1596326477e4SJohannes Berg if (trans_pcie->opmode_down) 1597326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 15983a6e168bSJohannes Berg } 15993a6e168bSJohannes Berg } 16003a6e168bSJohannes Berg 1601e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1602e705c121SKalle Valo { 1603e705c121SKalle Valo struct iwl_trans *trans = dev_id; 1604e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1605e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1606e705c121SKalle Valo u32 inta = 0; 1607e705c121SKalle Valo u32 handled = 0; 1608e705c121SKalle Valo 1609e705c121SKalle Valo lock_map_acquire(&trans->sync_cmd_lockdep_map); 1610e705c121SKalle Valo 1611e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1612e705c121SKalle Valo 1613e705c121SKalle Valo /* dram interrupt table not set yet, 1614e705c121SKalle Valo * use legacy interrupt. 1615e705c121SKalle Valo */ 1616e705c121SKalle Valo if (likely(trans_pcie->use_ict)) 1617e705c121SKalle Valo inta = iwl_pcie_int_cause_ict(trans); 1618e705c121SKalle Valo else 1619e705c121SKalle Valo inta = iwl_pcie_int_cause_non_ict(trans); 1620e705c121SKalle Valo 1621e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1622e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1623e705c121SKalle Valo "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1624e705c121SKalle Valo inta, trans_pcie->inta_mask, 1625e705c121SKalle Valo iwl_read32(trans, CSR_INT_MASK), 1626e705c121SKalle Valo iwl_read32(trans, CSR_FH_INT_STATUS)); 1627e705c121SKalle Valo if (inta & (~trans_pcie->inta_mask)) 1628e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1629e705c121SKalle Valo "We got a masked interrupt (0x%08x)\n", 1630e705c121SKalle Valo inta & (~trans_pcie->inta_mask)); 1631e705c121SKalle Valo } 1632e705c121SKalle Valo 1633e705c121SKalle Valo inta &= trans_pcie->inta_mask; 1634e705c121SKalle Valo 1635e705c121SKalle Valo /* 1636e705c121SKalle Valo * Ignore interrupt if there's nothing in NIC to service. 1637e705c121SKalle Valo * This may be due to IRQ shared with another device, 1638e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. 1639e705c121SKalle Valo */ 1640e705c121SKalle Valo if (unlikely(!inta)) { 1641e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1642e705c121SKalle Valo /* 1643e705c121SKalle Valo * Re-enable interrupts here since we don't 1644e705c121SKalle Valo * have anything to service 1645e705c121SKalle Valo */ 1646e705c121SKalle Valo if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1647f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 1648e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1649e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1650e705c121SKalle Valo return IRQ_NONE; 1651e705c121SKalle Valo } 1652e705c121SKalle Valo 1653e705c121SKalle Valo if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1654e705c121SKalle Valo /* 1655e705c121SKalle Valo * Hardware disappeared. It might have 1656e705c121SKalle Valo * already raised an interrupt. 1657e705c121SKalle Valo */ 1658e705c121SKalle Valo IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1659e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1660e705c121SKalle Valo goto out; 1661e705c121SKalle Valo } 1662e705c121SKalle Valo 1663e705c121SKalle Valo /* Ack/clear/reset pending uCode interrupts. 1664e705c121SKalle Valo * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1665e705c121SKalle Valo */ 1666e705c121SKalle Valo /* There is a hardware bug in the interrupt mask function that some 1667e705c121SKalle Valo * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1668e705c121SKalle Valo * they are disabled in the CSR_INT_MASK register. Furthermore the 1669e705c121SKalle Valo * ICT interrupt handling mechanism has another bug that might cause 1670e705c121SKalle Valo * these unmasked interrupts fail to be detected. We workaround the 1671e705c121SKalle Valo * hardware bugs here by ACKing all the possible interrupts so that 1672e705c121SKalle Valo * interrupt coalescing can still be achieved. 1673e705c121SKalle Valo */ 1674e705c121SKalle Valo iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1675e705c121SKalle Valo 1676e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) 1677e705c121SKalle Valo IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1678e705c121SKalle Valo inta, iwl_read32(trans, CSR_INT_MASK)); 1679e705c121SKalle Valo 1680e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1681e705c121SKalle Valo 1682e705c121SKalle Valo /* Now service all interrupt bits discovered above. */ 1683e705c121SKalle Valo if (inta & CSR_INT_BIT_HW_ERR) { 1684e705c121SKalle Valo IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1685e705c121SKalle Valo 1686e705c121SKalle Valo /* Tell the device to stop sending interrupts */ 1687e705c121SKalle Valo iwl_disable_interrupts(trans); 1688e705c121SKalle Valo 1689e705c121SKalle Valo isr_stats->hw++; 1690e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1691e705c121SKalle Valo 1692e705c121SKalle Valo handled |= CSR_INT_BIT_HW_ERR; 1693e705c121SKalle Valo 1694e705c121SKalle Valo goto out; 1695e705c121SKalle Valo } 1696e705c121SKalle Valo 1697e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1698e705c121SKalle Valo /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1699e705c121SKalle Valo if (inta & CSR_INT_BIT_SCD) { 1700e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1701e705c121SKalle Valo "Scheduler finished to transmit the frame/frames.\n"); 1702e705c121SKalle Valo isr_stats->sch++; 1703e705c121SKalle Valo } 1704e705c121SKalle Valo 1705e705c121SKalle Valo /* Alive notification via Rx interrupt will do the real work */ 1706e705c121SKalle Valo if (inta & CSR_INT_BIT_ALIVE) { 1707e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1708e705c121SKalle Valo isr_stats->alive++; 1709eda50cdeSSara Sharon if (trans->cfg->gen2) { 1710eda50cdeSSara Sharon /* 1711eda50cdeSSara Sharon * We can restock, since firmware configured 1712eda50cdeSSara Sharon * the RFH 1713eda50cdeSSara Sharon */ 1714eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1715eda50cdeSSara Sharon } 1716e705c121SKalle Valo } 1717e705c121SKalle Valo } 1718e705c121SKalle Valo 1719e705c121SKalle Valo /* Safely ignore these bits for debug checks below */ 1720e705c121SKalle Valo inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1721e705c121SKalle Valo 1722e705c121SKalle Valo /* HW RF KILL switch toggled */ 1723e705c121SKalle Valo if (inta & CSR_INT_BIT_RF_KILL) { 17243a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 1725e705c121SKalle Valo handled |= CSR_INT_BIT_RF_KILL; 1726e705c121SKalle Valo } 1727e705c121SKalle Valo 1728e705c121SKalle Valo /* Chip got too hot and stopped itself */ 1729e705c121SKalle Valo if (inta & CSR_INT_BIT_CT_KILL) { 1730e705c121SKalle Valo IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1731e705c121SKalle Valo isr_stats->ctkill++; 1732e705c121SKalle Valo handled |= CSR_INT_BIT_CT_KILL; 1733e705c121SKalle Valo } 1734e705c121SKalle Valo 1735e705c121SKalle Valo /* Error detected by uCode */ 1736e705c121SKalle Valo if (inta & CSR_INT_BIT_SW_ERR) { 1737e705c121SKalle Valo IWL_ERR(trans, "Microcode SW error detected. " 1738e705c121SKalle Valo " Restarting 0x%X.\n", inta); 1739e705c121SKalle Valo isr_stats->sw++; 1740e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1741e705c121SKalle Valo handled |= CSR_INT_BIT_SW_ERR; 1742e705c121SKalle Valo } 1743e705c121SKalle Valo 1744e705c121SKalle Valo /* uCode wakes up after power-down sleep */ 1745e705c121SKalle Valo if (inta & CSR_INT_BIT_WAKEUP) { 1746e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1747e705c121SKalle Valo iwl_pcie_rxq_check_wrptr(trans); 1748e705c121SKalle Valo iwl_pcie_txq_check_wrptrs(trans); 1749e705c121SKalle Valo 1750e705c121SKalle Valo isr_stats->wakeup++; 1751e705c121SKalle Valo 1752e705c121SKalle Valo handled |= CSR_INT_BIT_WAKEUP; 1753e705c121SKalle Valo } 1754e705c121SKalle Valo 1755e705c121SKalle Valo /* All uCode command responses, including Tx command responses, 1756e705c121SKalle Valo * Rx "responses" (frame-received notification), and other 1757e705c121SKalle Valo * notifications from uCode come through here*/ 1758e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1759e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC)) { 1760e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1761e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1762e705c121SKalle Valo handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1763e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 1764e705c121SKalle Valo CSR_FH_INT_RX_MASK); 1765e705c121SKalle Valo } 1766e705c121SKalle Valo if (inta & CSR_INT_BIT_RX_PERIODIC) { 1767e705c121SKalle Valo handled |= CSR_INT_BIT_RX_PERIODIC; 1768e705c121SKalle Valo iwl_write32(trans, 1769e705c121SKalle Valo CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1770e705c121SKalle Valo } 1771e705c121SKalle Valo /* Sending RX interrupt require many steps to be done in the 1772e705c121SKalle Valo * the device: 1773e705c121SKalle Valo * 1- write interrupt to current index in ICT table. 1774e705c121SKalle Valo * 2- dma RX frame. 1775e705c121SKalle Valo * 3- update RX shared data to indicate last write index. 1776e705c121SKalle Valo * 4- send interrupt. 1777e705c121SKalle Valo * This could lead to RX race, driver could receive RX interrupt 1778e705c121SKalle Valo * but the shared data changes does not reflect this; 1779e705c121SKalle Valo * periodic interrupt will detect any dangling Rx activity. 1780e705c121SKalle Valo */ 1781e705c121SKalle Valo 1782e705c121SKalle Valo /* Disable periodic interrupt; we use it as just a one-shot. */ 1783e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1784e705c121SKalle Valo CSR_INT_PERIODIC_DIS); 1785e705c121SKalle Valo 1786e705c121SKalle Valo /* 1787e705c121SKalle Valo * Enable periodic interrupt in 8 msec only if we received 1788e705c121SKalle Valo * real RX interrupt (instead of just periodic int), to catch 1789e705c121SKalle Valo * any dangling Rx interrupt. If it was just the periodic 1790e705c121SKalle Valo * interrupt, there was no dangling Rx activity, and no need 1791e705c121SKalle Valo * to extend the periodic interrupt; one-shot is enough. 1792e705c121SKalle Valo */ 1793e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1794e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1795e705c121SKalle Valo CSR_INT_PERIODIC_ENA); 1796e705c121SKalle Valo 1797e705c121SKalle Valo isr_stats->rx++; 1798e705c121SKalle Valo 1799e705c121SKalle Valo local_bh_disable(); 18002e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, 0); 1801e705c121SKalle Valo local_bh_enable(); 1802e705c121SKalle Valo } 1803e705c121SKalle Valo 1804e705c121SKalle Valo /* This "Tx" DMA channel is used only for loading uCode */ 1805e705c121SKalle Valo if (inta & CSR_INT_BIT_FH_TX) { 1806e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1807e705c121SKalle Valo IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1808e705c121SKalle Valo isr_stats->tx++; 1809e705c121SKalle Valo handled |= CSR_INT_BIT_FH_TX; 1810e705c121SKalle Valo /* Wake up uCode load routine, now that load is complete */ 1811e705c121SKalle Valo trans_pcie->ucode_write_complete = true; 1812e705c121SKalle Valo wake_up(&trans_pcie->ucode_write_waitq); 1813e705c121SKalle Valo } 1814e705c121SKalle Valo 1815e705c121SKalle Valo if (inta & ~handled) { 1816e705c121SKalle Valo IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 1817e705c121SKalle Valo isr_stats->unhandled++; 1818e705c121SKalle Valo } 1819e705c121SKalle Valo 1820e705c121SKalle Valo if (inta & ~(trans_pcie->inta_mask)) { 1821e705c121SKalle Valo IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 1822e705c121SKalle Valo inta & ~trans_pcie->inta_mask); 1823e705c121SKalle Valo } 1824e705c121SKalle Valo 1825f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 1826a6bd005fSEmmanuel Grumbach /* only Re-enable all interrupt if disabled by irq */ 1827f16c3ebfSEmmanuel Grumbach if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1828f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 1829f16c3ebfSEmmanuel Grumbach /* we are loading the firmware, enable FH_TX interrupt only */ 1830f16c3ebfSEmmanuel Grumbach else if (handled & CSR_INT_BIT_FH_TX) 1831f16c3ebfSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1832e705c121SKalle Valo /* Re-enable RF_KILL if it occurred */ 1833e705c121SKalle Valo else if (handled & CSR_INT_BIT_RF_KILL) 1834e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1835f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 1836e705c121SKalle Valo 1837e705c121SKalle Valo out: 1838e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1839e705c121SKalle Valo return IRQ_HANDLED; 1840e705c121SKalle Valo } 1841e705c121SKalle Valo 1842e705c121SKalle Valo /****************************************************************************** 1843e705c121SKalle Valo * 1844e705c121SKalle Valo * ICT functions 1845e705c121SKalle Valo * 1846e705c121SKalle Valo ******************************************************************************/ 1847e705c121SKalle Valo 1848e705c121SKalle Valo /* Free dram table */ 1849e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans) 1850e705c121SKalle Valo { 1851e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1852e705c121SKalle Valo 1853e705c121SKalle Valo if (trans_pcie->ict_tbl) { 1854e705c121SKalle Valo dma_free_coherent(trans->dev, ICT_SIZE, 1855e705c121SKalle Valo trans_pcie->ict_tbl, 1856e705c121SKalle Valo trans_pcie->ict_tbl_dma); 1857e705c121SKalle Valo trans_pcie->ict_tbl = NULL; 1858e705c121SKalle Valo trans_pcie->ict_tbl_dma = 0; 1859e705c121SKalle Valo } 1860e705c121SKalle Valo } 1861e705c121SKalle Valo 1862e705c121SKalle Valo /* 1863e705c121SKalle Valo * allocate dram shared table, it is an aligned memory 1864e705c121SKalle Valo * block of ICT_SIZE. 1865e705c121SKalle Valo * also reset all data related to ICT table interrupt. 1866e705c121SKalle Valo */ 1867e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans) 1868e705c121SKalle Valo { 1869e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1870e705c121SKalle Valo 1871e705c121SKalle Valo trans_pcie->ict_tbl = 1872e705c121SKalle Valo dma_zalloc_coherent(trans->dev, ICT_SIZE, 1873e705c121SKalle Valo &trans_pcie->ict_tbl_dma, 1874e705c121SKalle Valo GFP_KERNEL); 1875e705c121SKalle Valo if (!trans_pcie->ict_tbl) 1876e705c121SKalle Valo return -ENOMEM; 1877e705c121SKalle Valo 1878e705c121SKalle Valo /* just an API sanity check ... it is guaranteed to be aligned */ 1879e705c121SKalle Valo if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 1880e705c121SKalle Valo iwl_pcie_free_ict(trans); 1881e705c121SKalle Valo return -EINVAL; 1882e705c121SKalle Valo } 1883e705c121SKalle Valo 1884e705c121SKalle Valo return 0; 1885e705c121SKalle Valo } 1886e705c121SKalle Valo 1887e705c121SKalle Valo /* Device is going up inform it about using ICT interrupt table, 1888e705c121SKalle Valo * also we need to tell the driver to start using ICT interrupt. 1889e705c121SKalle Valo */ 1890e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans) 1891e705c121SKalle Valo { 1892e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1893e705c121SKalle Valo u32 val; 1894e705c121SKalle Valo 1895e705c121SKalle Valo if (!trans_pcie->ict_tbl) 1896e705c121SKalle Valo return; 1897e705c121SKalle Valo 1898e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1899f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 1900e705c121SKalle Valo 1901e705c121SKalle Valo memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 1902e705c121SKalle Valo 1903e705c121SKalle Valo val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 1904e705c121SKalle Valo 1905e705c121SKalle Valo val |= CSR_DRAM_INT_TBL_ENABLE | 1906e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRAP_CHECK | 1907e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRITE_POINTER; 1908e705c121SKalle Valo 1909e705c121SKalle Valo IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 1910e705c121SKalle Valo 1911e705c121SKalle Valo iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 1912e705c121SKalle Valo trans_pcie->use_ict = true; 1913e705c121SKalle Valo trans_pcie->ict_index = 0; 1914e705c121SKalle Valo iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 1915f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 1916e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1917e705c121SKalle Valo } 1918e705c121SKalle Valo 1919e705c121SKalle Valo /* Device is going down disable ict interrupt usage */ 1920e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans) 1921e705c121SKalle Valo { 1922e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1923e705c121SKalle Valo 1924e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1925e705c121SKalle Valo trans_pcie->use_ict = false; 1926e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1927e705c121SKalle Valo } 1928e705c121SKalle Valo 1929e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data) 1930e705c121SKalle Valo { 1931e705c121SKalle Valo struct iwl_trans *trans = data; 1932e705c121SKalle Valo 1933e705c121SKalle Valo if (!trans) 1934e705c121SKalle Valo return IRQ_NONE; 1935e705c121SKalle Valo 1936e705c121SKalle Valo /* Disable (but don't clear!) interrupts here to avoid 1937e705c121SKalle Valo * back-to-back ISRs and sporadic interrupts from our NIC. 1938e705c121SKalle Valo * If we have something to service, the tasklet will re-enable ints. 1939e705c121SKalle Valo * If we *don't* have something, we'll re-enable before leaving here. 1940e705c121SKalle Valo */ 1941e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 1942e705c121SKalle Valo 1943e705c121SKalle Valo return IRQ_WAKE_THREAD; 1944e705c121SKalle Valo } 19452e5d4a8fSHaim Dreyfuss 19462e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 19472e5d4a8fSHaim Dreyfuss { 19482e5d4a8fSHaim Dreyfuss return IRQ_WAKE_THREAD; 19492e5d4a8fSHaim Dreyfuss } 19502e5d4a8fSHaim Dreyfuss 19512e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 19522e5d4a8fSHaim Dreyfuss { 19532e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 19542e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 19552e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 195646167a8fSColin Ian King struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 19572e5d4a8fSHaim Dreyfuss u32 inta_fh, inta_hw; 19582e5d4a8fSHaim Dreyfuss 19592e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 19602e5d4a8fSHaim Dreyfuss 19612e5d4a8fSHaim Dreyfuss spin_lock(&trans_pcie->irq_lock); 19627ef3dd26SHaim Dreyfuss inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 19637ef3dd26SHaim Dreyfuss inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 19642e5d4a8fSHaim Dreyfuss /* 19652e5d4a8fSHaim Dreyfuss * Clear causes registers to avoid being handling the same cause. 19662e5d4a8fSHaim Dreyfuss */ 19677ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 19687ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 19692e5d4a8fSHaim Dreyfuss spin_unlock(&trans_pcie->irq_lock); 19702e5d4a8fSHaim Dreyfuss 1971c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 1972c42ff65dSJohannes Berg 19732e5d4a8fSHaim Dreyfuss if (unlikely(!(inta_fh | inta_hw))) { 19742e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 19752e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 19762e5d4a8fSHaim Dreyfuss return IRQ_NONE; 19772e5d4a8fSHaim Dreyfuss } 19782e5d4a8fSHaim Dreyfuss 19792e5d4a8fSHaim Dreyfuss if (iwl_have_debug_level(IWL_DL_ISR)) 19802e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "ISR inta_fh 0x%08x, enabled 0x%08x\n", 19812e5d4a8fSHaim Dreyfuss inta_fh, 19822e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 19832e5d4a8fSHaim Dreyfuss 1984496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 1985496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q0) { 1986496d83caSHaim Dreyfuss local_bh_disable(); 1987496d83caSHaim Dreyfuss iwl_pcie_rx_handle(trans, 0); 1988496d83caSHaim Dreyfuss local_bh_enable(); 1989496d83caSHaim Dreyfuss } 1990496d83caSHaim Dreyfuss 1991496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 1992496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q1) { 1993496d83caSHaim Dreyfuss local_bh_disable(); 1994496d83caSHaim Dreyfuss iwl_pcie_rx_handle(trans, 1); 1995496d83caSHaim Dreyfuss local_bh_enable(); 1996496d83caSHaim Dreyfuss } 1997496d83caSHaim Dreyfuss 19982e5d4a8fSHaim Dreyfuss /* This "Tx" DMA channel is used only for loading uCode */ 19992e5d4a8fSHaim Dreyfuss if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 20002e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 20012e5d4a8fSHaim Dreyfuss isr_stats->tx++; 20022e5d4a8fSHaim Dreyfuss /* 20032e5d4a8fSHaim Dreyfuss * Wake up uCode load routine, 20042e5d4a8fSHaim Dreyfuss * now that load is complete 20052e5d4a8fSHaim Dreyfuss */ 20062e5d4a8fSHaim Dreyfuss trans_pcie->ucode_write_complete = true; 20072e5d4a8fSHaim Dreyfuss wake_up(&trans_pcie->ucode_write_waitq); 20082e5d4a8fSHaim Dreyfuss } 20092e5d4a8fSHaim Dreyfuss 20102e5d4a8fSHaim Dreyfuss /* Error detected by uCode */ 20112e5d4a8fSHaim Dreyfuss if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 20129b58419eSGolan Ben Ami (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) || 20139b58419eSGolan Ben Ami (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_V2)) { 20142e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 20152e5d4a8fSHaim Dreyfuss "Microcode SW error detected. Restarting 0x%X.\n", 20162e5d4a8fSHaim Dreyfuss inta_fh); 20172e5d4a8fSHaim Dreyfuss isr_stats->sw++; 20182e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 20192e5d4a8fSHaim Dreyfuss } 20202e5d4a8fSHaim Dreyfuss 20212e5d4a8fSHaim Dreyfuss /* After checking FH register check HW register */ 20222e5d4a8fSHaim Dreyfuss if (iwl_have_debug_level(IWL_DL_ISR)) 20232e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, 20242e5d4a8fSHaim Dreyfuss "ISR inta_hw 0x%08x, enabled 0x%08x\n", 20252e5d4a8fSHaim Dreyfuss inta_hw, 20262e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 20272e5d4a8fSHaim Dreyfuss 20282e5d4a8fSHaim Dreyfuss /* Alive notification via Rx interrupt will do the real work */ 20292e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 20302e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 20312e5d4a8fSHaim Dreyfuss isr_stats->alive++; 2032eda50cdeSSara Sharon if (trans->cfg->gen2) { 2033eda50cdeSSara Sharon /* We can restock, since firmware configured the RFH */ 2034eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2035eda50cdeSSara Sharon } 20362e5d4a8fSHaim Dreyfuss } 20372e5d4a8fSHaim Dreyfuss 20389b58419eSGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560 && 20399b58419eSGolan Ben Ami inta_hw & MSIX_HW_INT_CAUSES_REG_IPC) { 20409b58419eSGolan Ben Ami /* Reflect IML transfer status */ 20419b58419eSGolan Ben Ami int res = iwl_read32(trans, CSR_IML_RESP_ADDR); 20429b58419eSGolan Ben Ami 20439b58419eSGolan Ben Ami IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res); 20449b58419eSGolan Ben Ami if (res == IWL_IMAGE_RESP_FAIL) { 20459b58419eSGolan Ben Ami isr_stats->sw++; 20469b58419eSGolan Ben Ami iwl_pcie_irq_handle_error(trans); 20479b58419eSGolan Ben Ami } 20489b58419eSGolan Ben Ami } else if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 20492e5d4a8fSHaim Dreyfuss /* uCode wakes up after power-down sleep */ 20502e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 20512e5d4a8fSHaim Dreyfuss iwl_pcie_rxq_check_wrptr(trans); 20522e5d4a8fSHaim Dreyfuss iwl_pcie_txq_check_wrptrs(trans); 20532e5d4a8fSHaim Dreyfuss 20542e5d4a8fSHaim Dreyfuss isr_stats->wakeup++; 20552e5d4a8fSHaim Dreyfuss } 20562e5d4a8fSHaim Dreyfuss 20572e5d4a8fSHaim Dreyfuss /* Chip got too hot and stopped itself */ 20582e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 20592e5d4a8fSHaim Dreyfuss IWL_ERR(trans, "Microcode CT kill error detected.\n"); 20602e5d4a8fSHaim Dreyfuss isr_stats->ctkill++; 20612e5d4a8fSHaim Dreyfuss } 20622e5d4a8fSHaim Dreyfuss 20632e5d4a8fSHaim Dreyfuss /* HW RF KILL switch toggled */ 20643a6e168bSJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 20653a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 20662e5d4a8fSHaim Dreyfuss 20672e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 20682e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 20692e5d4a8fSHaim Dreyfuss "Hardware error detected. Restarting.\n"); 20702e5d4a8fSHaim Dreyfuss 20712e5d4a8fSHaim Dreyfuss isr_stats->hw++; 20722e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 20732e5d4a8fSHaim Dreyfuss } 20742e5d4a8fSHaim Dreyfuss 20752e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 20762e5d4a8fSHaim Dreyfuss 20772e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 20782e5d4a8fSHaim Dreyfuss 20792e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 20802e5d4a8fSHaim Dreyfuss } 2081