1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 4e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 7e705c121SKalle Valo * 8e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 9e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 10e705c121SKalle Valo * 11e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 12e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 13e705c121SKalle Valo * published by the Free Software Foundation. 14e705c121SKalle Valo * 15e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 16e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18e705c121SKalle Valo * more details. 19e705c121SKalle Valo * 20e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 21e705c121SKalle Valo * file called LICENSE. 22e705c121SKalle Valo * 23e705c121SKalle Valo * Contact Information: 24d01c5366SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 25e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26e705c121SKalle Valo * 27e705c121SKalle Valo *****************************************************************************/ 28e705c121SKalle Valo #include <linux/sched.h> 29e705c121SKalle Valo #include <linux/wait.h> 30e705c121SKalle Valo #include <linux/gfp.h> 31e705c121SKalle Valo 32e705c121SKalle Valo #include "iwl-prph.h" 33e705c121SKalle Valo #include "iwl-io.h" 34e705c121SKalle Valo #include "internal.h" 35e705c121SKalle Valo #include "iwl-op-mode.h" 369b58419eSGolan Ben Ami #include "iwl-context-info-gen3.h" 37e705c121SKalle Valo 38e705c121SKalle Valo /****************************************************************************** 39e705c121SKalle Valo * 40e705c121SKalle Valo * RX path functions 41e705c121SKalle Valo * 42e705c121SKalle Valo ******************************************************************************/ 43e705c121SKalle Valo 44e705c121SKalle Valo /* 45e705c121SKalle Valo * Rx theory of operation 46e705c121SKalle Valo * 47e705c121SKalle Valo * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 48e705c121SKalle Valo * each of which point to Receive Buffers to be filled by the NIC. These get 49e705c121SKalle Valo * used not only for Rx frames, but for any command response or notification 50e705c121SKalle Valo * from the NIC. The driver and NIC manage the Rx buffers by means 51e705c121SKalle Valo * of indexes into the circular buffer. 52e705c121SKalle Valo * 53e705c121SKalle Valo * Rx Queue Indexes 54e705c121SKalle Valo * The host/firmware share two index registers for managing the Rx buffers. 55e705c121SKalle Valo * 56e705c121SKalle Valo * The READ index maps to the first position that the firmware may be writing 57e705c121SKalle Valo * to -- the driver can read up to (but not including) this position and get 58e705c121SKalle Valo * good data. 59e705c121SKalle Valo * The READ index is managed by the firmware once the card is enabled. 60e705c121SKalle Valo * 61e705c121SKalle Valo * The WRITE index maps to the last position the driver has read from -- the 62e705c121SKalle Valo * position preceding WRITE is the last slot the firmware can place a packet. 63e705c121SKalle Valo * 64e705c121SKalle Valo * The queue is empty (no good data) if WRITE = READ - 1, and is full if 65e705c121SKalle Valo * WRITE = READ. 66e705c121SKalle Valo * 67e705c121SKalle Valo * During initialization, the host sets up the READ queue position to the first 68e705c121SKalle Valo * INDEX position, and WRITE to the last (READ - 1 wrapped) 69e705c121SKalle Valo * 70e705c121SKalle Valo * When the firmware places a packet in a buffer, it will advance the READ index 71e705c121SKalle Valo * and fire the RX interrupt. The driver can then query the READ index and 72e705c121SKalle Valo * process as many packets as possible, moving the WRITE index forward as it 73e705c121SKalle Valo * resets the Rx queue buffers with new memory. 74e705c121SKalle Valo * 75e705c121SKalle Valo * The management in the driver is as follows: 76e705c121SKalle Valo * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 77e705c121SKalle Valo * When the interrupt handler is called, the request is processed. 78e705c121SKalle Valo * The page is either stolen - transferred to the upper layer 79e705c121SKalle Valo * or reused - added immediately to the iwl->rxq->rx_free list. 80e705c121SKalle Valo * + When the page is stolen - the driver updates the matching queue's used 81e705c121SKalle Valo * count, detaches the RBD and transfers it to the queue used list. 82e705c121SKalle Valo * When there are two used RBDs - they are transferred to the allocator empty 83e705c121SKalle Valo * list. Work is then scheduled for the allocator to start allocating 84e705c121SKalle Valo * eight buffers. 85e705c121SKalle Valo * When there are another 6 used RBDs - they are transferred to the allocator 86e705c121SKalle Valo * empty list and the driver tries to claim the pre-allocated buffers and 87e705c121SKalle Valo * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 88e705c121SKalle Valo * until ready. 89e705c121SKalle Valo * When there are 8+ buffers in the free list - either from allocation or from 90e705c121SKalle Valo * 8 reused unstolen pages - restock is called to update the FW and indexes. 91e705c121SKalle Valo * + In order to make sure the allocator always has RBDs to use for allocation 92e705c121SKalle Valo * the allocator has initial pool in the size of num_queues*(8-2) - the 93e705c121SKalle Valo * maximum missing RBDs per allocation request (request posted with 2 94e705c121SKalle Valo * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 95e705c121SKalle Valo * The queues supplies the recycle of the rest of the RBDs. 96e705c121SKalle Valo * + A received packet is processed and handed to the kernel network stack, 97e705c121SKalle Valo * detached from the iwl->rxq. The driver 'processed' index is updated. 98e705c121SKalle Valo * + If there are no allocated buffers in iwl->rxq->rx_free, 99e705c121SKalle Valo * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 100e705c121SKalle Valo * If there were enough free buffers and RX_STALLED is set it is cleared. 101e705c121SKalle Valo * 102e705c121SKalle Valo * 103e705c121SKalle Valo * Driver sequence: 104e705c121SKalle Valo * 105e705c121SKalle Valo * iwl_rxq_alloc() Allocates rx_free 106e705c121SKalle Valo * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 107e705c121SKalle Valo * iwl_pcie_rxq_restock. 108e705c121SKalle Valo * Used only during initialization. 109e705c121SKalle Valo * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 110e705c121SKalle Valo * queue, updates firmware pointers, and updates 111e705c121SKalle Valo * the WRITE index. 112e705c121SKalle Valo * iwl_pcie_rx_allocator() Background work for allocating pages. 113e705c121SKalle Valo * 114e705c121SKalle Valo * -- enable interrupts -- 115e705c121SKalle Valo * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 116e705c121SKalle Valo * READ INDEX, detaching the SKB from the pool. 117e705c121SKalle Valo * Moves the packet buffer from queue to rx_used. 118e705c121SKalle Valo * Posts and claims requests to the allocator. 119e705c121SKalle Valo * Calls iwl_pcie_rxq_restock to refill any empty 120e705c121SKalle Valo * slots. 121e705c121SKalle Valo * 122e705c121SKalle Valo * RBD life-cycle: 123e705c121SKalle Valo * 124e705c121SKalle Valo * Init: 125e705c121SKalle Valo * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 126e705c121SKalle Valo * 127e705c121SKalle Valo * Regular Receive interrupt: 128e705c121SKalle Valo * Page Stolen: 129e705c121SKalle Valo * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 130e705c121SKalle Valo * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 131e705c121SKalle Valo * Page not Stolen: 132e705c121SKalle Valo * rxq.queue -> rxq.rx_free -> rxq.queue 133e705c121SKalle Valo * ... 134e705c121SKalle Valo * 135e705c121SKalle Valo */ 136e705c121SKalle Valo 137e705c121SKalle Valo /* 138e705c121SKalle Valo * iwl_rxq_space - Return number of free slots available in queue. 139e705c121SKalle Valo */ 140e705c121SKalle Valo static int iwl_rxq_space(const struct iwl_rxq *rxq) 141e705c121SKalle Valo { 14296a6497bSSara Sharon /* Make sure rx queue size is a power of 2 */ 14396a6497bSSara Sharon WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 144e705c121SKalle Valo 145e705c121SKalle Valo /* 146e705c121SKalle Valo * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 147e705c121SKalle Valo * between empty and completely full queues. 148e705c121SKalle Valo * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 149e705c121SKalle Valo * defined for negative dividends. 150e705c121SKalle Valo */ 15196a6497bSSara Sharon return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 152e705c121SKalle Valo } 153e705c121SKalle Valo 154e705c121SKalle Valo /* 155e705c121SKalle Valo * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 156e705c121SKalle Valo */ 157e705c121SKalle Valo static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 158e705c121SKalle Valo { 159e705c121SKalle Valo return cpu_to_le32((u32)(dma_addr >> 8)); 160e705c121SKalle Valo } 161e705c121SKalle Valo 162e705c121SKalle Valo /* 163e705c121SKalle Valo * iwl_pcie_rx_stop - stops the Rx DMA 164e705c121SKalle Valo */ 165e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans) 166e705c121SKalle Valo { 167d0158235SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 168d0158235SGolan Ben Ami /* TODO: remove this for 22560 once fw does it */ 169d0158235SGolan Ben Ami iwl_write_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 170d0158235SGolan Ben Ami return iwl_poll_prph_bit(trans, RFH_GEN_STATUS_GEN3, 171d0158235SGolan Ben Ami RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 172d0158235SGolan Ben Ami } else if (trans->cfg->mq_rx_supported) { 173d7fdd0e5SSara Sharon iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 174d7fdd0e5SSara Sharon return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 175d7fdd0e5SSara Sharon RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 176d7fdd0e5SSara Sharon } else { 177e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 178e705c121SKalle Valo return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 179d7fdd0e5SSara Sharon FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 180d7fdd0e5SSara Sharon 1000); 181d7fdd0e5SSara Sharon } 182e705c121SKalle Valo } 183e705c121SKalle Valo 184e705c121SKalle Valo /* 185e705c121SKalle Valo * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 186e705c121SKalle Valo */ 18778485054SSara Sharon static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 18878485054SSara Sharon struct iwl_rxq *rxq) 189e705c121SKalle Valo { 190e705c121SKalle Valo u32 reg; 191e705c121SKalle Valo 192e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 193e705c121SKalle Valo 194e705c121SKalle Valo /* 195e705c121SKalle Valo * explicitly wake up the NIC if: 196e705c121SKalle Valo * 1. shadow registers aren't enabled 197e705c121SKalle Valo * 2. there is a chance that the NIC is asleep 198e705c121SKalle Valo */ 199e705c121SKalle Valo if (!trans->cfg->base_params->shadow_reg_enable && 200e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 201e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 202e705c121SKalle Valo 203e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 204e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 205e705c121SKalle Valo reg); 206e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 207a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 208e705c121SKalle Valo rxq->need_update = true; 209e705c121SKalle Valo return; 210e705c121SKalle Valo } 211e705c121SKalle Valo } 212e705c121SKalle Valo 213e705c121SKalle Valo rxq->write_actual = round_down(rxq->write, 8); 2141b493e30SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 2151b493e30SGolan Ben Ami iwl_write32(trans, HBUS_TARG_WRPTR, 2161b493e30SGolan Ben Ami (rxq->write_actual | 2171b493e30SGolan Ben Ami ((FIRST_RX_QUEUE + rxq->id) << 16))); 2181b493e30SGolan Ben Ami else if (trans->cfg->mq_rx_supported) 2191554ed20SSara Sharon iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 22096a6497bSSara Sharon rxq->write_actual); 2211316d595SSara Sharon else 222e705c121SKalle Valo iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 223e705c121SKalle Valo } 224e705c121SKalle Valo 225e705c121SKalle Valo static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 226e705c121SKalle Valo { 227e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 22878485054SSara Sharon int i; 229e705c121SKalle Valo 23078485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 23178485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 232e705c121SKalle Valo 233e705c121SKalle Valo if (!rxq->need_update) 23478485054SSara Sharon continue; 23578485054SSara Sharon spin_lock(&rxq->lock); 23678485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 237e705c121SKalle Valo rxq->need_update = false; 238e705c121SKalle Valo spin_unlock(&rxq->lock); 239e705c121SKalle Valo } 24078485054SSara Sharon } 241e705c121SKalle Valo 2420307c839SGolan Ben Ami static void iwl_pcie_restock_bd(struct iwl_trans *trans, 2430307c839SGolan Ben Ami struct iwl_rxq *rxq, 2440307c839SGolan Ben Ami struct iwl_rx_mem_buffer *rxb) 2450307c839SGolan Ben Ami { 2460307c839SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 2470307c839SGolan Ben Ami struct iwl_rx_transfer_desc *bd = rxq->bd; 2480307c839SGolan Ben Ami 2490307c839SGolan Ben Ami bd[rxq->write].type_n_size = 2500307c839SGolan Ben Ami cpu_to_le32((IWL_RX_TD_TYPE & IWL_RX_TD_TYPE_MSK) | 2510307c839SGolan Ben Ami ((IWL_RX_TD_SIZE_2K >> 8) & IWL_RX_TD_SIZE_MSK)); 2520307c839SGolan Ben Ami bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 2530307c839SGolan Ben Ami bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 2540307c839SGolan Ben Ami } else { 2550307c839SGolan Ben Ami __le64 *bd = rxq->bd; 2560307c839SGolan Ben Ami 2570307c839SGolan Ben Ami bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 2580307c839SGolan Ben Ami } 25985d78bb1SSara Sharon 26085d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n", 26185d78bb1SSara Sharon (u32)rxb->vid, rxq->id, rxq->write); 2620307c839SGolan Ben Ami } 2630307c839SGolan Ben Ami 264e0e168dcSGregory Greenman /* 2652047fa54SSara Sharon * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 266e0e168dcSGregory Greenman */ 2672047fa54SSara Sharon static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 26896a6497bSSara Sharon struct iwl_rxq *rxq) 26996a6497bSSara Sharon { 27096a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb; 27196a6497bSSara Sharon 27296a6497bSSara Sharon /* 27396a6497bSSara Sharon * If the device isn't enabled - no need to try to add buffers... 27496a6497bSSara Sharon * This can happen when we stop the device and still have an interrupt 27596a6497bSSara Sharon * pending. We stop the APM before we sync the interrupts because we 27696a6497bSSara Sharon * have to (see comment there). On the other hand, since the APM is 27796a6497bSSara Sharon * stopped, we cannot access the HW (in particular not prph). 27896a6497bSSara Sharon * So don't try to restock if the APM has been already stopped. 27996a6497bSSara Sharon */ 28096a6497bSSara Sharon if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 28196a6497bSSara Sharon return; 28296a6497bSSara Sharon 28396a6497bSSara Sharon spin_lock(&rxq->lock); 28496a6497bSSara Sharon while (rxq->free_count) { 28596a6497bSSara Sharon /* Get next free Rx buffer, remove from free list */ 28696a6497bSSara Sharon rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 28796a6497bSSara Sharon list); 28896a6497bSSara Sharon list_del(&rxb->list); 289b1753c62SSara Sharon rxb->invalid = false; 29096a6497bSSara Sharon /* 12 first bits are expected to be empty */ 29196a6497bSSara Sharon WARN_ON(rxb->page_dma & DMA_BIT_MASK(12)); 29296a6497bSSara Sharon /* Point to Rx buffer via next RBD in circular buffer */ 2930307c839SGolan Ben Ami iwl_pcie_restock_bd(trans, rxq, rxb); 29496a6497bSSara Sharon rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK; 29596a6497bSSara Sharon rxq->free_count--; 29696a6497bSSara Sharon } 29796a6497bSSara Sharon spin_unlock(&rxq->lock); 29896a6497bSSara Sharon 29996a6497bSSara Sharon /* 30096a6497bSSara Sharon * If we've added more space for the firmware to place data, tell it. 30196a6497bSSara Sharon * Increment device's write pointer in multiples of 8. 30296a6497bSSara Sharon */ 30396a6497bSSara Sharon if (rxq->write_actual != (rxq->write & ~0x7)) { 30496a6497bSSara Sharon spin_lock(&rxq->lock); 30596a6497bSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 30696a6497bSSara Sharon spin_unlock(&rxq->lock); 30796a6497bSSara Sharon } 30896a6497bSSara Sharon } 30996a6497bSSara Sharon 310e705c121SKalle Valo /* 3112047fa54SSara Sharon * iwl_pcie_rxsq_restock - restock implementation for single queue rx 312e705c121SKalle Valo */ 3132047fa54SSara Sharon static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 314e0e168dcSGregory Greenman struct iwl_rxq *rxq) 315e705c121SKalle Valo { 316e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 317e705c121SKalle Valo 318e705c121SKalle Valo /* 319e705c121SKalle Valo * If the device isn't enabled - not need to try to add buffers... 320e705c121SKalle Valo * This can happen when we stop the device and still have an interrupt 321e705c121SKalle Valo * pending. We stop the APM before we sync the interrupts because we 322e705c121SKalle Valo * have to (see comment there). On the other hand, since the APM is 323e705c121SKalle Valo * stopped, we cannot access the HW (in particular not prph). 324e705c121SKalle Valo * So don't try to restock if the APM has been already stopped. 325e705c121SKalle Valo */ 326e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 327e705c121SKalle Valo return; 328e705c121SKalle Valo 329e705c121SKalle Valo spin_lock(&rxq->lock); 330e705c121SKalle Valo while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 33196a6497bSSara Sharon __le32 *bd = (__le32 *)rxq->bd; 332e705c121SKalle Valo /* The overwritten rxb must be a used one */ 333e705c121SKalle Valo rxb = rxq->queue[rxq->write]; 334e705c121SKalle Valo BUG_ON(rxb && rxb->page); 335e705c121SKalle Valo 336e705c121SKalle Valo /* Get next free Rx buffer, remove from free list */ 337e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 338e705c121SKalle Valo list); 339e705c121SKalle Valo list_del(&rxb->list); 340b1753c62SSara Sharon rxb->invalid = false; 341e705c121SKalle Valo 342e705c121SKalle Valo /* Point to Rx buffer via next RBD in circular buffer */ 34396a6497bSSara Sharon bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 344e705c121SKalle Valo rxq->queue[rxq->write] = rxb; 345e705c121SKalle Valo rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 346e705c121SKalle Valo rxq->free_count--; 347e705c121SKalle Valo } 348e705c121SKalle Valo spin_unlock(&rxq->lock); 349e705c121SKalle Valo 350e705c121SKalle Valo /* If we've added more space for the firmware to place data, tell it. 351e705c121SKalle Valo * Increment device's write pointer in multiples of 8. */ 352e705c121SKalle Valo if (rxq->write_actual != (rxq->write & ~0x7)) { 353e705c121SKalle Valo spin_lock(&rxq->lock); 35478485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 355e705c121SKalle Valo spin_unlock(&rxq->lock); 356e705c121SKalle Valo } 357e705c121SKalle Valo } 358e705c121SKalle Valo 359e705c121SKalle Valo /* 360e0e168dcSGregory Greenman * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 361e0e168dcSGregory Greenman * 362e0e168dcSGregory Greenman * If there are slots in the RX queue that need to be restocked, 363e0e168dcSGregory Greenman * and we have free pre-allocated buffers, fill the ranks as much 364e0e168dcSGregory Greenman * as we can, pulling from rx_free. 365e0e168dcSGregory Greenman * 366e0e168dcSGregory Greenman * This moves the 'write' index forward to catch up with 'processed', and 367e0e168dcSGregory Greenman * also updates the memory address in the firmware to reference the new 368e0e168dcSGregory Greenman * target buffer. 369e0e168dcSGregory Greenman */ 370e0e168dcSGregory Greenman static 371e0e168dcSGregory Greenman void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 372e0e168dcSGregory Greenman { 373e0e168dcSGregory Greenman if (trans->cfg->mq_rx_supported) 3742047fa54SSara Sharon iwl_pcie_rxmq_restock(trans, rxq); 375e0e168dcSGregory Greenman else 3762047fa54SSara Sharon iwl_pcie_rxsq_restock(trans, rxq); 377e0e168dcSGregory Greenman } 378e0e168dcSGregory Greenman 379e0e168dcSGregory Greenman /* 380e705c121SKalle Valo * iwl_pcie_rx_alloc_page - allocates and returns a page. 381e705c121SKalle Valo * 382e705c121SKalle Valo */ 383e705c121SKalle Valo static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 384e705c121SKalle Valo gfp_t priority) 385e705c121SKalle Valo { 386e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 387e705c121SKalle Valo struct page *page; 388e705c121SKalle Valo gfp_t gfp_mask = priority; 389e705c121SKalle Valo 390e705c121SKalle Valo if (trans_pcie->rx_page_order > 0) 391e705c121SKalle Valo gfp_mask |= __GFP_COMP; 392e705c121SKalle Valo 393e705c121SKalle Valo /* Alloc a new receive buffer */ 394e705c121SKalle Valo page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 395e705c121SKalle Valo if (!page) { 396e705c121SKalle Valo if (net_ratelimit()) 397e705c121SKalle Valo IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 398e705c121SKalle Valo trans_pcie->rx_page_order); 39978485054SSara Sharon /* 40078485054SSara Sharon * Issue an error if we don't have enough pre-allocated 40178485054SSara Sharon * buffers. 402e705c121SKalle Valo ` */ 40378485054SSara Sharon if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 404e705c121SKalle Valo IWL_CRIT(trans, 40578485054SSara Sharon "Failed to alloc_pages\n"); 406e705c121SKalle Valo return NULL; 407e705c121SKalle Valo } 408e705c121SKalle Valo return page; 409e705c121SKalle Valo } 410e705c121SKalle Valo 411e705c121SKalle Valo /* 412e705c121SKalle Valo * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 413e705c121SKalle Valo * 414e705c121SKalle Valo * A used RBD is an Rx buffer that has been given to the stack. To use it again 415e705c121SKalle Valo * a page must be allocated and the RBD must point to the page. This function 416e705c121SKalle Valo * doesn't change the HW pointer but handles the list of pages that is used by 417e705c121SKalle Valo * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 418e705c121SKalle Valo * allocated buffers. 419e705c121SKalle Valo */ 420ff932f61SGolan Ben Ami void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 42178485054SSara Sharon struct iwl_rxq *rxq) 422e705c121SKalle Valo { 423e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 424e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 425e705c121SKalle Valo struct page *page; 426e705c121SKalle Valo 427e705c121SKalle Valo while (1) { 428e705c121SKalle Valo spin_lock(&rxq->lock); 429e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 430e705c121SKalle Valo spin_unlock(&rxq->lock); 431e705c121SKalle Valo return; 432e705c121SKalle Valo } 433e705c121SKalle Valo spin_unlock(&rxq->lock); 434e705c121SKalle Valo 435e705c121SKalle Valo /* Alloc a new receive buffer */ 436e705c121SKalle Valo page = iwl_pcie_rx_alloc_page(trans, priority); 437e705c121SKalle Valo if (!page) 438e705c121SKalle Valo return; 439e705c121SKalle Valo 440e705c121SKalle Valo spin_lock(&rxq->lock); 441e705c121SKalle Valo 442e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 443e705c121SKalle Valo spin_unlock(&rxq->lock); 444e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 445e705c121SKalle Valo return; 446e705c121SKalle Valo } 447e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 448e705c121SKalle Valo list); 449e705c121SKalle Valo list_del(&rxb->list); 450e705c121SKalle Valo spin_unlock(&rxq->lock); 451e705c121SKalle Valo 452e705c121SKalle Valo BUG_ON(rxb->page); 453e705c121SKalle Valo rxb->page = page; 454e705c121SKalle Valo /* Get physical address of the RB */ 455e705c121SKalle Valo rxb->page_dma = 456e705c121SKalle Valo dma_map_page(trans->dev, page, 0, 457e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 458e705c121SKalle Valo DMA_FROM_DEVICE); 459e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 460e705c121SKalle Valo rxb->page = NULL; 461e705c121SKalle Valo spin_lock(&rxq->lock); 462e705c121SKalle Valo list_add(&rxb->list, &rxq->rx_used); 463e705c121SKalle Valo spin_unlock(&rxq->lock); 464e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 465e705c121SKalle Valo return; 466e705c121SKalle Valo } 467e705c121SKalle Valo 468e705c121SKalle Valo spin_lock(&rxq->lock); 469e705c121SKalle Valo 470e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 471e705c121SKalle Valo rxq->free_count++; 472e705c121SKalle Valo 473e705c121SKalle Valo spin_unlock(&rxq->lock); 474e705c121SKalle Valo } 475e705c121SKalle Valo } 476e705c121SKalle Valo 477ff932f61SGolan Ben Ami void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 478e705c121SKalle Valo { 479e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 480e705c121SKalle Valo int i; 481e705c121SKalle Valo 4827b542436SSara Sharon for (i = 0; i < RX_POOL_SIZE; i++) { 48378485054SSara Sharon if (!trans_pcie->rx_pool[i].page) 484e705c121SKalle Valo continue; 48578485054SSara Sharon dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 486e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 487e705c121SKalle Valo DMA_FROM_DEVICE); 48878485054SSara Sharon __free_pages(trans_pcie->rx_pool[i].page, 48978485054SSara Sharon trans_pcie->rx_page_order); 49078485054SSara Sharon trans_pcie->rx_pool[i].page = NULL; 491e705c121SKalle Valo } 492e705c121SKalle Valo } 493e705c121SKalle Valo 494e705c121SKalle Valo /* 495e705c121SKalle Valo * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 496e705c121SKalle Valo * 497e705c121SKalle Valo * Allocates for each received request 8 pages 498e705c121SKalle Valo * Called as a scheduled work item. 499e705c121SKalle Valo */ 500e705c121SKalle Valo static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 501e705c121SKalle Valo { 502e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 503e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 504e705c121SKalle Valo struct list_head local_empty; 505e705c121SKalle Valo int pending = atomic_xchg(&rba->req_pending, 0); 506e705c121SKalle Valo 507e705c121SKalle Valo IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending); 508e705c121SKalle Valo 509e705c121SKalle Valo /* If we were scheduled - there is at least one request */ 510e705c121SKalle Valo spin_lock(&rba->lock); 511e705c121SKalle Valo /* swap out the rba->rbd_empty to a local list */ 512e705c121SKalle Valo list_replace_init(&rba->rbd_empty, &local_empty); 513e705c121SKalle Valo spin_unlock(&rba->lock); 514e705c121SKalle Valo 515e705c121SKalle Valo while (pending) { 516e705c121SKalle Valo int i; 5170979a913SJohannes Berg LIST_HEAD(local_allocated); 51878485054SSara Sharon gfp_t gfp_mask = GFP_KERNEL; 51978485054SSara Sharon 52078485054SSara Sharon /* Do not post a warning if there are only a few requests */ 52178485054SSara Sharon if (pending < RX_PENDING_WATERMARK) 52278485054SSara Sharon gfp_mask |= __GFP_NOWARN; 523e705c121SKalle Valo 524e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 525e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 526e705c121SKalle Valo struct page *page; 527e705c121SKalle Valo 528e705c121SKalle Valo /* List should never be empty - each reused RBD is 529e705c121SKalle Valo * returned to the list, and initial pool covers any 530e705c121SKalle Valo * possible gap between the time the page is allocated 531e705c121SKalle Valo * to the time the RBD is added. 532e705c121SKalle Valo */ 533e705c121SKalle Valo BUG_ON(list_empty(&local_empty)); 534e705c121SKalle Valo /* Get the first rxb from the rbd list */ 535e705c121SKalle Valo rxb = list_first_entry(&local_empty, 536e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 537e705c121SKalle Valo BUG_ON(rxb->page); 538e705c121SKalle Valo 539e705c121SKalle Valo /* Alloc a new receive buffer */ 54078485054SSara Sharon page = iwl_pcie_rx_alloc_page(trans, gfp_mask); 541e705c121SKalle Valo if (!page) 542e705c121SKalle Valo continue; 543e705c121SKalle Valo rxb->page = page; 544e705c121SKalle Valo 545e705c121SKalle Valo /* Get physical address of the RB */ 546e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, page, 0, 547e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 548e705c121SKalle Valo DMA_FROM_DEVICE); 549e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 550e705c121SKalle Valo rxb->page = NULL; 551e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 552e705c121SKalle Valo continue; 553e705c121SKalle Valo } 554e705c121SKalle Valo 555e705c121SKalle Valo /* move the allocated entry to the out list */ 556e705c121SKalle Valo list_move(&rxb->list, &local_allocated); 557e705c121SKalle Valo i++; 558e705c121SKalle Valo } 559e705c121SKalle Valo 560e705c121SKalle Valo pending--; 561e705c121SKalle Valo if (!pending) { 562e705c121SKalle Valo pending = atomic_xchg(&rba->req_pending, 0); 563e705c121SKalle Valo IWL_DEBUG_RX(trans, 564e705c121SKalle Valo "Pending allocation requests = %d\n", 565e705c121SKalle Valo pending); 566e705c121SKalle Valo } 567e705c121SKalle Valo 568e705c121SKalle Valo spin_lock(&rba->lock); 569e705c121SKalle Valo /* add the allocated rbds to the allocator allocated list */ 570e705c121SKalle Valo list_splice_tail(&local_allocated, &rba->rbd_allocated); 571e705c121SKalle Valo /* get more empty RBDs for current pending requests */ 572e705c121SKalle Valo list_splice_tail_init(&rba->rbd_empty, &local_empty); 573e705c121SKalle Valo spin_unlock(&rba->lock); 574e705c121SKalle Valo 575e705c121SKalle Valo atomic_inc(&rba->req_ready); 576e705c121SKalle Valo } 577e705c121SKalle Valo 578e705c121SKalle Valo spin_lock(&rba->lock); 579e705c121SKalle Valo /* return unused rbds to the allocator empty list */ 580e705c121SKalle Valo list_splice_tail(&local_empty, &rba->rbd_empty); 581e705c121SKalle Valo spin_unlock(&rba->lock); 582e705c121SKalle Valo } 583e705c121SKalle Valo 584e705c121SKalle Valo /* 585d56daea4SSara Sharon * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 586e705c121SKalle Valo .* 587e705c121SKalle Valo .* Called by queue when the queue posted allocation request and 588e705c121SKalle Valo * has freed 8 RBDs in order to restock itself. 589d56daea4SSara Sharon * This function directly moves the allocated RBs to the queue's ownership 590d56daea4SSara Sharon * and updates the relevant counters. 591e705c121SKalle Valo */ 592d56daea4SSara Sharon static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 593d56daea4SSara Sharon struct iwl_rxq *rxq) 594e705c121SKalle Valo { 595e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 596e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 597e705c121SKalle Valo int i; 598e705c121SKalle Valo 599d56daea4SSara Sharon lockdep_assert_held(&rxq->lock); 600d56daea4SSara Sharon 601e705c121SKalle Valo /* 602e705c121SKalle Valo * atomic_dec_if_positive returns req_ready - 1 for any scenario. 603e705c121SKalle Valo * If req_ready is 0 atomic_dec_if_positive will return -1 and this 604d56daea4SSara Sharon * function will return early, as there are no ready requests. 605e705c121SKalle Valo * atomic_dec_if_positive will perofrm the *actual* decrement only if 606e705c121SKalle Valo * req_ready > 0, i.e. - there are ready requests and the function 607e705c121SKalle Valo * hands one request to the caller. 608e705c121SKalle Valo */ 609e705c121SKalle Valo if (atomic_dec_if_positive(&rba->req_ready) < 0) 610d56daea4SSara Sharon return; 611e705c121SKalle Valo 612e705c121SKalle Valo spin_lock(&rba->lock); 613e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 614e705c121SKalle Valo /* Get next free Rx buffer, remove it from free list */ 615d56daea4SSara Sharon struct iwl_rx_mem_buffer *rxb = 616d56daea4SSara Sharon list_first_entry(&rba->rbd_allocated, 617e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 618d56daea4SSara Sharon 619d56daea4SSara Sharon list_move(&rxb->list, &rxq->rx_free); 620e705c121SKalle Valo } 621e705c121SKalle Valo spin_unlock(&rba->lock); 622e705c121SKalle Valo 623d56daea4SSara Sharon rxq->used_count -= RX_CLAIM_REQ_ALLOC; 624d56daea4SSara Sharon rxq->free_count += RX_CLAIM_REQ_ALLOC; 625e705c121SKalle Valo } 626e705c121SKalle Valo 62710a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data) 628e705c121SKalle Valo { 629e705c121SKalle Valo struct iwl_rb_allocator *rba_p = 630e705c121SKalle Valo container_of(data, struct iwl_rb_allocator, rx_alloc); 631e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 632e705c121SKalle Valo container_of(rba_p, struct iwl_trans_pcie, rba); 633e705c121SKalle Valo 634e705c121SKalle Valo iwl_pcie_rx_allocator(trans_pcie->trans); 635e705c121SKalle Valo } 636e705c121SKalle Valo 6370307c839SGolan Ben Ami static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td) 6380307c839SGolan Ben Ami { 6390307c839SGolan Ben Ami struct iwl_rx_transfer_desc *rx_td; 6400307c839SGolan Ben Ami 6410307c839SGolan Ben Ami if (use_rx_td) 6420307c839SGolan Ben Ami return sizeof(*rx_td); 6430307c839SGolan Ben Ami else 6440307c839SGolan Ben Ami return trans->cfg->mq_rx_supported ? sizeof(__le64) : 6450307c839SGolan Ben Ami sizeof(__le32); 6460307c839SGolan Ben Ami } 6470307c839SGolan Ben Ami 6481b493e30SGolan Ben Ami static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 6491b493e30SGolan Ben Ami struct iwl_rxq *rxq) 6501b493e30SGolan Ben Ami { 6511b493e30SGolan Ben Ami struct device *dev = trans->dev; 6520307c839SGolan Ben Ami bool use_rx_td = (trans->cfg->device_family >= 6530307c839SGolan Ben Ami IWL_DEVICE_FAMILY_22560); 6540307c839SGolan Ben Ami int free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 6551b493e30SGolan Ben Ami 6561b493e30SGolan Ben Ami if (rxq->bd) 6570307c839SGolan Ben Ami dma_free_coherent(trans->dev, 6580307c839SGolan Ben Ami free_size * rxq->queue_size, 6591b493e30SGolan Ben Ami rxq->bd, rxq->bd_dma); 6601b493e30SGolan Ben Ami rxq->bd_dma = 0; 6611b493e30SGolan Ben Ami rxq->bd = NULL; 6621b493e30SGolan Ben Ami 6631b493e30SGolan Ben Ami if (rxq->rb_stts) 6641b493e30SGolan Ben Ami dma_free_coherent(trans->dev, 6650307c839SGolan Ben Ami use_rx_td ? sizeof(__le16) : 6661b493e30SGolan Ben Ami sizeof(struct iwl_rb_status), 6671b493e30SGolan Ben Ami rxq->rb_stts, rxq->rb_stts_dma); 6681b493e30SGolan Ben Ami rxq->rb_stts_dma = 0; 6691b493e30SGolan Ben Ami rxq->rb_stts = NULL; 6701b493e30SGolan Ben Ami 6711b493e30SGolan Ben Ami if (rxq->used_bd) 6720307c839SGolan Ben Ami dma_free_coherent(trans->dev, 673b2a58c97SSara Sharon (use_rx_td ? sizeof(*rxq->cd) : 6740307c839SGolan Ben Ami sizeof(__le32)) * rxq->queue_size, 6751b493e30SGolan Ben Ami rxq->used_bd, rxq->used_bd_dma); 6761b493e30SGolan Ben Ami rxq->used_bd_dma = 0; 6771b493e30SGolan Ben Ami rxq->used_bd = NULL; 6781b493e30SGolan Ben Ami 6791b493e30SGolan Ben Ami if (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) 6801b493e30SGolan Ben Ami return; 6811b493e30SGolan Ben Ami 6821b493e30SGolan Ben Ami if (rxq->tr_tail) 6831b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 6841b493e30SGolan Ben Ami rxq->tr_tail, rxq->tr_tail_dma); 6851b493e30SGolan Ben Ami rxq->tr_tail_dma = 0; 6861b493e30SGolan Ben Ami rxq->tr_tail = NULL; 6871b493e30SGolan Ben Ami 6881b493e30SGolan Ben Ami if (rxq->cr_tail) 6891b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 6901b493e30SGolan Ben Ami rxq->cr_tail, rxq->cr_tail_dma); 6911b493e30SGolan Ben Ami rxq->cr_tail_dma = 0; 6921b493e30SGolan Ben Ami rxq->cr_tail = NULL; 6931b493e30SGolan Ben Ami } 6941b493e30SGolan Ben Ami 6951b493e30SGolan Ben Ami static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 6961b493e30SGolan Ben Ami struct iwl_rxq *rxq) 697e705c121SKalle Valo { 698e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 699e705c121SKalle Valo struct device *dev = trans->dev; 70078485054SSara Sharon int i; 7010307c839SGolan Ben Ami int free_size; 7020307c839SGolan Ben Ami bool use_rx_td = (trans->cfg->device_family >= 7030307c839SGolan Ben Ami IWL_DEVICE_FAMILY_22560); 704e705c121SKalle Valo 70578485054SSara Sharon spin_lock_init(&rxq->lock); 70696a6497bSSara Sharon if (trans->cfg->mq_rx_supported) 70796a6497bSSara Sharon rxq->queue_size = MQ_RX_TABLE_SIZE; 70896a6497bSSara Sharon else 70996a6497bSSara Sharon rxq->queue_size = RX_QUEUE_SIZE; 71096a6497bSSara Sharon 7110307c839SGolan Ben Ami free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 7120307c839SGolan Ben Ami 71378485054SSara Sharon /* 71478485054SSara Sharon * Allocate the circular buffer of Read Buffer Descriptors 71578485054SSara Sharon * (RBDs) 71678485054SSara Sharon */ 71778485054SSara Sharon rxq->bd = dma_zalloc_coherent(dev, 71896a6497bSSara Sharon free_size * rxq->queue_size, 719e705c121SKalle Valo &rxq->bd_dma, GFP_KERNEL); 720e705c121SKalle Valo if (!rxq->bd) 72178485054SSara Sharon goto err; 72278485054SSara Sharon 72396a6497bSSara Sharon if (trans->cfg->mq_rx_supported) { 72496a6497bSSara Sharon rxq->used_bd = dma_zalloc_coherent(dev, 7250307c839SGolan Ben Ami (use_rx_td ? 726b2a58c97SSara Sharon sizeof(*rxq->cd) : 7270307c839SGolan Ben Ami sizeof(__le32)) * 72896a6497bSSara Sharon rxq->queue_size, 72996a6497bSSara Sharon &rxq->used_bd_dma, 73096a6497bSSara Sharon GFP_KERNEL); 73196a6497bSSara Sharon if (!rxq->used_bd) 73296a6497bSSara Sharon goto err; 73396a6497bSSara Sharon } 734e705c121SKalle Valo 735e705c121SKalle Valo /* Allocate the driver's pointer to receive buffer status */ 7360307c839SGolan Ben Ami rxq->rb_stts = dma_zalloc_coherent(dev, use_rx_td ? 7370307c839SGolan Ben Ami sizeof(__le16) : 7380307c839SGolan Ben Ami sizeof(struct iwl_rb_status), 73978485054SSara Sharon &rxq->rb_stts_dma, 74078485054SSara Sharon GFP_KERNEL); 741e705c121SKalle Valo if (!rxq->rb_stts) 74278485054SSara Sharon goto err; 7431b493e30SGolan Ben Ami 7440307c839SGolan Ben Ami if (!use_rx_td) 7451b493e30SGolan Ben Ami return 0; 7461b493e30SGolan Ben Ami 7471b493e30SGolan Ben Ami /* Allocate the driver's pointer to TR tail */ 7481b493e30SGolan Ben Ami rxq->tr_tail = dma_zalloc_coherent(dev, sizeof(__le16), 7491b493e30SGolan Ben Ami &rxq->tr_tail_dma, 7501b493e30SGolan Ben Ami GFP_KERNEL); 7511b493e30SGolan Ben Ami if (!rxq->tr_tail) 7521b493e30SGolan Ben Ami goto err; 7531b493e30SGolan Ben Ami 7541b493e30SGolan Ben Ami /* Allocate the driver's pointer to CR tail */ 7551b493e30SGolan Ben Ami rxq->cr_tail = dma_zalloc_coherent(dev, sizeof(__le16), 7561b493e30SGolan Ben Ami &rxq->cr_tail_dma, 7571b493e30SGolan Ben Ami GFP_KERNEL); 7581b493e30SGolan Ben Ami if (!rxq->cr_tail) 7591b493e30SGolan Ben Ami goto err; 7600307c839SGolan Ben Ami /* 7610307c839SGolan Ben Ami * W/A 22560 device step Z0 must be non zero bug 7620307c839SGolan Ben Ami * TODO: remove this when stop supporting Z0 7630307c839SGolan Ben Ami */ 7640307c839SGolan Ben Ami *rxq->cr_tail = cpu_to_le16(500); 7651b493e30SGolan Ben Ami 766e705c121SKalle Valo return 0; 767e705c121SKalle Valo 76878485054SSara Sharon err: 76978485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 77078485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 77178485054SSara Sharon 7721b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 77378485054SSara Sharon } 77478485054SSara Sharon kfree(trans_pcie->rxq); 77596a6497bSSara Sharon 776e705c121SKalle Valo return -ENOMEM; 777e705c121SKalle Valo } 778e705c121SKalle Valo 77989d5e833SGolan Ben Ami int iwl_pcie_rx_alloc(struct iwl_trans *trans) 7801b493e30SGolan Ben Ami { 7811b493e30SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 7821b493e30SGolan Ben Ami struct iwl_rb_allocator *rba = &trans_pcie->rba; 7831b493e30SGolan Ben Ami int i, ret; 7841b493e30SGolan Ben Ami 7851b493e30SGolan Ben Ami if (WARN_ON(trans_pcie->rxq)) 7861b493e30SGolan Ben Ami return -EINVAL; 7871b493e30SGolan Ben Ami 7881b493e30SGolan Ben Ami trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 7891b493e30SGolan Ben Ami GFP_KERNEL); 7901b493e30SGolan Ben Ami if (!trans_pcie->rxq) 7911b493e30SGolan Ben Ami return -EINVAL; 7921b493e30SGolan Ben Ami 7931b493e30SGolan Ben Ami spin_lock_init(&rba->lock); 7941b493e30SGolan Ben Ami 7951b493e30SGolan Ben Ami for (i = 0; i < trans->num_rx_queues; i++) { 7961b493e30SGolan Ben Ami struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 7971b493e30SGolan Ben Ami 7981b493e30SGolan Ben Ami ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 7991b493e30SGolan Ben Ami if (ret) 8001b493e30SGolan Ben Ami return ret; 8011b493e30SGolan Ben Ami } 8021b493e30SGolan Ben Ami return 0; 8031b493e30SGolan Ben Ami } 8041b493e30SGolan Ben Ami 805e705c121SKalle Valo static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 806e705c121SKalle Valo { 807e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 808e705c121SKalle Valo u32 rb_size; 809dfcfeef9SSara Sharon unsigned long flags; 810e705c121SKalle Valo const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 811e705c121SKalle Valo 8126c4fbcbcSEmmanuel Grumbach switch (trans_pcie->rx_buf_size) { 8136c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 814e705c121SKalle Valo rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8156c4fbcbcSEmmanuel Grumbach break; 8166c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 8176c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 8186c4fbcbcSEmmanuel Grumbach break; 8196c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 8206c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 8216c4fbcbcSEmmanuel Grumbach break; 8226c4fbcbcSEmmanuel Grumbach default: 8236c4fbcbcSEmmanuel Grumbach WARN_ON(1); 8246c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8256c4fbcbcSEmmanuel Grumbach } 826e705c121SKalle Valo 827dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 828dfcfeef9SSara Sharon return; 829dfcfeef9SSara Sharon 830e705c121SKalle Valo /* Stop Rx DMA */ 831dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 832e705c121SKalle Valo /* reset and flush pointers */ 833dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 834dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 835dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 836e705c121SKalle Valo 837e705c121SKalle Valo /* Reset driver's Rx queue write index */ 838dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 839e705c121SKalle Valo 840e705c121SKalle Valo /* Tell device where to find RBD circular buffer in DRAM */ 841dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 842e705c121SKalle Valo (u32)(rxq->bd_dma >> 8)); 843e705c121SKalle Valo 844e705c121SKalle Valo /* Tell device where in DRAM to update its Rx status */ 845dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 846e705c121SKalle Valo rxq->rb_stts_dma >> 4); 847e705c121SKalle Valo 848e705c121SKalle Valo /* Enable Rx DMA 849e705c121SKalle Valo * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 850e705c121SKalle Valo * the credit mechanism in 5000 HW RX FIFO 851e705c121SKalle Valo * Direct rx interrupts to hosts 8526c4fbcbcSEmmanuel Grumbach * Rx buffer size 4 or 8k or 12k 853e705c121SKalle Valo * RB timeout 0x10 854e705c121SKalle Valo * 256 RBDs 855e705c121SKalle Valo */ 856dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 857e705c121SKalle Valo FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 858e705c121SKalle Valo FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 859e705c121SKalle Valo FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 860e705c121SKalle Valo rb_size | 861e705c121SKalle Valo (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 862e705c121SKalle Valo (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 863e705c121SKalle Valo 864dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 865dfcfeef9SSara Sharon 866e705c121SKalle Valo /* Set interrupt coalescing timer to default (2048 usecs) */ 867e705c121SKalle Valo iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 868e705c121SKalle Valo 869e705c121SKalle Valo /* W/A for interrupt coalescing bug in 7260 and 3160 */ 870e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) 871e705c121SKalle Valo iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 872e705c121SKalle Valo } 873e705c121SKalle Valo 874bce97731SSara Sharon static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 87596a6497bSSara Sharon { 87696a6497bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 87796a6497bSSara Sharon u32 rb_size, enabled = 0; 878dfcfeef9SSara Sharon unsigned long flags; 87996a6497bSSara Sharon int i; 88096a6497bSSara Sharon 88196a6497bSSara Sharon switch (trans_pcie->rx_buf_size) { 8821a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 8831a4968d1SGolan Ben Ami rb_size = RFH_RXF_DMA_RB_SIZE_2K; 8841a4968d1SGolan Ben Ami break; 88596a6497bSSara Sharon case IWL_AMSDU_4K: 88696a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 88796a6497bSSara Sharon break; 88896a6497bSSara Sharon case IWL_AMSDU_8K: 88996a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_8K; 89096a6497bSSara Sharon break; 89196a6497bSSara Sharon case IWL_AMSDU_12K: 89296a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_12K; 89396a6497bSSara Sharon break; 89496a6497bSSara Sharon default: 89596a6497bSSara Sharon WARN_ON(1); 89696a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 89796a6497bSSara Sharon } 89896a6497bSSara Sharon 899dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 900dfcfeef9SSara Sharon return; 901dfcfeef9SSara Sharon 90296a6497bSSara Sharon /* Stop Rx DMA */ 903dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 90496a6497bSSara Sharon /* disable free amd used rx queue operation */ 905dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 90696a6497bSSara Sharon 90796a6497bSSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 90896a6497bSSara Sharon /* Tell device where to find RBD free table in DRAM */ 90912a17458SSara Sharon iwl_write_prph64_no_grab(trans, 910dfcfeef9SSara Sharon RFH_Q_FRBDCB_BA_LSB(i), 911dfcfeef9SSara Sharon trans_pcie->rxq[i].bd_dma); 91296a6497bSSara Sharon /* Tell device where to find RBD used table in DRAM */ 91312a17458SSara Sharon iwl_write_prph64_no_grab(trans, 914dfcfeef9SSara Sharon RFH_Q_URBDCB_BA_LSB(i), 915dfcfeef9SSara Sharon trans_pcie->rxq[i].used_bd_dma); 91696a6497bSSara Sharon /* Tell device where in DRAM to update its Rx status */ 91712a17458SSara Sharon iwl_write_prph64_no_grab(trans, 918dfcfeef9SSara Sharon RFH_Q_URBD_STTS_WPTR_LSB(i), 919bce97731SSara Sharon trans_pcie->rxq[i].rb_stts_dma); 92096a6497bSSara Sharon /* Reset device indice tables */ 921dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 922dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 923dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 92496a6497bSSara Sharon 92596a6497bSSara Sharon enabled |= BIT(i) | BIT(i + 16); 92696a6497bSSara Sharon } 92796a6497bSSara Sharon 92896a6497bSSara Sharon /* 92996a6497bSSara Sharon * Enable Rx DMA 93096a6497bSSara Sharon * Rx buffer size 4 or 8k or 12k 93196a6497bSSara Sharon * Min RB size 4 or 8 93288076015SSara Sharon * Drop frames that exceed RB size 93396a6497bSSara Sharon * 512 RBDs 93496a6497bSSara Sharon */ 935dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 93663044335SSara Sharon RFH_DMA_EN_ENABLE_VAL | rb_size | 93796a6497bSSara Sharon RFH_RXF_DMA_MIN_RB_4_8 | 93888076015SSara Sharon RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 93996a6497bSSara Sharon RFH_RXF_DMA_RBDCB_SIZE_512); 94096a6497bSSara Sharon 94188076015SSara Sharon /* 94288076015SSara Sharon * Activate DMA snooping. 943b0262f07SSara Sharon * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 94488076015SSara Sharon * Default queue is 0 94588076015SSara Sharon */ 946f3779f47SJohannes Berg iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 947f3779f47SJohannes Berg RFH_GEN_CFG_RFH_DMA_SNOOP | 948f3779f47SJohannes Berg RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 949b0262f07SSara Sharon RFH_GEN_CFG_SERVICE_DMA_SNOOP | 950f3779f47SJohannes Berg RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 951f3779f47SJohannes Berg trans->cfg->integrated ? 952b0262f07SSara Sharon RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 953f3779f47SJohannes Berg RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 95488076015SSara Sharon /* Enable the relevant rx queues */ 955dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 956dfcfeef9SSara Sharon 957dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 95896a6497bSSara Sharon 95996a6497bSSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 96096a6497bSSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 96196a6497bSSara Sharon } 96296a6497bSSara Sharon 963ff932f61SGolan Ben Ami void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 964e705c121SKalle Valo { 965e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 966e705c121SKalle Valo 967e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_free); 968e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_used); 969e705c121SKalle Valo rxq->free_count = 0; 970e705c121SKalle Valo rxq->used_count = 0; 971e705c121SKalle Valo } 972e705c121SKalle Valo 973ff932f61SGolan Ben Ami int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) 974bce97731SSara Sharon { 975bce97731SSara Sharon WARN_ON(1); 976bce97731SSara Sharon return 0; 977bce97731SSara Sharon } 978bce97731SSara Sharon 97989d5e833SGolan Ben Ami int _iwl_pcie_rx_init(struct iwl_trans *trans) 980e705c121SKalle Valo { 981e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 98278485054SSara Sharon struct iwl_rxq *def_rxq; 983e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 9847b542436SSara Sharon int i, err, queue_size, allocator_pool_size, num_alloc; 985e705c121SKalle Valo 98678485054SSara Sharon if (!trans_pcie->rxq) { 987e705c121SKalle Valo err = iwl_pcie_rx_alloc(trans); 988e705c121SKalle Valo if (err) 989e705c121SKalle Valo return err; 990e705c121SKalle Valo } 99178485054SSara Sharon def_rxq = trans_pcie->rxq; 992e705c121SKalle Valo 9930f22e400SShaul Triebitz cancel_work_sync(&rba->rx_alloc); 9940f22e400SShaul Triebitz 995e705c121SKalle Valo spin_lock(&rba->lock); 996e705c121SKalle Valo atomic_set(&rba->req_pending, 0); 997e705c121SKalle Valo atomic_set(&rba->req_ready, 0); 99896a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_allocated); 99996a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_empty); 1000e705c121SKalle Valo spin_unlock(&rba->lock); 1001e705c121SKalle Valo 1002e705c121SKalle Valo /* free all first - we might be reconfigured for a different size */ 100378485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1004e705c121SKalle Valo 1005e705c121SKalle Valo for (i = 0; i < RX_QUEUE_SIZE; i++) 100678485054SSara Sharon def_rxq->queue[i] = NULL; 1007e705c121SKalle Valo 100878485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 100978485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1010e705c121SKalle Valo 101196a6497bSSara Sharon rxq->id = i; 101296a6497bSSara Sharon 1013e705c121SKalle Valo spin_lock(&rxq->lock); 101478485054SSara Sharon /* 101578485054SSara Sharon * Set read write pointer to reflect that we have processed 101678485054SSara Sharon * and used all buffers, but have not restocked the Rx queue 101778485054SSara Sharon * with fresh buffers 101878485054SSara Sharon */ 101978485054SSara Sharon rxq->read = 0; 102078485054SSara Sharon rxq->write = 0; 102178485054SSara Sharon rxq->write_actual = 0; 10220307c839SGolan Ben Ami memset(rxq->rb_stts, 0, 10230307c839SGolan Ben Ami (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ? 10240307c839SGolan Ben Ami sizeof(__le16) : sizeof(struct iwl_rb_status)); 102578485054SSara Sharon 102678485054SSara Sharon iwl_pcie_rx_init_rxb_lists(rxq); 102778485054SSara Sharon 1028bce97731SSara Sharon if (!rxq->napi.poll) 1029bce97731SSara Sharon netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 1030bce97731SSara Sharon iwl_pcie_dummy_napi_poll, 64); 1031bce97731SSara Sharon 1032e705c121SKalle Valo spin_unlock(&rxq->lock); 103378485054SSara Sharon } 103478485054SSara Sharon 103596a6497bSSara Sharon /* move the pool to the default queue and allocator ownerships */ 10367b542436SSara Sharon queue_size = trans->cfg->mq_rx_supported ? 10377b542436SSara Sharon MQ_RX_NUM_RBDS : RX_QUEUE_SIZE; 103896a6497bSSara Sharon allocator_pool_size = trans->num_rx_queues * 103996a6497bSSara Sharon (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 10407b542436SSara Sharon num_alloc = queue_size + allocator_pool_size; 104143146925SSara Sharon BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) != 104243146925SSara Sharon ARRAY_SIZE(trans_pcie->rx_pool)); 10437b542436SSara Sharon for (i = 0; i < num_alloc; i++) { 104496a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 104596a6497bSSara Sharon 104696a6497bSSara Sharon if (i < allocator_pool_size) 104796a6497bSSara Sharon list_add(&rxb->list, &rba->rbd_empty); 104896a6497bSSara Sharon else 104996a6497bSSara Sharon list_add(&rxb->list, &def_rxq->rx_used); 105096a6497bSSara Sharon trans_pcie->global_table[i] = rxb; 1051e25d65f2SSara Sharon rxb->vid = (u16)(i + 1); 1052b1753c62SSara Sharon rxb->invalid = true; 105396a6497bSSara Sharon } 105478485054SSara Sharon 105578485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 10562047fa54SSara Sharon 1057eda50cdeSSara Sharon return 0; 1058eda50cdeSSara Sharon } 1059eda50cdeSSara Sharon 1060eda50cdeSSara Sharon int iwl_pcie_rx_init(struct iwl_trans *trans) 1061eda50cdeSSara Sharon { 1062eda50cdeSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1063eda50cdeSSara Sharon int ret = _iwl_pcie_rx_init(trans); 1064eda50cdeSSara Sharon 1065eda50cdeSSara Sharon if (ret) 1066eda50cdeSSara Sharon return ret; 1067eda50cdeSSara Sharon 10682047fa54SSara Sharon if (trans->cfg->mq_rx_supported) 1069bce97731SSara Sharon iwl_pcie_rx_mq_hw_init(trans); 10702047fa54SSara Sharon else 1071eda50cdeSSara Sharon iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 10722047fa54SSara Sharon 1073eda50cdeSSara Sharon iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 107478485054SSara Sharon 1075eda50cdeSSara Sharon spin_lock(&trans_pcie->rxq->lock); 1076eda50cdeSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 1077eda50cdeSSara Sharon spin_unlock(&trans_pcie->rxq->lock); 1078e705c121SKalle Valo 1079e705c121SKalle Valo return 0; 1080e705c121SKalle Valo } 1081e705c121SKalle Valo 1082eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1083eda50cdeSSara Sharon { 1084e506b481SSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 1085e506b481SSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1086e506b481SSara Sharon 1087eda50cdeSSara Sharon /* 1088eda50cdeSSara Sharon * We don't configure the RFH. 1089eda50cdeSSara Sharon * Restock will be done at alive, after firmware configured the RFH. 1090eda50cdeSSara Sharon */ 1091eda50cdeSSara Sharon return _iwl_pcie_rx_init(trans); 1092eda50cdeSSara Sharon } 1093eda50cdeSSara Sharon 1094e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans) 1095e705c121SKalle Valo { 1096e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1097e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 109878485054SSara Sharon int i; 1099e705c121SKalle Valo 110078485054SSara Sharon /* 110178485054SSara Sharon * if rxq is NULL, it means that nothing has been allocated, 110278485054SSara Sharon * exit now 110378485054SSara Sharon */ 110478485054SSara Sharon if (!trans_pcie->rxq) { 1105e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1106e705c121SKalle Valo return; 1107e705c121SKalle Valo } 1108e705c121SKalle Valo 1109e705c121SKalle Valo cancel_work_sync(&rba->rx_alloc); 1110e705c121SKalle Valo 111178485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1112e705c121SKalle Valo 111378485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 111478485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 111578485054SSara Sharon 11161b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 1117bce97731SSara Sharon 1118bce97731SSara Sharon if (rxq->napi.poll) 1119bce97731SSara Sharon netif_napi_del(&rxq->napi); 112096a6497bSSara Sharon } 112178485054SSara Sharon kfree(trans_pcie->rxq); 1122e705c121SKalle Valo } 1123e705c121SKalle Valo 1124868a1e86SShaul Triebitz static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq, 1125868a1e86SShaul Triebitz struct iwl_rb_allocator *rba) 1126868a1e86SShaul Triebitz { 1127868a1e86SShaul Triebitz spin_lock(&rba->lock); 1128868a1e86SShaul Triebitz list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1129868a1e86SShaul Triebitz spin_unlock(&rba->lock); 1130868a1e86SShaul Triebitz } 1131868a1e86SShaul Triebitz 1132e705c121SKalle Valo /* 1133e705c121SKalle Valo * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1134e705c121SKalle Valo * 1135e705c121SKalle Valo * Called when a RBD can be reused. The RBD is transferred to the allocator. 1136e705c121SKalle Valo * When there are 2 empty RBDs - a request for allocation is posted 1137e705c121SKalle Valo */ 1138e705c121SKalle Valo static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1139e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 1140e705c121SKalle Valo struct iwl_rxq *rxq, bool emergency) 1141e705c121SKalle Valo { 1142e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1143e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 1144e705c121SKalle Valo 1145e705c121SKalle Valo /* Move the RBD to the used list, will be moved to allocator in batches 1146e705c121SKalle Valo * before claiming or posting a request*/ 1147e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_used); 1148e705c121SKalle Valo 1149e705c121SKalle Valo if (unlikely(emergency)) 1150e705c121SKalle Valo return; 1151e705c121SKalle Valo 1152e705c121SKalle Valo /* Count the allocator owned RBDs */ 1153e705c121SKalle Valo rxq->used_count++; 1154e705c121SKalle Valo 1155e705c121SKalle Valo /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1156e705c121SKalle Valo * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1157e705c121SKalle Valo * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1158e705c121SKalle Valo * after but we still need to post another request. 1159e705c121SKalle Valo */ 1160e705c121SKalle Valo if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1161e705c121SKalle Valo /* Move the 2 RBDs to the allocator ownership. 1162e705c121SKalle Valo Allocator has another 6 from pool for the request completion*/ 1163868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1164e705c121SKalle Valo 1165e705c121SKalle Valo atomic_inc(&rba->req_pending); 1166e705c121SKalle Valo queue_work(rba->alloc_wq, &rba->rx_alloc); 1167e705c121SKalle Valo } 1168e705c121SKalle Valo } 1169e705c121SKalle Valo 1170e705c121SKalle Valo static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 117178485054SSara Sharon struct iwl_rxq *rxq, 1172e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 11737891965dSSara Sharon bool emergency, 11747891965dSSara Sharon int i) 1175e705c121SKalle Valo { 1176e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1177b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1178e705c121SKalle Valo bool page_stolen = false; 1179e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 1180e705c121SKalle Valo u32 offset = 0; 1181e705c121SKalle Valo 1182e705c121SKalle Valo if (WARN_ON(!rxb)) 1183e705c121SKalle Valo return; 1184e705c121SKalle Valo 1185e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1186e705c121SKalle Valo 1187e705c121SKalle Valo while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1188e705c121SKalle Valo struct iwl_rx_packet *pkt; 1189e705c121SKalle Valo u16 sequence; 1190e705c121SKalle Valo bool reclaim; 1191e705c121SKalle Valo int index, cmd_index, len; 1192e705c121SKalle Valo struct iwl_rx_cmd_buffer rxcb = { 1193e705c121SKalle Valo ._offset = offset, 1194e705c121SKalle Valo ._rx_page_order = trans_pcie->rx_page_order, 1195e705c121SKalle Valo ._page = rxb->page, 1196e705c121SKalle Valo ._page_stolen = false, 1197e705c121SKalle Valo .truesize = max_len, 1198e705c121SKalle Valo }; 1199e705c121SKalle Valo 12007891965dSSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 12017891965dSSara Sharon rxcb.status = rxq->cd[i].status; 12027891965dSSara Sharon 1203e705c121SKalle Valo pkt = rxb_addr(&rxcb); 1204e705c121SKalle Valo 12053bfdee76SJohannes Berg if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 12063bfdee76SJohannes Berg IWL_DEBUG_RX(trans, 12073bfdee76SJohannes Berg "Q %d: RB end marker at offset %d\n", 12083bfdee76SJohannes Berg rxq->id, offset); 1209e705c121SKalle Valo break; 12103bfdee76SJohannes Berg } 1211e705c121SKalle Valo 1212a395058eSJohannes Berg WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1213a395058eSJohannes Berg FH_RSCSR_RXQ_POS != rxq->id, 1214a395058eSJohannes Berg "frame on invalid queue - is on %d and indicates %d\n", 1215a395058eSJohannes Berg rxq->id, 1216a395058eSJohannes Berg (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1217a395058eSJohannes Berg FH_RSCSR_RXQ_POS); 1218ab2e696bSSara Sharon 1219e705c121SKalle Valo IWL_DEBUG_RX(trans, 12203bfdee76SJohannes Berg "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 12213bfdee76SJohannes Berg rxq->id, offset, 122239bdb17eSSharon Dvir iwl_get_cmd_string(trans, 122339bdb17eSSharon Dvir iwl_cmd_id(pkt->hdr.cmd, 122439bdb17eSSharon Dvir pkt->hdr.group_id, 122539bdb17eSSharon Dvir 0)), 122635177c99SSara Sharon pkt->hdr.group_id, pkt->hdr.cmd, 122735177c99SSara Sharon le16_to_cpu(pkt->hdr.sequence)); 1228e705c121SKalle Valo 1229e705c121SKalle Valo len = iwl_rx_packet_len(pkt); 1230e705c121SKalle Valo len += sizeof(u32); /* account for status word */ 1231e705c121SKalle Valo trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1232e705c121SKalle Valo trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1233e705c121SKalle Valo 1234e705c121SKalle Valo /* Reclaim a command buffer only if this packet is a response 1235e705c121SKalle Valo * to a (driver-originated) command. 1236e705c121SKalle Valo * If the packet (e.g. Rx frame) originated from uCode, 1237e705c121SKalle Valo * there is no command buffer to reclaim. 1238e705c121SKalle Valo * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1239e705c121SKalle Valo * but apparently a few don't get set; catch them here. */ 1240e705c121SKalle Valo reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1241d8a130b0SJohannes Berg if (reclaim && !pkt->hdr.group_id) { 1242e705c121SKalle Valo int i; 1243e705c121SKalle Valo 1244e705c121SKalle Valo for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1245e705c121SKalle Valo if (trans_pcie->no_reclaim_cmds[i] == 1246e705c121SKalle Valo pkt->hdr.cmd) { 1247e705c121SKalle Valo reclaim = false; 1248e705c121SKalle Valo break; 1249e705c121SKalle Valo } 1250e705c121SKalle Valo } 1251e705c121SKalle Valo } 1252e705c121SKalle Valo 1253e705c121SKalle Valo sequence = le16_to_cpu(pkt->hdr.sequence); 1254e705c121SKalle Valo index = SEQ_TO_INDEX(sequence); 12554ecab561SEmmanuel Grumbach cmd_index = iwl_pcie_get_cmd_index(txq, index); 1256e705c121SKalle Valo 12579416560eSGolan Ben Ami if (rxq->id == trans_pcie->def_rx_queue) 1258bce97731SSara Sharon iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1259bce97731SSara Sharon &rxcb); 1260bce97731SSara Sharon else 1261bce97731SSara Sharon iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1262bce97731SSara Sharon &rxcb, rxq->id); 1263e705c121SKalle Valo 1264e705c121SKalle Valo if (reclaim) { 1265e705c121SKalle Valo kzfree(txq->entries[cmd_index].free_buf); 1266e705c121SKalle Valo txq->entries[cmd_index].free_buf = NULL; 1267e705c121SKalle Valo } 1268e705c121SKalle Valo 1269e705c121SKalle Valo /* 1270e705c121SKalle Valo * After here, we should always check rxcb._page_stolen, 1271e705c121SKalle Valo * if it is true then one of the handlers took the page. 1272e705c121SKalle Valo */ 1273e705c121SKalle Valo 1274e705c121SKalle Valo if (reclaim) { 1275e705c121SKalle Valo /* Invoke any callbacks, transfer the buffer to caller, 1276e705c121SKalle Valo * and fire off the (possibly) blocking 1277e705c121SKalle Valo * iwl_trans_send_cmd() 1278e705c121SKalle Valo * as we reclaim the driver command queue */ 1279e705c121SKalle Valo if (!rxcb._page_stolen) 1280e705c121SKalle Valo iwl_pcie_hcmd_complete(trans, &rxcb); 1281e705c121SKalle Valo else 1282e705c121SKalle Valo IWL_WARN(trans, "Claim null rxb?\n"); 1283e705c121SKalle Valo } 1284e705c121SKalle Valo 1285e705c121SKalle Valo page_stolen |= rxcb._page_stolen; 12860307c839SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 12870307c839SGolan Ben Ami break; 1288e705c121SKalle Valo offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1289e705c121SKalle Valo } 1290e705c121SKalle Valo 1291e705c121SKalle Valo /* page was stolen from us -- free our reference */ 1292e705c121SKalle Valo if (page_stolen) { 1293e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1294e705c121SKalle Valo rxb->page = NULL; 1295e705c121SKalle Valo } 1296e705c121SKalle Valo 1297e705c121SKalle Valo /* Reuse the page if possible. For notification packets and 1298e705c121SKalle Valo * SKBs that fail to Rx correctly, add them back into the 1299e705c121SKalle Valo * rx_free list for reuse later. */ 1300e705c121SKalle Valo if (rxb->page != NULL) { 1301e705c121SKalle Valo rxb->page_dma = 1302e705c121SKalle Valo dma_map_page(trans->dev, rxb->page, 0, 1303e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 1304e705c121SKalle Valo DMA_FROM_DEVICE); 1305e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1306e705c121SKalle Valo /* 1307e705c121SKalle Valo * free the page(s) as well to not break 1308e705c121SKalle Valo * the invariant that the items on the used 1309e705c121SKalle Valo * list have no page(s) 1310e705c121SKalle Valo */ 1311e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1312e705c121SKalle Valo rxb->page = NULL; 1313e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1314e705c121SKalle Valo } else { 1315e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 1316e705c121SKalle Valo rxq->free_count++; 1317e705c121SKalle Valo } 1318e705c121SKalle Valo } else 1319e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1320e705c121SKalle Valo } 1321e705c121SKalle Valo 13221b4bbe8bSSara Sharon static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans, 13231b4bbe8bSSara Sharon struct iwl_rxq *rxq, int i) 13241b4bbe8bSSara Sharon { 13251b4bbe8bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13261b4bbe8bSSara Sharon struct iwl_rx_mem_buffer *rxb; 13271b4bbe8bSSara Sharon u16 vid; 13281b4bbe8bSSara Sharon 13291b4bbe8bSSara Sharon if (!trans->cfg->mq_rx_supported) { 13301b4bbe8bSSara Sharon rxb = rxq->queue[i]; 13311b4bbe8bSSara Sharon rxq->queue[i] = NULL; 13321b4bbe8bSSara Sharon return rxb; 13331b4bbe8bSSara Sharon } 13341b4bbe8bSSara Sharon 13351b4bbe8bSSara Sharon /* used_bd is a 32/16 bit but only 12 are used to retrieve the vid */ 13361b4bbe8bSSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 13371b4bbe8bSSara Sharon vid = le16_to_cpu(rxq->cd[i].rbid) & 0x0FFF; 13381b4bbe8bSSara Sharon else 13391b4bbe8bSSara Sharon vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; 13401b4bbe8bSSara Sharon 13411b4bbe8bSSara Sharon if (!vid || vid > ARRAY_SIZE(trans_pcie->global_table)) 13421b4bbe8bSSara Sharon goto out_err; 13431b4bbe8bSSara Sharon 13441b4bbe8bSSara Sharon rxb = trans_pcie->global_table[vid - 1]; 13451b4bbe8bSSara Sharon if (rxb->invalid) 13461b4bbe8bSSara Sharon goto out_err; 13471b4bbe8bSSara Sharon 134885d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid); 134985d78bb1SSara Sharon 13501b4bbe8bSSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 13511b4bbe8bSSara Sharon rxb->size = le32_to_cpu(rxq->cd[i].size) & IWL_RX_CD_SIZE; 13521b4bbe8bSSara Sharon 13531b4bbe8bSSara Sharon rxb->invalid = true; 13541b4bbe8bSSara Sharon 13551b4bbe8bSSara Sharon return rxb; 13561b4bbe8bSSara Sharon 13571b4bbe8bSSara Sharon out_err: 13581b4bbe8bSSara Sharon WARN(1, "Invalid rxb from HW %u\n", (u32)vid); 13591b4bbe8bSSara Sharon iwl_force_nmi(trans); 13601b4bbe8bSSara Sharon return NULL; 13611b4bbe8bSSara Sharon } 13621b4bbe8bSSara Sharon 1363e705c121SKalle Valo /* 1364e705c121SKalle Valo * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1365e705c121SKalle Valo */ 13662e5d4a8fSHaim Dreyfuss static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue) 1367e705c121SKalle Valo { 1368e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13692e5d4a8fSHaim Dreyfuss struct iwl_rxq *rxq = &trans_pcie->rxq[queue]; 1370d56daea4SSara Sharon u32 r, i, count = 0; 1371e705c121SKalle Valo bool emergency = false; 1372e705c121SKalle Valo 1373e705c121SKalle Valo restart: 1374e705c121SKalle Valo spin_lock(&rxq->lock); 1375e705c121SKalle Valo /* uCode's read index (stored in shared DRAM) indicates the last Rx 1376e705c121SKalle Valo * buffer that the driver may process (last buffer filled by ucode). */ 13770307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1378e705c121SKalle Valo i = rxq->read; 1379e705c121SKalle Valo 13805eae443eSSara Sharon /* W/A 9000 device step A0 wrap-around bug */ 13815eae443eSSara Sharon r &= (rxq->queue_size - 1); 13825eae443eSSara Sharon 1383e705c121SKalle Valo /* Rx interrupt, but nothing sent from uCode */ 1384e705c121SKalle Valo if (i == r) 13855eae443eSSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1386e705c121SKalle Valo 1387e705c121SKalle Valo while (i != r) { 1388868a1e86SShaul Triebitz struct iwl_rb_allocator *rba = &trans_pcie->rba; 1389e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 1390868a1e86SShaul Triebitz /* number of RBDs still waiting for page allocation */ 1391868a1e86SShaul Triebitz u32 rb_pending_alloc = 1392868a1e86SShaul Triebitz atomic_read(&trans_pcie->rba.req_pending) * 1393868a1e86SShaul Triebitz RX_CLAIM_REQ_ALLOC; 1394e705c121SKalle Valo 1395868a1e86SShaul Triebitz if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 && 1396868a1e86SShaul Triebitz !emergency)) { 1397868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1398e705c121SKalle Valo emergency = true; 1399868a1e86SShaul Triebitz } 1400e705c121SKalle Valo 140185d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 140285d78bb1SSara Sharon 14031b4bbe8bSSara Sharon rxb = iwl_pcie_get_rxb(trans, rxq, i); 14041b4bbe8bSSara Sharon if (!rxb) 14055eae443eSSara Sharon goto out; 1406e705c121SKalle Valo 14077891965dSSara Sharon iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i); 1408e705c121SKalle Valo 140996a6497bSSara Sharon i = (i + 1) & (rxq->queue_size - 1); 1410e705c121SKalle Valo 1411d56daea4SSara Sharon /* 1412d56daea4SSara Sharon * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1413d56daea4SSara Sharon * try to claim the pre-allocated buffers from the allocator. 1414d56daea4SSara Sharon * If not ready - will try to reclaim next time. 1415d56daea4SSara Sharon * There is no need to reschedule work - allocator exits only 1416d56daea4SSara Sharon * on success 1417e705c121SKalle Valo */ 1418d56daea4SSara Sharon if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1419d56daea4SSara Sharon iwl_pcie_rx_allocator_get(trans, rxq); 1420e705c121SKalle Valo 1421d56daea4SSara Sharon if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1422d56daea4SSara Sharon /* Add the remaining empty RBDs for allocator use */ 1423868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1424d56daea4SSara Sharon } else if (emergency) { 1425e705c121SKalle Valo count++; 1426e705c121SKalle Valo if (count == 8) { 1427e705c121SKalle Valo count = 0; 1428868a1e86SShaul Triebitz if (rb_pending_alloc < rxq->queue_size / 3) 1429e705c121SKalle Valo emergency = false; 1430e0e168dcSGregory Greenman 1431e705c121SKalle Valo rxq->read = i; 1432e705c121SKalle Valo spin_unlock(&rxq->lock); 1433e0e168dcSGregory Greenman iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 143478485054SSara Sharon iwl_pcie_rxq_restock(trans, rxq); 1435e705c121SKalle Valo goto restart; 1436e705c121SKalle Valo } 1437e705c121SKalle Valo } 1438e0e168dcSGregory Greenman } 14395eae443eSSara Sharon out: 1440e705c121SKalle Valo /* Backtrack one entry */ 1441e705c121SKalle Valo rxq->read = i; 14420307c839SGolan Ben Ami /* update cr tail with the rxq read pointer */ 14430307c839SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 14440307c839SGolan Ben Ami *rxq->cr_tail = cpu_to_le16(r); 1445e705c121SKalle Valo spin_unlock(&rxq->lock); 1446e705c121SKalle Valo 1447e705c121SKalle Valo /* 1448e705c121SKalle Valo * handle a case where in emergency there are some unallocated RBDs. 1449e705c121SKalle Valo * those RBDs are in the used list, but are not tracked by the queue's 1450e705c121SKalle Valo * used_count which counts allocator owned RBDs. 1451e705c121SKalle Valo * unallocated emergency RBDs must be allocated on exit, otherwise 1452e705c121SKalle Valo * when called again the function may not be in emergency mode and 1453e705c121SKalle Valo * they will be handed to the allocator with no tracking in the RBD 1454e705c121SKalle Valo * allocator counters, which will lead to them never being claimed back 1455e705c121SKalle Valo * by the queue. 1456e705c121SKalle Valo * by allocating them here, they are now in the queue free list, and 1457e705c121SKalle Valo * will be restocked by the next call of iwl_pcie_rxq_restock. 1458e705c121SKalle Valo */ 1459e705c121SKalle Valo if (unlikely(emergency && count)) 146078485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1461e705c121SKalle Valo 1462bce97731SSara Sharon if (rxq->napi.poll) 1463bce97731SSara Sharon napi_gro_flush(&rxq->napi, false); 1464e0e168dcSGregory Greenman 1465e0e168dcSGregory Greenman iwl_pcie_rxq_restock(trans, rxq); 1466e705c121SKalle Valo } 1467e705c121SKalle Valo 14682e5d4a8fSHaim Dreyfuss static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 14692e5d4a8fSHaim Dreyfuss { 14702e5d4a8fSHaim Dreyfuss u8 queue = entry->entry; 14712e5d4a8fSHaim Dreyfuss struct msix_entry *entries = entry - queue; 14722e5d4a8fSHaim Dreyfuss 14732e5d4a8fSHaim Dreyfuss return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 14742e5d4a8fSHaim Dreyfuss } 14752e5d4a8fSHaim Dreyfuss 14762e5d4a8fSHaim Dreyfuss /* 14772e5d4a8fSHaim Dreyfuss * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 14782e5d4a8fSHaim Dreyfuss * This interrupt handler should be used with RSS queue only. 14792e5d4a8fSHaim Dreyfuss */ 14802e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 14812e5d4a8fSHaim Dreyfuss { 14822e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 14832e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 14842e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 14852e5d4a8fSHaim Dreyfuss 1486c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1487c42ff65dSJohannes Berg 14885eae443eSSara Sharon if (WARN_ON(entry->entry >= trans->num_rx_queues)) 14895eae443eSSara Sharon return IRQ_NONE; 14905eae443eSSara Sharon 14912e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 14922e5d4a8fSHaim Dreyfuss 14932e5d4a8fSHaim Dreyfuss local_bh_disable(); 14942e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, entry->entry); 14952e5d4a8fSHaim Dreyfuss local_bh_enable(); 14962e5d4a8fSHaim Dreyfuss 14972e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 14982e5d4a8fSHaim Dreyfuss 14992e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 15002e5d4a8fSHaim Dreyfuss 15012e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 15022e5d4a8fSHaim Dreyfuss } 15032e5d4a8fSHaim Dreyfuss 1504e705c121SKalle Valo /* 1505e705c121SKalle Valo * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1506e705c121SKalle Valo */ 1507e705c121SKalle Valo static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1508e705c121SKalle Valo { 1509e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1510e705c121SKalle Valo int i; 1511e705c121SKalle Valo 1512e705c121SKalle Valo /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1513e705c121SKalle Valo if (trans->cfg->internal_wimax_coex && 1514e705c121SKalle Valo !trans->cfg->apmg_not_supported && 1515e705c121SKalle Valo (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1516e705c121SKalle Valo APMS_CLK_VAL_MRB_FUNC_MODE) || 1517e705c121SKalle Valo (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1518e705c121SKalle Valo APMG_PS_CTRL_VAL_RESET_REQ))) { 1519e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1520e705c121SKalle Valo iwl_op_mode_wimax_active(trans->op_mode); 1521e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1522e705c121SKalle Valo return; 1523e705c121SKalle Valo } 1524e705c121SKalle Valo 152513a3a390SSara Sharon for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 152613a3a390SSara Sharon if (!trans_pcie->txq[i]) 152713a3a390SSara Sharon continue; 1528b2a3b1c1SSara Sharon del_timer(&trans_pcie->txq[i]->stuck_timer); 152913a3a390SSara Sharon } 1530e705c121SKalle Valo 15317d75f32eSEmmanuel Grumbach /* The STATUS_FW_ERROR bit is set in this function. This must happen 15327d75f32eSEmmanuel Grumbach * before we wake up the command caller, to ensure a proper cleanup. */ 15337d75f32eSEmmanuel Grumbach iwl_trans_fw_error(trans); 15347d75f32eSEmmanuel Grumbach 1535e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1536e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1537e705c121SKalle Valo } 1538e705c121SKalle Valo 1539e705c121SKalle Valo static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1540e705c121SKalle Valo { 1541e705c121SKalle Valo u32 inta; 1542e705c121SKalle Valo 1543e705c121SKalle Valo lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1544e705c121SKalle Valo 1545e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1546e705c121SKalle Valo 1547e705c121SKalle Valo /* Discover which interrupts are active/pending */ 1548e705c121SKalle Valo inta = iwl_read32(trans, CSR_INT); 1549e705c121SKalle Valo 1550e705c121SKalle Valo /* the thread will service interrupts and re-enable them */ 1551e705c121SKalle Valo return inta; 1552e705c121SKalle Valo } 1553e705c121SKalle Valo 1554e705c121SKalle Valo /* a device (PCI-E) page is 4096 bytes long */ 1555e705c121SKalle Valo #define ICT_SHIFT 12 1556e705c121SKalle Valo #define ICT_SIZE (1 << ICT_SHIFT) 1557e705c121SKalle Valo #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1558e705c121SKalle Valo 1559e705c121SKalle Valo /* interrupt handler using ict table, with this interrupt driver will 1560e705c121SKalle Valo * stop using INTA register to get device's interrupt, reading this register 1561e705c121SKalle Valo * is expensive, device will write interrupts in ICT dram table, increment 1562e705c121SKalle Valo * index then will fire interrupt to driver, driver will OR all ICT table 1563e705c121SKalle Valo * entries from current index up to table entry with 0 value. the result is 1564e705c121SKalle Valo * the interrupt we need to service, driver will set the entries back to 0 and 1565e705c121SKalle Valo * set index. 1566e705c121SKalle Valo */ 1567e705c121SKalle Valo static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1568e705c121SKalle Valo { 1569e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1570e705c121SKalle Valo u32 inta; 1571e705c121SKalle Valo u32 val = 0; 1572e705c121SKalle Valo u32 read; 1573e705c121SKalle Valo 1574e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1575e705c121SKalle Valo 1576e705c121SKalle Valo /* Ignore interrupt if there's nothing in NIC to service. 1577e705c121SKalle Valo * This may be due to IRQ shared with another device, 1578e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. */ 1579e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1580e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1581e705c121SKalle Valo if (!read) 1582e705c121SKalle Valo return 0; 1583e705c121SKalle Valo 1584e705c121SKalle Valo /* 1585e705c121SKalle Valo * Collect all entries up to the first 0, starting from ict_index; 1586e705c121SKalle Valo * note we already read at ict_index. 1587e705c121SKalle Valo */ 1588e705c121SKalle Valo do { 1589e705c121SKalle Valo val |= read; 1590e705c121SKalle Valo IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1591e705c121SKalle Valo trans_pcie->ict_index, read); 1592e705c121SKalle Valo trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1593e705c121SKalle Valo trans_pcie->ict_index = 1594e705c121SKalle Valo ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1595e705c121SKalle Valo 1596e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1597e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1598e705c121SKalle Valo read); 1599e705c121SKalle Valo } while (read); 1600e705c121SKalle Valo 1601e705c121SKalle Valo /* We should not get this value, just ignore it. */ 1602e705c121SKalle Valo if (val == 0xffffffff) 1603e705c121SKalle Valo val = 0; 1604e705c121SKalle Valo 1605e705c121SKalle Valo /* 1606e705c121SKalle Valo * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1607e705c121SKalle Valo * (bit 15 before shifting it to 31) to clear when using interrupt 1608e705c121SKalle Valo * coalescing. fortunately, bits 18 and 19 stay set when this happens 1609e705c121SKalle Valo * so we use them to decide on the real state of the Rx bit. 1610e705c121SKalle Valo * In order words, bit 15 is set if bit 18 or bit 19 are set. 1611e705c121SKalle Valo */ 1612e705c121SKalle Valo if (val & 0xC0000) 1613e705c121SKalle Valo val |= 0x8000; 1614e705c121SKalle Valo 1615e705c121SKalle Valo inta = (0xff & val) | ((0xff00 & val) << 16); 1616e705c121SKalle Valo return inta; 1617e705c121SKalle Valo } 1618e705c121SKalle Valo 1619fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 16203a6e168bSJohannes Berg { 16213a6e168bSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16223a6e168bSJohannes Berg struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1623326477e4SJohannes Berg bool hw_rfkill, prev, report; 16243a6e168bSJohannes Berg 16253a6e168bSJohannes Berg mutex_lock(&trans_pcie->mutex); 1626326477e4SJohannes Berg prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 16273a6e168bSJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1628326477e4SJohannes Berg if (hw_rfkill) { 1629326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1630326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1631326477e4SJohannes Berg } 1632326477e4SJohannes Berg if (trans_pcie->opmode_down) 1633326477e4SJohannes Berg report = hw_rfkill; 1634326477e4SJohannes Berg else 1635326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 16363a6e168bSJohannes Berg 16373a6e168bSJohannes Berg IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 16383a6e168bSJohannes Berg hw_rfkill ? "disable radio" : "enable radio"); 16393a6e168bSJohannes Berg 16403a6e168bSJohannes Berg isr_stats->rfkill++; 16413a6e168bSJohannes Berg 1642326477e4SJohannes Berg if (prev != report) 1643326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 16443a6e168bSJohannes Berg mutex_unlock(&trans_pcie->mutex); 16453a6e168bSJohannes Berg 16463a6e168bSJohannes Berg if (hw_rfkill) { 16473a6e168bSJohannes Berg if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 16483a6e168bSJohannes Berg &trans->status)) 16493a6e168bSJohannes Berg IWL_DEBUG_RF_KILL(trans, 16503a6e168bSJohannes Berg "Rfkill while SYNC HCMD in flight\n"); 16513a6e168bSJohannes Berg wake_up(&trans_pcie->wait_command_queue); 16523a6e168bSJohannes Berg } else { 1653326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1654326477e4SJohannes Berg if (trans_pcie->opmode_down) 1655326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 16563a6e168bSJohannes Berg } 16573a6e168bSJohannes Berg } 16583a6e168bSJohannes Berg 1659e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1660e705c121SKalle Valo { 1661e705c121SKalle Valo struct iwl_trans *trans = dev_id; 1662e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1663e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1664e705c121SKalle Valo u32 inta = 0; 1665e705c121SKalle Valo u32 handled = 0; 1666e705c121SKalle Valo 1667e705c121SKalle Valo lock_map_acquire(&trans->sync_cmd_lockdep_map); 1668e705c121SKalle Valo 1669e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1670e705c121SKalle Valo 1671e705c121SKalle Valo /* dram interrupt table not set yet, 1672e705c121SKalle Valo * use legacy interrupt. 1673e705c121SKalle Valo */ 1674e705c121SKalle Valo if (likely(trans_pcie->use_ict)) 1675e705c121SKalle Valo inta = iwl_pcie_int_cause_ict(trans); 1676e705c121SKalle Valo else 1677e705c121SKalle Valo inta = iwl_pcie_int_cause_non_ict(trans); 1678e705c121SKalle Valo 1679e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1680e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1681e705c121SKalle Valo "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1682e705c121SKalle Valo inta, trans_pcie->inta_mask, 1683e705c121SKalle Valo iwl_read32(trans, CSR_INT_MASK), 1684e705c121SKalle Valo iwl_read32(trans, CSR_FH_INT_STATUS)); 1685e705c121SKalle Valo if (inta & (~trans_pcie->inta_mask)) 1686e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1687e705c121SKalle Valo "We got a masked interrupt (0x%08x)\n", 1688e705c121SKalle Valo inta & (~trans_pcie->inta_mask)); 1689e705c121SKalle Valo } 1690e705c121SKalle Valo 1691e705c121SKalle Valo inta &= trans_pcie->inta_mask; 1692e705c121SKalle Valo 1693e705c121SKalle Valo /* 1694e705c121SKalle Valo * Ignore interrupt if there's nothing in NIC to service. 1695e705c121SKalle Valo * This may be due to IRQ shared with another device, 1696e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. 1697e705c121SKalle Valo */ 1698e705c121SKalle Valo if (unlikely(!inta)) { 1699e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1700e705c121SKalle Valo /* 1701e705c121SKalle Valo * Re-enable interrupts here since we don't 1702e705c121SKalle Valo * have anything to service 1703e705c121SKalle Valo */ 1704e705c121SKalle Valo if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1705f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 1706e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1707e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1708e705c121SKalle Valo return IRQ_NONE; 1709e705c121SKalle Valo } 1710e705c121SKalle Valo 1711e705c121SKalle Valo if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1712e705c121SKalle Valo /* 1713e705c121SKalle Valo * Hardware disappeared. It might have 1714e705c121SKalle Valo * already raised an interrupt. 1715e705c121SKalle Valo */ 1716e705c121SKalle Valo IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1717e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1718e705c121SKalle Valo goto out; 1719e705c121SKalle Valo } 1720e705c121SKalle Valo 1721e705c121SKalle Valo /* Ack/clear/reset pending uCode interrupts. 1722e705c121SKalle Valo * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1723e705c121SKalle Valo */ 1724e705c121SKalle Valo /* There is a hardware bug in the interrupt mask function that some 1725e705c121SKalle Valo * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1726e705c121SKalle Valo * they are disabled in the CSR_INT_MASK register. Furthermore the 1727e705c121SKalle Valo * ICT interrupt handling mechanism has another bug that might cause 1728e705c121SKalle Valo * these unmasked interrupts fail to be detected. We workaround the 1729e705c121SKalle Valo * hardware bugs here by ACKing all the possible interrupts so that 1730e705c121SKalle Valo * interrupt coalescing can still be achieved. 1731e705c121SKalle Valo */ 1732e705c121SKalle Valo iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1733e705c121SKalle Valo 1734e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) 1735e705c121SKalle Valo IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1736e705c121SKalle Valo inta, iwl_read32(trans, CSR_INT_MASK)); 1737e705c121SKalle Valo 1738e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1739e705c121SKalle Valo 1740e705c121SKalle Valo /* Now service all interrupt bits discovered above. */ 1741e705c121SKalle Valo if (inta & CSR_INT_BIT_HW_ERR) { 1742e705c121SKalle Valo IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1743e705c121SKalle Valo 1744e705c121SKalle Valo /* Tell the device to stop sending interrupts */ 1745e705c121SKalle Valo iwl_disable_interrupts(trans); 1746e705c121SKalle Valo 1747e705c121SKalle Valo isr_stats->hw++; 1748e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1749e705c121SKalle Valo 1750e705c121SKalle Valo handled |= CSR_INT_BIT_HW_ERR; 1751e705c121SKalle Valo 1752e705c121SKalle Valo goto out; 1753e705c121SKalle Valo } 1754e705c121SKalle Valo 1755e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1756e705c121SKalle Valo /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1757e705c121SKalle Valo if (inta & CSR_INT_BIT_SCD) { 1758e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1759e705c121SKalle Valo "Scheduler finished to transmit the frame/frames.\n"); 1760e705c121SKalle Valo isr_stats->sch++; 1761e705c121SKalle Valo } 1762e705c121SKalle Valo 1763e705c121SKalle Valo /* Alive notification via Rx interrupt will do the real work */ 1764e705c121SKalle Valo if (inta & CSR_INT_BIT_ALIVE) { 1765e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1766e705c121SKalle Valo isr_stats->alive++; 1767eda50cdeSSara Sharon if (trans->cfg->gen2) { 1768eda50cdeSSara Sharon /* 1769eda50cdeSSara Sharon * We can restock, since firmware configured 1770eda50cdeSSara Sharon * the RFH 1771eda50cdeSSara Sharon */ 1772eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1773eda50cdeSSara Sharon } 1774e705c121SKalle Valo } 1775e705c121SKalle Valo } 1776e705c121SKalle Valo 1777e705c121SKalle Valo /* Safely ignore these bits for debug checks below */ 1778e705c121SKalle Valo inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1779e705c121SKalle Valo 1780e705c121SKalle Valo /* HW RF KILL switch toggled */ 1781e705c121SKalle Valo if (inta & CSR_INT_BIT_RF_KILL) { 17823a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 1783e705c121SKalle Valo handled |= CSR_INT_BIT_RF_KILL; 1784e705c121SKalle Valo } 1785e705c121SKalle Valo 1786e705c121SKalle Valo /* Chip got too hot and stopped itself */ 1787e705c121SKalle Valo if (inta & CSR_INT_BIT_CT_KILL) { 1788e705c121SKalle Valo IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1789e705c121SKalle Valo isr_stats->ctkill++; 1790e705c121SKalle Valo handled |= CSR_INT_BIT_CT_KILL; 1791e705c121SKalle Valo } 1792e705c121SKalle Valo 1793e705c121SKalle Valo /* Error detected by uCode */ 1794e705c121SKalle Valo if (inta & CSR_INT_BIT_SW_ERR) { 1795e705c121SKalle Valo IWL_ERR(trans, "Microcode SW error detected. " 1796e705c121SKalle Valo " Restarting 0x%X.\n", inta); 1797e705c121SKalle Valo isr_stats->sw++; 1798e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1799e705c121SKalle Valo handled |= CSR_INT_BIT_SW_ERR; 1800e705c121SKalle Valo } 1801e705c121SKalle Valo 1802e705c121SKalle Valo /* uCode wakes up after power-down sleep */ 1803e705c121SKalle Valo if (inta & CSR_INT_BIT_WAKEUP) { 1804e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1805e705c121SKalle Valo iwl_pcie_rxq_check_wrptr(trans); 1806e705c121SKalle Valo iwl_pcie_txq_check_wrptrs(trans); 1807e705c121SKalle Valo 1808e705c121SKalle Valo isr_stats->wakeup++; 1809e705c121SKalle Valo 1810e705c121SKalle Valo handled |= CSR_INT_BIT_WAKEUP; 1811e705c121SKalle Valo } 1812e705c121SKalle Valo 1813e705c121SKalle Valo /* All uCode command responses, including Tx command responses, 1814e705c121SKalle Valo * Rx "responses" (frame-received notification), and other 1815e705c121SKalle Valo * notifications from uCode come through here*/ 1816e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1817e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC)) { 1818e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1819e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1820e705c121SKalle Valo handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1821e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 1822e705c121SKalle Valo CSR_FH_INT_RX_MASK); 1823e705c121SKalle Valo } 1824e705c121SKalle Valo if (inta & CSR_INT_BIT_RX_PERIODIC) { 1825e705c121SKalle Valo handled |= CSR_INT_BIT_RX_PERIODIC; 1826e705c121SKalle Valo iwl_write32(trans, 1827e705c121SKalle Valo CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1828e705c121SKalle Valo } 1829e705c121SKalle Valo /* Sending RX interrupt require many steps to be done in the 1830e705c121SKalle Valo * the device: 1831e705c121SKalle Valo * 1- write interrupt to current index in ICT table. 1832e705c121SKalle Valo * 2- dma RX frame. 1833e705c121SKalle Valo * 3- update RX shared data to indicate last write index. 1834e705c121SKalle Valo * 4- send interrupt. 1835e705c121SKalle Valo * This could lead to RX race, driver could receive RX interrupt 1836e705c121SKalle Valo * but the shared data changes does not reflect this; 1837e705c121SKalle Valo * periodic interrupt will detect any dangling Rx activity. 1838e705c121SKalle Valo */ 1839e705c121SKalle Valo 1840e705c121SKalle Valo /* Disable periodic interrupt; we use it as just a one-shot. */ 1841e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1842e705c121SKalle Valo CSR_INT_PERIODIC_DIS); 1843e705c121SKalle Valo 1844e705c121SKalle Valo /* 1845e705c121SKalle Valo * Enable periodic interrupt in 8 msec only if we received 1846e705c121SKalle Valo * real RX interrupt (instead of just periodic int), to catch 1847e705c121SKalle Valo * any dangling Rx interrupt. If it was just the periodic 1848e705c121SKalle Valo * interrupt, there was no dangling Rx activity, and no need 1849e705c121SKalle Valo * to extend the periodic interrupt; one-shot is enough. 1850e705c121SKalle Valo */ 1851e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1852e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1853e705c121SKalle Valo CSR_INT_PERIODIC_ENA); 1854e705c121SKalle Valo 1855e705c121SKalle Valo isr_stats->rx++; 1856e705c121SKalle Valo 1857e705c121SKalle Valo local_bh_disable(); 18582e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, 0); 1859e705c121SKalle Valo local_bh_enable(); 1860e705c121SKalle Valo } 1861e705c121SKalle Valo 1862e705c121SKalle Valo /* This "Tx" DMA channel is used only for loading uCode */ 1863e705c121SKalle Valo if (inta & CSR_INT_BIT_FH_TX) { 1864e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1865e705c121SKalle Valo IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1866e705c121SKalle Valo isr_stats->tx++; 1867e705c121SKalle Valo handled |= CSR_INT_BIT_FH_TX; 1868e705c121SKalle Valo /* Wake up uCode load routine, now that load is complete */ 1869e705c121SKalle Valo trans_pcie->ucode_write_complete = true; 1870e705c121SKalle Valo wake_up(&trans_pcie->ucode_write_waitq); 1871e705c121SKalle Valo } 1872e705c121SKalle Valo 1873e705c121SKalle Valo if (inta & ~handled) { 1874e705c121SKalle Valo IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 1875e705c121SKalle Valo isr_stats->unhandled++; 1876e705c121SKalle Valo } 1877e705c121SKalle Valo 1878e705c121SKalle Valo if (inta & ~(trans_pcie->inta_mask)) { 1879e705c121SKalle Valo IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 1880e705c121SKalle Valo inta & ~trans_pcie->inta_mask); 1881e705c121SKalle Valo } 1882e705c121SKalle Valo 1883f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 1884a6bd005fSEmmanuel Grumbach /* only Re-enable all interrupt if disabled by irq */ 1885f16c3ebfSEmmanuel Grumbach if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1886f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 1887f16c3ebfSEmmanuel Grumbach /* we are loading the firmware, enable FH_TX interrupt only */ 1888f16c3ebfSEmmanuel Grumbach else if (handled & CSR_INT_BIT_FH_TX) 1889f16c3ebfSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1890e705c121SKalle Valo /* Re-enable RF_KILL if it occurred */ 1891e705c121SKalle Valo else if (handled & CSR_INT_BIT_RF_KILL) 1892e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1893f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 1894e705c121SKalle Valo 1895e705c121SKalle Valo out: 1896e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1897e705c121SKalle Valo return IRQ_HANDLED; 1898e705c121SKalle Valo } 1899e705c121SKalle Valo 1900e705c121SKalle Valo /****************************************************************************** 1901e705c121SKalle Valo * 1902e705c121SKalle Valo * ICT functions 1903e705c121SKalle Valo * 1904e705c121SKalle Valo ******************************************************************************/ 1905e705c121SKalle Valo 1906e705c121SKalle Valo /* Free dram table */ 1907e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans) 1908e705c121SKalle Valo { 1909e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1910e705c121SKalle Valo 1911e705c121SKalle Valo if (trans_pcie->ict_tbl) { 1912e705c121SKalle Valo dma_free_coherent(trans->dev, ICT_SIZE, 1913e705c121SKalle Valo trans_pcie->ict_tbl, 1914e705c121SKalle Valo trans_pcie->ict_tbl_dma); 1915e705c121SKalle Valo trans_pcie->ict_tbl = NULL; 1916e705c121SKalle Valo trans_pcie->ict_tbl_dma = 0; 1917e705c121SKalle Valo } 1918e705c121SKalle Valo } 1919e705c121SKalle Valo 1920e705c121SKalle Valo /* 1921e705c121SKalle Valo * allocate dram shared table, it is an aligned memory 1922e705c121SKalle Valo * block of ICT_SIZE. 1923e705c121SKalle Valo * also reset all data related to ICT table interrupt. 1924e705c121SKalle Valo */ 1925e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans) 1926e705c121SKalle Valo { 1927e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1928e705c121SKalle Valo 1929e705c121SKalle Valo trans_pcie->ict_tbl = 1930e705c121SKalle Valo dma_zalloc_coherent(trans->dev, ICT_SIZE, 1931e705c121SKalle Valo &trans_pcie->ict_tbl_dma, 1932e705c121SKalle Valo GFP_KERNEL); 1933e705c121SKalle Valo if (!trans_pcie->ict_tbl) 1934e705c121SKalle Valo return -ENOMEM; 1935e705c121SKalle Valo 1936e705c121SKalle Valo /* just an API sanity check ... it is guaranteed to be aligned */ 1937e705c121SKalle Valo if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 1938e705c121SKalle Valo iwl_pcie_free_ict(trans); 1939e705c121SKalle Valo return -EINVAL; 1940e705c121SKalle Valo } 1941e705c121SKalle Valo 1942e705c121SKalle Valo return 0; 1943e705c121SKalle Valo } 1944e705c121SKalle Valo 1945e705c121SKalle Valo /* Device is going up inform it about using ICT interrupt table, 1946e705c121SKalle Valo * also we need to tell the driver to start using ICT interrupt. 1947e705c121SKalle Valo */ 1948e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans) 1949e705c121SKalle Valo { 1950e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1951e705c121SKalle Valo u32 val; 1952e705c121SKalle Valo 1953e705c121SKalle Valo if (!trans_pcie->ict_tbl) 1954e705c121SKalle Valo return; 1955e705c121SKalle Valo 1956e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1957f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 1958e705c121SKalle Valo 1959e705c121SKalle Valo memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 1960e705c121SKalle Valo 1961e705c121SKalle Valo val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 1962e705c121SKalle Valo 1963e705c121SKalle Valo val |= CSR_DRAM_INT_TBL_ENABLE | 1964e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRAP_CHECK | 1965e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRITE_POINTER; 1966e705c121SKalle Valo 1967e705c121SKalle Valo IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 1968e705c121SKalle Valo 1969e705c121SKalle Valo iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 1970e705c121SKalle Valo trans_pcie->use_ict = true; 1971e705c121SKalle Valo trans_pcie->ict_index = 0; 1972e705c121SKalle Valo iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 1973f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 1974e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1975e705c121SKalle Valo } 1976e705c121SKalle Valo 1977e705c121SKalle Valo /* Device is going down disable ict interrupt usage */ 1978e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans) 1979e705c121SKalle Valo { 1980e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1981e705c121SKalle Valo 1982e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1983e705c121SKalle Valo trans_pcie->use_ict = false; 1984e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1985e705c121SKalle Valo } 1986e705c121SKalle Valo 1987e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data) 1988e705c121SKalle Valo { 1989e705c121SKalle Valo struct iwl_trans *trans = data; 1990e705c121SKalle Valo 1991e705c121SKalle Valo if (!trans) 1992e705c121SKalle Valo return IRQ_NONE; 1993e705c121SKalle Valo 1994e705c121SKalle Valo /* Disable (but don't clear!) interrupts here to avoid 1995e705c121SKalle Valo * back-to-back ISRs and sporadic interrupts from our NIC. 1996e705c121SKalle Valo * If we have something to service, the tasklet will re-enable ints. 1997e705c121SKalle Valo * If we *don't* have something, we'll re-enable before leaving here. 1998e705c121SKalle Valo */ 1999e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2000e705c121SKalle Valo 2001e705c121SKalle Valo return IRQ_WAKE_THREAD; 2002e705c121SKalle Valo } 20032e5d4a8fSHaim Dreyfuss 20042e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 20052e5d4a8fSHaim Dreyfuss { 20062e5d4a8fSHaim Dreyfuss return IRQ_WAKE_THREAD; 20072e5d4a8fSHaim Dreyfuss } 20082e5d4a8fSHaim Dreyfuss 20092e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 20102e5d4a8fSHaim Dreyfuss { 20112e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 20122e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 20132e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 201446167a8fSColin Ian King struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 20152e5d4a8fSHaim Dreyfuss u32 inta_fh, inta_hw; 20162e5d4a8fSHaim Dreyfuss 20172e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 20182e5d4a8fSHaim Dreyfuss 20192e5d4a8fSHaim Dreyfuss spin_lock(&trans_pcie->irq_lock); 20207ef3dd26SHaim Dreyfuss inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 20217ef3dd26SHaim Dreyfuss inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 20222e5d4a8fSHaim Dreyfuss /* 20232e5d4a8fSHaim Dreyfuss * Clear causes registers to avoid being handling the same cause. 20242e5d4a8fSHaim Dreyfuss */ 20257ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 20267ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 20272e5d4a8fSHaim Dreyfuss spin_unlock(&trans_pcie->irq_lock); 20282e5d4a8fSHaim Dreyfuss 2029c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2030c42ff65dSJohannes Berg 20312e5d4a8fSHaim Dreyfuss if (unlikely(!(inta_fh | inta_hw))) { 20322e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 20332e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 20342e5d4a8fSHaim Dreyfuss return IRQ_NONE; 20352e5d4a8fSHaim Dreyfuss } 20362e5d4a8fSHaim Dreyfuss 20372e5d4a8fSHaim Dreyfuss if (iwl_have_debug_level(IWL_DL_ISR)) 20382e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "ISR inta_fh 0x%08x, enabled 0x%08x\n", 20392e5d4a8fSHaim Dreyfuss inta_fh, 20402e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 20412e5d4a8fSHaim Dreyfuss 2042496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2043496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2044496d83caSHaim Dreyfuss local_bh_disable(); 2045496d83caSHaim Dreyfuss iwl_pcie_rx_handle(trans, 0); 2046496d83caSHaim Dreyfuss local_bh_enable(); 2047496d83caSHaim Dreyfuss } 2048496d83caSHaim Dreyfuss 2049496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2050496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2051496d83caSHaim Dreyfuss local_bh_disable(); 2052496d83caSHaim Dreyfuss iwl_pcie_rx_handle(trans, 1); 2053496d83caSHaim Dreyfuss local_bh_enable(); 2054496d83caSHaim Dreyfuss } 2055496d83caSHaim Dreyfuss 20562e5d4a8fSHaim Dreyfuss /* This "Tx" DMA channel is used only for loading uCode */ 20572e5d4a8fSHaim Dreyfuss if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 20582e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 20592e5d4a8fSHaim Dreyfuss isr_stats->tx++; 20602e5d4a8fSHaim Dreyfuss /* 20612e5d4a8fSHaim Dreyfuss * Wake up uCode load routine, 20622e5d4a8fSHaim Dreyfuss * now that load is complete 20632e5d4a8fSHaim Dreyfuss */ 20642e5d4a8fSHaim Dreyfuss trans_pcie->ucode_write_complete = true; 20652e5d4a8fSHaim Dreyfuss wake_up(&trans_pcie->ucode_write_waitq); 20662e5d4a8fSHaim Dreyfuss } 20672e5d4a8fSHaim Dreyfuss 20682e5d4a8fSHaim Dreyfuss /* Error detected by uCode */ 20692e5d4a8fSHaim Dreyfuss if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 20709b58419eSGolan Ben Ami (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) || 20719b58419eSGolan Ben Ami (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_V2)) { 20722e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 20732e5d4a8fSHaim Dreyfuss "Microcode SW error detected. Restarting 0x%X.\n", 20742e5d4a8fSHaim Dreyfuss inta_fh); 20752e5d4a8fSHaim Dreyfuss isr_stats->sw++; 20762e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 20772e5d4a8fSHaim Dreyfuss } 20782e5d4a8fSHaim Dreyfuss 20792e5d4a8fSHaim Dreyfuss /* After checking FH register check HW register */ 20802e5d4a8fSHaim Dreyfuss if (iwl_have_debug_level(IWL_DL_ISR)) 20812e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, 20822e5d4a8fSHaim Dreyfuss "ISR inta_hw 0x%08x, enabled 0x%08x\n", 20832e5d4a8fSHaim Dreyfuss inta_hw, 20842e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 20852e5d4a8fSHaim Dreyfuss 20862e5d4a8fSHaim Dreyfuss /* Alive notification via Rx interrupt will do the real work */ 20872e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 20882e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 20892e5d4a8fSHaim Dreyfuss isr_stats->alive++; 2090eda50cdeSSara Sharon if (trans->cfg->gen2) { 2091eda50cdeSSara Sharon /* We can restock, since firmware configured the RFH */ 2092eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2093eda50cdeSSara Sharon } 20942e5d4a8fSHaim Dreyfuss } 20952e5d4a8fSHaim Dreyfuss 20969b58419eSGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560 && 20979b58419eSGolan Ben Ami inta_hw & MSIX_HW_INT_CAUSES_REG_IPC) { 20989b58419eSGolan Ben Ami /* Reflect IML transfer status */ 20999b58419eSGolan Ben Ami int res = iwl_read32(trans, CSR_IML_RESP_ADDR); 21009b58419eSGolan Ben Ami 21019b58419eSGolan Ben Ami IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res); 21029b58419eSGolan Ben Ami if (res == IWL_IMAGE_RESP_FAIL) { 21039b58419eSGolan Ben Ami isr_stats->sw++; 21049b58419eSGolan Ben Ami iwl_pcie_irq_handle_error(trans); 21059b58419eSGolan Ben Ami } 21069b58419eSGolan Ben Ami } else if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 21072e5d4a8fSHaim Dreyfuss /* uCode wakes up after power-down sleep */ 21082e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 21092e5d4a8fSHaim Dreyfuss iwl_pcie_rxq_check_wrptr(trans); 21102e5d4a8fSHaim Dreyfuss iwl_pcie_txq_check_wrptrs(trans); 21112e5d4a8fSHaim Dreyfuss 21122e5d4a8fSHaim Dreyfuss isr_stats->wakeup++; 21132e5d4a8fSHaim Dreyfuss } 21142e5d4a8fSHaim Dreyfuss 21152e5d4a8fSHaim Dreyfuss /* Chip got too hot and stopped itself */ 21162e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 21172e5d4a8fSHaim Dreyfuss IWL_ERR(trans, "Microcode CT kill error detected.\n"); 21182e5d4a8fSHaim Dreyfuss isr_stats->ctkill++; 21192e5d4a8fSHaim Dreyfuss } 21202e5d4a8fSHaim Dreyfuss 21212e5d4a8fSHaim Dreyfuss /* HW RF KILL switch toggled */ 21223a6e168bSJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 21233a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 21242e5d4a8fSHaim Dreyfuss 21252e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 21262e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 21272e5d4a8fSHaim Dreyfuss "Hardware error detected. Restarting.\n"); 21282e5d4a8fSHaim Dreyfuss 21292e5d4a8fSHaim Dreyfuss isr_stats->hw++; 21302e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 21312e5d4a8fSHaim Dreyfuss } 21322e5d4a8fSHaim Dreyfuss 21332e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 21342e5d4a8fSHaim Dreyfuss 21352e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 21362e5d4a8fSHaim Dreyfuss 21372e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 21382e5d4a8fSHaim Dreyfuss } 2139