18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 3*5d19e208SJohannes Berg * Copyright (C) 2003-2014, 2018-2022 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #include <linux/sched.h> 8e705c121SKalle Valo #include <linux/wait.h> 9e705c121SKalle Valo #include <linux/gfp.h> 10e705c121SKalle Valo 11e705c121SKalle Valo #include "iwl-prph.h" 12e705c121SKalle Valo #include "iwl-io.h" 13e705c121SKalle Valo #include "internal.h" 14e705c121SKalle Valo #include "iwl-op-mode.h" 159b58419eSGolan Ben Ami #include "iwl-context-info-gen3.h" 16e705c121SKalle Valo 17e705c121SKalle Valo /****************************************************************************** 18e705c121SKalle Valo * 19e705c121SKalle Valo * RX path functions 20e705c121SKalle Valo * 21e705c121SKalle Valo ******************************************************************************/ 22e705c121SKalle Valo 23e705c121SKalle Valo /* 24e705c121SKalle Valo * Rx theory of operation 25e705c121SKalle Valo * 26e705c121SKalle Valo * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 27e705c121SKalle Valo * each of which point to Receive Buffers to be filled by the NIC. These get 28e705c121SKalle Valo * used not only for Rx frames, but for any command response or notification 29e705c121SKalle Valo * from the NIC. The driver and NIC manage the Rx buffers by means 30e705c121SKalle Valo * of indexes into the circular buffer. 31e705c121SKalle Valo * 32e705c121SKalle Valo * Rx Queue Indexes 33e705c121SKalle Valo * The host/firmware share two index registers for managing the Rx buffers. 34e705c121SKalle Valo * 35e705c121SKalle Valo * The READ index maps to the first position that the firmware may be writing 36e705c121SKalle Valo * to -- the driver can read up to (but not including) this position and get 37e705c121SKalle Valo * good data. 38e705c121SKalle Valo * The READ index is managed by the firmware once the card is enabled. 39e705c121SKalle Valo * 40e705c121SKalle Valo * The WRITE index maps to the last position the driver has read from -- the 41e705c121SKalle Valo * position preceding WRITE is the last slot the firmware can place a packet. 42e705c121SKalle Valo * 43e705c121SKalle Valo * The queue is empty (no good data) if WRITE = READ - 1, and is full if 44e705c121SKalle Valo * WRITE = READ. 45e705c121SKalle Valo * 46e705c121SKalle Valo * During initialization, the host sets up the READ queue position to the first 47e705c121SKalle Valo * INDEX position, and WRITE to the last (READ - 1 wrapped) 48e705c121SKalle Valo * 49e705c121SKalle Valo * When the firmware places a packet in a buffer, it will advance the READ index 50e705c121SKalle Valo * and fire the RX interrupt. The driver can then query the READ index and 51e705c121SKalle Valo * process as many packets as possible, moving the WRITE index forward as it 52e705c121SKalle Valo * resets the Rx queue buffers with new memory. 53e705c121SKalle Valo * 54e705c121SKalle Valo * The management in the driver is as follows: 55e705c121SKalle Valo * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 56e705c121SKalle Valo * When the interrupt handler is called, the request is processed. 57e705c121SKalle Valo * The page is either stolen - transferred to the upper layer 58e705c121SKalle Valo * or reused - added immediately to the iwl->rxq->rx_free list. 59e705c121SKalle Valo * + When the page is stolen - the driver updates the matching queue's used 60e705c121SKalle Valo * count, detaches the RBD and transfers it to the queue used list. 61e705c121SKalle Valo * When there are two used RBDs - they are transferred to the allocator empty 62e705c121SKalle Valo * list. Work is then scheduled for the allocator to start allocating 63e705c121SKalle Valo * eight buffers. 64e705c121SKalle Valo * When there are another 6 used RBDs - they are transferred to the allocator 65e705c121SKalle Valo * empty list and the driver tries to claim the pre-allocated buffers and 66e705c121SKalle Valo * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 67e705c121SKalle Valo * until ready. 68e705c121SKalle Valo * When there are 8+ buffers in the free list - either from allocation or from 69e705c121SKalle Valo * 8 reused unstolen pages - restock is called to update the FW and indexes. 70e705c121SKalle Valo * + In order to make sure the allocator always has RBDs to use for allocation 71e705c121SKalle Valo * the allocator has initial pool in the size of num_queues*(8-2) - the 72e705c121SKalle Valo * maximum missing RBDs per allocation request (request posted with 2 73e705c121SKalle Valo * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 74e705c121SKalle Valo * The queues supplies the recycle of the rest of the RBDs. 75e705c121SKalle Valo * + A received packet is processed and handed to the kernel network stack, 76e705c121SKalle Valo * detached from the iwl->rxq. The driver 'processed' index is updated. 77e705c121SKalle Valo * + If there are no allocated buffers in iwl->rxq->rx_free, 78e705c121SKalle Valo * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 79e705c121SKalle Valo * If there were enough free buffers and RX_STALLED is set it is cleared. 80e705c121SKalle Valo * 81e705c121SKalle Valo * 82e705c121SKalle Valo * Driver sequence: 83e705c121SKalle Valo * 84e705c121SKalle Valo * iwl_rxq_alloc() Allocates rx_free 85e705c121SKalle Valo * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 86e705c121SKalle Valo * iwl_pcie_rxq_restock. 87e705c121SKalle Valo * Used only during initialization. 88e705c121SKalle Valo * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 89e705c121SKalle Valo * queue, updates firmware pointers, and updates 90e705c121SKalle Valo * the WRITE index. 91e705c121SKalle Valo * iwl_pcie_rx_allocator() Background work for allocating pages. 92e705c121SKalle Valo * 93e705c121SKalle Valo * -- enable interrupts -- 94e705c121SKalle Valo * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 95e705c121SKalle Valo * READ INDEX, detaching the SKB from the pool. 96e705c121SKalle Valo * Moves the packet buffer from queue to rx_used. 97e705c121SKalle Valo * Posts and claims requests to the allocator. 98e705c121SKalle Valo * Calls iwl_pcie_rxq_restock to refill any empty 99e705c121SKalle Valo * slots. 100e705c121SKalle Valo * 101e705c121SKalle Valo * RBD life-cycle: 102e705c121SKalle Valo * 103e705c121SKalle Valo * Init: 104e705c121SKalle Valo * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 105e705c121SKalle Valo * 106e705c121SKalle Valo * Regular Receive interrupt: 107e705c121SKalle Valo * Page Stolen: 108e705c121SKalle Valo * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 109e705c121SKalle Valo * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 110e705c121SKalle Valo * Page not Stolen: 111e705c121SKalle Valo * rxq.queue -> rxq.rx_free -> rxq.queue 112e705c121SKalle Valo * ... 113e705c121SKalle Valo * 114e705c121SKalle Valo */ 115e705c121SKalle Valo 116e705c121SKalle Valo /* 117e705c121SKalle Valo * iwl_rxq_space - Return number of free slots available in queue. 118e705c121SKalle Valo */ 119e705c121SKalle Valo static int iwl_rxq_space(const struct iwl_rxq *rxq) 120e705c121SKalle Valo { 12196a6497bSSara Sharon /* Make sure rx queue size is a power of 2 */ 12296a6497bSSara Sharon WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 123e705c121SKalle Valo 124e705c121SKalle Valo /* 125e705c121SKalle Valo * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 126e705c121SKalle Valo * between empty and completely full queues. 127e705c121SKalle Valo * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 128e705c121SKalle Valo * defined for negative dividends. 129e705c121SKalle Valo */ 13096a6497bSSara Sharon return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 131e705c121SKalle Valo } 132e705c121SKalle Valo 133e705c121SKalle Valo /* 134e705c121SKalle Valo * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 135e705c121SKalle Valo */ 136e705c121SKalle Valo static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 137e705c121SKalle Valo { 138e705c121SKalle Valo return cpu_to_le32((u32)(dma_addr >> 8)); 139e705c121SKalle Valo } 140e705c121SKalle Valo 141e705c121SKalle Valo /* 142e705c121SKalle Valo * iwl_pcie_rx_stop - stops the Rx DMA 143e705c121SKalle Valo */ 144e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans) 145e705c121SKalle Valo { 1463681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1473681021fSJohannes Berg /* TODO: remove this once fw does it */ 148ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 149ea695b7cSShaul Triebitz return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3, 150d0158235SGolan Ben Ami RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 151286ca8ebSLuca Coelho } else if (trans->trans_cfg->mq_rx_supported) { 152d7fdd0e5SSara Sharon iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 153d7fdd0e5SSara Sharon return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 154d7fdd0e5SSara Sharon RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 155d7fdd0e5SSara Sharon } else { 156e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 157e705c121SKalle Valo return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 158d7fdd0e5SSara Sharon FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 159d7fdd0e5SSara Sharon 1000); 160d7fdd0e5SSara Sharon } 161e705c121SKalle Valo } 162e705c121SKalle Valo 163e705c121SKalle Valo /* 164e705c121SKalle Valo * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 165e705c121SKalle Valo */ 16678485054SSara Sharon static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 16778485054SSara Sharon struct iwl_rxq *rxq) 168e705c121SKalle Valo { 169e705c121SKalle Valo u32 reg; 170e705c121SKalle Valo 171e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 172e705c121SKalle Valo 173e705c121SKalle Valo /* 174e705c121SKalle Valo * explicitly wake up the NIC if: 175e705c121SKalle Valo * 1. shadow registers aren't enabled 176e705c121SKalle Valo * 2. there is a chance that the NIC is asleep 177e705c121SKalle Valo */ 178286ca8ebSLuca Coelho if (!trans->trans_cfg->base_params->shadow_reg_enable && 179e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 180e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 181e705c121SKalle Valo 182e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 183e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 184e705c121SKalle Valo reg); 185e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 1866dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 187e705c121SKalle Valo rxq->need_update = true; 188e705c121SKalle Valo return; 189e705c121SKalle Valo } 190e705c121SKalle Valo } 191e705c121SKalle Valo 192e705c121SKalle Valo rxq->write_actual = round_down(rxq->write, 8); 1933681021fSJohannes Berg if (trans->trans_cfg->mq_rx_supported) 1941554ed20SSara Sharon iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 19596a6497bSSara Sharon rxq->write_actual); 1961316d595SSara Sharon else 197e705c121SKalle Valo iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 198e705c121SKalle Valo } 199e705c121SKalle Valo 200e705c121SKalle Valo static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 201e705c121SKalle Valo { 202e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20378485054SSara Sharon int i; 204e705c121SKalle Valo 20578485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 20678485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 207e705c121SKalle Valo 208e705c121SKalle Valo if (!rxq->need_update) 20978485054SSara Sharon continue; 21025edc8f2SJohannes Berg spin_lock_bh(&rxq->lock); 21178485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 212e705c121SKalle Valo rxq->need_update = false; 21325edc8f2SJohannes Berg spin_unlock_bh(&rxq->lock); 214e705c121SKalle Valo } 21578485054SSara Sharon } 216e705c121SKalle Valo 2170307c839SGolan Ben Ami static void iwl_pcie_restock_bd(struct iwl_trans *trans, 2180307c839SGolan Ben Ami struct iwl_rxq *rxq, 2190307c839SGolan Ben Ami struct iwl_rx_mem_buffer *rxb) 2200307c839SGolan Ben Ami { 2213681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 2220307c839SGolan Ben Ami struct iwl_rx_transfer_desc *bd = rxq->bd; 2230307c839SGolan Ben Ami 224f826faaaSJohannes Berg BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64)); 225f826faaaSJohannes Berg 2260307c839SGolan Ben Ami bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 2270307c839SGolan Ben Ami bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 2280307c839SGolan Ben Ami } else { 2290307c839SGolan Ben Ami __le64 *bd = rxq->bd; 2300307c839SGolan Ben Ami 2310307c839SGolan Ben Ami bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 2320307c839SGolan Ben Ami } 23385d78bb1SSara Sharon 23485d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n", 23585d78bb1SSara Sharon (u32)rxb->vid, rxq->id, rxq->write); 2360307c839SGolan Ben Ami } 2370307c839SGolan Ben Ami 238e0e168dcSGregory Greenman /* 2392047fa54SSara Sharon * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 240e0e168dcSGregory Greenman */ 2412047fa54SSara Sharon static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 24296a6497bSSara Sharon struct iwl_rxq *rxq) 24396a6497bSSara Sharon { 244cfdc20efSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 24596a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb; 24696a6497bSSara Sharon 24796a6497bSSara Sharon /* 24896a6497bSSara Sharon * If the device isn't enabled - no need to try to add buffers... 24996a6497bSSara Sharon * This can happen when we stop the device and still have an interrupt 25096a6497bSSara Sharon * pending. We stop the APM before we sync the interrupts because we 25196a6497bSSara Sharon * have to (see comment there). On the other hand, since the APM is 25296a6497bSSara Sharon * stopped, we cannot access the HW (in particular not prph). 25396a6497bSSara Sharon * So don't try to restock if the APM has been already stopped. 25496a6497bSSara Sharon */ 25596a6497bSSara Sharon if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 25696a6497bSSara Sharon return; 25796a6497bSSara Sharon 25825edc8f2SJohannes Berg spin_lock_bh(&rxq->lock); 25996a6497bSSara Sharon while (rxq->free_count) { 26096a6497bSSara Sharon /* Get next free Rx buffer, remove from free list */ 26196a6497bSSara Sharon rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 26296a6497bSSara Sharon list); 26396a6497bSSara Sharon list_del(&rxb->list); 264b1753c62SSara Sharon rxb->invalid = false; 265cfdc20efSJohannes Berg /* some low bits are expected to be unset (depending on hw) */ 266cfdc20efSJohannes Berg WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask); 26796a6497bSSara Sharon /* Point to Rx buffer via next RBD in circular buffer */ 2680307c839SGolan Ben Ami iwl_pcie_restock_bd(trans, rxq, rxb); 2695661925aSJohannes Berg rxq->write = (rxq->write + 1) & (rxq->queue_size - 1); 27096a6497bSSara Sharon rxq->free_count--; 27196a6497bSSara Sharon } 27225edc8f2SJohannes Berg spin_unlock_bh(&rxq->lock); 27396a6497bSSara Sharon 27496a6497bSSara Sharon /* 27596a6497bSSara Sharon * If we've added more space for the firmware to place data, tell it. 27696a6497bSSara Sharon * Increment device's write pointer in multiples of 8. 27796a6497bSSara Sharon */ 27896a6497bSSara Sharon if (rxq->write_actual != (rxq->write & ~0x7)) { 27925edc8f2SJohannes Berg spin_lock_bh(&rxq->lock); 28096a6497bSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 28125edc8f2SJohannes Berg spin_unlock_bh(&rxq->lock); 28296a6497bSSara Sharon } 28396a6497bSSara Sharon } 28496a6497bSSara Sharon 285e705c121SKalle Valo /* 2862047fa54SSara Sharon * iwl_pcie_rxsq_restock - restock implementation for single queue rx 287e705c121SKalle Valo */ 2882047fa54SSara Sharon static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 289e0e168dcSGregory Greenman struct iwl_rxq *rxq) 290e705c121SKalle Valo { 291e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 292e705c121SKalle Valo 293e705c121SKalle Valo /* 294e705c121SKalle Valo * If the device isn't enabled - not need to try to add buffers... 295e705c121SKalle Valo * This can happen when we stop the device and still have an interrupt 296e705c121SKalle Valo * pending. We stop the APM before we sync the interrupts because we 297e705c121SKalle Valo * have to (see comment there). On the other hand, since the APM is 298e705c121SKalle Valo * stopped, we cannot access the HW (in particular not prph). 299e705c121SKalle Valo * So don't try to restock if the APM has been already stopped. 300e705c121SKalle Valo */ 301e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 302e705c121SKalle Valo return; 303e705c121SKalle Valo 30447ef328cSIlan Peer spin_lock_bh(&rxq->lock); 305e705c121SKalle Valo while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 30696a6497bSSara Sharon __le32 *bd = (__le32 *)rxq->bd; 307e705c121SKalle Valo /* The overwritten rxb must be a used one */ 308e705c121SKalle Valo rxb = rxq->queue[rxq->write]; 309e705c121SKalle Valo BUG_ON(rxb && rxb->page); 310e705c121SKalle Valo 311e705c121SKalle Valo /* Get next free Rx buffer, remove from free list */ 312e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 313e705c121SKalle Valo list); 314e705c121SKalle Valo list_del(&rxb->list); 315b1753c62SSara Sharon rxb->invalid = false; 316e705c121SKalle Valo 317e705c121SKalle Valo /* Point to Rx buffer via next RBD in circular buffer */ 31896a6497bSSara Sharon bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 319e705c121SKalle Valo rxq->queue[rxq->write] = rxb; 320e705c121SKalle Valo rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 321e705c121SKalle Valo rxq->free_count--; 322e705c121SKalle Valo } 32347ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 324e705c121SKalle Valo 325e705c121SKalle Valo /* If we've added more space for the firmware to place data, tell it. 326e705c121SKalle Valo * Increment device's write pointer in multiples of 8. */ 327e705c121SKalle Valo if (rxq->write_actual != (rxq->write & ~0x7)) { 32847ef328cSIlan Peer spin_lock_bh(&rxq->lock); 32978485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 33047ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 331e705c121SKalle Valo } 332e705c121SKalle Valo } 333e705c121SKalle Valo 334e705c121SKalle Valo /* 335e0e168dcSGregory Greenman * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 336e0e168dcSGregory Greenman * 337e0e168dcSGregory Greenman * If there are slots in the RX queue that need to be restocked, 338e0e168dcSGregory Greenman * and we have free pre-allocated buffers, fill the ranks as much 339e0e168dcSGregory Greenman * as we can, pulling from rx_free. 340e0e168dcSGregory Greenman * 341e0e168dcSGregory Greenman * This moves the 'write' index forward to catch up with 'processed', and 342e0e168dcSGregory Greenman * also updates the memory address in the firmware to reference the new 343e0e168dcSGregory Greenman * target buffer. 344e0e168dcSGregory Greenman */ 345e0e168dcSGregory Greenman static 346e0e168dcSGregory Greenman void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 347e0e168dcSGregory Greenman { 348286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 3492047fa54SSara Sharon iwl_pcie_rxmq_restock(trans, rxq); 350e0e168dcSGregory Greenman else 3512047fa54SSara Sharon iwl_pcie_rxsq_restock(trans, rxq); 352e0e168dcSGregory Greenman } 353e0e168dcSGregory Greenman 354e0e168dcSGregory Greenman /* 355e705c121SKalle Valo * iwl_pcie_rx_alloc_page - allocates and returns a page. 356e705c121SKalle Valo * 357e705c121SKalle Valo */ 358e705c121SKalle Valo static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 359cfdc20efSJohannes Berg u32 *offset, gfp_t priority) 360e705c121SKalle Valo { 361e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 362cfdc20efSJohannes Berg unsigned int rbsize = iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 363cfdc20efSJohannes Berg unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order; 364e705c121SKalle Valo struct page *page; 365e705c121SKalle Valo gfp_t gfp_mask = priority; 366e705c121SKalle Valo 367e705c121SKalle Valo if (trans_pcie->rx_page_order > 0) 368e705c121SKalle Valo gfp_mask |= __GFP_COMP; 369e705c121SKalle Valo 370cfdc20efSJohannes Berg if (trans_pcie->alloc_page) { 371cfdc20efSJohannes Berg spin_lock_bh(&trans_pcie->alloc_page_lock); 372cfdc20efSJohannes Berg /* recheck */ 373cfdc20efSJohannes Berg if (trans_pcie->alloc_page) { 374cfdc20efSJohannes Berg *offset = trans_pcie->alloc_page_used; 375cfdc20efSJohannes Berg page = trans_pcie->alloc_page; 376cfdc20efSJohannes Berg trans_pcie->alloc_page_used += rbsize; 377cfdc20efSJohannes Berg if (trans_pcie->alloc_page_used >= allocsize) 378cfdc20efSJohannes Berg trans_pcie->alloc_page = NULL; 379cfdc20efSJohannes Berg else 380cfdc20efSJohannes Berg get_page(page); 381cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 382cfdc20efSJohannes Berg return page; 383cfdc20efSJohannes Berg } 384cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 385cfdc20efSJohannes Berg } 386cfdc20efSJohannes Berg 387e705c121SKalle Valo /* Alloc a new receive buffer */ 388e705c121SKalle Valo page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 389e705c121SKalle Valo if (!page) { 390e705c121SKalle Valo if (net_ratelimit()) 391e705c121SKalle Valo IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 392e705c121SKalle Valo trans_pcie->rx_page_order); 39378485054SSara Sharon /* 39478485054SSara Sharon * Issue an error if we don't have enough pre-allocated 39578485054SSara Sharon * buffers. 3961da3823dSLuca Coelho */ 39778485054SSara Sharon if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 398e705c121SKalle Valo IWL_CRIT(trans, 39978485054SSara Sharon "Failed to alloc_pages\n"); 400e705c121SKalle Valo return NULL; 401e705c121SKalle Valo } 402cfdc20efSJohannes Berg 403cfdc20efSJohannes Berg if (2 * rbsize <= allocsize) { 404cfdc20efSJohannes Berg spin_lock_bh(&trans_pcie->alloc_page_lock); 405cfdc20efSJohannes Berg if (!trans_pcie->alloc_page) { 406cfdc20efSJohannes Berg get_page(page); 407cfdc20efSJohannes Berg trans_pcie->alloc_page = page; 408cfdc20efSJohannes Berg trans_pcie->alloc_page_used = rbsize; 409cfdc20efSJohannes Berg } 410cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 411cfdc20efSJohannes Berg } 412cfdc20efSJohannes Berg 413cfdc20efSJohannes Berg *offset = 0; 414e705c121SKalle Valo return page; 415e705c121SKalle Valo } 416e705c121SKalle Valo 417e705c121SKalle Valo /* 418e705c121SKalle Valo * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 419e705c121SKalle Valo * 420e705c121SKalle Valo * A used RBD is an Rx buffer that has been given to the stack. To use it again 421e705c121SKalle Valo * a page must be allocated and the RBD must point to the page. This function 422e705c121SKalle Valo * doesn't change the HW pointer but handles the list of pages that is used by 423e705c121SKalle Valo * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 424e705c121SKalle Valo * allocated buffers. 425e705c121SKalle Valo */ 426ff932f61SGolan Ben Ami void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 42778485054SSara Sharon struct iwl_rxq *rxq) 428e705c121SKalle Valo { 429e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 430e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 431e705c121SKalle Valo struct page *page; 432e705c121SKalle Valo 433e705c121SKalle Valo while (1) { 434cfdc20efSJohannes Berg unsigned int offset; 435cfdc20efSJohannes Berg 43647ef328cSIlan Peer spin_lock_bh(&rxq->lock); 437e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 43847ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 439e705c121SKalle Valo return; 440e705c121SKalle Valo } 44147ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 442e705c121SKalle Valo 443cfdc20efSJohannes Berg page = iwl_pcie_rx_alloc_page(trans, &offset, priority); 444e705c121SKalle Valo if (!page) 445e705c121SKalle Valo return; 446e705c121SKalle Valo 44747ef328cSIlan Peer spin_lock_bh(&rxq->lock); 448e705c121SKalle Valo 449e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 45047ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 451e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 452e705c121SKalle Valo return; 453e705c121SKalle Valo } 454e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 455e705c121SKalle Valo list); 456e705c121SKalle Valo list_del(&rxb->list); 45747ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 458e705c121SKalle Valo 459e705c121SKalle Valo BUG_ON(rxb->page); 460e705c121SKalle Valo rxb->page = page; 461cfdc20efSJohannes Berg rxb->offset = offset; 462e705c121SKalle Valo /* Get physical address of the RB */ 463e705c121SKalle Valo rxb->page_dma = 464cfdc20efSJohannes Berg dma_map_page(trans->dev, page, rxb->offset, 46580084e35SJohannes Berg trans_pcie->rx_buf_bytes, 466e705c121SKalle Valo DMA_FROM_DEVICE); 467e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 468e705c121SKalle Valo rxb->page = NULL; 46947ef328cSIlan Peer spin_lock_bh(&rxq->lock); 470e705c121SKalle Valo list_add(&rxb->list, &rxq->rx_used); 47147ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 472e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 473e705c121SKalle Valo return; 474e705c121SKalle Valo } 475e705c121SKalle Valo 47647ef328cSIlan Peer spin_lock_bh(&rxq->lock); 477e705c121SKalle Valo 478e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 479e705c121SKalle Valo rxq->free_count++; 480e705c121SKalle Valo 48147ef328cSIlan Peer spin_unlock_bh(&rxq->lock); 482e705c121SKalle Valo } 483e705c121SKalle Valo } 484e705c121SKalle Valo 485ff932f61SGolan Ben Ami void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 486e705c121SKalle Valo { 487e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 488e705c121SKalle Valo int i; 489e705c121SKalle Valo 4906ac57200SJohannes Berg if (!trans_pcie->rx_pool) 4916ac57200SJohannes Berg return; 4926ac57200SJohannes Berg 493c042f0c7SJohannes Berg for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) { 49478485054SSara Sharon if (!trans_pcie->rx_pool[i].page) 495e705c121SKalle Valo continue; 49678485054SSara Sharon dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 49780084e35SJohannes Berg trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE); 49878485054SSara Sharon __free_pages(trans_pcie->rx_pool[i].page, 49978485054SSara Sharon trans_pcie->rx_page_order); 50078485054SSara Sharon trans_pcie->rx_pool[i].page = NULL; 501e705c121SKalle Valo } 502e705c121SKalle Valo } 503e705c121SKalle Valo 504e705c121SKalle Valo /* 505e705c121SKalle Valo * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 506e705c121SKalle Valo * 507e705c121SKalle Valo * Allocates for each received request 8 pages 508e705c121SKalle Valo * Called as a scheduled work item. 509e705c121SKalle Valo */ 510e705c121SKalle Valo static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 511e705c121SKalle Valo { 512e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 513e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 514e705c121SKalle Valo struct list_head local_empty; 515c6ac9f9fSSara Sharon int pending = atomic_read(&rba->req_pending); 516e705c121SKalle Valo 5176dcdd165SSara Sharon IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending); 518e705c121SKalle Valo 519e705c121SKalle Valo /* If we were scheduled - there is at least one request */ 52025edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 521e705c121SKalle Valo /* swap out the rba->rbd_empty to a local list */ 522e705c121SKalle Valo list_replace_init(&rba->rbd_empty, &local_empty); 52325edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 524e705c121SKalle Valo 525e705c121SKalle Valo while (pending) { 526e705c121SKalle Valo int i; 5270979a913SJohannes Berg LIST_HEAD(local_allocated); 52878485054SSara Sharon gfp_t gfp_mask = GFP_KERNEL; 52978485054SSara Sharon 53078485054SSara Sharon /* Do not post a warning if there are only a few requests */ 53178485054SSara Sharon if (pending < RX_PENDING_WATERMARK) 53278485054SSara Sharon gfp_mask |= __GFP_NOWARN; 533e705c121SKalle Valo 534e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 535e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 536e705c121SKalle Valo struct page *page; 537e705c121SKalle Valo 538e705c121SKalle Valo /* List should never be empty - each reused RBD is 539e705c121SKalle Valo * returned to the list, and initial pool covers any 540e705c121SKalle Valo * possible gap between the time the page is allocated 541e705c121SKalle Valo * to the time the RBD is added. 542e705c121SKalle Valo */ 543e705c121SKalle Valo BUG_ON(list_empty(&local_empty)); 544e705c121SKalle Valo /* Get the first rxb from the rbd list */ 545e705c121SKalle Valo rxb = list_first_entry(&local_empty, 546e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 547e705c121SKalle Valo BUG_ON(rxb->page); 548e705c121SKalle Valo 549e705c121SKalle Valo /* Alloc a new receive buffer */ 550cfdc20efSJohannes Berg page = iwl_pcie_rx_alloc_page(trans, &rxb->offset, 551cfdc20efSJohannes Berg gfp_mask); 552e705c121SKalle Valo if (!page) 553e705c121SKalle Valo continue; 554e705c121SKalle Valo rxb->page = page; 555e705c121SKalle Valo 556e705c121SKalle Valo /* Get physical address of the RB */ 557cfdc20efSJohannes Berg rxb->page_dma = dma_map_page(trans->dev, page, 558cfdc20efSJohannes Berg rxb->offset, 55980084e35SJohannes Berg trans_pcie->rx_buf_bytes, 560e705c121SKalle Valo DMA_FROM_DEVICE); 561e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 562e705c121SKalle Valo rxb->page = NULL; 563e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 564e705c121SKalle Valo continue; 565e705c121SKalle Valo } 566e705c121SKalle Valo 567e705c121SKalle Valo /* move the allocated entry to the out list */ 568e705c121SKalle Valo list_move(&rxb->list, &local_allocated); 569e705c121SKalle Valo i++; 570e705c121SKalle Valo } 571e705c121SKalle Valo 572c6ac9f9fSSara Sharon atomic_dec(&rba->req_pending); 573e705c121SKalle Valo pending--; 574c6ac9f9fSSara Sharon 575e705c121SKalle Valo if (!pending) { 576c6ac9f9fSSara Sharon pending = atomic_read(&rba->req_pending); 5776dcdd165SSara Sharon if (pending) 5786dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 579c6ac9f9fSSara Sharon "Got more pending allocation requests = %d\n", 580e705c121SKalle Valo pending); 581e705c121SKalle Valo } 582e705c121SKalle Valo 58325edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 584e705c121SKalle Valo /* add the allocated rbds to the allocator allocated list */ 585e705c121SKalle Valo list_splice_tail(&local_allocated, &rba->rbd_allocated); 586e705c121SKalle Valo /* get more empty RBDs for current pending requests */ 587e705c121SKalle Valo list_splice_tail_init(&rba->rbd_empty, &local_empty); 58825edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 589e705c121SKalle Valo 590e705c121SKalle Valo atomic_inc(&rba->req_ready); 591c6ac9f9fSSara Sharon 592e705c121SKalle Valo } 593e705c121SKalle Valo 59425edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 595e705c121SKalle Valo /* return unused rbds to the allocator empty list */ 596e705c121SKalle Valo list_splice_tail(&local_empty, &rba->rbd_empty); 59725edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 598c6ac9f9fSSara Sharon 5996dcdd165SSara Sharon IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__); 600e705c121SKalle Valo } 601e705c121SKalle Valo 602e705c121SKalle Valo /* 603d56daea4SSara Sharon * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 604e705c121SKalle Valo .* 605e705c121SKalle Valo .* Called by queue when the queue posted allocation request and 606e705c121SKalle Valo * has freed 8 RBDs in order to restock itself. 607d56daea4SSara Sharon * This function directly moves the allocated RBs to the queue's ownership 608d56daea4SSara Sharon * and updates the relevant counters. 609e705c121SKalle Valo */ 610d56daea4SSara Sharon static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 611d56daea4SSara Sharon struct iwl_rxq *rxq) 612e705c121SKalle Valo { 613e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 614e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 615e705c121SKalle Valo int i; 616e705c121SKalle Valo 617d56daea4SSara Sharon lockdep_assert_held(&rxq->lock); 618d56daea4SSara Sharon 619e705c121SKalle Valo /* 620e705c121SKalle Valo * atomic_dec_if_positive returns req_ready - 1 for any scenario. 621e705c121SKalle Valo * If req_ready is 0 atomic_dec_if_positive will return -1 and this 622d56daea4SSara Sharon * function will return early, as there are no ready requests. 623e705c121SKalle Valo * atomic_dec_if_positive will perofrm the *actual* decrement only if 624e705c121SKalle Valo * req_ready > 0, i.e. - there are ready requests and the function 625e705c121SKalle Valo * hands one request to the caller. 626e705c121SKalle Valo */ 627e705c121SKalle Valo if (atomic_dec_if_positive(&rba->req_ready) < 0) 628d56daea4SSara Sharon return; 629e705c121SKalle Valo 630e705c121SKalle Valo spin_lock(&rba->lock); 631e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 632e705c121SKalle Valo /* Get next free Rx buffer, remove it from free list */ 633d56daea4SSara Sharon struct iwl_rx_mem_buffer *rxb = 634d56daea4SSara Sharon list_first_entry(&rba->rbd_allocated, 635e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 636d56daea4SSara Sharon 637d56daea4SSara Sharon list_move(&rxb->list, &rxq->rx_free); 638e705c121SKalle Valo } 639e705c121SKalle Valo spin_unlock(&rba->lock); 640e705c121SKalle Valo 641d56daea4SSara Sharon rxq->used_count -= RX_CLAIM_REQ_ALLOC; 642d56daea4SSara Sharon rxq->free_count += RX_CLAIM_REQ_ALLOC; 643e705c121SKalle Valo } 644e705c121SKalle Valo 64510a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data) 646e705c121SKalle Valo { 647e705c121SKalle Valo struct iwl_rb_allocator *rba_p = 648e705c121SKalle Valo container_of(data, struct iwl_rb_allocator, rx_alloc); 649e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 650e705c121SKalle Valo container_of(rba_p, struct iwl_trans_pcie, rba); 651e705c121SKalle Valo 652e705c121SKalle Valo iwl_pcie_rx_allocator(trans_pcie->trans); 653e705c121SKalle Valo } 654e705c121SKalle Valo 655*5d19e208SJohannes Berg static int iwl_pcie_free_bd_size(struct iwl_trans *trans) 6560307c839SGolan Ben Ami { 657*5d19e208SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 658*5d19e208SJohannes Berg return sizeof(struct iwl_rx_transfer_desc); 6590307c839SGolan Ben Ami 660*5d19e208SJohannes Berg return trans->trans_cfg->mq_rx_supported ? 661*5d19e208SJohannes Berg sizeof(__le64) : sizeof(__le32); 662*5d19e208SJohannes Berg } 663*5d19e208SJohannes Berg 664*5d19e208SJohannes Berg static int iwl_pcie_used_bd_size(struct iwl_trans *trans) 665*5d19e208SJohannes Berg { 666*5d19e208SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 667*5d19e208SJohannes Berg return sizeof(struct iwl_rx_completion_desc_bz); 668*5d19e208SJohannes Berg 669*5d19e208SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 670*5d19e208SJohannes Berg return sizeof(struct iwl_rx_completion_desc); 671*5d19e208SJohannes Berg 672*5d19e208SJohannes Berg return sizeof(__le32); 6730307c839SGolan Ben Ami } 6740307c839SGolan Ben Ami 6751b493e30SGolan Ben Ami static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 6761b493e30SGolan Ben Ami struct iwl_rxq *rxq) 6771b493e30SGolan Ben Ami { 678*5d19e208SJohannes Berg int free_size = iwl_pcie_free_bd_size(trans); 6791b493e30SGolan Ben Ami 6801b493e30SGolan Ben Ami if (rxq->bd) 6810307c839SGolan Ben Ami dma_free_coherent(trans->dev, 6820307c839SGolan Ben Ami free_size * rxq->queue_size, 6831b493e30SGolan Ben Ami rxq->bd, rxq->bd_dma); 6841b493e30SGolan Ben Ami rxq->bd_dma = 0; 6851b493e30SGolan Ben Ami rxq->bd = NULL; 6861b493e30SGolan Ben Ami 6871b493e30SGolan Ben Ami rxq->rb_stts_dma = 0; 6881b493e30SGolan Ben Ami rxq->rb_stts = NULL; 6891b493e30SGolan Ben Ami 6901b493e30SGolan Ben Ami if (rxq->used_bd) 6910307c839SGolan Ben Ami dma_free_coherent(trans->dev, 692*5d19e208SJohannes Berg iwl_pcie_used_bd_size(trans) * 693*5d19e208SJohannes Berg rxq->queue_size, 6941b493e30SGolan Ben Ami rxq->used_bd, rxq->used_bd_dma); 6951b493e30SGolan Ben Ami rxq->used_bd_dma = 0; 6961b493e30SGolan Ben Ami rxq->used_bd = NULL; 6971b493e30SGolan Ben Ami } 6981b493e30SGolan Ben Ami 6991b493e30SGolan Ben Ami static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 7001b493e30SGolan Ben Ami struct iwl_rxq *rxq) 701e705c121SKalle Valo { 702e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 703e705c121SKalle Valo struct device *dev = trans->dev; 70478485054SSara Sharon int i; 7050307c839SGolan Ben Ami int free_size; 706286ca8ebSLuca Coelho bool use_rx_td = (trans->trans_cfg->device_family >= 7073681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210); 7086cc6ba3aSTriebitz size_t rb_stts_size = use_rx_td ? sizeof(__le16) : 7096cc6ba3aSTriebitz sizeof(struct iwl_rb_status); 710e705c121SKalle Valo 71178485054SSara Sharon spin_lock_init(&rxq->lock); 712286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 713c042f0c7SJohannes Berg rxq->queue_size = trans->cfg->num_rbds; 71496a6497bSSara Sharon else 71596a6497bSSara Sharon rxq->queue_size = RX_QUEUE_SIZE; 71696a6497bSSara Sharon 717*5d19e208SJohannes Berg free_size = iwl_pcie_free_bd_size(trans); 7180307c839SGolan Ben Ami 71978485054SSara Sharon /* 72078485054SSara Sharon * Allocate the circular buffer of Read Buffer Descriptors 72178485054SSara Sharon * (RBDs) 72278485054SSara Sharon */ 723750afb08SLuis Chamberlain rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size, 724e705c121SKalle Valo &rxq->bd_dma, GFP_KERNEL); 725e705c121SKalle Valo if (!rxq->bd) 72678485054SSara Sharon goto err; 72778485054SSara Sharon 728286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) { 729750afb08SLuis Chamberlain rxq->used_bd = dma_alloc_coherent(dev, 730*5d19e208SJohannes Berg iwl_pcie_used_bd_size(trans) * 731*5d19e208SJohannes Berg rxq->queue_size, 73296a6497bSSara Sharon &rxq->used_bd_dma, 73396a6497bSSara Sharon GFP_KERNEL); 73496a6497bSSara Sharon if (!rxq->used_bd) 73596a6497bSSara Sharon goto err; 73696a6497bSSara Sharon } 737e705c121SKalle Valo 7383827cb59SJohannes Berg rxq->rb_stts = (u8 *)trans_pcie->base_rb_stts + rxq->id * rb_stts_size; 7396cc6ba3aSTriebitz rxq->rb_stts_dma = 7406cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size; 7411b493e30SGolan Ben Ami 742e705c121SKalle Valo return 0; 743e705c121SKalle Valo 74478485054SSara Sharon err: 74578485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 74678485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 74778485054SSara Sharon 7481b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 74978485054SSara Sharon } 75096a6497bSSara Sharon 751e705c121SKalle Valo return -ENOMEM; 752e705c121SKalle Valo } 753e705c121SKalle Valo 754ab393cb1SJohannes Berg static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 7551b493e30SGolan Ben Ami { 7561b493e30SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 7571b493e30SGolan Ben Ami struct iwl_rb_allocator *rba = &trans_pcie->rba; 7581b493e30SGolan Ben Ami int i, ret; 759286ca8ebSLuca Coelho size_t rb_stts_size = trans->trans_cfg->device_family >= 7603681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210 ? 7616cc6ba3aSTriebitz sizeof(__le16) : sizeof(struct iwl_rb_status); 7621b493e30SGolan Ben Ami 7631b493e30SGolan Ben Ami if (WARN_ON(trans_pcie->rxq)) 7641b493e30SGolan Ben Ami return -EINVAL; 7651b493e30SGolan Ben Ami 7661b493e30SGolan Ben Ami trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 7671b493e30SGolan Ben Ami GFP_KERNEL); 768c042f0c7SJohannes Berg trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 769c042f0c7SJohannes Berg sizeof(trans_pcie->rx_pool[0]), 770c042f0c7SJohannes Berg GFP_KERNEL); 771c042f0c7SJohannes Berg trans_pcie->global_table = 772c042f0c7SJohannes Berg kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 773c042f0c7SJohannes Berg sizeof(trans_pcie->global_table[0]), 774c042f0c7SJohannes Berg GFP_KERNEL); 775c042f0c7SJohannes Berg if (!trans_pcie->rxq || !trans_pcie->rx_pool || 776c042f0c7SJohannes Berg !trans_pcie->global_table) { 777c042f0c7SJohannes Berg ret = -ENOMEM; 778c042f0c7SJohannes Berg goto err; 779c042f0c7SJohannes Berg } 7801b493e30SGolan Ben Ami 7811b493e30SGolan Ben Ami spin_lock_init(&rba->lock); 7821b493e30SGolan Ben Ami 7836cc6ba3aSTriebitz /* 7846cc6ba3aSTriebitz * Allocate the driver's pointer to receive buffer status. 7856cc6ba3aSTriebitz * Allocate for all queues continuously (HW requirement). 7866cc6ba3aSTriebitz */ 7876cc6ba3aSTriebitz trans_pcie->base_rb_stts = 7886cc6ba3aSTriebitz dma_alloc_coherent(trans->dev, 7896cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 7906cc6ba3aSTriebitz &trans_pcie->base_rb_stts_dma, 7916cc6ba3aSTriebitz GFP_KERNEL); 7926cc6ba3aSTriebitz if (!trans_pcie->base_rb_stts) { 7936cc6ba3aSTriebitz ret = -ENOMEM; 7946cc6ba3aSTriebitz goto err; 7956cc6ba3aSTriebitz } 7966cc6ba3aSTriebitz 7971b493e30SGolan Ben Ami for (i = 0; i < trans->num_rx_queues; i++) { 7981b493e30SGolan Ben Ami struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 7991b493e30SGolan Ben Ami 8006cc6ba3aSTriebitz rxq->id = i; 8011b493e30SGolan Ben Ami ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 8021b493e30SGolan Ben Ami if (ret) 8036cc6ba3aSTriebitz goto err; 8041b493e30SGolan Ben Ami } 8051b493e30SGolan Ben Ami return 0; 8066cc6ba3aSTriebitz 8076cc6ba3aSTriebitz err: 8086cc6ba3aSTriebitz if (trans_pcie->base_rb_stts) { 8096cc6ba3aSTriebitz dma_free_coherent(trans->dev, 8106cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 8116cc6ba3aSTriebitz trans_pcie->base_rb_stts, 8126cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma); 8136cc6ba3aSTriebitz trans_pcie->base_rb_stts = NULL; 8146cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma = 0; 8156cc6ba3aSTriebitz } 816c042f0c7SJohannes Berg kfree(trans_pcie->rx_pool); 8179cf671d6SEmmanuel Grumbach trans_pcie->rx_pool = NULL; 818c042f0c7SJohannes Berg kfree(trans_pcie->global_table); 8199cf671d6SEmmanuel Grumbach trans_pcie->global_table = NULL; 8206cc6ba3aSTriebitz kfree(trans_pcie->rxq); 8219cf671d6SEmmanuel Grumbach trans_pcie->rxq = NULL; 8226cc6ba3aSTriebitz 8236cc6ba3aSTriebitz return ret; 8241b493e30SGolan Ben Ami } 8251b493e30SGolan Ben Ami 826e705c121SKalle Valo static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 827e705c121SKalle Valo { 828e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 829e705c121SKalle Valo u32 rb_size; 830e705c121SKalle Valo const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 831e705c121SKalle Valo 8326c4fbcbcSEmmanuel Grumbach switch (trans_pcie->rx_buf_size) { 8336c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 834e705c121SKalle Valo rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8356c4fbcbcSEmmanuel Grumbach break; 8366c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 8376c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 8386c4fbcbcSEmmanuel Grumbach break; 8396c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 8406c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 8416c4fbcbcSEmmanuel Grumbach break; 8426c4fbcbcSEmmanuel Grumbach default: 8436c4fbcbcSEmmanuel Grumbach WARN_ON(1); 8446c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8456c4fbcbcSEmmanuel Grumbach } 846e705c121SKalle Valo 8471ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 848dfcfeef9SSara Sharon return; 849dfcfeef9SSara Sharon 850e705c121SKalle Valo /* Stop Rx DMA */ 851dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 852e705c121SKalle Valo /* reset and flush pointers */ 853dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 854dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 855dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 856e705c121SKalle Valo 857e705c121SKalle Valo /* Reset driver's Rx queue write index */ 858dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 859e705c121SKalle Valo 860e705c121SKalle Valo /* Tell device where to find RBD circular buffer in DRAM */ 861dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 862e705c121SKalle Valo (u32)(rxq->bd_dma >> 8)); 863e705c121SKalle Valo 864e705c121SKalle Valo /* Tell device where in DRAM to update its Rx status */ 865dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 866e705c121SKalle Valo rxq->rb_stts_dma >> 4); 867e705c121SKalle Valo 868e705c121SKalle Valo /* Enable Rx DMA 869e705c121SKalle Valo * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 870e705c121SKalle Valo * the credit mechanism in 5000 HW RX FIFO 871e705c121SKalle Valo * Direct rx interrupts to hosts 8726c4fbcbcSEmmanuel Grumbach * Rx buffer size 4 or 8k or 12k 873e705c121SKalle Valo * RB timeout 0x10 874e705c121SKalle Valo * 256 RBDs 875e705c121SKalle Valo */ 876dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 877e705c121SKalle Valo FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 878e705c121SKalle Valo FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 879e705c121SKalle Valo FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 880e705c121SKalle Valo rb_size | 881e705c121SKalle Valo (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 882e705c121SKalle Valo (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 883e705c121SKalle Valo 8841ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 885dfcfeef9SSara Sharon 886e705c121SKalle Valo /* Set interrupt coalescing timer to default (2048 usecs) */ 887e705c121SKalle Valo iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 888e705c121SKalle Valo 889e705c121SKalle Valo /* W/A for interrupt coalescing bug in 7260 and 3160 */ 890e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) 891e705c121SKalle Valo iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 892e705c121SKalle Valo } 893e705c121SKalle Valo 894bce97731SSara Sharon static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 89596a6497bSSara Sharon { 89696a6497bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 89796a6497bSSara Sharon u32 rb_size, enabled = 0; 89896a6497bSSara Sharon int i; 89996a6497bSSara Sharon 90096a6497bSSara Sharon switch (trans_pcie->rx_buf_size) { 9011a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 9021a4968d1SGolan Ben Ami rb_size = RFH_RXF_DMA_RB_SIZE_2K; 9031a4968d1SGolan Ben Ami break; 90496a6497bSSara Sharon case IWL_AMSDU_4K: 90596a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 90696a6497bSSara Sharon break; 90796a6497bSSara Sharon case IWL_AMSDU_8K: 90896a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_8K; 90996a6497bSSara Sharon break; 91096a6497bSSara Sharon case IWL_AMSDU_12K: 91196a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_12K; 91296a6497bSSara Sharon break; 91396a6497bSSara Sharon default: 91496a6497bSSara Sharon WARN_ON(1); 91596a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 91696a6497bSSara Sharon } 91796a6497bSSara Sharon 9181ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 919dfcfeef9SSara Sharon return; 920dfcfeef9SSara Sharon 92196a6497bSSara Sharon /* Stop Rx DMA */ 922dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 92396a6497bSSara Sharon /* disable free amd used rx queue operation */ 924dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 92596a6497bSSara Sharon 92696a6497bSSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 92796a6497bSSara Sharon /* Tell device where to find RBD free table in DRAM */ 92812a17458SSara Sharon iwl_write_prph64_no_grab(trans, 929dfcfeef9SSara Sharon RFH_Q_FRBDCB_BA_LSB(i), 930dfcfeef9SSara Sharon trans_pcie->rxq[i].bd_dma); 93196a6497bSSara Sharon /* Tell device where to find RBD used table in DRAM */ 93212a17458SSara Sharon iwl_write_prph64_no_grab(trans, 933dfcfeef9SSara Sharon RFH_Q_URBDCB_BA_LSB(i), 934dfcfeef9SSara Sharon trans_pcie->rxq[i].used_bd_dma); 93596a6497bSSara Sharon /* Tell device where in DRAM to update its Rx status */ 93612a17458SSara Sharon iwl_write_prph64_no_grab(trans, 937dfcfeef9SSara Sharon RFH_Q_URBD_STTS_WPTR_LSB(i), 938bce97731SSara Sharon trans_pcie->rxq[i].rb_stts_dma); 93996a6497bSSara Sharon /* Reset device indice tables */ 940dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 941dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 942dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 94396a6497bSSara Sharon 94496a6497bSSara Sharon enabled |= BIT(i) | BIT(i + 16); 94596a6497bSSara Sharon } 94696a6497bSSara Sharon 94796a6497bSSara Sharon /* 94896a6497bSSara Sharon * Enable Rx DMA 94996a6497bSSara Sharon * Rx buffer size 4 or 8k or 12k 95096a6497bSSara Sharon * Min RB size 4 or 8 95188076015SSara Sharon * Drop frames that exceed RB size 95296a6497bSSara Sharon * 512 RBDs 95396a6497bSSara Sharon */ 954dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 95563044335SSara Sharon RFH_DMA_EN_ENABLE_VAL | rb_size | 95696a6497bSSara Sharon RFH_RXF_DMA_MIN_RB_4_8 | 95788076015SSara Sharon RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 95896a6497bSSara Sharon RFH_RXF_DMA_RBDCB_SIZE_512); 95996a6497bSSara Sharon 96088076015SSara Sharon /* 96188076015SSara Sharon * Activate DMA snooping. 962b0262f07SSara Sharon * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 96388076015SSara Sharon * Default queue is 0 96488076015SSara Sharon */ 965f3779f47SJohannes Berg iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 966f3779f47SJohannes Berg RFH_GEN_CFG_RFH_DMA_SNOOP | 967f3779f47SJohannes Berg RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 968b0262f07SSara Sharon RFH_GEN_CFG_SERVICE_DMA_SNOOP | 969f3779f47SJohannes Berg RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 9707897dfa2SLuca Coelho trans->trans_cfg->integrated ? 971b0262f07SSara Sharon RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 972f3779f47SJohannes Berg RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 97388076015SSara Sharon /* Enable the relevant rx queues */ 974dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 975dfcfeef9SSara Sharon 9761ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 97796a6497bSSara Sharon 97896a6497bSSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 97996a6497bSSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 98096a6497bSSara Sharon } 98196a6497bSSara Sharon 982ff932f61SGolan Ben Ami void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 983e705c121SKalle Valo { 984e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 985e705c121SKalle Valo 986e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_free); 987e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_used); 988e705c121SKalle Valo rxq->free_count = 0; 989e705c121SKalle Valo rxq->used_count = 0; 990e705c121SKalle Valo } 991e705c121SKalle Valo 99225edc8f2SJohannes Berg static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget); 99325edc8f2SJohannes Berg 99425edc8f2SJohannes Berg static int iwl_pcie_napi_poll(struct napi_struct *napi, int budget) 995bce97731SSara Sharon { 99625edc8f2SJohannes Berg struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 99725edc8f2SJohannes Berg struct iwl_trans_pcie *trans_pcie; 99825edc8f2SJohannes Berg struct iwl_trans *trans; 99925edc8f2SJohannes Berg int ret; 100025edc8f2SJohannes Berg 100125edc8f2SJohannes Berg trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 100225edc8f2SJohannes Berg trans = trans_pcie->trans; 100325edc8f2SJohannes Berg 100425edc8f2SJohannes Berg ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 100525edc8f2SJohannes Berg 10069d401222SMordechay Goodstein IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", 10079d401222SMordechay Goodstein rxq->id, ret, budget); 10089d401222SMordechay Goodstein 100925edc8f2SJohannes Berg if (ret < budget) { 101025edc8f2SJohannes Berg spin_lock(&trans_pcie->irq_lock); 101125edc8f2SJohannes Berg if (test_bit(STATUS_INT_ENABLED, &trans->status)) 101225edc8f2SJohannes Berg _iwl_enable_interrupts(trans); 101325edc8f2SJohannes Berg spin_unlock(&trans_pcie->irq_lock); 101425edc8f2SJohannes Berg 101525edc8f2SJohannes Berg napi_complete_done(&rxq->napi, ret); 101625edc8f2SJohannes Berg } 101725edc8f2SJohannes Berg 101825edc8f2SJohannes Berg return ret; 101925edc8f2SJohannes Berg } 102025edc8f2SJohannes Berg 102125edc8f2SJohannes Berg static int iwl_pcie_napi_poll_msix(struct napi_struct *napi, int budget) 102225edc8f2SJohannes Berg { 102325edc8f2SJohannes Berg struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 102425edc8f2SJohannes Berg struct iwl_trans_pcie *trans_pcie; 102525edc8f2SJohannes Berg struct iwl_trans *trans; 102625edc8f2SJohannes Berg int ret; 102725edc8f2SJohannes Berg 102825edc8f2SJohannes Berg trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 102925edc8f2SJohannes Berg trans = trans_pcie->trans; 103025edc8f2SJohannes Berg 103125edc8f2SJohannes Berg ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 10322b616666SMordechay Goodstein IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", rxq->id, ret, 10332b616666SMordechay Goodstein budget); 103425edc8f2SJohannes Berg 103525edc8f2SJohannes Berg if (ret < budget) { 10362b616666SMordechay Goodstein int irq_line = rxq->id; 10372b616666SMordechay Goodstein 10382b616666SMordechay Goodstein /* FIRST_RSS is shared with line 0 */ 10392b616666SMordechay Goodstein if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS && 10402b616666SMordechay Goodstein rxq->id == 1) 10412b616666SMordechay Goodstein irq_line = 0; 10422b616666SMordechay Goodstein 104325edc8f2SJohannes Berg spin_lock(&trans_pcie->irq_lock); 10442b616666SMordechay Goodstein iwl_pcie_clear_irq(trans, irq_line); 104525edc8f2SJohannes Berg spin_unlock(&trans_pcie->irq_lock); 104625edc8f2SJohannes Berg 104725edc8f2SJohannes Berg napi_complete_done(&rxq->napi, ret); 104825edc8f2SJohannes Berg } 104925edc8f2SJohannes Berg 105025edc8f2SJohannes Berg return ret; 1051bce97731SSara Sharon } 1052bce97731SSara Sharon 1053ab393cb1SJohannes Berg static int _iwl_pcie_rx_init(struct iwl_trans *trans) 1054e705c121SKalle Valo { 1055e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 105678485054SSara Sharon struct iwl_rxq *def_rxq; 1057e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 10587b542436SSara Sharon int i, err, queue_size, allocator_pool_size, num_alloc; 1059e705c121SKalle Valo 106078485054SSara Sharon if (!trans_pcie->rxq) { 1061e705c121SKalle Valo err = iwl_pcie_rx_alloc(trans); 1062e705c121SKalle Valo if (err) 1063e705c121SKalle Valo return err; 1064e705c121SKalle Valo } 106578485054SSara Sharon def_rxq = trans_pcie->rxq; 1066e705c121SKalle Valo 10670f22e400SShaul Triebitz cancel_work_sync(&rba->rx_alloc); 10680f22e400SShaul Triebitz 106925edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 1070e705c121SKalle Valo atomic_set(&rba->req_pending, 0); 1071e705c121SKalle Valo atomic_set(&rba->req_ready, 0); 107296a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_allocated); 107396a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_empty); 107425edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 1075e705c121SKalle Valo 10766ac57200SJohannes Berg /* free all first - we overwrite everything here */ 107778485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1078e705c121SKalle Valo 1079e705c121SKalle Valo for (i = 0; i < RX_QUEUE_SIZE; i++) 108078485054SSara Sharon def_rxq->queue[i] = NULL; 1081e705c121SKalle Valo 108278485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 108378485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1084e705c121SKalle Valo 108547ef328cSIlan Peer spin_lock_bh(&rxq->lock); 108678485054SSara Sharon /* 108778485054SSara Sharon * Set read write pointer to reflect that we have processed 108878485054SSara Sharon * and used all buffers, but have not restocked the Rx queue 108978485054SSara Sharon * with fresh buffers 109078485054SSara Sharon */ 109178485054SSara Sharon rxq->read = 0; 109278485054SSara Sharon rxq->write = 0; 109378485054SSara Sharon rxq->write_actual = 0; 10943681021fSJohannes Berg memset(rxq->rb_stts, 0, 10953681021fSJohannes Berg (trans->trans_cfg->device_family >= 10963681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210) ? 10970307c839SGolan Ben Ami sizeof(__le16) : sizeof(struct iwl_rb_status)); 109878485054SSara Sharon 109978485054SSara Sharon iwl_pcie_rx_init_rxb_lists(rxq); 110078485054SSara Sharon 1101295d4cd8SJiri Kosina spin_unlock_bh(&rxq->lock); 1102295d4cd8SJiri Kosina 110325edc8f2SJohannes Berg if (!rxq->napi.poll) { 110425edc8f2SJohannes Berg int (*poll)(struct napi_struct *, int) = iwl_pcie_napi_poll; 110525edc8f2SJohannes Berg 11062b616666SMordechay Goodstein if (trans_pcie->msix_enabled) 110725edc8f2SJohannes Berg poll = iwl_pcie_napi_poll_msix; 110825edc8f2SJohannes Berg 1109bce97731SSara Sharon netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 111025edc8f2SJohannes Berg poll, NAPI_POLL_WEIGHT); 111125edc8f2SJohannes Berg napi_enable(&rxq->napi); 111225edc8f2SJohannes Berg } 1113bce97731SSara Sharon 111478485054SSara Sharon } 111578485054SSara Sharon 111696a6497bSSara Sharon /* move the pool to the default queue and allocator ownerships */ 1117286ca8ebSLuca Coelho queue_size = trans->trans_cfg->mq_rx_supported ? 1118c042f0c7SJohannes Berg trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE; 111996a6497bSSara Sharon allocator_pool_size = trans->num_rx_queues * 112096a6497bSSara Sharon (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 11217b542436SSara Sharon num_alloc = queue_size + allocator_pool_size; 1122c042f0c7SJohannes Berg 11237b542436SSara Sharon for (i = 0; i < num_alloc; i++) { 112496a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 112596a6497bSSara Sharon 112696a6497bSSara Sharon if (i < allocator_pool_size) 112796a6497bSSara Sharon list_add(&rxb->list, &rba->rbd_empty); 112896a6497bSSara Sharon else 112996a6497bSSara Sharon list_add(&rxb->list, &def_rxq->rx_used); 113096a6497bSSara Sharon trans_pcie->global_table[i] = rxb; 1131e25d65f2SSara Sharon rxb->vid = (u16)(i + 1); 1132b1753c62SSara Sharon rxb->invalid = true; 113396a6497bSSara Sharon } 113478485054SSara Sharon 113578485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 11362047fa54SSara Sharon 1137eda50cdeSSara Sharon return 0; 1138eda50cdeSSara Sharon } 1139eda50cdeSSara Sharon 1140eda50cdeSSara Sharon int iwl_pcie_rx_init(struct iwl_trans *trans) 1141eda50cdeSSara Sharon { 1142eda50cdeSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1143eda50cdeSSara Sharon int ret = _iwl_pcie_rx_init(trans); 1144eda50cdeSSara Sharon 1145eda50cdeSSara Sharon if (ret) 1146eda50cdeSSara Sharon return ret; 1147eda50cdeSSara Sharon 1148286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 1149bce97731SSara Sharon iwl_pcie_rx_mq_hw_init(trans); 11502047fa54SSara Sharon else 1151eda50cdeSSara Sharon iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 11522047fa54SSara Sharon 1153eda50cdeSSara Sharon iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 115478485054SSara Sharon 115547ef328cSIlan Peer spin_lock_bh(&trans_pcie->rxq->lock); 1156eda50cdeSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 115747ef328cSIlan Peer spin_unlock_bh(&trans_pcie->rxq->lock); 1158e705c121SKalle Valo 1159e705c121SKalle Valo return 0; 1160e705c121SKalle Valo } 1161e705c121SKalle Valo 1162eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1163eda50cdeSSara Sharon { 1164e506b481SSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 1165e506b481SSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1166e506b481SSara Sharon 1167eda50cdeSSara Sharon /* 1168eda50cdeSSara Sharon * We don't configure the RFH. 1169eda50cdeSSara Sharon * Restock will be done at alive, after firmware configured the RFH. 1170eda50cdeSSara Sharon */ 1171eda50cdeSSara Sharon return _iwl_pcie_rx_init(trans); 1172eda50cdeSSara Sharon } 1173eda50cdeSSara Sharon 1174e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans) 1175e705c121SKalle Valo { 1176e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1177e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 117878485054SSara Sharon int i; 1179286ca8ebSLuca Coelho size_t rb_stts_size = trans->trans_cfg->device_family >= 11803681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210 ? 11816cc6ba3aSTriebitz sizeof(__le16) : sizeof(struct iwl_rb_status); 1182e705c121SKalle Valo 118378485054SSara Sharon /* 118478485054SSara Sharon * if rxq is NULL, it means that nothing has been allocated, 118578485054SSara Sharon * exit now 118678485054SSara Sharon */ 118778485054SSara Sharon if (!trans_pcie->rxq) { 1188e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1189e705c121SKalle Valo return; 1190e705c121SKalle Valo } 1191e705c121SKalle Valo 1192e705c121SKalle Valo cancel_work_sync(&rba->rx_alloc); 1193e705c121SKalle Valo 119478485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1195e705c121SKalle Valo 11966cc6ba3aSTriebitz if (trans_pcie->base_rb_stts) { 11976cc6ba3aSTriebitz dma_free_coherent(trans->dev, 11986cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 11996cc6ba3aSTriebitz trans_pcie->base_rb_stts, 12006cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma); 12016cc6ba3aSTriebitz trans_pcie->base_rb_stts = NULL; 12026cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma = 0; 12036cc6ba3aSTriebitz } 12046cc6ba3aSTriebitz 120578485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 120678485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 120778485054SSara Sharon 12081b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 1209bce97731SSara Sharon 121025edc8f2SJohannes Berg if (rxq->napi.poll) { 121125edc8f2SJohannes Berg napi_disable(&rxq->napi); 1212bce97731SSara Sharon netif_napi_del(&rxq->napi); 121396a6497bSSara Sharon } 121425edc8f2SJohannes Berg } 1215c042f0c7SJohannes Berg kfree(trans_pcie->rx_pool); 1216c042f0c7SJohannes Berg kfree(trans_pcie->global_table); 121778485054SSara Sharon kfree(trans_pcie->rxq); 1218cfdc20efSJohannes Berg 1219cfdc20efSJohannes Berg if (trans_pcie->alloc_page) 1220cfdc20efSJohannes Berg __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order); 1221e705c121SKalle Valo } 1222e705c121SKalle Valo 1223868a1e86SShaul Triebitz static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq, 1224868a1e86SShaul Triebitz struct iwl_rb_allocator *rba) 1225868a1e86SShaul Triebitz { 1226868a1e86SShaul Triebitz spin_lock(&rba->lock); 1227868a1e86SShaul Triebitz list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1228868a1e86SShaul Triebitz spin_unlock(&rba->lock); 1229868a1e86SShaul Triebitz } 1230868a1e86SShaul Triebitz 1231e705c121SKalle Valo /* 1232e705c121SKalle Valo * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1233e705c121SKalle Valo * 1234e705c121SKalle Valo * Called when a RBD can be reused. The RBD is transferred to the allocator. 1235e705c121SKalle Valo * When there are 2 empty RBDs - a request for allocation is posted 1236e705c121SKalle Valo */ 1237e705c121SKalle Valo static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1238e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 1239e705c121SKalle Valo struct iwl_rxq *rxq, bool emergency) 1240e705c121SKalle Valo { 1241e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1242e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 1243e705c121SKalle Valo 1244e705c121SKalle Valo /* Move the RBD to the used list, will be moved to allocator in batches 1245e705c121SKalle Valo * before claiming or posting a request*/ 1246e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_used); 1247e705c121SKalle Valo 1248e705c121SKalle Valo if (unlikely(emergency)) 1249e705c121SKalle Valo return; 1250e705c121SKalle Valo 1251e705c121SKalle Valo /* Count the allocator owned RBDs */ 1252e705c121SKalle Valo rxq->used_count++; 1253e705c121SKalle Valo 1254e705c121SKalle Valo /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1255e705c121SKalle Valo * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1256e705c121SKalle Valo * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1257e705c121SKalle Valo * after but we still need to post another request. 1258e705c121SKalle Valo */ 1259e705c121SKalle Valo if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1260e705c121SKalle Valo /* Move the 2 RBDs to the allocator ownership. 1261e705c121SKalle Valo Allocator has another 6 from pool for the request completion*/ 1262868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1263e705c121SKalle Valo 1264e705c121SKalle Valo atomic_inc(&rba->req_pending); 1265e705c121SKalle Valo queue_work(rba->alloc_wq, &rba->rx_alloc); 1266e705c121SKalle Valo } 1267e705c121SKalle Valo } 1268e705c121SKalle Valo 1269e705c121SKalle Valo static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 127078485054SSara Sharon struct iwl_rxq *rxq, 1271e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 12727891965dSSara Sharon bool emergency, 12737891965dSSara Sharon int i) 1274e705c121SKalle Valo { 1275e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 12764f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id]; 1277e705c121SKalle Valo bool page_stolen = false; 127880084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 1279e705c121SKalle Valo u32 offset = 0; 1280e705c121SKalle Valo 1281e705c121SKalle Valo if (WARN_ON(!rxb)) 1282e705c121SKalle Valo return; 1283e705c121SKalle Valo 1284e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1285e705c121SKalle Valo 1286e705c121SKalle Valo while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1287e705c121SKalle Valo struct iwl_rx_packet *pkt; 1288e705c121SKalle Valo bool reclaim; 1289e4475583SJohannes Berg int len; 1290e705c121SKalle Valo struct iwl_rx_cmd_buffer rxcb = { 1291cfdc20efSJohannes Berg ._offset = rxb->offset + offset, 1292e705c121SKalle Valo ._rx_page_order = trans_pcie->rx_page_order, 1293e705c121SKalle Valo ._page = rxb->page, 1294e705c121SKalle Valo ._page_stolen = false, 1295e705c121SKalle Valo .truesize = max_len, 1296e705c121SKalle Valo }; 1297e705c121SKalle Valo 1298e705c121SKalle Valo pkt = rxb_addr(&rxcb); 1299e705c121SKalle Valo 13003bfdee76SJohannes Berg if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 13013bfdee76SJohannes Berg IWL_DEBUG_RX(trans, 13023bfdee76SJohannes Berg "Q %d: RB end marker at offset %d\n", 13033bfdee76SJohannes Berg rxq->id, offset); 1304e705c121SKalle Valo break; 13053bfdee76SJohannes Berg } 1306e705c121SKalle Valo 1307a395058eSJohannes Berg WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1308a395058eSJohannes Berg FH_RSCSR_RXQ_POS != rxq->id, 1309a395058eSJohannes Berg "frame on invalid queue - is on %d and indicates %d\n", 1310a395058eSJohannes Berg rxq->id, 1311a395058eSJohannes Berg (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1312a395058eSJohannes Berg FH_RSCSR_RXQ_POS); 1313ab2e696bSSara Sharon 1314e705c121SKalle Valo IWL_DEBUG_RX(trans, 13153bfdee76SJohannes Berg "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 13163bfdee76SJohannes Berg rxq->id, offset, 131739bdb17eSSharon Dvir iwl_get_cmd_string(trans, 1318f0c86427SJohannes Berg WIDE_ID(pkt->hdr.group_id, pkt->hdr.cmd)), 131935177c99SSara Sharon pkt->hdr.group_id, pkt->hdr.cmd, 132035177c99SSara Sharon le16_to_cpu(pkt->hdr.sequence)); 1321e705c121SKalle Valo 1322e705c121SKalle Valo len = iwl_rx_packet_len(pkt); 1323e705c121SKalle Valo len += sizeof(u32); /* account for status word */ 1324df72138dSJohannes Berg 1325df72138dSJohannes Berg offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1326df72138dSJohannes Berg 1327df72138dSJohannes Berg /* check that what the device tells us made sense */ 1328f1658dcbSAndrei Otcheretianski if (len < sizeof(*pkt) || offset > max_len) 1329df72138dSJohannes Berg break; 1330df72138dSJohannes Berg 1331e705c121SKalle Valo trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1332e705c121SKalle Valo trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1333e705c121SKalle Valo 1334e705c121SKalle Valo /* Reclaim a command buffer only if this packet is a response 1335e705c121SKalle Valo * to a (driver-originated) command. 1336e705c121SKalle Valo * If the packet (e.g. Rx frame) originated from uCode, 1337e705c121SKalle Valo * there is no command buffer to reclaim. 1338e705c121SKalle Valo * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1339e705c121SKalle Valo * but apparently a few don't get set; catch them here. */ 1340e705c121SKalle Valo reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1341d8a130b0SJohannes Berg if (reclaim && !pkt->hdr.group_id) { 1342e705c121SKalle Valo int i; 1343e705c121SKalle Valo 1344e705c121SKalle Valo for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1345e705c121SKalle Valo if (trans_pcie->no_reclaim_cmds[i] == 1346e705c121SKalle Valo pkt->hdr.cmd) { 1347e705c121SKalle Valo reclaim = false; 1348e705c121SKalle Valo break; 1349e705c121SKalle Valo } 1350e705c121SKalle Valo } 1351e705c121SKalle Valo } 1352e705c121SKalle Valo 13539416560eSGolan Ben Ami if (rxq->id == trans_pcie->def_rx_queue) 1354bce97731SSara Sharon iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1355bce97731SSara Sharon &rxcb); 1356bce97731SSara Sharon else 1357bce97731SSara Sharon iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1358bce97731SSara Sharon &rxcb, rxq->id); 1359e705c121SKalle Valo 1360e705c121SKalle Valo /* 1361e705c121SKalle Valo * After here, we should always check rxcb._page_stolen, 1362e705c121SKalle Valo * if it is true then one of the handlers took the page. 1363e705c121SKalle Valo */ 1364e705c121SKalle Valo 1365e705c121SKalle Valo if (reclaim) { 1366e4475583SJohannes Berg u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1367e4475583SJohannes Berg int index = SEQ_TO_INDEX(sequence); 1368e4475583SJohannes Berg int cmd_index = iwl_txq_get_cmd_index(txq, index); 1369e4475583SJohannes Berg 1370e4475583SJohannes Berg kfree_sensitive(txq->entries[cmd_index].free_buf); 1371e4475583SJohannes Berg txq->entries[cmd_index].free_buf = NULL; 1372e4475583SJohannes Berg 1373e705c121SKalle Valo /* Invoke any callbacks, transfer the buffer to caller, 1374e705c121SKalle Valo * and fire off the (possibly) blocking 1375e705c121SKalle Valo * iwl_trans_send_cmd() 1376e705c121SKalle Valo * as we reclaim the driver command queue */ 1377e705c121SKalle Valo if (!rxcb._page_stolen) 1378e705c121SKalle Valo iwl_pcie_hcmd_complete(trans, &rxcb); 1379e705c121SKalle Valo else 1380e705c121SKalle Valo IWL_WARN(trans, "Claim null rxb?\n"); 1381e705c121SKalle Valo } 1382e705c121SKalle Valo 1383e705c121SKalle Valo page_stolen |= rxcb._page_stolen; 13843681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 13850307c839SGolan Ben Ami break; 1386e705c121SKalle Valo } 1387e705c121SKalle Valo 1388e705c121SKalle Valo /* page was stolen from us -- free our reference */ 1389e705c121SKalle Valo if (page_stolen) { 1390e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1391e705c121SKalle Valo rxb->page = NULL; 1392e705c121SKalle Valo } 1393e705c121SKalle Valo 1394e705c121SKalle Valo /* Reuse the page if possible. For notification packets and 1395e705c121SKalle Valo * SKBs that fail to Rx correctly, add them back into the 1396e705c121SKalle Valo * rx_free list for reuse later. */ 1397e705c121SKalle Valo if (rxb->page != NULL) { 1398e705c121SKalle Valo rxb->page_dma = 1399cfdc20efSJohannes Berg dma_map_page(trans->dev, rxb->page, rxb->offset, 140080084e35SJohannes Berg trans_pcie->rx_buf_bytes, 1401e705c121SKalle Valo DMA_FROM_DEVICE); 1402e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1403e705c121SKalle Valo /* 1404e705c121SKalle Valo * free the page(s) as well to not break 1405e705c121SKalle Valo * the invariant that the items on the used 1406e705c121SKalle Valo * list have no page(s) 1407e705c121SKalle Valo */ 1408e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1409e705c121SKalle Valo rxb->page = NULL; 1410e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1411e705c121SKalle Valo } else { 1412e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 1413e705c121SKalle Valo rxq->free_count++; 1414e705c121SKalle Valo } 1415e705c121SKalle Valo } else 1416e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1417e705c121SKalle Valo } 1418e705c121SKalle Valo 14191b4bbe8bSSara Sharon static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans, 1420b1c860f6SJohannes Berg struct iwl_rxq *rxq, int i, 1421b1c860f6SJohannes Berg bool *join) 14221b4bbe8bSSara Sharon { 14231b4bbe8bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 14241b4bbe8bSSara Sharon struct iwl_rx_mem_buffer *rxb; 14251b4bbe8bSSara Sharon u16 vid; 14261b4bbe8bSSara Sharon 1427f826faaaSJohannes Berg BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32); 1428*5d19e208SJohannes Berg BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc_bz) != 4); 1429f826faaaSJohannes Berg 1430286ca8ebSLuca Coelho if (!trans->trans_cfg->mq_rx_supported) { 14311b4bbe8bSSara Sharon rxb = rxq->queue[i]; 14321b4bbe8bSSara Sharon rxq->queue[i] = NULL; 14331b4bbe8bSSara Sharon return rxb; 14341b4bbe8bSSara Sharon } 14351b4bbe8bSSara Sharon 1436*5d19e208SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1437*5d19e208SJohannes Berg struct iwl_rx_completion_desc_bz *cd = rxq->used_bd; 1438*5d19e208SJohannes Berg 1439*5d19e208SJohannes Berg vid = le16_to_cpu(cd[i].rbid); 1440*5d19e208SJohannes Berg *join = cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED; 1441*5d19e208SJohannes Berg } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1442*5d19e208SJohannes Berg struct iwl_rx_completion_desc *cd = rxq->used_bd; 1443*5d19e208SJohannes Berg 1444*5d19e208SJohannes Berg vid = le16_to_cpu(cd[i].rbid); 1445*5d19e208SJohannes Berg *join = cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED; 1446b1c860f6SJohannes Berg } else { 1447*5d19e208SJohannes Berg __le32 *cd = rxq->used_bd; 1448*5d19e208SJohannes Berg 1449*5d19e208SJohannes Berg vid = le32_to_cpu(cd[i]) & 0x0FFF; /* 12-bit VID */ 1450b1c860f6SJohannes Berg } 14511b4bbe8bSSara Sharon 1452c042f0c7SJohannes Berg if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs)) 14531b4bbe8bSSara Sharon goto out_err; 14541b4bbe8bSSara Sharon 14551b4bbe8bSSara Sharon rxb = trans_pcie->global_table[vid - 1]; 14561b4bbe8bSSara Sharon if (rxb->invalid) 14571b4bbe8bSSara Sharon goto out_err; 14581b4bbe8bSSara Sharon 145985d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid); 146085d78bb1SSara Sharon 14611b4bbe8bSSara Sharon rxb->invalid = true; 14621b4bbe8bSSara Sharon 14631b4bbe8bSSara Sharon return rxb; 14641b4bbe8bSSara Sharon 14651b4bbe8bSSara Sharon out_err: 14661b4bbe8bSSara Sharon WARN(1, "Invalid rxb from HW %u\n", (u32)vid); 14671b4bbe8bSSara Sharon iwl_force_nmi(trans); 14681b4bbe8bSSara Sharon return NULL; 14691b4bbe8bSSara Sharon } 14701b4bbe8bSSara Sharon 1471e705c121SKalle Valo /* 1472e705c121SKalle Valo * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1473e705c121SKalle Valo */ 147425edc8f2SJohannes Berg static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget) 1475e705c121SKalle Valo { 1476e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 147730f24eabSJohannes Berg struct iwl_rxq *rxq; 147825edc8f2SJohannes Berg u32 r, i, count = 0, handled = 0; 1479e705c121SKalle Valo bool emergency = false; 1480e705c121SKalle Valo 148130f24eabSJohannes Berg if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd)) 148225edc8f2SJohannes Berg return budget; 148330f24eabSJohannes Berg 148430f24eabSJohannes Berg rxq = &trans_pcie->rxq[queue]; 148530f24eabSJohannes Berg 1486e705c121SKalle Valo restart: 1487e705c121SKalle Valo spin_lock(&rxq->lock); 1488e705c121SKalle Valo /* uCode's read index (stored in shared DRAM) indicates the last Rx 1489e705c121SKalle Valo * buffer that the driver may process (last buffer filled by ucode). */ 14900307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1491e705c121SKalle Valo i = rxq->read; 1492e705c121SKalle Valo 14935eae443eSSara Sharon /* W/A 9000 device step A0 wrap-around bug */ 14945eae443eSSara Sharon r &= (rxq->queue_size - 1); 14955eae443eSSara Sharon 1496e705c121SKalle Valo /* Rx interrupt, but nothing sent from uCode */ 1497e705c121SKalle Valo if (i == r) 14985eae443eSSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1499e705c121SKalle Valo 150025edc8f2SJohannes Berg while (i != r && ++handled < budget) { 1501868a1e86SShaul Triebitz struct iwl_rb_allocator *rba = &trans_pcie->rba; 1502e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 1503868a1e86SShaul Triebitz /* number of RBDs still waiting for page allocation */ 1504868a1e86SShaul Triebitz u32 rb_pending_alloc = 1505868a1e86SShaul Triebitz atomic_read(&trans_pcie->rba.req_pending) * 1506868a1e86SShaul Triebitz RX_CLAIM_REQ_ALLOC; 1507b1c860f6SJohannes Berg bool join = false; 1508e705c121SKalle Valo 1509868a1e86SShaul Triebitz if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 && 1510868a1e86SShaul Triebitz !emergency)) { 1511868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1512e705c121SKalle Valo emergency = true; 15136dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 15146dcdd165SSara Sharon "RX path is in emergency. Pending allocations %d\n", 15156dcdd165SSara Sharon rb_pending_alloc); 1516868a1e86SShaul Triebitz } 1517e705c121SKalle Valo 151885d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 151985d78bb1SSara Sharon 1520b1c860f6SJohannes Berg rxb = iwl_pcie_get_rxb(trans, rxq, i, &join); 15211b4bbe8bSSara Sharon if (!rxb) 15225eae443eSSara Sharon goto out; 1523e705c121SKalle Valo 1524b1c860f6SJohannes Berg if (unlikely(join || rxq->next_rb_is_fragment)) { 1525b1c860f6SJohannes Berg rxq->next_rb_is_fragment = join; 1526b1c860f6SJohannes Berg /* 1527b1c860f6SJohannes Berg * We can only get a multi-RB in the following cases: 1528b1c860f6SJohannes Berg * - firmware issue, sending a too big notification 1529b1c860f6SJohannes Berg * - sniffer mode with a large A-MSDU 1530b1c860f6SJohannes Berg * - large MTU frames (>2k) 1531b1c860f6SJohannes Berg * since the multi-RB functionality is limited to newer 1532b1c860f6SJohannes Berg * hardware that cannot put multiple entries into a 1533b1c860f6SJohannes Berg * single RB. 1534b1c860f6SJohannes Berg * 1535b1c860f6SJohannes Berg * Right now, the higher layers aren't set up to deal 1536b1c860f6SJohannes Berg * with that, so discard all of these. 1537b1c860f6SJohannes Berg */ 1538b1c860f6SJohannes Berg list_add_tail(&rxb->list, &rxq->rx_free); 1539b1c860f6SJohannes Berg rxq->free_count++; 1540b1c860f6SJohannes Berg } else { 15417891965dSSara Sharon iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i); 1542b1c860f6SJohannes Berg } 1543e705c121SKalle Valo 154496a6497bSSara Sharon i = (i + 1) & (rxq->queue_size - 1); 1545e705c121SKalle Valo 1546d56daea4SSara Sharon /* 1547d56daea4SSara Sharon * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1548d56daea4SSara Sharon * try to claim the pre-allocated buffers from the allocator. 1549d56daea4SSara Sharon * If not ready - will try to reclaim next time. 1550d56daea4SSara Sharon * There is no need to reschedule work - allocator exits only 1551d56daea4SSara Sharon * on success 1552e705c121SKalle Valo */ 1553d56daea4SSara Sharon if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1554d56daea4SSara Sharon iwl_pcie_rx_allocator_get(trans, rxq); 1555e705c121SKalle Valo 1556d56daea4SSara Sharon if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1557d56daea4SSara Sharon /* Add the remaining empty RBDs for allocator use */ 1558868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1559d56daea4SSara Sharon } else if (emergency) { 1560e705c121SKalle Valo count++; 1561e705c121SKalle Valo if (count == 8) { 1562e705c121SKalle Valo count = 0; 15636dcdd165SSara Sharon if (rb_pending_alloc < rxq->queue_size / 3) { 15646dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 15656dcdd165SSara Sharon "RX path exited emergency. Pending allocations %d\n", 15666dcdd165SSara Sharon rb_pending_alloc); 1567e705c121SKalle Valo emergency = false; 15686dcdd165SSara Sharon } 1569e0e168dcSGregory Greenman 1570e705c121SKalle Valo rxq->read = i; 1571e705c121SKalle Valo spin_unlock(&rxq->lock); 1572e0e168dcSGregory Greenman iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 157378485054SSara Sharon iwl_pcie_rxq_restock(trans, rxq); 1574e705c121SKalle Valo goto restart; 1575e705c121SKalle Valo } 1576e705c121SKalle Valo } 1577e0e168dcSGregory Greenman } 15785eae443eSSara Sharon out: 1579e705c121SKalle Valo /* Backtrack one entry */ 1580e705c121SKalle Valo rxq->read = i; 1581e705c121SKalle Valo spin_unlock(&rxq->lock); 1582e705c121SKalle Valo 1583e705c121SKalle Valo /* 1584e705c121SKalle Valo * handle a case where in emergency there are some unallocated RBDs. 1585e705c121SKalle Valo * those RBDs are in the used list, but are not tracked by the queue's 1586e705c121SKalle Valo * used_count which counts allocator owned RBDs. 1587e705c121SKalle Valo * unallocated emergency RBDs must be allocated on exit, otherwise 1588e705c121SKalle Valo * when called again the function may not be in emergency mode and 1589e705c121SKalle Valo * they will be handed to the allocator with no tracking in the RBD 1590e705c121SKalle Valo * allocator counters, which will lead to them never being claimed back 1591e705c121SKalle Valo * by the queue. 1592e705c121SKalle Valo * by allocating them here, they are now in the queue free list, and 1593e705c121SKalle Valo * will be restocked by the next call of iwl_pcie_rxq_restock. 1594e705c121SKalle Valo */ 1595e705c121SKalle Valo if (unlikely(emergency && count)) 159678485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1597e705c121SKalle Valo 1598e0e168dcSGregory Greenman iwl_pcie_rxq_restock(trans, rxq); 159925edc8f2SJohannes Berg 160025edc8f2SJohannes Berg return handled; 1601e705c121SKalle Valo } 1602e705c121SKalle Valo 16032e5d4a8fSHaim Dreyfuss static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 16042e5d4a8fSHaim Dreyfuss { 16052e5d4a8fSHaim Dreyfuss u8 queue = entry->entry; 16062e5d4a8fSHaim Dreyfuss struct msix_entry *entries = entry - queue; 16072e5d4a8fSHaim Dreyfuss 16082e5d4a8fSHaim Dreyfuss return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 16092e5d4a8fSHaim Dreyfuss } 16102e5d4a8fSHaim Dreyfuss 16112e5d4a8fSHaim Dreyfuss /* 16122e5d4a8fSHaim Dreyfuss * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 16132e5d4a8fSHaim Dreyfuss * This interrupt handler should be used with RSS queue only. 16142e5d4a8fSHaim Dreyfuss */ 16152e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 16162e5d4a8fSHaim Dreyfuss { 16172e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 16182e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 16192e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 162025edc8f2SJohannes Berg struct iwl_rxq *rxq = &trans_pcie->rxq[entry->entry]; 16212e5d4a8fSHaim Dreyfuss 1622c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1623c42ff65dSJohannes Berg 16245eae443eSSara Sharon if (WARN_ON(entry->entry >= trans->num_rx_queues)) 16255eae443eSSara Sharon return IRQ_NONE; 16265eae443eSSara Sharon 16279d401222SMordechay Goodstein if (WARN_ONCE(!rxq, 16289d401222SMordechay Goodstein "[%d] Got MSI-X interrupt before we have Rx queues", 16299d401222SMordechay Goodstein entry->entry)) 1630abc599efSEmmanuel Grumbach return IRQ_NONE; 1631abc599efSEmmanuel Grumbach 16322e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 16339d401222SMordechay Goodstein IWL_DEBUG_ISR(trans, "[%d] Got interrupt\n", entry->entry); 16342e5d4a8fSHaim Dreyfuss 16352e5d4a8fSHaim Dreyfuss local_bh_disable(); 163625edc8f2SJohannes Berg if (napi_schedule_prep(&rxq->napi)) 163725edc8f2SJohannes Berg __napi_schedule(&rxq->napi); 163825edc8f2SJohannes Berg else 163925edc8f2SJohannes Berg iwl_pcie_clear_irq(trans, entry->entry); 16402e5d4a8fSHaim Dreyfuss local_bh_enable(); 16412e5d4a8fSHaim Dreyfuss 16422e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 16432e5d4a8fSHaim Dreyfuss 16442e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 16452e5d4a8fSHaim Dreyfuss } 16462e5d4a8fSHaim Dreyfuss 1647e705c121SKalle Valo /* 1648e705c121SKalle Valo * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1649e705c121SKalle Valo */ 1650e705c121SKalle Valo static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1651e705c121SKalle Valo { 1652e705c121SKalle Valo int i; 1653e705c121SKalle Valo 1654e705c121SKalle Valo /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1655e705c121SKalle Valo if (trans->cfg->internal_wimax_coex && 1656e705c121SKalle Valo !trans->cfg->apmg_not_supported && 1657e705c121SKalle Valo (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1658e705c121SKalle Valo APMS_CLK_VAL_MRB_FUNC_MODE) || 1659e705c121SKalle Valo (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1660e705c121SKalle Valo APMG_PS_CTRL_VAL_RESET_REQ))) { 1661e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1662e705c121SKalle Valo iwl_op_mode_wimax_active(trans->op_mode); 166313f028b4SMordechay Goodstein wake_up(&trans->wait_command_queue); 1664e705c121SKalle Valo return; 1665e705c121SKalle Valo } 1666e705c121SKalle Valo 1667286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 16684f4822b7SMordechay Goodstein if (!trans->txqs.txq[i]) 166913a3a390SSara Sharon continue; 16704f4822b7SMordechay Goodstein del_timer(&trans->txqs.txq[i]->stuck_timer); 167113a3a390SSara Sharon } 1672e705c121SKalle Valo 16737d75f32eSEmmanuel Grumbach /* The STATUS_FW_ERROR bit is set in this function. This must happen 16747d75f32eSEmmanuel Grumbach * before we wake up the command caller, to ensure a proper cleanup. */ 1675b8221b0fSJohannes Berg iwl_trans_fw_error(trans, false); 16767d75f32eSEmmanuel Grumbach 1677e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 167813f028b4SMordechay Goodstein wake_up(&trans->wait_command_queue); 1679e705c121SKalle Valo } 1680e705c121SKalle Valo 1681e705c121SKalle Valo static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1682e705c121SKalle Valo { 1683e705c121SKalle Valo u32 inta; 1684e705c121SKalle Valo 1685e705c121SKalle Valo lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1686e705c121SKalle Valo 1687e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1688e705c121SKalle Valo 1689e705c121SKalle Valo /* Discover which interrupts are active/pending */ 1690e705c121SKalle Valo inta = iwl_read32(trans, CSR_INT); 1691e705c121SKalle Valo 1692e705c121SKalle Valo /* the thread will service interrupts and re-enable them */ 1693e705c121SKalle Valo return inta; 1694e705c121SKalle Valo } 1695e705c121SKalle Valo 1696e705c121SKalle Valo /* a device (PCI-E) page is 4096 bytes long */ 1697e705c121SKalle Valo #define ICT_SHIFT 12 1698e705c121SKalle Valo #define ICT_SIZE (1 << ICT_SHIFT) 1699e705c121SKalle Valo #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1700e705c121SKalle Valo 1701e705c121SKalle Valo /* interrupt handler using ict table, with this interrupt driver will 1702e705c121SKalle Valo * stop using INTA register to get device's interrupt, reading this register 1703e705c121SKalle Valo * is expensive, device will write interrupts in ICT dram table, increment 1704e705c121SKalle Valo * index then will fire interrupt to driver, driver will OR all ICT table 1705e705c121SKalle Valo * entries from current index up to table entry with 0 value. the result is 1706e705c121SKalle Valo * the interrupt we need to service, driver will set the entries back to 0 and 1707e705c121SKalle Valo * set index. 1708e705c121SKalle Valo */ 1709e705c121SKalle Valo static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1710e705c121SKalle Valo { 1711e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1712e705c121SKalle Valo u32 inta; 1713e705c121SKalle Valo u32 val = 0; 1714e705c121SKalle Valo u32 read; 1715e705c121SKalle Valo 1716e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1717e705c121SKalle Valo 1718e705c121SKalle Valo /* Ignore interrupt if there's nothing in NIC to service. 1719e705c121SKalle Valo * This may be due to IRQ shared with another device, 1720e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. */ 1721e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1722e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1723e705c121SKalle Valo if (!read) 1724e705c121SKalle Valo return 0; 1725e705c121SKalle Valo 1726e705c121SKalle Valo /* 1727e705c121SKalle Valo * Collect all entries up to the first 0, starting from ict_index; 1728e705c121SKalle Valo * note we already read at ict_index. 1729e705c121SKalle Valo */ 1730e705c121SKalle Valo do { 1731e705c121SKalle Valo val |= read; 1732e705c121SKalle Valo IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1733e705c121SKalle Valo trans_pcie->ict_index, read); 1734e705c121SKalle Valo trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1735e705c121SKalle Valo trans_pcie->ict_index = 1736e705c121SKalle Valo ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1737e705c121SKalle Valo 1738e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1739e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1740e705c121SKalle Valo read); 1741e705c121SKalle Valo } while (read); 1742e705c121SKalle Valo 1743e705c121SKalle Valo /* We should not get this value, just ignore it. */ 1744e705c121SKalle Valo if (val == 0xffffffff) 1745e705c121SKalle Valo val = 0; 1746e705c121SKalle Valo 1747e705c121SKalle Valo /* 1748e705c121SKalle Valo * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1749e705c121SKalle Valo * (bit 15 before shifting it to 31) to clear when using interrupt 1750e705c121SKalle Valo * coalescing. fortunately, bits 18 and 19 stay set when this happens 1751e705c121SKalle Valo * so we use them to decide on the real state of the Rx bit. 1752e705c121SKalle Valo * In order words, bit 15 is set if bit 18 or bit 19 are set. 1753e705c121SKalle Valo */ 1754e705c121SKalle Valo if (val & 0xC0000) 1755e705c121SKalle Valo val |= 0x8000; 1756e705c121SKalle Valo 1757e705c121SKalle Valo inta = (0xff & val) | ((0xff00 & val) << 16); 1758e705c121SKalle Valo return inta; 1759e705c121SKalle Valo } 1760e705c121SKalle Valo 1761fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 17623a6e168bSJohannes Berg { 17633a6e168bSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17643a6e168bSJohannes Berg struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1765326477e4SJohannes Berg bool hw_rfkill, prev, report; 17663a6e168bSJohannes Berg 17673a6e168bSJohannes Berg mutex_lock(&trans_pcie->mutex); 1768326477e4SJohannes Berg prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 17693a6e168bSJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1770326477e4SJohannes Berg if (hw_rfkill) { 1771326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1772326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1773326477e4SJohannes Berg } 1774326477e4SJohannes Berg if (trans_pcie->opmode_down) 1775326477e4SJohannes Berg report = hw_rfkill; 1776326477e4SJohannes Berg else 1777326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 17783a6e168bSJohannes Berg 17793a6e168bSJohannes Berg IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 17803a6e168bSJohannes Berg hw_rfkill ? "disable radio" : "enable radio"); 17813a6e168bSJohannes Berg 17823a6e168bSJohannes Berg isr_stats->rfkill++; 17833a6e168bSJohannes Berg 1784326477e4SJohannes Berg if (prev != report) 1785326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 17863a6e168bSJohannes Berg mutex_unlock(&trans_pcie->mutex); 17873a6e168bSJohannes Berg 17883a6e168bSJohannes Berg if (hw_rfkill) { 17893a6e168bSJohannes Berg if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 17903a6e168bSJohannes Berg &trans->status)) 17913a6e168bSJohannes Berg IWL_DEBUG_RF_KILL(trans, 17923a6e168bSJohannes Berg "Rfkill while SYNC HCMD in flight\n"); 179313f028b4SMordechay Goodstein wake_up(&trans->wait_command_queue); 17943a6e168bSJohannes Berg } else { 1795326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1796326477e4SJohannes Berg if (trans_pcie->opmode_down) 1797326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 17983a6e168bSJohannes Berg } 17993a6e168bSJohannes Berg } 18003a6e168bSJohannes Berg 1801e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1802e705c121SKalle Valo { 1803e705c121SKalle Valo struct iwl_trans *trans = dev_id; 1804e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1805e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1806e705c121SKalle Valo u32 inta = 0; 1807e705c121SKalle Valo u32 handled = 0; 180825edc8f2SJohannes Berg bool polling = false; 1809e705c121SKalle Valo 1810e705c121SKalle Valo lock_map_acquire(&trans->sync_cmd_lockdep_map); 1811e705c121SKalle Valo 181225edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 1813e705c121SKalle Valo 1814e705c121SKalle Valo /* dram interrupt table not set yet, 1815e705c121SKalle Valo * use legacy interrupt. 1816e705c121SKalle Valo */ 1817e705c121SKalle Valo if (likely(trans_pcie->use_ict)) 1818e705c121SKalle Valo inta = iwl_pcie_int_cause_ict(trans); 1819e705c121SKalle Valo else 1820e705c121SKalle Valo inta = iwl_pcie_int_cause_non_ict(trans); 1821e705c121SKalle Valo 1822e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1823e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1824e705c121SKalle Valo "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1825e705c121SKalle Valo inta, trans_pcie->inta_mask, 1826e705c121SKalle Valo iwl_read32(trans, CSR_INT_MASK), 1827e705c121SKalle Valo iwl_read32(trans, CSR_FH_INT_STATUS)); 1828e705c121SKalle Valo if (inta & (~trans_pcie->inta_mask)) 1829e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1830e705c121SKalle Valo "We got a masked interrupt (0x%08x)\n", 1831e705c121SKalle Valo inta & (~trans_pcie->inta_mask)); 1832e705c121SKalle Valo } 1833e705c121SKalle Valo 1834e705c121SKalle Valo inta &= trans_pcie->inta_mask; 1835e705c121SKalle Valo 1836e705c121SKalle Valo /* 1837e705c121SKalle Valo * Ignore interrupt if there's nothing in NIC to service. 1838e705c121SKalle Valo * This may be due to IRQ shared with another device, 1839e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. 1840e705c121SKalle Valo */ 1841e705c121SKalle Valo if (unlikely(!inta)) { 1842e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1843e705c121SKalle Valo /* 1844e705c121SKalle Valo * Re-enable interrupts here since we don't 1845e705c121SKalle Valo * have anything to service 1846e705c121SKalle Valo */ 1847e705c121SKalle Valo if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1848f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 184925edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 1850e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1851e705c121SKalle Valo return IRQ_NONE; 1852e705c121SKalle Valo } 1853e705c121SKalle Valo 1854e705c121SKalle Valo if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1855e705c121SKalle Valo /* 1856e705c121SKalle Valo * Hardware disappeared. It might have 1857e705c121SKalle Valo * already raised an interrupt. 1858e705c121SKalle Valo */ 1859e705c121SKalle Valo IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 186025edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 1861e705c121SKalle Valo goto out; 1862e705c121SKalle Valo } 1863e705c121SKalle Valo 1864e705c121SKalle Valo /* Ack/clear/reset pending uCode interrupts. 1865e705c121SKalle Valo * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1866e705c121SKalle Valo */ 1867e705c121SKalle Valo /* There is a hardware bug in the interrupt mask function that some 1868e705c121SKalle Valo * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1869e705c121SKalle Valo * they are disabled in the CSR_INT_MASK register. Furthermore the 1870e705c121SKalle Valo * ICT interrupt handling mechanism has another bug that might cause 1871e705c121SKalle Valo * these unmasked interrupts fail to be detected. We workaround the 1872e705c121SKalle Valo * hardware bugs here by ACKing all the possible interrupts so that 1873e705c121SKalle Valo * interrupt coalescing can still be achieved. 1874e705c121SKalle Valo */ 1875e705c121SKalle Valo iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1876e705c121SKalle Valo 1877e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) 1878e705c121SKalle Valo IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1879e705c121SKalle Valo inta, iwl_read32(trans, CSR_INT_MASK)); 1880e705c121SKalle Valo 188125edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 1882e705c121SKalle Valo 1883e705c121SKalle Valo /* Now service all interrupt bits discovered above. */ 1884e705c121SKalle Valo if (inta & CSR_INT_BIT_HW_ERR) { 1885e705c121SKalle Valo IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1886e705c121SKalle Valo 1887e705c121SKalle Valo /* Tell the device to stop sending interrupts */ 1888e705c121SKalle Valo iwl_disable_interrupts(trans); 1889e705c121SKalle Valo 1890e705c121SKalle Valo isr_stats->hw++; 1891e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1892e705c121SKalle Valo 1893e705c121SKalle Valo handled |= CSR_INT_BIT_HW_ERR; 1894e705c121SKalle Valo 1895e705c121SKalle Valo goto out; 1896e705c121SKalle Valo } 1897e705c121SKalle Valo 1898e705c121SKalle Valo /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1899e705c121SKalle Valo if (inta & CSR_INT_BIT_SCD) { 1900e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1901e705c121SKalle Valo "Scheduler finished to transmit the frame/frames.\n"); 1902e705c121SKalle Valo isr_stats->sch++; 1903e705c121SKalle Valo } 1904e705c121SKalle Valo 1905e705c121SKalle Valo /* Alive notification via Rx interrupt will do the real work */ 1906e705c121SKalle Valo if (inta & CSR_INT_BIT_ALIVE) { 1907e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1908e705c121SKalle Valo isr_stats->alive++; 1909286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) { 1910eda50cdeSSara Sharon /* 1911eda50cdeSSara Sharon * We can restock, since firmware configured 1912eda50cdeSSara Sharon * the RFH 1913eda50cdeSSara Sharon */ 1914eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1915eda50cdeSSara Sharon } 1916ed3e4c6dSEmmanuel Grumbach 1917ed3e4c6dSEmmanuel Grumbach handled |= CSR_INT_BIT_ALIVE; 1918e705c121SKalle Valo } 1919e705c121SKalle Valo 1920e705c121SKalle Valo /* Safely ignore these bits for debug checks below */ 1921e705c121SKalle Valo inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1922e705c121SKalle Valo 1923e705c121SKalle Valo /* HW RF KILL switch toggled */ 1924e705c121SKalle Valo if (inta & CSR_INT_BIT_RF_KILL) { 19253a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 1926e705c121SKalle Valo handled |= CSR_INT_BIT_RF_KILL; 1927e705c121SKalle Valo } 1928e705c121SKalle Valo 1929e705c121SKalle Valo /* Chip got too hot and stopped itself */ 1930e705c121SKalle Valo if (inta & CSR_INT_BIT_CT_KILL) { 1931e705c121SKalle Valo IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1932e705c121SKalle Valo isr_stats->ctkill++; 1933e705c121SKalle Valo handled |= CSR_INT_BIT_CT_KILL; 1934e705c121SKalle Valo } 1935e705c121SKalle Valo 1936e705c121SKalle Valo /* Error detected by uCode */ 1937e705c121SKalle Valo if (inta & CSR_INT_BIT_SW_ERR) { 1938e705c121SKalle Valo IWL_ERR(trans, "Microcode SW error detected. " 1939e705c121SKalle Valo " Restarting 0x%X.\n", inta); 1940e705c121SKalle Valo isr_stats->sw++; 1941e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1942e705c121SKalle Valo handled |= CSR_INT_BIT_SW_ERR; 1943e705c121SKalle Valo } 1944e705c121SKalle Valo 1945e705c121SKalle Valo /* uCode wakes up after power-down sleep */ 1946e705c121SKalle Valo if (inta & CSR_INT_BIT_WAKEUP) { 1947e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1948e705c121SKalle Valo iwl_pcie_rxq_check_wrptr(trans); 1949e705c121SKalle Valo iwl_pcie_txq_check_wrptrs(trans); 1950e705c121SKalle Valo 1951e705c121SKalle Valo isr_stats->wakeup++; 1952e705c121SKalle Valo 1953e705c121SKalle Valo handled |= CSR_INT_BIT_WAKEUP; 1954e705c121SKalle Valo } 1955e705c121SKalle Valo 1956e705c121SKalle Valo /* All uCode command responses, including Tx command responses, 1957e705c121SKalle Valo * Rx "responses" (frame-received notification), and other 1958e705c121SKalle Valo * notifications from uCode come through here*/ 1959e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1960e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC)) { 1961e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1962e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1963e705c121SKalle Valo handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1964e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 1965e705c121SKalle Valo CSR_FH_INT_RX_MASK); 1966e705c121SKalle Valo } 1967e705c121SKalle Valo if (inta & CSR_INT_BIT_RX_PERIODIC) { 1968e705c121SKalle Valo handled |= CSR_INT_BIT_RX_PERIODIC; 1969e705c121SKalle Valo iwl_write32(trans, 1970e705c121SKalle Valo CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1971e705c121SKalle Valo } 1972e705c121SKalle Valo /* Sending RX interrupt require many steps to be done in the 1973e705c121SKalle Valo * the device: 1974e705c121SKalle Valo * 1- write interrupt to current index in ICT table. 1975e705c121SKalle Valo * 2- dma RX frame. 1976e705c121SKalle Valo * 3- update RX shared data to indicate last write index. 1977e705c121SKalle Valo * 4- send interrupt. 1978e705c121SKalle Valo * This could lead to RX race, driver could receive RX interrupt 1979e705c121SKalle Valo * but the shared data changes does not reflect this; 1980e705c121SKalle Valo * periodic interrupt will detect any dangling Rx activity. 1981e705c121SKalle Valo */ 1982e705c121SKalle Valo 1983e705c121SKalle Valo /* Disable periodic interrupt; we use it as just a one-shot. */ 1984e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1985e705c121SKalle Valo CSR_INT_PERIODIC_DIS); 1986e705c121SKalle Valo 1987e705c121SKalle Valo /* 1988e705c121SKalle Valo * Enable periodic interrupt in 8 msec only if we received 1989e705c121SKalle Valo * real RX interrupt (instead of just periodic int), to catch 1990e705c121SKalle Valo * any dangling Rx interrupt. If it was just the periodic 1991e705c121SKalle Valo * interrupt, there was no dangling Rx activity, and no need 1992e705c121SKalle Valo * to extend the periodic interrupt; one-shot is enough. 1993e705c121SKalle Valo */ 1994e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1995e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1996e705c121SKalle Valo CSR_INT_PERIODIC_ENA); 1997e705c121SKalle Valo 1998e705c121SKalle Valo isr_stats->rx++; 1999e705c121SKalle Valo 2000e705c121SKalle Valo local_bh_disable(); 200125edc8f2SJohannes Berg if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 200225edc8f2SJohannes Berg polling = true; 200325edc8f2SJohannes Berg __napi_schedule(&trans_pcie->rxq[0].napi); 200425edc8f2SJohannes Berg } 2005e705c121SKalle Valo local_bh_enable(); 2006e705c121SKalle Valo } 2007e705c121SKalle Valo 2008e705c121SKalle Valo /* This "Tx" DMA channel is used only for loading uCode */ 2009e705c121SKalle Valo if (inta & CSR_INT_BIT_FH_TX) { 2010e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 2011e705c121SKalle Valo IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 2012e705c121SKalle Valo isr_stats->tx++; 2013e705c121SKalle Valo handled |= CSR_INT_BIT_FH_TX; 2014e705c121SKalle Valo /* Wake up uCode load routine, now that load is complete */ 2015e705c121SKalle Valo trans_pcie->ucode_write_complete = true; 2016e705c121SKalle Valo wake_up(&trans_pcie->ucode_write_waitq); 2017c0941aceSMukesh Sisodiya /* Wake up IMR write routine, now that write to SRAM is complete */ 2018c0941aceSMukesh Sisodiya if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2019c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_COMPLETED; 2020c0941aceSMukesh Sisodiya wake_up(&trans_pcie->ucode_write_waitq); 2021c0941aceSMukesh Sisodiya } 2022e705c121SKalle Valo } 2023e705c121SKalle Valo 2024e705c121SKalle Valo if (inta & ~handled) { 2025e705c121SKalle Valo IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 2026e705c121SKalle Valo isr_stats->unhandled++; 2027e705c121SKalle Valo } 2028e705c121SKalle Valo 2029e705c121SKalle Valo if (inta & ~(trans_pcie->inta_mask)) { 2030e705c121SKalle Valo IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 2031e705c121SKalle Valo inta & ~trans_pcie->inta_mask); 2032e705c121SKalle Valo } 2033e705c121SKalle Valo 203425edc8f2SJohannes Berg if (!polling) { 203525edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 2036a6bd005fSEmmanuel Grumbach /* only Re-enable all interrupt if disabled by irq */ 2037f16c3ebfSEmmanuel Grumbach if (test_bit(STATUS_INT_ENABLED, &trans->status)) 2038f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 2039f16c3ebfSEmmanuel Grumbach /* we are loading the firmware, enable FH_TX interrupt only */ 2040f16c3ebfSEmmanuel Grumbach else if (handled & CSR_INT_BIT_FH_TX) 2041f16c3ebfSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 2042e705c121SKalle Valo /* Re-enable RF_KILL if it occurred */ 2043e705c121SKalle Valo else if (handled & CSR_INT_BIT_RF_KILL) 2044e705c121SKalle Valo iwl_enable_rfkill_int(trans); 2045ed3e4c6dSEmmanuel Grumbach /* Re-enable the ALIVE / Rx interrupt if it occurred */ 2046ed3e4c6dSEmmanuel Grumbach else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX)) 2047ed3e4c6dSEmmanuel Grumbach iwl_enable_fw_load_int_ctx_info(trans); 204825edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 204925edc8f2SJohannes Berg } 2050e705c121SKalle Valo 2051e705c121SKalle Valo out: 2052e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 2053e705c121SKalle Valo return IRQ_HANDLED; 2054e705c121SKalle Valo } 2055e705c121SKalle Valo 2056e705c121SKalle Valo /****************************************************************************** 2057e705c121SKalle Valo * 2058e705c121SKalle Valo * ICT functions 2059e705c121SKalle Valo * 2060e705c121SKalle Valo ******************************************************************************/ 2061e705c121SKalle Valo 2062e705c121SKalle Valo /* Free dram table */ 2063e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans) 2064e705c121SKalle Valo { 2065e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2066e705c121SKalle Valo 2067e705c121SKalle Valo if (trans_pcie->ict_tbl) { 2068e705c121SKalle Valo dma_free_coherent(trans->dev, ICT_SIZE, 2069e705c121SKalle Valo trans_pcie->ict_tbl, 2070e705c121SKalle Valo trans_pcie->ict_tbl_dma); 2071e705c121SKalle Valo trans_pcie->ict_tbl = NULL; 2072e705c121SKalle Valo trans_pcie->ict_tbl_dma = 0; 2073e705c121SKalle Valo } 2074e705c121SKalle Valo } 2075e705c121SKalle Valo 2076e705c121SKalle Valo /* 2077e705c121SKalle Valo * allocate dram shared table, it is an aligned memory 2078e705c121SKalle Valo * block of ICT_SIZE. 2079e705c121SKalle Valo * also reset all data related to ICT table interrupt. 2080e705c121SKalle Valo */ 2081e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans) 2082e705c121SKalle Valo { 2083e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2084e705c121SKalle Valo 2085e705c121SKalle Valo trans_pcie->ict_tbl = 2086750afb08SLuis Chamberlain dma_alloc_coherent(trans->dev, ICT_SIZE, 2087750afb08SLuis Chamberlain &trans_pcie->ict_tbl_dma, GFP_KERNEL); 2088e705c121SKalle Valo if (!trans_pcie->ict_tbl) 2089e705c121SKalle Valo return -ENOMEM; 2090e705c121SKalle Valo 2091e705c121SKalle Valo /* just an API sanity check ... it is guaranteed to be aligned */ 2092e705c121SKalle Valo if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 2093e705c121SKalle Valo iwl_pcie_free_ict(trans); 2094e705c121SKalle Valo return -EINVAL; 2095e705c121SKalle Valo } 2096e705c121SKalle Valo 2097e705c121SKalle Valo return 0; 2098e705c121SKalle Valo } 2099e705c121SKalle Valo 2100e705c121SKalle Valo /* Device is going up inform it about using ICT interrupt table, 2101e705c121SKalle Valo * also we need to tell the driver to start using ICT interrupt. 2102e705c121SKalle Valo */ 2103e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans) 2104e705c121SKalle Valo { 2105e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2106e705c121SKalle Valo u32 val; 2107e705c121SKalle Valo 2108e705c121SKalle Valo if (!trans_pcie->ict_tbl) 2109e705c121SKalle Valo return; 2110e705c121SKalle Valo 211125edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 2112f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 2113e705c121SKalle Valo 2114e705c121SKalle Valo memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 2115e705c121SKalle Valo 2116e705c121SKalle Valo val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 2117e705c121SKalle Valo 2118e705c121SKalle Valo val |= CSR_DRAM_INT_TBL_ENABLE | 2119e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRAP_CHECK | 2120e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRITE_POINTER; 2121e705c121SKalle Valo 2122e705c121SKalle Valo IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 2123e705c121SKalle Valo 2124e705c121SKalle Valo iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 2125e705c121SKalle Valo trans_pcie->use_ict = true; 2126e705c121SKalle Valo trans_pcie->ict_index = 0; 2127e705c121SKalle Valo iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 2128f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 212925edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 2130e705c121SKalle Valo } 2131e705c121SKalle Valo 2132e705c121SKalle Valo /* Device is going down disable ict interrupt usage */ 2133e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans) 2134e705c121SKalle Valo { 2135e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2136e705c121SKalle Valo 213725edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 2138e705c121SKalle Valo trans_pcie->use_ict = false; 213925edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 2140e705c121SKalle Valo } 2141e705c121SKalle Valo 2142e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data) 2143e705c121SKalle Valo { 2144e705c121SKalle Valo struct iwl_trans *trans = data; 2145e705c121SKalle Valo 2146e705c121SKalle Valo if (!trans) 2147e705c121SKalle Valo return IRQ_NONE; 2148e705c121SKalle Valo 2149e705c121SKalle Valo /* Disable (but don't clear!) interrupts here to avoid 2150e705c121SKalle Valo * back-to-back ISRs and sporadic interrupts from our NIC. 2151e705c121SKalle Valo * If we have something to service, the tasklet will re-enable ints. 2152e705c121SKalle Valo * If we *don't* have something, we'll re-enable before leaving here. 2153e705c121SKalle Valo */ 2154e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2155e705c121SKalle Valo 2156e705c121SKalle Valo return IRQ_WAKE_THREAD; 2157e705c121SKalle Valo } 21582e5d4a8fSHaim Dreyfuss 21592e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 21602e5d4a8fSHaim Dreyfuss { 21612e5d4a8fSHaim Dreyfuss return IRQ_WAKE_THREAD; 21622e5d4a8fSHaim Dreyfuss } 21632e5d4a8fSHaim Dreyfuss 21642e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 21652e5d4a8fSHaim Dreyfuss { 21662e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 21672e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 21682e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 216946167a8fSColin Ian King struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2170d4626f91SMordechay Goodstein u32 inta_fh_msk = ~MSIX_FH_INT_CAUSES_DATA_QUEUE; 21712e5d4a8fSHaim Dreyfuss u32 inta_fh, inta_hw; 217225edc8f2SJohannes Berg bool polling = false; 2173571836a0SMike Golant bool sw_err; 21742e5d4a8fSHaim Dreyfuss 2175d4626f91SMordechay Goodstein if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 2176d4626f91SMordechay Goodstein inta_fh_msk |= MSIX_FH_INT_CAUSES_Q0; 2177d4626f91SMordechay Goodstein 2178d4626f91SMordechay Goodstein if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 2179d4626f91SMordechay Goodstein inta_fh_msk |= MSIX_FH_INT_CAUSES_Q1; 2180d4626f91SMordechay Goodstein 21812e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 21822e5d4a8fSHaim Dreyfuss 218325edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 21847ef3dd26SHaim Dreyfuss inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 21857ef3dd26SHaim Dreyfuss inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 21862e5d4a8fSHaim Dreyfuss /* 21872e5d4a8fSHaim Dreyfuss * Clear causes registers to avoid being handling the same cause. 21882e5d4a8fSHaim Dreyfuss */ 2189d4626f91SMordechay Goodstein iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk); 21907ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 219125edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 21922e5d4a8fSHaim Dreyfuss 2193c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2194c42ff65dSJohannes Berg 21952e5d4a8fSHaim Dreyfuss if (unlikely(!(inta_fh | inta_hw))) { 21962e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 21972e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 21982e5d4a8fSHaim Dreyfuss return IRQ_NONE; 21992e5d4a8fSHaim Dreyfuss } 22002e5d4a8fSHaim Dreyfuss 22013b57a10cSEmmanuel Grumbach if (iwl_have_debug_level(IWL_DL_ISR)) { 22023b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 22039d401222SMordechay Goodstein "ISR[%d] inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 22049d401222SMordechay Goodstein entry->entry, inta_fh, trans_pcie->fh_mask, 22052e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 22063b57a10cSEmmanuel Grumbach if (inta_fh & ~trans_pcie->fh_mask) 22073b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 22083b57a10cSEmmanuel Grumbach "We got a masked interrupt (0x%08x)\n", 22093b57a10cSEmmanuel Grumbach inta_fh & ~trans_pcie->fh_mask); 22103b57a10cSEmmanuel Grumbach } 22113b57a10cSEmmanuel Grumbach 22123b57a10cSEmmanuel Grumbach inta_fh &= trans_pcie->fh_mask; 22132e5d4a8fSHaim Dreyfuss 2214496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2215496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2216496d83caSHaim Dreyfuss local_bh_disable(); 221725edc8f2SJohannes Berg if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 221825edc8f2SJohannes Berg polling = true; 221925edc8f2SJohannes Berg __napi_schedule(&trans_pcie->rxq[0].napi); 222025edc8f2SJohannes Berg } 2221496d83caSHaim Dreyfuss local_bh_enable(); 2222496d83caSHaim Dreyfuss } 2223496d83caSHaim Dreyfuss 2224496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2225496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2226496d83caSHaim Dreyfuss local_bh_disable(); 222725edc8f2SJohannes Berg if (napi_schedule_prep(&trans_pcie->rxq[1].napi)) { 222825edc8f2SJohannes Berg polling = true; 222925edc8f2SJohannes Berg __napi_schedule(&trans_pcie->rxq[1].napi); 223025edc8f2SJohannes Berg } 2231496d83caSHaim Dreyfuss local_bh_enable(); 2232496d83caSHaim Dreyfuss } 2233496d83caSHaim Dreyfuss 22342e5d4a8fSHaim Dreyfuss /* This "Tx" DMA channel is used only for loading uCode */ 2235c0941aceSMukesh Sisodiya if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM && 2236c0941aceSMukesh Sisodiya trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2237c0941aceSMukesh Sisodiya IWL_DEBUG_ISR(trans, "IMR Complete interrupt\n"); 2238c0941aceSMukesh Sisodiya isr_stats->tx++; 2239c0941aceSMukesh Sisodiya 2240c0941aceSMukesh Sisodiya /* Wake up IMR routine once write to SRAM is complete */ 2241c0941aceSMukesh Sisodiya if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2242c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_COMPLETED; 2243c0941aceSMukesh Sisodiya wake_up(&trans_pcie->ucode_write_waitq); 2244c0941aceSMukesh Sisodiya } 2245c0941aceSMukesh Sisodiya } else if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 22462e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 22472e5d4a8fSHaim Dreyfuss isr_stats->tx++; 22482e5d4a8fSHaim Dreyfuss /* 22492e5d4a8fSHaim Dreyfuss * Wake up uCode load routine, 22502e5d4a8fSHaim Dreyfuss * now that load is complete 22512e5d4a8fSHaim Dreyfuss */ 22522e5d4a8fSHaim Dreyfuss trans_pcie->ucode_write_complete = true; 22532e5d4a8fSHaim Dreyfuss wake_up(&trans_pcie->ucode_write_waitq); 2254c0941aceSMukesh Sisodiya 2255c0941aceSMukesh Sisodiya /* Wake up IMR routine once write to SRAM is complete */ 2256c0941aceSMukesh Sisodiya if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2257c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_COMPLETED; 2258c0941aceSMukesh Sisodiya wake_up(&trans_pcie->ucode_write_waitq); 2259c0941aceSMukesh Sisodiya } 22602e5d4a8fSHaim Dreyfuss } 22612e5d4a8fSHaim Dreyfuss 2262571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2263571836a0SMike Golant sw_err = inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 2264571836a0SMike Golant else 2265571836a0SMike Golant sw_err = inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR; 2266571836a0SMike Golant 22672e5d4a8fSHaim Dreyfuss /* Error detected by uCode */ 2268571836a0SMike Golant if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || sw_err) { 22692e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 22702e5d4a8fSHaim Dreyfuss "Microcode SW error detected. Restarting 0x%X.\n", 22712e5d4a8fSHaim Dreyfuss inta_fh); 22722e5d4a8fSHaim Dreyfuss isr_stats->sw++; 2273e63aafeaSJohannes Berg /* during FW reset flow report errors from there */ 2274c0941aceSMukesh Sisodiya if (trans_pcie->imr_status == IMR_D2S_REQUESTED) { 2275c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_ERROR; 2276c0941aceSMukesh Sisodiya wake_up(&trans_pcie->imr_waitq); 2277c0941aceSMukesh Sisodiya } else if (trans_pcie->fw_reset_state == FW_RESET_REQUESTED) { 2278e63aafeaSJohannes Berg trans_pcie->fw_reset_state = FW_RESET_ERROR; 2279e63aafeaSJohannes Berg wake_up(&trans_pcie->fw_reset_waitq); 2280e63aafeaSJohannes Berg } else { 22812e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 22822e5d4a8fSHaim Dreyfuss } 2283e63aafeaSJohannes Berg } 22842e5d4a8fSHaim Dreyfuss 22852e5d4a8fSHaim Dreyfuss /* After checking FH register check HW register */ 22863b57a10cSEmmanuel Grumbach if (iwl_have_debug_level(IWL_DL_ISR)) { 22872e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, 22889d401222SMordechay Goodstein "ISR[%d] inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 22899d401222SMordechay Goodstein entry->entry, inta_hw, trans_pcie->hw_mask, 22902e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 22913b57a10cSEmmanuel Grumbach if (inta_hw & ~trans_pcie->hw_mask) 22923b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 22933b57a10cSEmmanuel Grumbach "We got a masked interrupt 0x%08x\n", 22943b57a10cSEmmanuel Grumbach inta_hw & ~trans_pcie->hw_mask); 22953b57a10cSEmmanuel Grumbach } 22963b57a10cSEmmanuel Grumbach 22973b57a10cSEmmanuel Grumbach inta_hw &= trans_pcie->hw_mask; 22982e5d4a8fSHaim Dreyfuss 22992e5d4a8fSHaim Dreyfuss /* Alive notification via Rx interrupt will do the real work */ 23002e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 23012e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 23022e5d4a8fSHaim Dreyfuss isr_stats->alive++; 2303286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) { 2304eda50cdeSSara Sharon /* We can restock, since firmware configured the RFH */ 2305eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2306eda50cdeSSara Sharon } 23072e5d4a8fSHaim Dreyfuss } 23082e5d4a8fSHaim Dreyfuss 2309459fc0f2SLuca Coelho /* 2310459fc0f2SLuca Coelho * In some rare cases when the HW is in a bad state, we may 2311459fc0f2SLuca Coelho * get this interrupt too early, when prph_info is still NULL. 2312459fc0f2SLuca Coelho * So make sure that it's not NULL to prevent crashing. 2313459fc0f2SLuca Coelho */ 2314459fc0f2SLuca Coelho if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP && trans_pcie->prph_info) { 2315e5f3f215SHaim Dreyfuss u32 sleep_notif = 2316e5f3f215SHaim Dreyfuss le32_to_cpu(trans_pcie->prph_info->sleep_notif); 2317e5f3f215SHaim Dreyfuss if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND || 2318e5f3f215SHaim Dreyfuss sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) { 2319e5f3f215SHaim Dreyfuss IWL_DEBUG_ISR(trans, 2320e5f3f215SHaim Dreyfuss "Sx interrupt: sleep notification = 0x%x\n", 2321e5f3f215SHaim Dreyfuss sleep_notif); 2322e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = true; 2323e5f3f215SHaim Dreyfuss wake_up(&trans_pcie->sx_waitq); 2324e5f3f215SHaim Dreyfuss } else { 23252e5d4a8fSHaim Dreyfuss /* uCode wakes up after power-down sleep */ 23262e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 23272e5d4a8fSHaim Dreyfuss iwl_pcie_rxq_check_wrptr(trans); 23282e5d4a8fSHaim Dreyfuss iwl_pcie_txq_check_wrptrs(trans); 23292e5d4a8fSHaim Dreyfuss 23302e5d4a8fSHaim Dreyfuss isr_stats->wakeup++; 23312e5d4a8fSHaim Dreyfuss } 2332e5f3f215SHaim Dreyfuss } 23332e5d4a8fSHaim Dreyfuss 23342e5d4a8fSHaim Dreyfuss /* Chip got too hot and stopped itself */ 23352e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 23362e5d4a8fSHaim Dreyfuss IWL_ERR(trans, "Microcode CT kill error detected.\n"); 23372e5d4a8fSHaim Dreyfuss isr_stats->ctkill++; 23382e5d4a8fSHaim Dreyfuss } 23392e5d4a8fSHaim Dreyfuss 23402e5d4a8fSHaim Dreyfuss /* HW RF KILL switch toggled */ 23413a6e168bSJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 23423a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 23432e5d4a8fSHaim Dreyfuss 23442e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 23452e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 23462e5d4a8fSHaim Dreyfuss "Hardware error detected. Restarting.\n"); 23472e5d4a8fSHaim Dreyfuss 23482e5d4a8fSHaim Dreyfuss isr_stats->hw++; 234991c28b83SShahar S Matityahu trans->dbg.hw_error = true; 23502e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 23512e5d4a8fSHaim Dreyfuss } 23522e5d4a8fSHaim Dreyfuss 2353906d4eb8SJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE) { 2354906d4eb8SJohannes Berg IWL_DEBUG_ISR(trans, "Reset flow completed\n"); 2355e63aafeaSJohannes Berg trans_pcie->fw_reset_state = FW_RESET_OK; 2356906d4eb8SJohannes Berg wake_up(&trans_pcie->fw_reset_waitq); 2357906d4eb8SJohannes Berg } 2358906d4eb8SJohannes Berg 235925edc8f2SJohannes Berg if (!polling) 236025edc8f2SJohannes Berg iwl_pcie_clear_irq(trans, entry->entry); 23612e5d4a8fSHaim Dreyfuss 23622e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 23632e5d4a8fSHaim Dreyfuss 23642e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 23652e5d4a8fSHaim Dreyfuss } 2366