1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 4e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5bce97731SSara Sharon * Copyright(c) 2016 Intel Deutschland GmbH 6e705c121SKalle Valo * 7e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 8e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 9e705c121SKalle Valo * 10e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 11e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 12e705c121SKalle Valo * published by the Free Software Foundation. 13e705c121SKalle Valo * 14e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 15e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17e705c121SKalle Valo * more details. 18e705c121SKalle Valo * 19e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 20e705c121SKalle Valo * this program; if not, write to the Free Software Foundation, Inc., 21e705c121SKalle Valo * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 22e705c121SKalle Valo * 23e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 24e705c121SKalle Valo * file called LICENSE. 25e705c121SKalle Valo * 26e705c121SKalle Valo * Contact Information: 27d01c5366SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 28e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29e705c121SKalle Valo * 30e705c121SKalle Valo *****************************************************************************/ 31e705c121SKalle Valo #include <linux/sched.h> 32e705c121SKalle Valo #include <linux/wait.h> 33e705c121SKalle Valo #include <linux/gfp.h> 34e705c121SKalle Valo 35e705c121SKalle Valo #include "iwl-prph.h" 36e705c121SKalle Valo #include "iwl-io.h" 37e705c121SKalle Valo #include "internal.h" 38e705c121SKalle Valo #include "iwl-op-mode.h" 39e705c121SKalle Valo 40e705c121SKalle Valo /****************************************************************************** 41e705c121SKalle Valo * 42e705c121SKalle Valo * RX path functions 43e705c121SKalle Valo * 44e705c121SKalle Valo ******************************************************************************/ 45e705c121SKalle Valo 46e705c121SKalle Valo /* 47e705c121SKalle Valo * Rx theory of operation 48e705c121SKalle Valo * 49e705c121SKalle Valo * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 50e705c121SKalle Valo * each of which point to Receive Buffers to be filled by the NIC. These get 51e705c121SKalle Valo * used not only for Rx frames, but for any command response or notification 52e705c121SKalle Valo * from the NIC. The driver and NIC manage the Rx buffers by means 53e705c121SKalle Valo * of indexes into the circular buffer. 54e705c121SKalle Valo * 55e705c121SKalle Valo * Rx Queue Indexes 56e705c121SKalle Valo * The host/firmware share two index registers for managing the Rx buffers. 57e705c121SKalle Valo * 58e705c121SKalle Valo * The READ index maps to the first position that the firmware may be writing 59e705c121SKalle Valo * to -- the driver can read up to (but not including) this position and get 60e705c121SKalle Valo * good data. 61e705c121SKalle Valo * The READ index is managed by the firmware once the card is enabled. 62e705c121SKalle Valo * 63e705c121SKalle Valo * The WRITE index maps to the last position the driver has read from -- the 64e705c121SKalle Valo * position preceding WRITE is the last slot the firmware can place a packet. 65e705c121SKalle Valo * 66e705c121SKalle Valo * The queue is empty (no good data) if WRITE = READ - 1, and is full if 67e705c121SKalle Valo * WRITE = READ. 68e705c121SKalle Valo * 69e705c121SKalle Valo * During initialization, the host sets up the READ queue position to the first 70e705c121SKalle Valo * INDEX position, and WRITE to the last (READ - 1 wrapped) 71e705c121SKalle Valo * 72e705c121SKalle Valo * When the firmware places a packet in a buffer, it will advance the READ index 73e705c121SKalle Valo * and fire the RX interrupt. The driver can then query the READ index and 74e705c121SKalle Valo * process as many packets as possible, moving the WRITE index forward as it 75e705c121SKalle Valo * resets the Rx queue buffers with new memory. 76e705c121SKalle Valo * 77e705c121SKalle Valo * The management in the driver is as follows: 78e705c121SKalle Valo * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 79e705c121SKalle Valo * When the interrupt handler is called, the request is processed. 80e705c121SKalle Valo * The page is either stolen - transferred to the upper layer 81e705c121SKalle Valo * or reused - added immediately to the iwl->rxq->rx_free list. 82e705c121SKalle Valo * + When the page is stolen - the driver updates the matching queue's used 83e705c121SKalle Valo * count, detaches the RBD and transfers it to the queue used list. 84e705c121SKalle Valo * When there are two used RBDs - they are transferred to the allocator empty 85e705c121SKalle Valo * list. Work is then scheduled for the allocator to start allocating 86e705c121SKalle Valo * eight buffers. 87e705c121SKalle Valo * When there are another 6 used RBDs - they are transferred to the allocator 88e705c121SKalle Valo * empty list and the driver tries to claim the pre-allocated buffers and 89e705c121SKalle Valo * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 90e705c121SKalle Valo * until ready. 91e705c121SKalle Valo * When there are 8+ buffers in the free list - either from allocation or from 92e705c121SKalle Valo * 8 reused unstolen pages - restock is called to update the FW and indexes. 93e705c121SKalle Valo * + In order to make sure the allocator always has RBDs to use for allocation 94e705c121SKalle Valo * the allocator has initial pool in the size of num_queues*(8-2) - the 95e705c121SKalle Valo * maximum missing RBDs per allocation request (request posted with 2 96e705c121SKalle Valo * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 97e705c121SKalle Valo * The queues supplies the recycle of the rest of the RBDs. 98e705c121SKalle Valo * + A received packet is processed and handed to the kernel network stack, 99e705c121SKalle Valo * detached from the iwl->rxq. The driver 'processed' index is updated. 100e705c121SKalle Valo * + If there are no allocated buffers in iwl->rxq->rx_free, 101e705c121SKalle Valo * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 102e705c121SKalle Valo * If there were enough free buffers and RX_STALLED is set it is cleared. 103e705c121SKalle Valo * 104e705c121SKalle Valo * 105e705c121SKalle Valo * Driver sequence: 106e705c121SKalle Valo * 107e705c121SKalle Valo * iwl_rxq_alloc() Allocates rx_free 108e705c121SKalle Valo * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 109e705c121SKalle Valo * iwl_pcie_rxq_restock. 110e705c121SKalle Valo * Used only during initialization. 111e705c121SKalle Valo * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 112e705c121SKalle Valo * queue, updates firmware pointers, and updates 113e705c121SKalle Valo * the WRITE index. 114e705c121SKalle Valo * iwl_pcie_rx_allocator() Background work for allocating pages. 115e705c121SKalle Valo * 116e705c121SKalle Valo * -- enable interrupts -- 117e705c121SKalle Valo * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 118e705c121SKalle Valo * READ INDEX, detaching the SKB from the pool. 119e705c121SKalle Valo * Moves the packet buffer from queue to rx_used. 120e705c121SKalle Valo * Posts and claims requests to the allocator. 121e705c121SKalle Valo * Calls iwl_pcie_rxq_restock to refill any empty 122e705c121SKalle Valo * slots. 123e705c121SKalle Valo * 124e705c121SKalle Valo * RBD life-cycle: 125e705c121SKalle Valo * 126e705c121SKalle Valo * Init: 127e705c121SKalle Valo * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 128e705c121SKalle Valo * 129e705c121SKalle Valo * Regular Receive interrupt: 130e705c121SKalle Valo * Page Stolen: 131e705c121SKalle Valo * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 132e705c121SKalle Valo * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 133e705c121SKalle Valo * Page not Stolen: 134e705c121SKalle Valo * rxq.queue -> rxq.rx_free -> rxq.queue 135e705c121SKalle Valo * ... 136e705c121SKalle Valo * 137e705c121SKalle Valo */ 138e705c121SKalle Valo 139e705c121SKalle Valo /* 140e705c121SKalle Valo * iwl_rxq_space - Return number of free slots available in queue. 141e705c121SKalle Valo */ 142e705c121SKalle Valo static int iwl_rxq_space(const struct iwl_rxq *rxq) 143e705c121SKalle Valo { 14496a6497bSSara Sharon /* Make sure rx queue size is a power of 2 */ 14596a6497bSSara Sharon WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 146e705c121SKalle Valo 147e705c121SKalle Valo /* 148e705c121SKalle Valo * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 149e705c121SKalle Valo * between empty and completely full queues. 150e705c121SKalle Valo * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 151e705c121SKalle Valo * defined for negative dividends. 152e705c121SKalle Valo */ 15396a6497bSSara Sharon return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 154e705c121SKalle Valo } 155e705c121SKalle Valo 156e705c121SKalle Valo /* 157e705c121SKalle Valo * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 158e705c121SKalle Valo */ 159e705c121SKalle Valo static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 160e705c121SKalle Valo { 161e705c121SKalle Valo return cpu_to_le32((u32)(dma_addr >> 8)); 162e705c121SKalle Valo } 163e705c121SKalle Valo 16496a6497bSSara Sharon static void iwl_pcie_write_prph_64(struct iwl_trans *trans, u64 ofs, u64 val) 16596a6497bSSara Sharon { 16696a6497bSSara Sharon iwl_write_prph(trans, ofs, val & 0xffffffff); 16796a6497bSSara Sharon iwl_write_prph(trans, ofs + 4, val >> 32); 16896a6497bSSara Sharon } 16996a6497bSSara Sharon 170e705c121SKalle Valo /* 171e705c121SKalle Valo * iwl_pcie_rx_stop - stops the Rx DMA 172e705c121SKalle Valo */ 173e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans) 174e705c121SKalle Valo { 175e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 176e705c121SKalle Valo return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 177e705c121SKalle Valo FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); 178e705c121SKalle Valo } 179e705c121SKalle Valo 180e705c121SKalle Valo /* 181e705c121SKalle Valo * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 182e705c121SKalle Valo */ 18378485054SSara Sharon static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 18478485054SSara Sharon struct iwl_rxq *rxq) 185e705c121SKalle Valo { 186e705c121SKalle Valo u32 reg; 187e705c121SKalle Valo 188e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 189e705c121SKalle Valo 190e705c121SKalle Valo /* 191e705c121SKalle Valo * explicitly wake up the NIC if: 192e705c121SKalle Valo * 1. shadow registers aren't enabled 193e705c121SKalle Valo * 2. there is a chance that the NIC is asleep 194e705c121SKalle Valo */ 195e705c121SKalle Valo if (!trans->cfg->base_params->shadow_reg_enable && 196e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 197e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 198e705c121SKalle Valo 199e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 200e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 201e705c121SKalle Valo reg); 202e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 203e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 204e705c121SKalle Valo rxq->need_update = true; 205e705c121SKalle Valo return; 206e705c121SKalle Valo } 207e705c121SKalle Valo } 208e705c121SKalle Valo 209e705c121SKalle Valo rxq->write_actual = round_down(rxq->write, 8); 21096a6497bSSara Sharon if (trans->cfg->mq_rx_supported) 21196a6497bSSara Sharon iwl_write_prph(trans, RFH_Q_FRBDCB_WIDX(rxq->id), 21296a6497bSSara Sharon rxq->write_actual); 21396a6497bSSara Sharon else 214e705c121SKalle Valo iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 215e705c121SKalle Valo } 216e705c121SKalle Valo 217e705c121SKalle Valo static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 218e705c121SKalle Valo { 219e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 22078485054SSara Sharon int i; 221e705c121SKalle Valo 22278485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 22378485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 224e705c121SKalle Valo 225e705c121SKalle Valo if (!rxq->need_update) 22678485054SSara Sharon continue; 22778485054SSara Sharon spin_lock(&rxq->lock); 22878485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 229e705c121SKalle Valo rxq->need_update = false; 230e705c121SKalle Valo spin_unlock(&rxq->lock); 231e705c121SKalle Valo } 23278485054SSara Sharon } 233e705c121SKalle Valo 23496a6497bSSara Sharon static void iwl_pcie_rxq_mq_restock(struct iwl_trans *trans, 23596a6497bSSara Sharon struct iwl_rxq *rxq) 23696a6497bSSara Sharon { 23796a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb; 23896a6497bSSara Sharon 23996a6497bSSara Sharon /* 24096a6497bSSara Sharon * If the device isn't enabled - no need to try to add buffers... 24196a6497bSSara Sharon * This can happen when we stop the device and still have an interrupt 24296a6497bSSara Sharon * pending. We stop the APM before we sync the interrupts because we 24396a6497bSSara Sharon * have to (see comment there). On the other hand, since the APM is 24496a6497bSSara Sharon * stopped, we cannot access the HW (in particular not prph). 24596a6497bSSara Sharon * So don't try to restock if the APM has been already stopped. 24696a6497bSSara Sharon */ 24796a6497bSSara Sharon if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 24896a6497bSSara Sharon return; 24996a6497bSSara Sharon 25096a6497bSSara Sharon spin_lock(&rxq->lock); 25196a6497bSSara Sharon while (rxq->free_count) { 25296a6497bSSara Sharon __le64 *bd = (__le64 *)rxq->bd; 25396a6497bSSara Sharon 25496a6497bSSara Sharon /* Get next free Rx buffer, remove from free list */ 25596a6497bSSara Sharon rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 25696a6497bSSara Sharon list); 25796a6497bSSara Sharon list_del(&rxb->list); 25896a6497bSSara Sharon 25996a6497bSSara Sharon /* 12 first bits are expected to be empty */ 26096a6497bSSara Sharon WARN_ON(rxb->page_dma & DMA_BIT_MASK(12)); 26196a6497bSSara Sharon /* Point to Rx buffer via next RBD in circular buffer */ 26296a6497bSSara Sharon bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 26396a6497bSSara Sharon rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK; 26496a6497bSSara Sharon rxq->free_count--; 26596a6497bSSara Sharon } 26696a6497bSSara Sharon spin_unlock(&rxq->lock); 26796a6497bSSara Sharon 26896a6497bSSara Sharon /* 26996a6497bSSara Sharon * If we've added more space for the firmware to place data, tell it. 27096a6497bSSara Sharon * Increment device's write pointer in multiples of 8. 27196a6497bSSara Sharon */ 27296a6497bSSara Sharon if (rxq->write_actual != (rxq->write & ~0x7)) { 27396a6497bSSara Sharon spin_lock(&rxq->lock); 27496a6497bSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 27596a6497bSSara Sharon spin_unlock(&rxq->lock); 27696a6497bSSara Sharon } 27796a6497bSSara Sharon } 27896a6497bSSara Sharon 279e705c121SKalle Valo /* 280e705c121SKalle Valo * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 281e705c121SKalle Valo * 282e705c121SKalle Valo * If there are slots in the RX queue that need to be restocked, 283e705c121SKalle Valo * and we have free pre-allocated buffers, fill the ranks as much 284e705c121SKalle Valo * as we can, pulling from rx_free. 285e705c121SKalle Valo * 286e705c121SKalle Valo * This moves the 'write' index forward to catch up with 'processed', and 287e705c121SKalle Valo * also updates the memory address in the firmware to reference the new 288e705c121SKalle Valo * target buffer. 289e705c121SKalle Valo */ 29078485054SSara Sharon static void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 291e705c121SKalle Valo { 292e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 293e705c121SKalle Valo 294e705c121SKalle Valo /* 295e705c121SKalle Valo * If the device isn't enabled - not need to try to add buffers... 296e705c121SKalle Valo * This can happen when we stop the device and still have an interrupt 297e705c121SKalle Valo * pending. We stop the APM before we sync the interrupts because we 298e705c121SKalle Valo * have to (see comment there). On the other hand, since the APM is 299e705c121SKalle Valo * stopped, we cannot access the HW (in particular not prph). 300e705c121SKalle Valo * So don't try to restock if the APM has been already stopped. 301e705c121SKalle Valo */ 302e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 303e705c121SKalle Valo return; 304e705c121SKalle Valo 305e705c121SKalle Valo spin_lock(&rxq->lock); 306e705c121SKalle Valo while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 30796a6497bSSara Sharon __le32 *bd = (__le32 *)rxq->bd; 308e705c121SKalle Valo /* The overwritten rxb must be a used one */ 309e705c121SKalle Valo rxb = rxq->queue[rxq->write]; 310e705c121SKalle Valo BUG_ON(rxb && rxb->page); 311e705c121SKalle Valo 312e705c121SKalle Valo /* Get next free Rx buffer, remove from free list */ 313e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 314e705c121SKalle Valo list); 315e705c121SKalle Valo list_del(&rxb->list); 316e705c121SKalle Valo 317e705c121SKalle Valo /* Point to Rx buffer via next RBD in circular buffer */ 31896a6497bSSara Sharon bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 319e705c121SKalle Valo rxq->queue[rxq->write] = rxb; 320e705c121SKalle Valo rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 321e705c121SKalle Valo rxq->free_count--; 322e705c121SKalle Valo } 323e705c121SKalle Valo spin_unlock(&rxq->lock); 324e705c121SKalle Valo 325e705c121SKalle Valo /* If we've added more space for the firmware to place data, tell it. 326e705c121SKalle Valo * Increment device's write pointer in multiples of 8. */ 327e705c121SKalle Valo if (rxq->write_actual != (rxq->write & ~0x7)) { 328e705c121SKalle Valo spin_lock(&rxq->lock); 32978485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 330e705c121SKalle Valo spin_unlock(&rxq->lock); 331e705c121SKalle Valo } 332e705c121SKalle Valo } 333e705c121SKalle Valo 334e705c121SKalle Valo /* 335e705c121SKalle Valo * iwl_pcie_rx_alloc_page - allocates and returns a page. 336e705c121SKalle Valo * 337e705c121SKalle Valo */ 338e705c121SKalle Valo static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 339e705c121SKalle Valo gfp_t priority) 340e705c121SKalle Valo { 341e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 342e705c121SKalle Valo struct page *page; 343e705c121SKalle Valo gfp_t gfp_mask = priority; 344e705c121SKalle Valo 345e705c121SKalle Valo if (trans_pcie->rx_page_order > 0) 346e705c121SKalle Valo gfp_mask |= __GFP_COMP; 347e705c121SKalle Valo 348e705c121SKalle Valo /* Alloc a new receive buffer */ 349e705c121SKalle Valo page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 350e705c121SKalle Valo if (!page) { 351e705c121SKalle Valo if (net_ratelimit()) 352e705c121SKalle Valo IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 353e705c121SKalle Valo trans_pcie->rx_page_order); 35478485054SSara Sharon /* 35578485054SSara Sharon * Issue an error if we don't have enough pre-allocated 35678485054SSara Sharon * buffers. 357e705c121SKalle Valo ` */ 35878485054SSara Sharon if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 359e705c121SKalle Valo IWL_CRIT(trans, 36078485054SSara Sharon "Failed to alloc_pages\n"); 361e705c121SKalle Valo return NULL; 362e705c121SKalle Valo } 363e705c121SKalle Valo return page; 364e705c121SKalle Valo } 365e705c121SKalle Valo 366e705c121SKalle Valo /* 367e705c121SKalle Valo * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 368e705c121SKalle Valo * 369e705c121SKalle Valo * A used RBD is an Rx buffer that has been given to the stack. To use it again 370e705c121SKalle Valo * a page must be allocated and the RBD must point to the page. This function 371e705c121SKalle Valo * doesn't change the HW pointer but handles the list of pages that is used by 372e705c121SKalle Valo * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 373e705c121SKalle Valo * allocated buffers. 374e705c121SKalle Valo */ 37578485054SSara Sharon static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 37678485054SSara Sharon struct iwl_rxq *rxq) 377e705c121SKalle Valo { 378e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 379e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 380e705c121SKalle Valo struct page *page; 381e705c121SKalle Valo 382e705c121SKalle Valo while (1) { 383e705c121SKalle Valo spin_lock(&rxq->lock); 384e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 385e705c121SKalle Valo spin_unlock(&rxq->lock); 386e705c121SKalle Valo return; 387e705c121SKalle Valo } 388e705c121SKalle Valo spin_unlock(&rxq->lock); 389e705c121SKalle Valo 390e705c121SKalle Valo /* Alloc a new receive buffer */ 391e705c121SKalle Valo page = iwl_pcie_rx_alloc_page(trans, priority); 392e705c121SKalle Valo if (!page) 393e705c121SKalle Valo return; 394e705c121SKalle Valo 395e705c121SKalle Valo spin_lock(&rxq->lock); 396e705c121SKalle Valo 397e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 398e705c121SKalle Valo spin_unlock(&rxq->lock); 399e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 400e705c121SKalle Valo return; 401e705c121SKalle Valo } 402e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 403e705c121SKalle Valo list); 404e705c121SKalle Valo list_del(&rxb->list); 405e705c121SKalle Valo spin_unlock(&rxq->lock); 406e705c121SKalle Valo 407e705c121SKalle Valo BUG_ON(rxb->page); 408e705c121SKalle Valo rxb->page = page; 409e705c121SKalle Valo /* Get physical address of the RB */ 410e705c121SKalle Valo rxb->page_dma = 411e705c121SKalle Valo dma_map_page(trans->dev, page, 0, 412e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 413e705c121SKalle Valo DMA_FROM_DEVICE); 414e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 415e705c121SKalle Valo rxb->page = NULL; 416e705c121SKalle Valo spin_lock(&rxq->lock); 417e705c121SKalle Valo list_add(&rxb->list, &rxq->rx_used); 418e705c121SKalle Valo spin_unlock(&rxq->lock); 419e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 420e705c121SKalle Valo return; 421e705c121SKalle Valo } 422e705c121SKalle Valo 423e705c121SKalle Valo spin_lock(&rxq->lock); 424e705c121SKalle Valo 425e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 426e705c121SKalle Valo rxq->free_count++; 427e705c121SKalle Valo 428e705c121SKalle Valo spin_unlock(&rxq->lock); 429e705c121SKalle Valo } 430e705c121SKalle Valo } 431e705c121SKalle Valo 43278485054SSara Sharon static void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 433e705c121SKalle Valo { 434e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 435e705c121SKalle Valo int i; 436e705c121SKalle Valo 43796a6497bSSara Sharon for (i = 0; i < MQ_RX_POOL_SIZE; i++) { 43878485054SSara Sharon if (!trans_pcie->rx_pool[i].page) 439e705c121SKalle Valo continue; 44078485054SSara Sharon dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 441e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 442e705c121SKalle Valo DMA_FROM_DEVICE); 44378485054SSara Sharon __free_pages(trans_pcie->rx_pool[i].page, 44478485054SSara Sharon trans_pcie->rx_page_order); 44578485054SSara Sharon trans_pcie->rx_pool[i].page = NULL; 446e705c121SKalle Valo } 447e705c121SKalle Valo } 448e705c121SKalle Valo 449e705c121SKalle Valo /* 450e705c121SKalle Valo * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 451e705c121SKalle Valo * 452e705c121SKalle Valo * Allocates for each received request 8 pages 453e705c121SKalle Valo * Called as a scheduled work item. 454e705c121SKalle Valo */ 455e705c121SKalle Valo static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 456e705c121SKalle Valo { 457e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 458e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 459e705c121SKalle Valo struct list_head local_empty; 460e705c121SKalle Valo int pending = atomic_xchg(&rba->req_pending, 0); 461e705c121SKalle Valo 462e705c121SKalle Valo IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending); 463e705c121SKalle Valo 464e705c121SKalle Valo /* If we were scheduled - there is at least one request */ 465e705c121SKalle Valo spin_lock(&rba->lock); 466e705c121SKalle Valo /* swap out the rba->rbd_empty to a local list */ 467e705c121SKalle Valo list_replace_init(&rba->rbd_empty, &local_empty); 468e705c121SKalle Valo spin_unlock(&rba->lock); 469e705c121SKalle Valo 470e705c121SKalle Valo while (pending) { 471e705c121SKalle Valo int i; 472e705c121SKalle Valo struct list_head local_allocated; 47378485054SSara Sharon gfp_t gfp_mask = GFP_KERNEL; 47478485054SSara Sharon 47578485054SSara Sharon /* Do not post a warning if there are only a few requests */ 47678485054SSara Sharon if (pending < RX_PENDING_WATERMARK) 47778485054SSara Sharon gfp_mask |= __GFP_NOWARN; 478e705c121SKalle Valo 479e705c121SKalle Valo INIT_LIST_HEAD(&local_allocated); 480e705c121SKalle Valo 481e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 482e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 483e705c121SKalle Valo struct page *page; 484e705c121SKalle Valo 485e705c121SKalle Valo /* List should never be empty - each reused RBD is 486e705c121SKalle Valo * returned to the list, and initial pool covers any 487e705c121SKalle Valo * possible gap between the time the page is allocated 488e705c121SKalle Valo * to the time the RBD is added. 489e705c121SKalle Valo */ 490e705c121SKalle Valo BUG_ON(list_empty(&local_empty)); 491e705c121SKalle Valo /* Get the first rxb from the rbd list */ 492e705c121SKalle Valo rxb = list_first_entry(&local_empty, 493e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 494e705c121SKalle Valo BUG_ON(rxb->page); 495e705c121SKalle Valo 496e705c121SKalle Valo /* Alloc a new receive buffer */ 49778485054SSara Sharon page = iwl_pcie_rx_alloc_page(trans, gfp_mask); 498e705c121SKalle Valo if (!page) 499e705c121SKalle Valo continue; 500e705c121SKalle Valo rxb->page = page; 501e705c121SKalle Valo 502e705c121SKalle Valo /* Get physical address of the RB */ 503e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, page, 0, 504e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 505e705c121SKalle Valo DMA_FROM_DEVICE); 506e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 507e705c121SKalle Valo rxb->page = NULL; 508e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 509e705c121SKalle Valo continue; 510e705c121SKalle Valo } 511e705c121SKalle Valo 512e705c121SKalle Valo /* move the allocated entry to the out list */ 513e705c121SKalle Valo list_move(&rxb->list, &local_allocated); 514e705c121SKalle Valo i++; 515e705c121SKalle Valo } 516e705c121SKalle Valo 517e705c121SKalle Valo pending--; 518e705c121SKalle Valo if (!pending) { 519e705c121SKalle Valo pending = atomic_xchg(&rba->req_pending, 0); 520e705c121SKalle Valo IWL_DEBUG_RX(trans, 521e705c121SKalle Valo "Pending allocation requests = %d\n", 522e705c121SKalle Valo pending); 523e705c121SKalle Valo } 524e705c121SKalle Valo 525e705c121SKalle Valo spin_lock(&rba->lock); 526e705c121SKalle Valo /* add the allocated rbds to the allocator allocated list */ 527e705c121SKalle Valo list_splice_tail(&local_allocated, &rba->rbd_allocated); 528e705c121SKalle Valo /* get more empty RBDs for current pending requests */ 529e705c121SKalle Valo list_splice_tail_init(&rba->rbd_empty, &local_empty); 530e705c121SKalle Valo spin_unlock(&rba->lock); 531e705c121SKalle Valo 532e705c121SKalle Valo atomic_inc(&rba->req_ready); 533e705c121SKalle Valo } 534e705c121SKalle Valo 535e705c121SKalle Valo spin_lock(&rba->lock); 536e705c121SKalle Valo /* return unused rbds to the allocator empty list */ 537e705c121SKalle Valo list_splice_tail(&local_empty, &rba->rbd_empty); 538e705c121SKalle Valo spin_unlock(&rba->lock); 539e705c121SKalle Valo } 540e705c121SKalle Valo 541e705c121SKalle Valo /* 542e705c121SKalle Valo * iwl_pcie_rx_allocator_get - Returns the pre-allocated pages 543e705c121SKalle Valo .* 544e705c121SKalle Valo .* Called by queue when the queue posted allocation request and 545e705c121SKalle Valo * has freed 8 RBDs in order to restock itself. 546e705c121SKalle Valo */ 547e705c121SKalle Valo static int iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 548e705c121SKalle Valo struct iwl_rx_mem_buffer 549e705c121SKalle Valo *out[RX_CLAIM_REQ_ALLOC]) 550e705c121SKalle Valo { 551e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 552e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 553e705c121SKalle Valo int i; 554e705c121SKalle Valo 555e705c121SKalle Valo /* 556e705c121SKalle Valo * atomic_dec_if_positive returns req_ready - 1 for any scenario. 557e705c121SKalle Valo * If req_ready is 0 atomic_dec_if_positive will return -1 and this 558e705c121SKalle Valo * function will return -ENOMEM, as there are no ready requests. 559e705c121SKalle Valo * atomic_dec_if_positive will perofrm the *actual* decrement only if 560e705c121SKalle Valo * req_ready > 0, i.e. - there are ready requests and the function 561e705c121SKalle Valo * hands one request to the caller. 562e705c121SKalle Valo */ 563e705c121SKalle Valo if (atomic_dec_if_positive(&rba->req_ready) < 0) 564e705c121SKalle Valo return -ENOMEM; 565e705c121SKalle Valo 566e705c121SKalle Valo spin_lock(&rba->lock); 567e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 568e705c121SKalle Valo /* Get next free Rx buffer, remove it from free list */ 569e705c121SKalle Valo out[i] = list_first_entry(&rba->rbd_allocated, 570e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 571e705c121SKalle Valo list_del(&out[i]->list); 572e705c121SKalle Valo } 573e705c121SKalle Valo spin_unlock(&rba->lock); 574e705c121SKalle Valo 575e705c121SKalle Valo return 0; 576e705c121SKalle Valo } 577e705c121SKalle Valo 578e705c121SKalle Valo static void iwl_pcie_rx_allocator_work(struct work_struct *data) 579e705c121SKalle Valo { 580e705c121SKalle Valo struct iwl_rb_allocator *rba_p = 581e705c121SKalle Valo container_of(data, struct iwl_rb_allocator, rx_alloc); 582e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 583e705c121SKalle Valo container_of(rba_p, struct iwl_trans_pcie, rba); 584e705c121SKalle Valo 585e705c121SKalle Valo iwl_pcie_rx_allocator(trans_pcie->trans); 586e705c121SKalle Valo } 587e705c121SKalle Valo 588e705c121SKalle Valo static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 589e705c121SKalle Valo { 590e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 591e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 592e705c121SKalle Valo struct device *dev = trans->dev; 59378485054SSara Sharon int i; 59496a6497bSSara Sharon int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) : 59596a6497bSSara Sharon sizeof(__le32); 596e705c121SKalle Valo 59778485054SSara Sharon if (WARN_ON(trans_pcie->rxq)) 598e705c121SKalle Valo return -EINVAL; 599e705c121SKalle Valo 60078485054SSara Sharon trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 60178485054SSara Sharon GFP_KERNEL); 60278485054SSara Sharon if (!trans_pcie->rxq) 60378485054SSara Sharon return -EINVAL; 60478485054SSara Sharon 60578485054SSara Sharon spin_lock_init(&rba->lock); 60678485054SSara Sharon 60778485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 60878485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 60978485054SSara Sharon 61078485054SSara Sharon spin_lock_init(&rxq->lock); 61196a6497bSSara Sharon if (trans->cfg->mq_rx_supported) 61296a6497bSSara Sharon rxq->queue_size = MQ_RX_TABLE_SIZE; 61396a6497bSSara Sharon else 61496a6497bSSara Sharon rxq->queue_size = RX_QUEUE_SIZE; 61596a6497bSSara Sharon 61678485054SSara Sharon /* 61778485054SSara Sharon * Allocate the circular buffer of Read Buffer Descriptors 61878485054SSara Sharon * (RBDs) 61978485054SSara Sharon */ 62078485054SSara Sharon rxq->bd = dma_zalloc_coherent(dev, 62196a6497bSSara Sharon free_size * rxq->queue_size, 622e705c121SKalle Valo &rxq->bd_dma, GFP_KERNEL); 623e705c121SKalle Valo if (!rxq->bd) 62478485054SSara Sharon goto err; 62578485054SSara Sharon 62696a6497bSSara Sharon if (trans->cfg->mq_rx_supported) { 62796a6497bSSara Sharon rxq->used_bd = dma_zalloc_coherent(dev, 62896a6497bSSara Sharon sizeof(__le32) * 62996a6497bSSara Sharon rxq->queue_size, 63096a6497bSSara Sharon &rxq->used_bd_dma, 63196a6497bSSara Sharon GFP_KERNEL); 63296a6497bSSara Sharon if (!rxq->used_bd) 63396a6497bSSara Sharon goto err; 63496a6497bSSara Sharon } 635e705c121SKalle Valo 636e705c121SKalle Valo /*Allocate the driver's pointer to receive buffer status */ 637e705c121SKalle Valo rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts), 63878485054SSara Sharon &rxq->rb_stts_dma, 63978485054SSara Sharon GFP_KERNEL); 640e705c121SKalle Valo if (!rxq->rb_stts) 64178485054SSara Sharon goto err; 64278485054SSara Sharon } 643e705c121SKalle Valo return 0; 644e705c121SKalle Valo 64578485054SSara Sharon err: 64678485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 64778485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 64878485054SSara Sharon 64978485054SSara Sharon if (rxq->bd) 65096a6497bSSara Sharon dma_free_coherent(dev, free_size * rxq->queue_size, 651e705c121SKalle Valo rxq->bd, rxq->bd_dma); 652e705c121SKalle Valo rxq->bd_dma = 0; 653e705c121SKalle Valo rxq->bd = NULL; 65478485054SSara Sharon 65578485054SSara Sharon if (rxq->rb_stts) 65678485054SSara Sharon dma_free_coherent(trans->dev, 65778485054SSara Sharon sizeof(struct iwl_rb_status), 65878485054SSara Sharon rxq->rb_stts, rxq->rb_stts_dma); 65996a6497bSSara Sharon 66096a6497bSSara Sharon if (rxq->used_bd) 66196a6497bSSara Sharon dma_free_coherent(dev, sizeof(__le32) * rxq->queue_size, 66296a6497bSSara Sharon rxq->used_bd, rxq->used_bd_dma); 66396a6497bSSara Sharon rxq->used_bd_dma = 0; 66496a6497bSSara Sharon rxq->used_bd = NULL; 66578485054SSara Sharon } 66678485054SSara Sharon kfree(trans_pcie->rxq); 66796a6497bSSara Sharon 668e705c121SKalle Valo return -ENOMEM; 669e705c121SKalle Valo } 670e705c121SKalle Valo 671e705c121SKalle Valo static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 672e705c121SKalle Valo { 673e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 674e705c121SKalle Valo u32 rb_size; 675e705c121SKalle Valo const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 676e705c121SKalle Valo 6776c4fbcbcSEmmanuel Grumbach switch (trans_pcie->rx_buf_size) { 6786c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 679e705c121SKalle Valo rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 6806c4fbcbcSEmmanuel Grumbach break; 6816c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 6826c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 6836c4fbcbcSEmmanuel Grumbach break; 6846c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 6856c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 6866c4fbcbcSEmmanuel Grumbach break; 6876c4fbcbcSEmmanuel Grumbach default: 6886c4fbcbcSEmmanuel Grumbach WARN_ON(1); 6896c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 6906c4fbcbcSEmmanuel Grumbach } 691e705c121SKalle Valo 692e705c121SKalle Valo /* Stop Rx DMA */ 693e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 694e705c121SKalle Valo /* reset and flush pointers */ 695e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 696e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 697e705c121SKalle Valo iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 698e705c121SKalle Valo 699e705c121SKalle Valo /* Reset driver's Rx queue write index */ 700e705c121SKalle Valo iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 701e705c121SKalle Valo 702e705c121SKalle Valo /* Tell device where to find RBD circular buffer in DRAM */ 703e705c121SKalle Valo iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 704e705c121SKalle Valo (u32)(rxq->bd_dma >> 8)); 705e705c121SKalle Valo 706e705c121SKalle Valo /* Tell device where in DRAM to update its Rx status */ 707e705c121SKalle Valo iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 708e705c121SKalle Valo rxq->rb_stts_dma >> 4); 709e705c121SKalle Valo 710e705c121SKalle Valo /* Enable Rx DMA 711e705c121SKalle Valo * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 712e705c121SKalle Valo * the credit mechanism in 5000 HW RX FIFO 713e705c121SKalle Valo * Direct rx interrupts to hosts 7146c4fbcbcSEmmanuel Grumbach * Rx buffer size 4 or 8k or 12k 715e705c121SKalle Valo * RB timeout 0x10 716e705c121SKalle Valo * 256 RBDs 717e705c121SKalle Valo */ 718e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 719e705c121SKalle Valo FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 720e705c121SKalle Valo FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 721e705c121SKalle Valo FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 722e705c121SKalle Valo rb_size| 723e705c121SKalle Valo (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| 724e705c121SKalle Valo (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 725e705c121SKalle Valo 726e705c121SKalle Valo /* Set interrupt coalescing timer to default (2048 usecs) */ 727e705c121SKalle Valo iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 728e705c121SKalle Valo 729e705c121SKalle Valo /* W/A for interrupt coalescing bug in 7260 and 3160 */ 730e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) 731e705c121SKalle Valo iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 732e705c121SKalle Valo } 733e705c121SKalle Valo 734bce97731SSara Sharon static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 73596a6497bSSara Sharon { 73696a6497bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 73796a6497bSSara Sharon u32 rb_size, enabled = 0; 73896a6497bSSara Sharon int i; 73996a6497bSSara Sharon 74096a6497bSSara Sharon switch (trans_pcie->rx_buf_size) { 74196a6497bSSara Sharon case IWL_AMSDU_4K: 74296a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 74396a6497bSSara Sharon break; 74496a6497bSSara Sharon case IWL_AMSDU_8K: 74596a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_8K; 74696a6497bSSara Sharon break; 74796a6497bSSara Sharon case IWL_AMSDU_12K: 74896a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_12K; 74996a6497bSSara Sharon break; 75096a6497bSSara Sharon default: 75196a6497bSSara Sharon WARN_ON(1); 75296a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 75396a6497bSSara Sharon } 75496a6497bSSara Sharon 75596a6497bSSara Sharon /* Stop Rx DMA */ 75696a6497bSSara Sharon iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 75796a6497bSSara Sharon /* disable free amd used rx queue operation */ 75896a6497bSSara Sharon iwl_write_prph(trans, RFH_RXF_RXQ_ACTIVE, 0); 75996a6497bSSara Sharon 76096a6497bSSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 76196a6497bSSara Sharon /* Tell device where to find RBD free table in DRAM */ 76296a6497bSSara Sharon iwl_pcie_write_prph_64(trans, RFH_Q_FRBDCB_BA_LSB(i), 763bce97731SSara Sharon (u64)(trans_pcie->rxq[i].bd_dma)); 76496a6497bSSara Sharon /* Tell device where to find RBD used table in DRAM */ 76596a6497bSSara Sharon iwl_pcie_write_prph_64(trans, RFH_Q_URBDCB_BA_LSB(i), 766bce97731SSara Sharon (u64)(trans_pcie->rxq[i].used_bd_dma)); 76796a6497bSSara Sharon /* Tell device where in DRAM to update its Rx status */ 76896a6497bSSara Sharon iwl_pcie_write_prph_64(trans, RFH_Q_URBD_STTS_WPTR_LSB(i), 769bce97731SSara Sharon trans_pcie->rxq[i].rb_stts_dma); 77096a6497bSSara Sharon /* Reset device indice tables */ 77196a6497bSSara Sharon iwl_write_prph(trans, RFH_Q_FRBDCB_WIDX(i), 0); 77296a6497bSSara Sharon iwl_write_prph(trans, RFH_Q_FRBDCB_RIDX(i), 0); 77396a6497bSSara Sharon iwl_write_prph(trans, RFH_Q_URBDCB_WIDX(i), 0); 77496a6497bSSara Sharon 77596a6497bSSara Sharon enabled |= BIT(i) | BIT(i + 16); 77696a6497bSSara Sharon } 77796a6497bSSara Sharon 77896a6497bSSara Sharon /* restock default queue */ 77996a6497bSSara Sharon iwl_pcie_rxq_mq_restock(trans, &trans_pcie->rxq[0]); 78096a6497bSSara Sharon 78196a6497bSSara Sharon /* 78296a6497bSSara Sharon * Enable Rx DMA 78396a6497bSSara Sharon * Single frame mode 78496a6497bSSara Sharon * Rx buffer size 4 or 8k or 12k 78596a6497bSSara Sharon * Min RB size 4 or 8 78696a6497bSSara Sharon * 512 RBDs 78796a6497bSSara Sharon */ 78896a6497bSSara Sharon iwl_write_prph(trans, RFH_RXF_DMA_CFG, 78996a6497bSSara Sharon RFH_DMA_EN_ENABLE_VAL | 79096a6497bSSara Sharon rb_size | RFH_RXF_DMA_SINGLE_FRAME_MASK | 79196a6497bSSara Sharon RFH_RXF_DMA_MIN_RB_4_8 | 79296a6497bSSara Sharon RFH_RXF_DMA_RBDCB_SIZE_512); 79396a6497bSSara Sharon 79496a6497bSSara Sharon iwl_write_prph(trans, RFH_GEN_CFG, RFH_GEN_CFG_RFH_DMA_SNOOP | 79596a6497bSSara Sharon RFH_GEN_CFG_SERVICE_DMA_SNOOP); 79696a6497bSSara Sharon iwl_write_prph(trans, RFH_RXF_RXQ_ACTIVE, enabled); 79796a6497bSSara Sharon 79896a6497bSSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 79996a6497bSSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 80096a6497bSSara Sharon } 80196a6497bSSara Sharon 802e705c121SKalle Valo static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 803e705c121SKalle Valo { 804e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 805e705c121SKalle Valo 806e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_free); 807e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_used); 808e705c121SKalle Valo rxq->free_count = 0; 809e705c121SKalle Valo rxq->used_count = 0; 810e705c121SKalle Valo } 811e705c121SKalle Valo 812bce97731SSara Sharon static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) 813bce97731SSara Sharon { 814bce97731SSara Sharon WARN_ON(1); 815bce97731SSara Sharon return 0; 816bce97731SSara Sharon } 817bce97731SSara Sharon 818e705c121SKalle Valo int iwl_pcie_rx_init(struct iwl_trans *trans) 819e705c121SKalle Valo { 820e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 82178485054SSara Sharon struct iwl_rxq *def_rxq; 822e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 82396a6497bSSara Sharon int i, err, num_rbds, allocator_pool_size; 824e705c121SKalle Valo 82578485054SSara Sharon if (!trans_pcie->rxq) { 826e705c121SKalle Valo err = iwl_pcie_rx_alloc(trans); 827e705c121SKalle Valo if (err) 828e705c121SKalle Valo return err; 829e705c121SKalle Valo } 83078485054SSara Sharon def_rxq = trans_pcie->rxq; 831e705c121SKalle Valo if (!rba->alloc_wq) 832e705c121SKalle Valo rba->alloc_wq = alloc_workqueue("rb_allocator", 833e705c121SKalle Valo WQ_HIGHPRI | WQ_UNBOUND, 1); 834e705c121SKalle Valo INIT_WORK(&rba->rx_alloc, iwl_pcie_rx_allocator_work); 835e705c121SKalle Valo 836e705c121SKalle Valo spin_lock(&rba->lock); 837e705c121SKalle Valo atomic_set(&rba->req_pending, 0); 838e705c121SKalle Valo atomic_set(&rba->req_ready, 0); 83996a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_allocated); 84096a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_empty); 841e705c121SKalle Valo spin_unlock(&rba->lock); 842e705c121SKalle Valo 843e705c121SKalle Valo /* free all first - we might be reconfigured for a different size */ 84478485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 845e705c121SKalle Valo 846e705c121SKalle Valo for (i = 0; i < RX_QUEUE_SIZE; i++) 84778485054SSara Sharon def_rxq->queue[i] = NULL; 848e705c121SKalle Valo 84978485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 85078485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 851e705c121SKalle Valo 85296a6497bSSara Sharon rxq->id = i; 85396a6497bSSara Sharon 854e705c121SKalle Valo spin_lock(&rxq->lock); 85578485054SSara Sharon /* 85678485054SSara Sharon * Set read write pointer to reflect that we have processed 85778485054SSara Sharon * and used all buffers, but have not restocked the Rx queue 85878485054SSara Sharon * with fresh buffers 85978485054SSara Sharon */ 86078485054SSara Sharon rxq->read = 0; 86178485054SSara Sharon rxq->write = 0; 86278485054SSara Sharon rxq->write_actual = 0; 86378485054SSara Sharon memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts)); 86478485054SSara Sharon 86578485054SSara Sharon iwl_pcie_rx_init_rxb_lists(rxq); 86678485054SSara Sharon 867bce97731SSara Sharon if (!rxq->napi.poll) 868bce97731SSara Sharon netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 869bce97731SSara Sharon iwl_pcie_dummy_napi_poll, 64); 870bce97731SSara Sharon 871e705c121SKalle Valo spin_unlock(&rxq->lock); 87278485054SSara Sharon } 87378485054SSara Sharon 87496a6497bSSara Sharon /* move the pool to the default queue and allocator ownerships */ 87596a6497bSSara Sharon num_rbds = trans->cfg->mq_rx_supported ? 87696a6497bSSara Sharon MQ_RX_POOL_SIZE : RX_QUEUE_SIZE; 87796a6497bSSara Sharon allocator_pool_size = trans->num_rx_queues * 87896a6497bSSara Sharon (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 87996a6497bSSara Sharon for (i = 0; i < num_rbds; i++) { 88096a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 88196a6497bSSara Sharon 88296a6497bSSara Sharon if (i < allocator_pool_size) 88396a6497bSSara Sharon list_add(&rxb->list, &rba->rbd_empty); 88496a6497bSSara Sharon else 88596a6497bSSara Sharon list_add(&rxb->list, &def_rxq->rx_used); 88696a6497bSSara Sharon trans_pcie->global_table[i] = rxb; 88796a6497bSSara Sharon rxb->vid = (u16)i; 88896a6497bSSara Sharon } 88978485054SSara Sharon 89078485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 89196a6497bSSara Sharon if (trans->cfg->mq_rx_supported) { 892bce97731SSara Sharon iwl_pcie_rx_mq_hw_init(trans); 89396a6497bSSara Sharon } else { 89478485054SSara Sharon iwl_pcie_rxq_restock(trans, def_rxq); 89578485054SSara Sharon iwl_pcie_rx_hw_init(trans, def_rxq); 89696a6497bSSara Sharon } 89778485054SSara Sharon 89878485054SSara Sharon spin_lock(&def_rxq->lock); 89978485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, def_rxq); 90078485054SSara Sharon spin_unlock(&def_rxq->lock); 901e705c121SKalle Valo 902e705c121SKalle Valo return 0; 903e705c121SKalle Valo } 904e705c121SKalle Valo 905e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans) 906e705c121SKalle Valo { 907e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 908e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 90996a6497bSSara Sharon int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) : 91096a6497bSSara Sharon sizeof(__le32); 91178485054SSara Sharon int i; 912e705c121SKalle Valo 91378485054SSara Sharon /* 91478485054SSara Sharon * if rxq is NULL, it means that nothing has been allocated, 91578485054SSara Sharon * exit now 91678485054SSara Sharon */ 91778485054SSara Sharon if (!trans_pcie->rxq) { 918e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 919e705c121SKalle Valo return; 920e705c121SKalle Valo } 921e705c121SKalle Valo 922e705c121SKalle Valo cancel_work_sync(&rba->rx_alloc); 923e705c121SKalle Valo if (rba->alloc_wq) { 924e705c121SKalle Valo destroy_workqueue(rba->alloc_wq); 925e705c121SKalle Valo rba->alloc_wq = NULL; 926e705c121SKalle Valo } 927e705c121SKalle Valo 92878485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 929e705c121SKalle Valo 93078485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 93178485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 93278485054SSara Sharon 93378485054SSara Sharon if (rxq->bd) 93478485054SSara Sharon dma_free_coherent(trans->dev, 93596a6497bSSara Sharon free_size * rxq->queue_size, 936e705c121SKalle Valo rxq->bd, rxq->bd_dma); 937e705c121SKalle Valo rxq->bd_dma = 0; 938e705c121SKalle Valo rxq->bd = NULL; 939e705c121SKalle Valo 940e705c121SKalle Valo if (rxq->rb_stts) 941e705c121SKalle Valo dma_free_coherent(trans->dev, 942e705c121SKalle Valo sizeof(struct iwl_rb_status), 943e705c121SKalle Valo rxq->rb_stts, rxq->rb_stts_dma); 944e705c121SKalle Valo else 94578485054SSara Sharon IWL_DEBUG_INFO(trans, 94678485054SSara Sharon "Free rxq->rb_stts which is NULL\n"); 94778485054SSara Sharon 94896a6497bSSara Sharon if (rxq->used_bd) 94996a6497bSSara Sharon dma_free_coherent(trans->dev, 95096a6497bSSara Sharon sizeof(__le32) * rxq->queue_size, 95196a6497bSSara Sharon rxq->used_bd, rxq->used_bd_dma); 95296a6497bSSara Sharon rxq->used_bd_dma = 0; 95396a6497bSSara Sharon rxq->used_bd = NULL; 954bce97731SSara Sharon 955bce97731SSara Sharon if (rxq->napi.poll) 956bce97731SSara Sharon netif_napi_del(&rxq->napi); 95796a6497bSSara Sharon } 95878485054SSara Sharon kfree(trans_pcie->rxq); 959e705c121SKalle Valo } 960e705c121SKalle Valo 961e705c121SKalle Valo /* 962e705c121SKalle Valo * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 963e705c121SKalle Valo * 964e705c121SKalle Valo * Called when a RBD can be reused. The RBD is transferred to the allocator. 965e705c121SKalle Valo * When there are 2 empty RBDs - a request for allocation is posted 966e705c121SKalle Valo */ 967e705c121SKalle Valo static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 968e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 969e705c121SKalle Valo struct iwl_rxq *rxq, bool emergency) 970e705c121SKalle Valo { 971e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 972e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 973e705c121SKalle Valo 974e705c121SKalle Valo /* Move the RBD to the used list, will be moved to allocator in batches 975e705c121SKalle Valo * before claiming or posting a request*/ 976e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_used); 977e705c121SKalle Valo 978e705c121SKalle Valo if (unlikely(emergency)) 979e705c121SKalle Valo return; 980e705c121SKalle Valo 981e705c121SKalle Valo /* Count the allocator owned RBDs */ 982e705c121SKalle Valo rxq->used_count++; 983e705c121SKalle Valo 984e705c121SKalle Valo /* If we have RX_POST_REQ_ALLOC new released rx buffers - 985e705c121SKalle Valo * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 986e705c121SKalle Valo * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 987e705c121SKalle Valo * after but we still need to post another request. 988e705c121SKalle Valo */ 989e705c121SKalle Valo if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 990e705c121SKalle Valo /* Move the 2 RBDs to the allocator ownership. 991e705c121SKalle Valo Allocator has another 6 from pool for the request completion*/ 992e705c121SKalle Valo spin_lock(&rba->lock); 993e705c121SKalle Valo list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 994e705c121SKalle Valo spin_unlock(&rba->lock); 995e705c121SKalle Valo 996e705c121SKalle Valo atomic_inc(&rba->req_pending); 997e705c121SKalle Valo queue_work(rba->alloc_wq, &rba->rx_alloc); 998e705c121SKalle Valo } 999e705c121SKalle Valo } 1000e705c121SKalle Valo 1001e705c121SKalle Valo static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 100278485054SSara Sharon struct iwl_rxq *rxq, 1003e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 1004e705c121SKalle Valo bool emergency) 1005e705c121SKalle Valo { 1006e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1007e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1008e705c121SKalle Valo bool page_stolen = false; 1009e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 1010e705c121SKalle Valo u32 offset = 0; 1011e705c121SKalle Valo 1012e705c121SKalle Valo if (WARN_ON(!rxb)) 1013e705c121SKalle Valo return; 1014e705c121SKalle Valo 1015e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1016e705c121SKalle Valo 1017e705c121SKalle Valo while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1018e705c121SKalle Valo struct iwl_rx_packet *pkt; 1019e705c121SKalle Valo u16 sequence; 1020e705c121SKalle Valo bool reclaim; 1021e705c121SKalle Valo int index, cmd_index, len; 1022e705c121SKalle Valo struct iwl_rx_cmd_buffer rxcb = { 1023e705c121SKalle Valo ._offset = offset, 1024e705c121SKalle Valo ._rx_page_order = trans_pcie->rx_page_order, 1025e705c121SKalle Valo ._page = rxb->page, 1026e705c121SKalle Valo ._page_stolen = false, 1027e705c121SKalle Valo .truesize = max_len, 1028e705c121SKalle Valo }; 1029e705c121SKalle Valo 1030e705c121SKalle Valo pkt = rxb_addr(&rxcb); 1031e705c121SKalle Valo 1032e705c121SKalle Valo if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) 1033e705c121SKalle Valo break; 1034e705c121SKalle Valo 1035e705c121SKalle Valo IWL_DEBUG_RX(trans, 1036e705c121SKalle Valo "cmd at offset %d: %s (0x%.2x, seq 0x%x)\n", 1037e705c121SKalle Valo rxcb._offset, 103839bdb17eSSharon Dvir iwl_get_cmd_string(trans, 103939bdb17eSSharon Dvir iwl_cmd_id(pkt->hdr.cmd, 104039bdb17eSSharon Dvir pkt->hdr.group_id, 104139bdb17eSSharon Dvir 0)), 1042e705c121SKalle Valo pkt->hdr.cmd, le16_to_cpu(pkt->hdr.sequence)); 1043e705c121SKalle Valo 1044e705c121SKalle Valo len = iwl_rx_packet_len(pkt); 1045e705c121SKalle Valo len += sizeof(u32); /* account for status word */ 1046e705c121SKalle Valo trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1047e705c121SKalle Valo trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1048e705c121SKalle Valo 1049e705c121SKalle Valo /* Reclaim a command buffer only if this packet is a response 1050e705c121SKalle Valo * to a (driver-originated) command. 1051e705c121SKalle Valo * If the packet (e.g. Rx frame) originated from uCode, 1052e705c121SKalle Valo * there is no command buffer to reclaim. 1053e705c121SKalle Valo * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1054e705c121SKalle Valo * but apparently a few don't get set; catch them here. */ 1055e705c121SKalle Valo reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1056e705c121SKalle Valo if (reclaim) { 1057e705c121SKalle Valo int i; 1058e705c121SKalle Valo 1059e705c121SKalle Valo for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1060e705c121SKalle Valo if (trans_pcie->no_reclaim_cmds[i] == 1061e705c121SKalle Valo pkt->hdr.cmd) { 1062e705c121SKalle Valo reclaim = false; 1063e705c121SKalle Valo break; 1064e705c121SKalle Valo } 1065e705c121SKalle Valo } 1066e705c121SKalle Valo } 1067e705c121SKalle Valo 1068e705c121SKalle Valo sequence = le16_to_cpu(pkt->hdr.sequence); 1069e705c121SKalle Valo index = SEQ_TO_INDEX(sequence); 1070e705c121SKalle Valo cmd_index = get_cmd_index(&txq->q, index); 1071e705c121SKalle Valo 1072bce97731SSara Sharon if (rxq->id == 0) 1073bce97731SSara Sharon iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1074bce97731SSara Sharon &rxcb); 1075bce97731SSara Sharon else 1076bce97731SSara Sharon iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1077bce97731SSara Sharon &rxcb, rxq->id); 1078e705c121SKalle Valo 1079e705c121SKalle Valo if (reclaim) { 1080e705c121SKalle Valo kzfree(txq->entries[cmd_index].free_buf); 1081e705c121SKalle Valo txq->entries[cmd_index].free_buf = NULL; 1082e705c121SKalle Valo } 1083e705c121SKalle Valo 1084e705c121SKalle Valo /* 1085e705c121SKalle Valo * After here, we should always check rxcb._page_stolen, 1086e705c121SKalle Valo * if it is true then one of the handlers took the page. 1087e705c121SKalle Valo */ 1088e705c121SKalle Valo 1089e705c121SKalle Valo if (reclaim) { 1090e705c121SKalle Valo /* Invoke any callbacks, transfer the buffer to caller, 1091e705c121SKalle Valo * and fire off the (possibly) blocking 1092e705c121SKalle Valo * iwl_trans_send_cmd() 1093e705c121SKalle Valo * as we reclaim the driver command queue */ 1094e705c121SKalle Valo if (!rxcb._page_stolen) 1095e705c121SKalle Valo iwl_pcie_hcmd_complete(trans, &rxcb); 1096e705c121SKalle Valo else 1097e705c121SKalle Valo IWL_WARN(trans, "Claim null rxb?\n"); 1098e705c121SKalle Valo } 1099e705c121SKalle Valo 1100e705c121SKalle Valo page_stolen |= rxcb._page_stolen; 1101e705c121SKalle Valo offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1102e705c121SKalle Valo } 1103e705c121SKalle Valo 1104e705c121SKalle Valo /* page was stolen from us -- free our reference */ 1105e705c121SKalle Valo if (page_stolen) { 1106e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1107e705c121SKalle Valo rxb->page = NULL; 1108e705c121SKalle Valo } 1109e705c121SKalle Valo 1110e705c121SKalle Valo /* Reuse the page if possible. For notification packets and 1111e705c121SKalle Valo * SKBs that fail to Rx correctly, add them back into the 1112e705c121SKalle Valo * rx_free list for reuse later. */ 1113e705c121SKalle Valo if (rxb->page != NULL) { 1114e705c121SKalle Valo rxb->page_dma = 1115e705c121SKalle Valo dma_map_page(trans->dev, rxb->page, 0, 1116e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 1117e705c121SKalle Valo DMA_FROM_DEVICE); 1118e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1119e705c121SKalle Valo /* 1120e705c121SKalle Valo * free the page(s) as well to not break 1121e705c121SKalle Valo * the invariant that the items on the used 1122e705c121SKalle Valo * list have no page(s) 1123e705c121SKalle Valo */ 1124e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1125e705c121SKalle Valo rxb->page = NULL; 1126e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1127e705c121SKalle Valo } else { 1128e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 1129e705c121SKalle Valo rxq->free_count++; 1130e705c121SKalle Valo } 1131e705c121SKalle Valo } else 1132e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1133e705c121SKalle Valo } 1134e705c121SKalle Valo 1135e705c121SKalle Valo /* 1136e705c121SKalle Valo * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1137e705c121SKalle Valo */ 11382e5d4a8fSHaim Dreyfuss static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue) 1139e705c121SKalle Valo { 1140e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11412e5d4a8fSHaim Dreyfuss struct iwl_rxq *rxq = &trans_pcie->rxq[queue]; 1142e705c121SKalle Valo u32 r, i, j, count = 0; 1143e705c121SKalle Valo bool emergency = false; 1144e705c121SKalle Valo 1145e705c121SKalle Valo restart: 1146e705c121SKalle Valo spin_lock(&rxq->lock); 1147e705c121SKalle Valo /* uCode's read index (stored in shared DRAM) indicates the last Rx 1148e705c121SKalle Valo * buffer that the driver may process (last buffer filled by ucode). */ 1149e705c121SKalle Valo r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 1150e705c121SKalle Valo i = rxq->read; 1151e705c121SKalle Valo 1152e705c121SKalle Valo /* Rx interrupt, but nothing sent from uCode */ 1153e705c121SKalle Valo if (i == r) 1154e705c121SKalle Valo IWL_DEBUG_RX(trans, "HW = SW = %d\n", r); 1155e705c121SKalle Valo 1156e705c121SKalle Valo while (i != r) { 1157e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 1158e705c121SKalle Valo 115996a6497bSSara Sharon if (unlikely(rxq->used_count == rxq->queue_size / 2)) 1160e705c121SKalle Valo emergency = true; 1161e705c121SKalle Valo 116296a6497bSSara Sharon if (trans->cfg->mq_rx_supported) { 116396a6497bSSara Sharon /* 116496a6497bSSara Sharon * used_bd is a 32 bit but only 12 are used to retrieve 116596a6497bSSara Sharon * the vid 116696a6497bSSara Sharon */ 116796a6497bSSara Sharon u16 vid = (u16)le32_to_cpu(rxq->used_bd[i]); 116896a6497bSSara Sharon 116996a6497bSSara Sharon rxb = trans_pcie->global_table[vid]; 117096a6497bSSara Sharon } else { 1171e705c121SKalle Valo rxb = rxq->queue[i]; 1172e705c121SKalle Valo rxq->queue[i] = NULL; 117396a6497bSSara Sharon } 1174e705c121SKalle Valo 1175f02d2ccdSJohannes Berg IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d\n", r, i); 117678485054SSara Sharon iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency); 1177e705c121SKalle Valo 117896a6497bSSara Sharon i = (i + 1) & (rxq->queue_size - 1); 1179e705c121SKalle Valo 1180e705c121SKalle Valo /* If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1181e705c121SKalle Valo * try to claim the pre-allocated buffers from the allocator */ 1182e705c121SKalle Valo if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) { 1183e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 1184e705c121SKalle Valo struct iwl_rx_mem_buffer *out[RX_CLAIM_REQ_ALLOC]; 1185e705c121SKalle Valo 1186e705c121SKalle Valo if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && 1187e705c121SKalle Valo !emergency) { 1188e705c121SKalle Valo /* Add the remaining 6 empty RBDs 1189e705c121SKalle Valo * for allocator use 1190e705c121SKalle Valo */ 1191e705c121SKalle Valo spin_lock(&rba->lock); 1192e705c121SKalle Valo list_splice_tail_init(&rxq->rx_used, 1193e705c121SKalle Valo &rba->rbd_empty); 1194e705c121SKalle Valo spin_unlock(&rba->lock); 1195e705c121SKalle Valo } 1196e705c121SKalle Valo 1197e705c121SKalle Valo /* If not ready - continue, will try to reclaim later. 1198e705c121SKalle Valo * No need to reschedule work - allocator exits only on 1199e705c121SKalle Valo * success */ 1200e705c121SKalle Valo if (!iwl_pcie_rx_allocator_get(trans, out)) { 1201e705c121SKalle Valo /* If success - then RX_CLAIM_REQ_ALLOC 1202e705c121SKalle Valo * buffers were retrieved and should be added 1203e705c121SKalle Valo * to free list */ 1204e705c121SKalle Valo rxq->used_count -= RX_CLAIM_REQ_ALLOC; 1205e705c121SKalle Valo for (j = 0; j < RX_CLAIM_REQ_ALLOC; j++) { 1206e705c121SKalle Valo list_add_tail(&out[j]->list, 1207e705c121SKalle Valo &rxq->rx_free); 1208e705c121SKalle Valo rxq->free_count++; 1209e705c121SKalle Valo } 1210e705c121SKalle Valo } 1211e705c121SKalle Valo } 1212e705c121SKalle Valo if (emergency) { 1213e705c121SKalle Valo count++; 1214e705c121SKalle Valo if (count == 8) { 1215e705c121SKalle Valo count = 0; 121696a6497bSSara Sharon if (rxq->used_count < rxq->queue_size / 3) 1217e705c121SKalle Valo emergency = false; 1218e705c121SKalle Valo spin_unlock(&rxq->lock); 121978485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1220e705c121SKalle Valo spin_lock(&rxq->lock); 1221e705c121SKalle Valo } 1222e705c121SKalle Valo } 1223e705c121SKalle Valo /* handle restock for three cases, can be all of them at once: 1224e705c121SKalle Valo * - we just pulled buffers from the allocator 1225e705c121SKalle Valo * - we have 8+ unstolen pages accumulated 1226e705c121SKalle Valo * - we are in emergency and allocated buffers 1227e705c121SKalle Valo */ 1228e705c121SKalle Valo if (rxq->free_count >= RX_CLAIM_REQ_ALLOC) { 1229e705c121SKalle Valo rxq->read = i; 1230e705c121SKalle Valo spin_unlock(&rxq->lock); 123196a6497bSSara Sharon if (trans->cfg->mq_rx_supported) 123296a6497bSSara Sharon iwl_pcie_rxq_mq_restock(trans, rxq); 123396a6497bSSara Sharon else 123478485054SSara Sharon iwl_pcie_rxq_restock(trans, rxq); 1235e705c121SKalle Valo goto restart; 1236e705c121SKalle Valo } 1237e705c121SKalle Valo } 1238e705c121SKalle Valo 1239e705c121SKalle Valo /* Backtrack one entry */ 1240e705c121SKalle Valo rxq->read = i; 1241e705c121SKalle Valo spin_unlock(&rxq->lock); 1242e705c121SKalle Valo 1243e705c121SKalle Valo /* 1244e705c121SKalle Valo * handle a case where in emergency there are some unallocated RBDs. 1245e705c121SKalle Valo * those RBDs are in the used list, but are not tracked by the queue's 1246e705c121SKalle Valo * used_count which counts allocator owned RBDs. 1247e705c121SKalle Valo * unallocated emergency RBDs must be allocated on exit, otherwise 1248e705c121SKalle Valo * when called again the function may not be in emergency mode and 1249e705c121SKalle Valo * they will be handed to the allocator with no tracking in the RBD 1250e705c121SKalle Valo * allocator counters, which will lead to them never being claimed back 1251e705c121SKalle Valo * by the queue. 1252e705c121SKalle Valo * by allocating them here, they are now in the queue free list, and 1253e705c121SKalle Valo * will be restocked by the next call of iwl_pcie_rxq_restock. 1254e705c121SKalle Valo */ 1255e705c121SKalle Valo if (unlikely(emergency && count)) 125678485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1257e705c121SKalle Valo 1258bce97731SSara Sharon if (rxq->napi.poll) 1259bce97731SSara Sharon napi_gro_flush(&rxq->napi, false); 1260e705c121SKalle Valo } 1261e705c121SKalle Valo 12622e5d4a8fSHaim Dreyfuss static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 12632e5d4a8fSHaim Dreyfuss { 12642e5d4a8fSHaim Dreyfuss u8 queue = entry->entry; 12652e5d4a8fSHaim Dreyfuss struct msix_entry *entries = entry - queue; 12662e5d4a8fSHaim Dreyfuss 12672e5d4a8fSHaim Dreyfuss return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 12682e5d4a8fSHaim Dreyfuss } 12692e5d4a8fSHaim Dreyfuss 12702e5d4a8fSHaim Dreyfuss static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 12712e5d4a8fSHaim Dreyfuss struct msix_entry *entry) 12722e5d4a8fSHaim Dreyfuss { 12732e5d4a8fSHaim Dreyfuss /* 12742e5d4a8fSHaim Dreyfuss * Before sending the interrupt the HW disables it to prevent 12752e5d4a8fSHaim Dreyfuss * a nested interrupt. This is done by writing 1 to the corresponding 12762e5d4a8fSHaim Dreyfuss * bit in the mask register. After handling the interrupt, it should be 12772e5d4a8fSHaim Dreyfuss * re-enabled by clearing this bit. This register is defined as 12782e5d4a8fSHaim Dreyfuss * write 1 clear (W1C) register, meaning that it's being clear 12792e5d4a8fSHaim Dreyfuss * by writing 1 to the bit. 12802e5d4a8fSHaim Dreyfuss */ 12812e5d4a8fSHaim Dreyfuss iwl_write_direct32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 12822e5d4a8fSHaim Dreyfuss } 12832e5d4a8fSHaim Dreyfuss 12842e5d4a8fSHaim Dreyfuss /* 12852e5d4a8fSHaim Dreyfuss * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 12862e5d4a8fSHaim Dreyfuss * This interrupt handler should be used with RSS queue only. 12872e5d4a8fSHaim Dreyfuss */ 12882e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 12892e5d4a8fSHaim Dreyfuss { 12902e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 12912e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 12922e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 12932e5d4a8fSHaim Dreyfuss 12942e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 12952e5d4a8fSHaim Dreyfuss 12962e5d4a8fSHaim Dreyfuss local_bh_disable(); 12972e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, entry->entry); 12982e5d4a8fSHaim Dreyfuss local_bh_enable(); 12992e5d4a8fSHaim Dreyfuss 13002e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 13012e5d4a8fSHaim Dreyfuss 13022e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 13032e5d4a8fSHaim Dreyfuss 13042e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 13052e5d4a8fSHaim Dreyfuss } 13062e5d4a8fSHaim Dreyfuss 1307e705c121SKalle Valo /* 1308e705c121SKalle Valo * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1309e705c121SKalle Valo */ 1310e705c121SKalle Valo static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1311e705c121SKalle Valo { 1312e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1313e705c121SKalle Valo int i; 1314e705c121SKalle Valo 1315e705c121SKalle Valo /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1316e705c121SKalle Valo if (trans->cfg->internal_wimax_coex && 1317e705c121SKalle Valo !trans->cfg->apmg_not_supported && 1318e705c121SKalle Valo (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1319e705c121SKalle Valo APMS_CLK_VAL_MRB_FUNC_MODE) || 1320e705c121SKalle Valo (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1321e705c121SKalle Valo APMG_PS_CTRL_VAL_RESET_REQ))) { 1322e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1323e705c121SKalle Valo iwl_op_mode_wimax_active(trans->op_mode); 1324e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1325e705c121SKalle Valo return; 1326e705c121SKalle Valo } 1327e705c121SKalle Valo 1328e705c121SKalle Valo iwl_pcie_dump_csr(trans); 1329e705c121SKalle Valo iwl_dump_fh(trans, NULL); 1330e705c121SKalle Valo 1331e705c121SKalle Valo local_bh_disable(); 1332e705c121SKalle Valo /* The STATUS_FW_ERROR bit is set in this function. This must happen 1333e705c121SKalle Valo * before we wake up the command caller, to ensure a proper cleanup. */ 1334e705c121SKalle Valo iwl_trans_fw_error(trans); 1335e705c121SKalle Valo local_bh_enable(); 1336e705c121SKalle Valo 1337e705c121SKalle Valo for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) 1338e705c121SKalle Valo del_timer(&trans_pcie->txq[i].stuck_timer); 1339e705c121SKalle Valo 1340e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1341e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1342e705c121SKalle Valo } 1343e705c121SKalle Valo 1344e705c121SKalle Valo static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1345e705c121SKalle Valo { 1346e705c121SKalle Valo u32 inta; 1347e705c121SKalle Valo 1348e705c121SKalle Valo lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1349e705c121SKalle Valo 1350e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1351e705c121SKalle Valo 1352e705c121SKalle Valo /* Discover which interrupts are active/pending */ 1353e705c121SKalle Valo inta = iwl_read32(trans, CSR_INT); 1354e705c121SKalle Valo 1355e705c121SKalle Valo /* the thread will service interrupts and re-enable them */ 1356e705c121SKalle Valo return inta; 1357e705c121SKalle Valo } 1358e705c121SKalle Valo 1359e705c121SKalle Valo /* a device (PCI-E) page is 4096 bytes long */ 1360e705c121SKalle Valo #define ICT_SHIFT 12 1361e705c121SKalle Valo #define ICT_SIZE (1 << ICT_SHIFT) 1362e705c121SKalle Valo #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1363e705c121SKalle Valo 1364e705c121SKalle Valo /* interrupt handler using ict table, with this interrupt driver will 1365e705c121SKalle Valo * stop using INTA register to get device's interrupt, reading this register 1366e705c121SKalle Valo * is expensive, device will write interrupts in ICT dram table, increment 1367e705c121SKalle Valo * index then will fire interrupt to driver, driver will OR all ICT table 1368e705c121SKalle Valo * entries from current index up to table entry with 0 value. the result is 1369e705c121SKalle Valo * the interrupt we need to service, driver will set the entries back to 0 and 1370e705c121SKalle Valo * set index. 1371e705c121SKalle Valo */ 1372e705c121SKalle Valo static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1373e705c121SKalle Valo { 1374e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1375e705c121SKalle Valo u32 inta; 1376e705c121SKalle Valo u32 val = 0; 1377e705c121SKalle Valo u32 read; 1378e705c121SKalle Valo 1379e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1380e705c121SKalle Valo 1381e705c121SKalle Valo /* Ignore interrupt if there's nothing in NIC to service. 1382e705c121SKalle Valo * This may be due to IRQ shared with another device, 1383e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. */ 1384e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1385e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1386e705c121SKalle Valo if (!read) 1387e705c121SKalle Valo return 0; 1388e705c121SKalle Valo 1389e705c121SKalle Valo /* 1390e705c121SKalle Valo * Collect all entries up to the first 0, starting from ict_index; 1391e705c121SKalle Valo * note we already read at ict_index. 1392e705c121SKalle Valo */ 1393e705c121SKalle Valo do { 1394e705c121SKalle Valo val |= read; 1395e705c121SKalle Valo IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1396e705c121SKalle Valo trans_pcie->ict_index, read); 1397e705c121SKalle Valo trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1398e705c121SKalle Valo trans_pcie->ict_index = 1399e705c121SKalle Valo ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1400e705c121SKalle Valo 1401e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1402e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1403e705c121SKalle Valo read); 1404e705c121SKalle Valo } while (read); 1405e705c121SKalle Valo 1406e705c121SKalle Valo /* We should not get this value, just ignore it. */ 1407e705c121SKalle Valo if (val == 0xffffffff) 1408e705c121SKalle Valo val = 0; 1409e705c121SKalle Valo 1410e705c121SKalle Valo /* 1411e705c121SKalle Valo * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1412e705c121SKalle Valo * (bit 15 before shifting it to 31) to clear when using interrupt 1413e705c121SKalle Valo * coalescing. fortunately, bits 18 and 19 stay set when this happens 1414e705c121SKalle Valo * so we use them to decide on the real state of the Rx bit. 1415e705c121SKalle Valo * In order words, bit 15 is set if bit 18 or bit 19 are set. 1416e705c121SKalle Valo */ 1417e705c121SKalle Valo if (val & 0xC0000) 1418e705c121SKalle Valo val |= 0x8000; 1419e705c121SKalle Valo 1420e705c121SKalle Valo inta = (0xff & val) | ((0xff00 & val) << 16); 1421e705c121SKalle Valo return inta; 1422e705c121SKalle Valo } 1423e705c121SKalle Valo 1424e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1425e705c121SKalle Valo { 1426e705c121SKalle Valo struct iwl_trans *trans = dev_id; 1427e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1428e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1429e705c121SKalle Valo u32 inta = 0; 1430e705c121SKalle Valo u32 handled = 0; 1431e705c121SKalle Valo 1432e705c121SKalle Valo lock_map_acquire(&trans->sync_cmd_lockdep_map); 1433e705c121SKalle Valo 1434e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1435e705c121SKalle Valo 1436e705c121SKalle Valo /* dram interrupt table not set yet, 1437e705c121SKalle Valo * use legacy interrupt. 1438e705c121SKalle Valo */ 1439e705c121SKalle Valo if (likely(trans_pcie->use_ict)) 1440e705c121SKalle Valo inta = iwl_pcie_int_cause_ict(trans); 1441e705c121SKalle Valo else 1442e705c121SKalle Valo inta = iwl_pcie_int_cause_non_ict(trans); 1443e705c121SKalle Valo 1444e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1445e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1446e705c121SKalle Valo "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1447e705c121SKalle Valo inta, trans_pcie->inta_mask, 1448e705c121SKalle Valo iwl_read32(trans, CSR_INT_MASK), 1449e705c121SKalle Valo iwl_read32(trans, CSR_FH_INT_STATUS)); 1450e705c121SKalle Valo if (inta & (~trans_pcie->inta_mask)) 1451e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1452e705c121SKalle Valo "We got a masked interrupt (0x%08x)\n", 1453e705c121SKalle Valo inta & (~trans_pcie->inta_mask)); 1454e705c121SKalle Valo } 1455e705c121SKalle Valo 1456e705c121SKalle Valo inta &= trans_pcie->inta_mask; 1457e705c121SKalle Valo 1458e705c121SKalle Valo /* 1459e705c121SKalle Valo * Ignore interrupt if there's nothing in NIC to service. 1460e705c121SKalle Valo * This may be due to IRQ shared with another device, 1461e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. 1462e705c121SKalle Valo */ 1463e705c121SKalle Valo if (unlikely(!inta)) { 1464e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1465e705c121SKalle Valo /* 1466e705c121SKalle Valo * Re-enable interrupts here since we don't 1467e705c121SKalle Valo * have anything to service 1468e705c121SKalle Valo */ 1469e705c121SKalle Valo if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1470e705c121SKalle Valo iwl_enable_interrupts(trans); 1471e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1472e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1473e705c121SKalle Valo return IRQ_NONE; 1474e705c121SKalle Valo } 1475e705c121SKalle Valo 1476e705c121SKalle Valo if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1477e705c121SKalle Valo /* 1478e705c121SKalle Valo * Hardware disappeared. It might have 1479e705c121SKalle Valo * already raised an interrupt. 1480e705c121SKalle Valo */ 1481e705c121SKalle Valo IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1482e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1483e705c121SKalle Valo goto out; 1484e705c121SKalle Valo } 1485e705c121SKalle Valo 1486e705c121SKalle Valo /* Ack/clear/reset pending uCode interrupts. 1487e705c121SKalle Valo * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1488e705c121SKalle Valo */ 1489e705c121SKalle Valo /* There is a hardware bug in the interrupt mask function that some 1490e705c121SKalle Valo * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1491e705c121SKalle Valo * they are disabled in the CSR_INT_MASK register. Furthermore the 1492e705c121SKalle Valo * ICT interrupt handling mechanism has another bug that might cause 1493e705c121SKalle Valo * these unmasked interrupts fail to be detected. We workaround the 1494e705c121SKalle Valo * hardware bugs here by ACKing all the possible interrupts so that 1495e705c121SKalle Valo * interrupt coalescing can still be achieved. 1496e705c121SKalle Valo */ 1497e705c121SKalle Valo iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1498e705c121SKalle Valo 1499e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) 1500e705c121SKalle Valo IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1501e705c121SKalle Valo inta, iwl_read32(trans, CSR_INT_MASK)); 1502e705c121SKalle Valo 1503e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1504e705c121SKalle Valo 1505e705c121SKalle Valo /* Now service all interrupt bits discovered above. */ 1506e705c121SKalle Valo if (inta & CSR_INT_BIT_HW_ERR) { 1507e705c121SKalle Valo IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1508e705c121SKalle Valo 1509e705c121SKalle Valo /* Tell the device to stop sending interrupts */ 1510e705c121SKalle Valo iwl_disable_interrupts(trans); 1511e705c121SKalle Valo 1512e705c121SKalle Valo isr_stats->hw++; 1513e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1514e705c121SKalle Valo 1515e705c121SKalle Valo handled |= CSR_INT_BIT_HW_ERR; 1516e705c121SKalle Valo 1517e705c121SKalle Valo goto out; 1518e705c121SKalle Valo } 1519e705c121SKalle Valo 1520e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1521e705c121SKalle Valo /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1522e705c121SKalle Valo if (inta & CSR_INT_BIT_SCD) { 1523e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1524e705c121SKalle Valo "Scheduler finished to transmit the frame/frames.\n"); 1525e705c121SKalle Valo isr_stats->sch++; 1526e705c121SKalle Valo } 1527e705c121SKalle Valo 1528e705c121SKalle Valo /* Alive notification via Rx interrupt will do the real work */ 1529e705c121SKalle Valo if (inta & CSR_INT_BIT_ALIVE) { 1530e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1531e705c121SKalle Valo isr_stats->alive++; 1532e705c121SKalle Valo } 1533e705c121SKalle Valo } 1534e705c121SKalle Valo 1535e705c121SKalle Valo /* Safely ignore these bits for debug checks below */ 1536e705c121SKalle Valo inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1537e705c121SKalle Valo 1538e705c121SKalle Valo /* HW RF KILL switch toggled */ 1539e705c121SKalle Valo if (inta & CSR_INT_BIT_RF_KILL) { 1540e705c121SKalle Valo bool hw_rfkill; 1541e705c121SKalle Valo 1542e705c121SKalle Valo hw_rfkill = iwl_is_rfkill_set(trans); 1543e705c121SKalle Valo IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 1544e705c121SKalle Valo hw_rfkill ? "disable radio" : "enable radio"); 1545e705c121SKalle Valo 1546e705c121SKalle Valo isr_stats->rfkill++; 1547e705c121SKalle Valo 1548e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1549e705c121SKalle Valo iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1550e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1551e705c121SKalle Valo if (hw_rfkill) { 1552e705c121SKalle Valo set_bit(STATUS_RFKILL, &trans->status); 1553e705c121SKalle Valo if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 1554e705c121SKalle Valo &trans->status)) 1555e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, 1556e705c121SKalle Valo "Rfkill while SYNC HCMD in flight\n"); 1557e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1558e705c121SKalle Valo } else { 1559e705c121SKalle Valo clear_bit(STATUS_RFKILL, &trans->status); 1560e705c121SKalle Valo } 1561e705c121SKalle Valo 1562e705c121SKalle Valo handled |= CSR_INT_BIT_RF_KILL; 1563e705c121SKalle Valo } 1564e705c121SKalle Valo 1565e705c121SKalle Valo /* Chip got too hot and stopped itself */ 1566e705c121SKalle Valo if (inta & CSR_INT_BIT_CT_KILL) { 1567e705c121SKalle Valo IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1568e705c121SKalle Valo isr_stats->ctkill++; 1569e705c121SKalle Valo handled |= CSR_INT_BIT_CT_KILL; 1570e705c121SKalle Valo } 1571e705c121SKalle Valo 1572e705c121SKalle Valo /* Error detected by uCode */ 1573e705c121SKalle Valo if (inta & CSR_INT_BIT_SW_ERR) { 1574e705c121SKalle Valo IWL_ERR(trans, "Microcode SW error detected. " 1575e705c121SKalle Valo " Restarting 0x%X.\n", inta); 1576e705c121SKalle Valo isr_stats->sw++; 1577e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1578e705c121SKalle Valo handled |= CSR_INT_BIT_SW_ERR; 1579e705c121SKalle Valo } 1580e705c121SKalle Valo 1581e705c121SKalle Valo /* uCode wakes up after power-down sleep */ 1582e705c121SKalle Valo if (inta & CSR_INT_BIT_WAKEUP) { 1583e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1584e705c121SKalle Valo iwl_pcie_rxq_check_wrptr(trans); 1585e705c121SKalle Valo iwl_pcie_txq_check_wrptrs(trans); 1586e705c121SKalle Valo 1587e705c121SKalle Valo isr_stats->wakeup++; 1588e705c121SKalle Valo 1589e705c121SKalle Valo handled |= CSR_INT_BIT_WAKEUP; 1590e705c121SKalle Valo } 1591e705c121SKalle Valo 1592e705c121SKalle Valo /* All uCode command responses, including Tx command responses, 1593e705c121SKalle Valo * Rx "responses" (frame-received notification), and other 1594e705c121SKalle Valo * notifications from uCode come through here*/ 1595e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1596e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC)) { 1597e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1598e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1599e705c121SKalle Valo handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1600e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 1601e705c121SKalle Valo CSR_FH_INT_RX_MASK); 1602e705c121SKalle Valo } 1603e705c121SKalle Valo if (inta & CSR_INT_BIT_RX_PERIODIC) { 1604e705c121SKalle Valo handled |= CSR_INT_BIT_RX_PERIODIC; 1605e705c121SKalle Valo iwl_write32(trans, 1606e705c121SKalle Valo CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1607e705c121SKalle Valo } 1608e705c121SKalle Valo /* Sending RX interrupt require many steps to be done in the 1609e705c121SKalle Valo * the device: 1610e705c121SKalle Valo * 1- write interrupt to current index in ICT table. 1611e705c121SKalle Valo * 2- dma RX frame. 1612e705c121SKalle Valo * 3- update RX shared data to indicate last write index. 1613e705c121SKalle Valo * 4- send interrupt. 1614e705c121SKalle Valo * This could lead to RX race, driver could receive RX interrupt 1615e705c121SKalle Valo * but the shared data changes does not reflect this; 1616e705c121SKalle Valo * periodic interrupt will detect any dangling Rx activity. 1617e705c121SKalle Valo */ 1618e705c121SKalle Valo 1619e705c121SKalle Valo /* Disable periodic interrupt; we use it as just a one-shot. */ 1620e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1621e705c121SKalle Valo CSR_INT_PERIODIC_DIS); 1622e705c121SKalle Valo 1623e705c121SKalle Valo /* 1624e705c121SKalle Valo * Enable periodic interrupt in 8 msec only if we received 1625e705c121SKalle Valo * real RX interrupt (instead of just periodic int), to catch 1626e705c121SKalle Valo * any dangling Rx interrupt. If it was just the periodic 1627e705c121SKalle Valo * interrupt, there was no dangling Rx activity, and no need 1628e705c121SKalle Valo * to extend the periodic interrupt; one-shot is enough. 1629e705c121SKalle Valo */ 1630e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1631e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1632e705c121SKalle Valo CSR_INT_PERIODIC_ENA); 1633e705c121SKalle Valo 1634e705c121SKalle Valo isr_stats->rx++; 1635e705c121SKalle Valo 1636e705c121SKalle Valo local_bh_disable(); 16372e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, 0); 1638e705c121SKalle Valo local_bh_enable(); 1639e705c121SKalle Valo } 1640e705c121SKalle Valo 1641e705c121SKalle Valo /* This "Tx" DMA channel is used only for loading uCode */ 1642e705c121SKalle Valo if (inta & CSR_INT_BIT_FH_TX) { 1643e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1644e705c121SKalle Valo IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1645e705c121SKalle Valo isr_stats->tx++; 1646e705c121SKalle Valo handled |= CSR_INT_BIT_FH_TX; 1647e705c121SKalle Valo /* Wake up uCode load routine, now that load is complete */ 1648e705c121SKalle Valo trans_pcie->ucode_write_complete = true; 1649e705c121SKalle Valo wake_up(&trans_pcie->ucode_write_waitq); 1650e705c121SKalle Valo } 1651e705c121SKalle Valo 1652e705c121SKalle Valo if (inta & ~handled) { 1653e705c121SKalle Valo IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 1654e705c121SKalle Valo isr_stats->unhandled++; 1655e705c121SKalle Valo } 1656e705c121SKalle Valo 1657e705c121SKalle Valo if (inta & ~(trans_pcie->inta_mask)) { 1658e705c121SKalle Valo IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 1659e705c121SKalle Valo inta & ~trans_pcie->inta_mask); 1660e705c121SKalle Valo } 1661e705c121SKalle Valo 1662a6bd005fSEmmanuel Grumbach /* we are loading the firmware, enable FH_TX interrupt only */ 1663a6bd005fSEmmanuel Grumbach if (handled & CSR_INT_BIT_FH_TX) 1664a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1665a6bd005fSEmmanuel Grumbach /* only Re-enable all interrupt if disabled by irq */ 1666a6bd005fSEmmanuel Grumbach else if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1667e705c121SKalle Valo iwl_enable_interrupts(trans); 1668e705c121SKalle Valo /* Re-enable RF_KILL if it occurred */ 1669e705c121SKalle Valo else if (handled & CSR_INT_BIT_RF_KILL) 1670e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1671e705c121SKalle Valo 1672e705c121SKalle Valo out: 1673e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1674e705c121SKalle Valo return IRQ_HANDLED; 1675e705c121SKalle Valo } 1676e705c121SKalle Valo 1677e705c121SKalle Valo /****************************************************************************** 1678e705c121SKalle Valo * 1679e705c121SKalle Valo * ICT functions 1680e705c121SKalle Valo * 1681e705c121SKalle Valo ******************************************************************************/ 1682e705c121SKalle Valo 1683e705c121SKalle Valo /* Free dram table */ 1684e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans) 1685e705c121SKalle Valo { 1686e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1687e705c121SKalle Valo 1688e705c121SKalle Valo if (trans_pcie->ict_tbl) { 1689e705c121SKalle Valo dma_free_coherent(trans->dev, ICT_SIZE, 1690e705c121SKalle Valo trans_pcie->ict_tbl, 1691e705c121SKalle Valo trans_pcie->ict_tbl_dma); 1692e705c121SKalle Valo trans_pcie->ict_tbl = NULL; 1693e705c121SKalle Valo trans_pcie->ict_tbl_dma = 0; 1694e705c121SKalle Valo } 1695e705c121SKalle Valo } 1696e705c121SKalle Valo 1697e705c121SKalle Valo /* 1698e705c121SKalle Valo * allocate dram shared table, it is an aligned memory 1699e705c121SKalle Valo * block of ICT_SIZE. 1700e705c121SKalle Valo * also reset all data related to ICT table interrupt. 1701e705c121SKalle Valo */ 1702e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans) 1703e705c121SKalle Valo { 1704e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1705e705c121SKalle Valo 1706e705c121SKalle Valo trans_pcie->ict_tbl = 1707e705c121SKalle Valo dma_zalloc_coherent(trans->dev, ICT_SIZE, 1708e705c121SKalle Valo &trans_pcie->ict_tbl_dma, 1709e705c121SKalle Valo GFP_KERNEL); 1710e705c121SKalle Valo if (!trans_pcie->ict_tbl) 1711e705c121SKalle Valo return -ENOMEM; 1712e705c121SKalle Valo 1713e705c121SKalle Valo /* just an API sanity check ... it is guaranteed to be aligned */ 1714e705c121SKalle Valo if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 1715e705c121SKalle Valo iwl_pcie_free_ict(trans); 1716e705c121SKalle Valo return -EINVAL; 1717e705c121SKalle Valo } 1718e705c121SKalle Valo 1719e705c121SKalle Valo return 0; 1720e705c121SKalle Valo } 1721e705c121SKalle Valo 1722e705c121SKalle Valo /* Device is going up inform it about using ICT interrupt table, 1723e705c121SKalle Valo * also we need to tell the driver to start using ICT interrupt. 1724e705c121SKalle Valo */ 1725e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans) 1726e705c121SKalle Valo { 1727e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1728e705c121SKalle Valo u32 val; 1729e705c121SKalle Valo 1730e705c121SKalle Valo if (!trans_pcie->ict_tbl) 1731e705c121SKalle Valo return; 1732e705c121SKalle Valo 1733e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1734e705c121SKalle Valo iwl_disable_interrupts(trans); 1735e705c121SKalle Valo 1736e705c121SKalle Valo memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 1737e705c121SKalle Valo 1738e705c121SKalle Valo val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 1739e705c121SKalle Valo 1740e705c121SKalle Valo val |= CSR_DRAM_INT_TBL_ENABLE | 1741e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRAP_CHECK | 1742e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRITE_POINTER; 1743e705c121SKalle Valo 1744e705c121SKalle Valo IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 1745e705c121SKalle Valo 1746e705c121SKalle Valo iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 1747e705c121SKalle Valo trans_pcie->use_ict = true; 1748e705c121SKalle Valo trans_pcie->ict_index = 0; 1749e705c121SKalle Valo iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 1750e705c121SKalle Valo iwl_enable_interrupts(trans); 1751e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1752e705c121SKalle Valo } 1753e705c121SKalle Valo 1754e705c121SKalle Valo /* Device is going down disable ict interrupt usage */ 1755e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans) 1756e705c121SKalle Valo { 1757e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1758e705c121SKalle Valo 1759e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1760e705c121SKalle Valo trans_pcie->use_ict = false; 1761e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1762e705c121SKalle Valo } 1763e705c121SKalle Valo 1764e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data) 1765e705c121SKalle Valo { 1766e705c121SKalle Valo struct iwl_trans *trans = data; 1767e705c121SKalle Valo 1768e705c121SKalle Valo if (!trans) 1769e705c121SKalle Valo return IRQ_NONE; 1770e705c121SKalle Valo 1771e705c121SKalle Valo /* Disable (but don't clear!) interrupts here to avoid 1772e705c121SKalle Valo * back-to-back ISRs and sporadic interrupts from our NIC. 1773e705c121SKalle Valo * If we have something to service, the tasklet will re-enable ints. 1774e705c121SKalle Valo * If we *don't* have something, we'll re-enable before leaving here. 1775e705c121SKalle Valo */ 1776e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 1777e705c121SKalle Valo 1778e705c121SKalle Valo return IRQ_WAKE_THREAD; 1779e705c121SKalle Valo } 17802e5d4a8fSHaim Dreyfuss 17812e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 17822e5d4a8fSHaim Dreyfuss { 17832e5d4a8fSHaim Dreyfuss return IRQ_WAKE_THREAD; 17842e5d4a8fSHaim Dreyfuss } 17852e5d4a8fSHaim Dreyfuss 17862e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 17872e5d4a8fSHaim Dreyfuss { 17882e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 17892e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 17902e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 17912e5d4a8fSHaim Dreyfuss struct isr_statistics *isr_stats = isr_stats = &trans_pcie->isr_stats; 17922e5d4a8fSHaim Dreyfuss u32 inta_fh, inta_hw; 17932e5d4a8fSHaim Dreyfuss 17942e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 17952e5d4a8fSHaim Dreyfuss 17962e5d4a8fSHaim Dreyfuss spin_lock(&trans_pcie->irq_lock); 17972e5d4a8fSHaim Dreyfuss inta_fh = iwl_read_direct32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 17982e5d4a8fSHaim Dreyfuss inta_hw = iwl_read_direct32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 17992e5d4a8fSHaim Dreyfuss /* 18002e5d4a8fSHaim Dreyfuss * Clear causes registers to avoid being handling the same cause. 18012e5d4a8fSHaim Dreyfuss */ 18022e5d4a8fSHaim Dreyfuss iwl_write_direct32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 18032e5d4a8fSHaim Dreyfuss iwl_write_direct32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 18042e5d4a8fSHaim Dreyfuss spin_unlock(&trans_pcie->irq_lock); 18052e5d4a8fSHaim Dreyfuss 18062e5d4a8fSHaim Dreyfuss if (unlikely(!(inta_fh | inta_hw))) { 18072e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 18082e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 18092e5d4a8fSHaim Dreyfuss return IRQ_NONE; 18102e5d4a8fSHaim Dreyfuss } 18112e5d4a8fSHaim Dreyfuss 18122e5d4a8fSHaim Dreyfuss if (iwl_have_debug_level(IWL_DL_ISR)) 18132e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "ISR inta_fh 0x%08x, enabled 0x%08x\n", 18142e5d4a8fSHaim Dreyfuss inta_fh, 18152e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 18162e5d4a8fSHaim Dreyfuss 18172e5d4a8fSHaim Dreyfuss /* This "Tx" DMA channel is used only for loading uCode */ 18182e5d4a8fSHaim Dreyfuss if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 18192e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 18202e5d4a8fSHaim Dreyfuss isr_stats->tx++; 18212e5d4a8fSHaim Dreyfuss /* 18222e5d4a8fSHaim Dreyfuss * Wake up uCode load routine, 18232e5d4a8fSHaim Dreyfuss * now that load is complete 18242e5d4a8fSHaim Dreyfuss */ 18252e5d4a8fSHaim Dreyfuss trans_pcie->ucode_write_complete = true; 18262e5d4a8fSHaim Dreyfuss wake_up(&trans_pcie->ucode_write_waitq); 18272e5d4a8fSHaim Dreyfuss } 18282e5d4a8fSHaim Dreyfuss 18292e5d4a8fSHaim Dreyfuss /* Error detected by uCode */ 18302e5d4a8fSHaim Dreyfuss if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 18312e5d4a8fSHaim Dreyfuss (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) { 18322e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 18332e5d4a8fSHaim Dreyfuss "Microcode SW error detected. Restarting 0x%X.\n", 18342e5d4a8fSHaim Dreyfuss inta_fh); 18352e5d4a8fSHaim Dreyfuss isr_stats->sw++; 18362e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 18372e5d4a8fSHaim Dreyfuss } 18382e5d4a8fSHaim Dreyfuss 18392e5d4a8fSHaim Dreyfuss /* After checking FH register check HW register */ 18402e5d4a8fSHaim Dreyfuss if (iwl_have_debug_level(IWL_DL_ISR)) 18412e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, 18422e5d4a8fSHaim Dreyfuss "ISR inta_hw 0x%08x, enabled 0x%08x\n", 18432e5d4a8fSHaim Dreyfuss inta_hw, 18442e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 18452e5d4a8fSHaim Dreyfuss 18462e5d4a8fSHaim Dreyfuss /* Alive notification via Rx interrupt will do the real work */ 18472e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 18482e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 18492e5d4a8fSHaim Dreyfuss isr_stats->alive++; 18502e5d4a8fSHaim Dreyfuss } 18512e5d4a8fSHaim Dreyfuss 18522e5d4a8fSHaim Dreyfuss /* uCode wakes up after power-down sleep */ 18532e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 18542e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 18552e5d4a8fSHaim Dreyfuss iwl_pcie_rxq_check_wrptr(trans); 18562e5d4a8fSHaim Dreyfuss iwl_pcie_txq_check_wrptrs(trans); 18572e5d4a8fSHaim Dreyfuss 18582e5d4a8fSHaim Dreyfuss isr_stats->wakeup++; 18592e5d4a8fSHaim Dreyfuss } 18602e5d4a8fSHaim Dreyfuss 18612e5d4a8fSHaim Dreyfuss /* Chip got too hot and stopped itself */ 18622e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 18632e5d4a8fSHaim Dreyfuss IWL_ERR(trans, "Microcode CT kill error detected.\n"); 18642e5d4a8fSHaim Dreyfuss isr_stats->ctkill++; 18652e5d4a8fSHaim Dreyfuss } 18662e5d4a8fSHaim Dreyfuss 18672e5d4a8fSHaim Dreyfuss /* HW RF KILL switch toggled */ 18682e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) { 18692e5d4a8fSHaim Dreyfuss bool hw_rfkill; 18702e5d4a8fSHaim Dreyfuss 18712e5d4a8fSHaim Dreyfuss hw_rfkill = iwl_is_rfkill_set(trans); 18722e5d4a8fSHaim Dreyfuss IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 18732e5d4a8fSHaim Dreyfuss hw_rfkill ? "disable radio" : "enable radio"); 18742e5d4a8fSHaim Dreyfuss 18752e5d4a8fSHaim Dreyfuss isr_stats->rfkill++; 18762e5d4a8fSHaim Dreyfuss 18772e5d4a8fSHaim Dreyfuss mutex_lock(&trans_pcie->mutex); 18782e5d4a8fSHaim Dreyfuss iwl_trans_pcie_rf_kill(trans, hw_rfkill); 18792e5d4a8fSHaim Dreyfuss mutex_unlock(&trans_pcie->mutex); 18802e5d4a8fSHaim Dreyfuss if (hw_rfkill) { 18812e5d4a8fSHaim Dreyfuss set_bit(STATUS_RFKILL, &trans->status); 18822e5d4a8fSHaim Dreyfuss if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 18832e5d4a8fSHaim Dreyfuss &trans->status)) 18842e5d4a8fSHaim Dreyfuss IWL_DEBUG_RF_KILL(trans, 18852e5d4a8fSHaim Dreyfuss "Rfkill while SYNC HCMD in flight\n"); 18862e5d4a8fSHaim Dreyfuss wake_up(&trans_pcie->wait_command_queue); 18872e5d4a8fSHaim Dreyfuss } else { 18882e5d4a8fSHaim Dreyfuss clear_bit(STATUS_RFKILL, &trans->status); 18892e5d4a8fSHaim Dreyfuss } 18902e5d4a8fSHaim Dreyfuss } 18912e5d4a8fSHaim Dreyfuss 18922e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 18932e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 18942e5d4a8fSHaim Dreyfuss "Hardware error detected. Restarting.\n"); 18952e5d4a8fSHaim Dreyfuss 18962e5d4a8fSHaim Dreyfuss isr_stats->hw++; 18972e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 18982e5d4a8fSHaim Dreyfuss } 18992e5d4a8fSHaim Dreyfuss 19002e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 19012e5d4a8fSHaim Dreyfuss 19022e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 19032e5d4a8fSHaim Dreyfuss 19042e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 19052e5d4a8fSHaim Dreyfuss } 1906