1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3cefec29eSJohannes Berg * This file is provided under a dual BSD/GPLv2 license. When using or 4cefec29eSJohannes Berg * redistributing this file, you may do so under either license. 5cefec29eSJohannes Berg * 6cefec29eSJohannes Berg * GPL LICENSE SUMMARY 7cefec29eSJohannes Berg * 8e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 14e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 18e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20e705c121SKalle Valo * more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 23cefec29eSJohannes Berg * file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26d01c5366SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29cefec29eSJohannes Berg * BSD LICENSE 30cefec29eSJohannes Berg * 31cefec29eSJohannes Berg * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 32cefec29eSJohannes Berg * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33cefec29eSJohannes Berg * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 35cefec29eSJohannes Berg * All rights reserved. 36cefec29eSJohannes Berg * 37cefec29eSJohannes Berg * Redistribution and use in source and binary forms, with or without 38cefec29eSJohannes Berg * modification, are permitted provided that the following conditions 39cefec29eSJohannes Berg * are met: 40cefec29eSJohannes Berg * 41cefec29eSJohannes Berg * * Redistributions of source code must retain the above copyright 42cefec29eSJohannes Berg * notice, this list of conditions and the following disclaimer. 43cefec29eSJohannes Berg * * Redistributions in binary form must reproduce the above copyright 44cefec29eSJohannes Berg * notice, this list of conditions and the following disclaimer in 45cefec29eSJohannes Berg * the documentation and/or other materials provided with the 46cefec29eSJohannes Berg * distribution. 47cefec29eSJohannes Berg * * Neither the name Intel Corporation nor the names of its 48cefec29eSJohannes Berg * contributors may be used to endorse or promote products derived 49cefec29eSJohannes Berg * from this software without specific prior written permission. 50cefec29eSJohannes Berg * 51cefec29eSJohannes Berg * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52cefec29eSJohannes Berg * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53cefec29eSJohannes Berg * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54cefec29eSJohannes Berg * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55cefec29eSJohannes Berg * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56cefec29eSJohannes Berg * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57cefec29eSJohannes Berg * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58cefec29eSJohannes Berg * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59cefec29eSJohannes Berg * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60cefec29eSJohannes Berg * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61cefec29eSJohannes Berg * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62cefec29eSJohannes Berg * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #include <linux/sched.h> 65e705c121SKalle Valo #include <linux/wait.h> 66e705c121SKalle Valo #include <linux/gfp.h> 67e705c121SKalle Valo 68e705c121SKalle Valo #include "iwl-prph.h" 69e705c121SKalle Valo #include "iwl-io.h" 70e705c121SKalle Valo #include "internal.h" 71e705c121SKalle Valo #include "iwl-op-mode.h" 729b58419eSGolan Ben Ami #include "iwl-context-info-gen3.h" 73e705c121SKalle Valo 74e705c121SKalle Valo /****************************************************************************** 75e705c121SKalle Valo * 76e705c121SKalle Valo * RX path functions 77e705c121SKalle Valo * 78e705c121SKalle Valo ******************************************************************************/ 79e705c121SKalle Valo 80e705c121SKalle Valo /* 81e705c121SKalle Valo * Rx theory of operation 82e705c121SKalle Valo * 83e705c121SKalle Valo * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 84e705c121SKalle Valo * each of which point to Receive Buffers to be filled by the NIC. These get 85e705c121SKalle Valo * used not only for Rx frames, but for any command response or notification 86e705c121SKalle Valo * from the NIC. The driver and NIC manage the Rx buffers by means 87e705c121SKalle Valo * of indexes into the circular buffer. 88e705c121SKalle Valo * 89e705c121SKalle Valo * Rx Queue Indexes 90e705c121SKalle Valo * The host/firmware share two index registers for managing the Rx buffers. 91e705c121SKalle Valo * 92e705c121SKalle Valo * The READ index maps to the first position that the firmware may be writing 93e705c121SKalle Valo * to -- the driver can read up to (but not including) this position and get 94e705c121SKalle Valo * good data. 95e705c121SKalle Valo * The READ index is managed by the firmware once the card is enabled. 96e705c121SKalle Valo * 97e705c121SKalle Valo * The WRITE index maps to the last position the driver has read from -- the 98e705c121SKalle Valo * position preceding WRITE is the last slot the firmware can place a packet. 99e705c121SKalle Valo * 100e705c121SKalle Valo * The queue is empty (no good data) if WRITE = READ - 1, and is full if 101e705c121SKalle Valo * WRITE = READ. 102e705c121SKalle Valo * 103e705c121SKalle Valo * During initialization, the host sets up the READ queue position to the first 104e705c121SKalle Valo * INDEX position, and WRITE to the last (READ - 1 wrapped) 105e705c121SKalle Valo * 106e705c121SKalle Valo * When the firmware places a packet in a buffer, it will advance the READ index 107e705c121SKalle Valo * and fire the RX interrupt. The driver can then query the READ index and 108e705c121SKalle Valo * process as many packets as possible, moving the WRITE index forward as it 109e705c121SKalle Valo * resets the Rx queue buffers with new memory. 110e705c121SKalle Valo * 111e705c121SKalle Valo * The management in the driver is as follows: 112e705c121SKalle Valo * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 113e705c121SKalle Valo * When the interrupt handler is called, the request is processed. 114e705c121SKalle Valo * The page is either stolen - transferred to the upper layer 115e705c121SKalle Valo * or reused - added immediately to the iwl->rxq->rx_free list. 116e705c121SKalle Valo * + When the page is stolen - the driver updates the matching queue's used 117e705c121SKalle Valo * count, detaches the RBD and transfers it to the queue used list. 118e705c121SKalle Valo * When there are two used RBDs - they are transferred to the allocator empty 119e705c121SKalle Valo * list. Work is then scheduled for the allocator to start allocating 120e705c121SKalle Valo * eight buffers. 121e705c121SKalle Valo * When there are another 6 used RBDs - they are transferred to the allocator 122e705c121SKalle Valo * empty list and the driver tries to claim the pre-allocated buffers and 123e705c121SKalle Valo * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 124e705c121SKalle Valo * until ready. 125e705c121SKalle Valo * When there are 8+ buffers in the free list - either from allocation or from 126e705c121SKalle Valo * 8 reused unstolen pages - restock is called to update the FW and indexes. 127e705c121SKalle Valo * + In order to make sure the allocator always has RBDs to use for allocation 128e705c121SKalle Valo * the allocator has initial pool in the size of num_queues*(8-2) - the 129e705c121SKalle Valo * maximum missing RBDs per allocation request (request posted with 2 130e705c121SKalle Valo * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 131e705c121SKalle Valo * The queues supplies the recycle of the rest of the RBDs. 132e705c121SKalle Valo * + A received packet is processed and handed to the kernel network stack, 133e705c121SKalle Valo * detached from the iwl->rxq. The driver 'processed' index is updated. 134e705c121SKalle Valo * + If there are no allocated buffers in iwl->rxq->rx_free, 135e705c121SKalle Valo * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 136e705c121SKalle Valo * If there were enough free buffers and RX_STALLED is set it is cleared. 137e705c121SKalle Valo * 138e705c121SKalle Valo * 139e705c121SKalle Valo * Driver sequence: 140e705c121SKalle Valo * 141e705c121SKalle Valo * iwl_rxq_alloc() Allocates rx_free 142e705c121SKalle Valo * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 143e705c121SKalle Valo * iwl_pcie_rxq_restock. 144e705c121SKalle Valo * Used only during initialization. 145e705c121SKalle Valo * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 146e705c121SKalle Valo * queue, updates firmware pointers, and updates 147e705c121SKalle Valo * the WRITE index. 148e705c121SKalle Valo * iwl_pcie_rx_allocator() Background work for allocating pages. 149e705c121SKalle Valo * 150e705c121SKalle Valo * -- enable interrupts -- 151e705c121SKalle Valo * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 152e705c121SKalle Valo * READ INDEX, detaching the SKB from the pool. 153e705c121SKalle Valo * Moves the packet buffer from queue to rx_used. 154e705c121SKalle Valo * Posts and claims requests to the allocator. 155e705c121SKalle Valo * Calls iwl_pcie_rxq_restock to refill any empty 156e705c121SKalle Valo * slots. 157e705c121SKalle Valo * 158e705c121SKalle Valo * RBD life-cycle: 159e705c121SKalle Valo * 160e705c121SKalle Valo * Init: 161e705c121SKalle Valo * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 162e705c121SKalle Valo * 163e705c121SKalle Valo * Regular Receive interrupt: 164e705c121SKalle Valo * Page Stolen: 165e705c121SKalle Valo * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 166e705c121SKalle Valo * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 167e705c121SKalle Valo * Page not Stolen: 168e705c121SKalle Valo * rxq.queue -> rxq.rx_free -> rxq.queue 169e705c121SKalle Valo * ... 170e705c121SKalle Valo * 171e705c121SKalle Valo */ 172e705c121SKalle Valo 173e705c121SKalle Valo /* 174e705c121SKalle Valo * iwl_rxq_space - Return number of free slots available in queue. 175e705c121SKalle Valo */ 176e705c121SKalle Valo static int iwl_rxq_space(const struct iwl_rxq *rxq) 177e705c121SKalle Valo { 17896a6497bSSara Sharon /* Make sure rx queue size is a power of 2 */ 17996a6497bSSara Sharon WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 180e705c121SKalle Valo 181e705c121SKalle Valo /* 182e705c121SKalle Valo * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 183e705c121SKalle Valo * between empty and completely full queues. 184e705c121SKalle Valo * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 185e705c121SKalle Valo * defined for negative dividends. 186e705c121SKalle Valo */ 18796a6497bSSara Sharon return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 188e705c121SKalle Valo } 189e705c121SKalle Valo 190e705c121SKalle Valo /* 191e705c121SKalle Valo * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 192e705c121SKalle Valo */ 193e705c121SKalle Valo static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 194e705c121SKalle Valo { 195e705c121SKalle Valo return cpu_to_le32((u32)(dma_addr >> 8)); 196e705c121SKalle Valo } 197e705c121SKalle Valo 198e705c121SKalle Valo /* 199e705c121SKalle Valo * iwl_pcie_rx_stop - stops the Rx DMA 200e705c121SKalle Valo */ 201e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans) 202e705c121SKalle Valo { 203d0158235SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 204d0158235SGolan Ben Ami /* TODO: remove this for 22560 once fw does it */ 205ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 206ea695b7cSShaul Triebitz return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3, 207d0158235SGolan Ben Ami RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 208d0158235SGolan Ben Ami } else if (trans->cfg->mq_rx_supported) { 209d7fdd0e5SSara Sharon iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 210d7fdd0e5SSara Sharon return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 211d7fdd0e5SSara Sharon RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 212d7fdd0e5SSara Sharon } else { 213e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 214e705c121SKalle Valo return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 215d7fdd0e5SSara Sharon FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 216d7fdd0e5SSara Sharon 1000); 217d7fdd0e5SSara Sharon } 218e705c121SKalle Valo } 219e705c121SKalle Valo 220e705c121SKalle Valo /* 221e705c121SKalle Valo * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 222e705c121SKalle Valo */ 22378485054SSara Sharon static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 22478485054SSara Sharon struct iwl_rxq *rxq) 225e705c121SKalle Valo { 226e705c121SKalle Valo u32 reg; 227e705c121SKalle Valo 228e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 229e705c121SKalle Valo 230e705c121SKalle Valo /* 231e705c121SKalle Valo * explicitly wake up the NIC if: 232e705c121SKalle Valo * 1. shadow registers aren't enabled 233e705c121SKalle Valo * 2. there is a chance that the NIC is asleep 234e705c121SKalle Valo */ 235e705c121SKalle Valo if (!trans->cfg->base_params->shadow_reg_enable && 236e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 237e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 238e705c121SKalle Valo 239e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 240e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 241e705c121SKalle Valo reg); 242e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 243a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 244e705c121SKalle Valo rxq->need_update = true; 245e705c121SKalle Valo return; 246e705c121SKalle Valo } 247e705c121SKalle Valo } 248e705c121SKalle Valo 249e705c121SKalle Valo rxq->write_actual = round_down(rxq->write, 8); 250ff911dcaSShaul Triebitz if (trans->cfg->device_family == IWL_DEVICE_FAMILY_22560) 2511b493e30SGolan Ben Ami iwl_write32(trans, HBUS_TARG_WRPTR, 2521b493e30SGolan Ben Ami (rxq->write_actual | 2531b493e30SGolan Ben Ami ((FIRST_RX_QUEUE + rxq->id) << 16))); 2541b493e30SGolan Ben Ami else if (trans->cfg->mq_rx_supported) 2551554ed20SSara Sharon iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 25696a6497bSSara Sharon rxq->write_actual); 2571316d595SSara Sharon else 258e705c121SKalle Valo iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 259e705c121SKalle Valo } 260e705c121SKalle Valo 261e705c121SKalle Valo static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 262e705c121SKalle Valo { 263e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 26478485054SSara Sharon int i; 265e705c121SKalle Valo 26678485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 26778485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 268e705c121SKalle Valo 269e705c121SKalle Valo if (!rxq->need_update) 27078485054SSara Sharon continue; 27178485054SSara Sharon spin_lock(&rxq->lock); 27278485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 273e705c121SKalle Valo rxq->need_update = false; 274e705c121SKalle Valo spin_unlock(&rxq->lock); 275e705c121SKalle Valo } 27678485054SSara Sharon } 277e705c121SKalle Valo 2780307c839SGolan Ben Ami static void iwl_pcie_restock_bd(struct iwl_trans *trans, 2790307c839SGolan Ben Ami struct iwl_rxq *rxq, 2800307c839SGolan Ben Ami struct iwl_rx_mem_buffer *rxb) 2810307c839SGolan Ben Ami { 2820307c839SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 2830307c839SGolan Ben Ami struct iwl_rx_transfer_desc *bd = rxq->bd; 2840307c839SGolan Ben Ami 285f826faaaSJohannes Berg BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64)); 286f826faaaSJohannes Berg 2870307c839SGolan Ben Ami bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 2880307c839SGolan Ben Ami bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 2890307c839SGolan Ben Ami } else { 2900307c839SGolan Ben Ami __le64 *bd = rxq->bd; 2910307c839SGolan Ben Ami 2920307c839SGolan Ben Ami bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 2930307c839SGolan Ben Ami } 29485d78bb1SSara Sharon 29585d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n", 29685d78bb1SSara Sharon (u32)rxb->vid, rxq->id, rxq->write); 2970307c839SGolan Ben Ami } 2980307c839SGolan Ben Ami 299e0e168dcSGregory Greenman /* 3002047fa54SSara Sharon * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 301e0e168dcSGregory Greenman */ 3022047fa54SSara Sharon static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 30396a6497bSSara Sharon struct iwl_rxq *rxq) 30496a6497bSSara Sharon { 30596a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb; 30696a6497bSSara Sharon 30796a6497bSSara Sharon /* 30896a6497bSSara Sharon * If the device isn't enabled - no need to try to add buffers... 30996a6497bSSara Sharon * This can happen when we stop the device and still have an interrupt 31096a6497bSSara Sharon * pending. We stop the APM before we sync the interrupts because we 31196a6497bSSara Sharon * have to (see comment there). On the other hand, since the APM is 31296a6497bSSara Sharon * stopped, we cannot access the HW (in particular not prph). 31396a6497bSSara Sharon * So don't try to restock if the APM has been already stopped. 31496a6497bSSara Sharon */ 31596a6497bSSara Sharon if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 31696a6497bSSara Sharon return; 31796a6497bSSara Sharon 31896a6497bSSara Sharon spin_lock(&rxq->lock); 31996a6497bSSara Sharon while (rxq->free_count) { 32096a6497bSSara Sharon /* Get next free Rx buffer, remove from free list */ 32196a6497bSSara Sharon rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 32296a6497bSSara Sharon list); 32396a6497bSSara Sharon list_del(&rxb->list); 324b1753c62SSara Sharon rxb->invalid = false; 32596a6497bSSara Sharon /* 12 first bits are expected to be empty */ 32696a6497bSSara Sharon WARN_ON(rxb->page_dma & DMA_BIT_MASK(12)); 32796a6497bSSara Sharon /* Point to Rx buffer via next RBD in circular buffer */ 3280307c839SGolan Ben Ami iwl_pcie_restock_bd(trans, rxq, rxb); 32996a6497bSSara Sharon rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK; 33096a6497bSSara Sharon rxq->free_count--; 33196a6497bSSara Sharon } 33296a6497bSSara Sharon spin_unlock(&rxq->lock); 33396a6497bSSara Sharon 33496a6497bSSara Sharon /* 33596a6497bSSara Sharon * If we've added more space for the firmware to place data, tell it. 33696a6497bSSara Sharon * Increment device's write pointer in multiples of 8. 33796a6497bSSara Sharon */ 33896a6497bSSara Sharon if (rxq->write_actual != (rxq->write & ~0x7)) { 33996a6497bSSara Sharon spin_lock(&rxq->lock); 34096a6497bSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 34196a6497bSSara Sharon spin_unlock(&rxq->lock); 34296a6497bSSara Sharon } 34396a6497bSSara Sharon } 34496a6497bSSara Sharon 345e705c121SKalle Valo /* 3462047fa54SSara Sharon * iwl_pcie_rxsq_restock - restock implementation for single queue rx 347e705c121SKalle Valo */ 3482047fa54SSara Sharon static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 349e0e168dcSGregory Greenman struct iwl_rxq *rxq) 350e705c121SKalle Valo { 351e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 352e705c121SKalle Valo 353e705c121SKalle Valo /* 354e705c121SKalle Valo * If the device isn't enabled - not need to try to add buffers... 355e705c121SKalle Valo * This can happen when we stop the device and still have an interrupt 356e705c121SKalle Valo * pending. We stop the APM before we sync the interrupts because we 357e705c121SKalle Valo * have to (see comment there). On the other hand, since the APM is 358e705c121SKalle Valo * stopped, we cannot access the HW (in particular not prph). 359e705c121SKalle Valo * So don't try to restock if the APM has been already stopped. 360e705c121SKalle Valo */ 361e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 362e705c121SKalle Valo return; 363e705c121SKalle Valo 364e705c121SKalle Valo spin_lock(&rxq->lock); 365e705c121SKalle Valo while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 36696a6497bSSara Sharon __le32 *bd = (__le32 *)rxq->bd; 367e705c121SKalle Valo /* The overwritten rxb must be a used one */ 368e705c121SKalle Valo rxb = rxq->queue[rxq->write]; 369e705c121SKalle Valo BUG_ON(rxb && rxb->page); 370e705c121SKalle Valo 371e705c121SKalle Valo /* Get next free Rx buffer, remove from free list */ 372e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 373e705c121SKalle Valo list); 374e705c121SKalle Valo list_del(&rxb->list); 375b1753c62SSara Sharon rxb->invalid = false; 376e705c121SKalle Valo 377e705c121SKalle Valo /* Point to Rx buffer via next RBD in circular buffer */ 37896a6497bSSara Sharon bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 379e705c121SKalle Valo rxq->queue[rxq->write] = rxb; 380e705c121SKalle Valo rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 381e705c121SKalle Valo rxq->free_count--; 382e705c121SKalle Valo } 383e705c121SKalle Valo spin_unlock(&rxq->lock); 384e705c121SKalle Valo 385e705c121SKalle Valo /* If we've added more space for the firmware to place data, tell it. 386e705c121SKalle Valo * Increment device's write pointer in multiples of 8. */ 387e705c121SKalle Valo if (rxq->write_actual != (rxq->write & ~0x7)) { 388e705c121SKalle Valo spin_lock(&rxq->lock); 38978485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 390e705c121SKalle Valo spin_unlock(&rxq->lock); 391e705c121SKalle Valo } 392e705c121SKalle Valo } 393e705c121SKalle Valo 394e705c121SKalle Valo /* 395e0e168dcSGregory Greenman * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 396e0e168dcSGregory Greenman * 397e0e168dcSGregory Greenman * If there are slots in the RX queue that need to be restocked, 398e0e168dcSGregory Greenman * and we have free pre-allocated buffers, fill the ranks as much 399e0e168dcSGregory Greenman * as we can, pulling from rx_free. 400e0e168dcSGregory Greenman * 401e0e168dcSGregory Greenman * This moves the 'write' index forward to catch up with 'processed', and 402e0e168dcSGregory Greenman * also updates the memory address in the firmware to reference the new 403e0e168dcSGregory Greenman * target buffer. 404e0e168dcSGregory Greenman */ 405e0e168dcSGregory Greenman static 406e0e168dcSGregory Greenman void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 407e0e168dcSGregory Greenman { 408e0e168dcSGregory Greenman if (trans->cfg->mq_rx_supported) 4092047fa54SSara Sharon iwl_pcie_rxmq_restock(trans, rxq); 410e0e168dcSGregory Greenman else 4112047fa54SSara Sharon iwl_pcie_rxsq_restock(trans, rxq); 412e0e168dcSGregory Greenman } 413e0e168dcSGregory Greenman 414e0e168dcSGregory Greenman /* 415e705c121SKalle Valo * iwl_pcie_rx_alloc_page - allocates and returns a page. 416e705c121SKalle Valo * 417e705c121SKalle Valo */ 418e705c121SKalle Valo static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 419e705c121SKalle Valo gfp_t priority) 420e705c121SKalle Valo { 421e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 422e705c121SKalle Valo struct page *page; 423e705c121SKalle Valo gfp_t gfp_mask = priority; 424e705c121SKalle Valo 425e705c121SKalle Valo if (trans_pcie->rx_page_order > 0) 426e705c121SKalle Valo gfp_mask |= __GFP_COMP; 427e705c121SKalle Valo 428e705c121SKalle Valo /* Alloc a new receive buffer */ 429e705c121SKalle Valo page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 430e705c121SKalle Valo if (!page) { 431e705c121SKalle Valo if (net_ratelimit()) 432e705c121SKalle Valo IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 433e705c121SKalle Valo trans_pcie->rx_page_order); 43478485054SSara Sharon /* 43578485054SSara Sharon * Issue an error if we don't have enough pre-allocated 43678485054SSara Sharon * buffers. 4371da3823dSLuca Coelho */ 43878485054SSara Sharon if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 439e705c121SKalle Valo IWL_CRIT(trans, 44078485054SSara Sharon "Failed to alloc_pages\n"); 441e705c121SKalle Valo return NULL; 442e705c121SKalle Valo } 443e705c121SKalle Valo return page; 444e705c121SKalle Valo } 445e705c121SKalle Valo 446e705c121SKalle Valo /* 447e705c121SKalle Valo * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 448e705c121SKalle Valo * 449e705c121SKalle Valo * A used RBD is an Rx buffer that has been given to the stack. To use it again 450e705c121SKalle Valo * a page must be allocated and the RBD must point to the page. This function 451e705c121SKalle Valo * doesn't change the HW pointer but handles the list of pages that is used by 452e705c121SKalle Valo * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 453e705c121SKalle Valo * allocated buffers. 454e705c121SKalle Valo */ 455ff932f61SGolan Ben Ami void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 45678485054SSara Sharon struct iwl_rxq *rxq) 457e705c121SKalle Valo { 458e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 459e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 460e705c121SKalle Valo struct page *page; 461e705c121SKalle Valo 462e705c121SKalle Valo while (1) { 463e705c121SKalle Valo spin_lock(&rxq->lock); 464e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 465e705c121SKalle Valo spin_unlock(&rxq->lock); 466e705c121SKalle Valo return; 467e705c121SKalle Valo } 468e705c121SKalle Valo spin_unlock(&rxq->lock); 469e705c121SKalle Valo 470e705c121SKalle Valo /* Alloc a new receive buffer */ 471e705c121SKalle Valo page = iwl_pcie_rx_alloc_page(trans, priority); 472e705c121SKalle Valo if (!page) 473e705c121SKalle Valo return; 474e705c121SKalle Valo 475e705c121SKalle Valo spin_lock(&rxq->lock); 476e705c121SKalle Valo 477e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 478e705c121SKalle Valo spin_unlock(&rxq->lock); 479e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 480e705c121SKalle Valo return; 481e705c121SKalle Valo } 482e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 483e705c121SKalle Valo list); 484e705c121SKalle Valo list_del(&rxb->list); 485e705c121SKalle Valo spin_unlock(&rxq->lock); 486e705c121SKalle Valo 487e705c121SKalle Valo BUG_ON(rxb->page); 488e705c121SKalle Valo rxb->page = page; 489e705c121SKalle Valo /* Get physical address of the RB */ 490e705c121SKalle Valo rxb->page_dma = 491e705c121SKalle Valo dma_map_page(trans->dev, page, 0, 492e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 493e705c121SKalle Valo DMA_FROM_DEVICE); 494e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 495e705c121SKalle Valo rxb->page = NULL; 496e705c121SKalle Valo spin_lock(&rxq->lock); 497e705c121SKalle Valo list_add(&rxb->list, &rxq->rx_used); 498e705c121SKalle Valo spin_unlock(&rxq->lock); 499e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 500e705c121SKalle Valo return; 501e705c121SKalle Valo } 502e705c121SKalle Valo 503e705c121SKalle Valo spin_lock(&rxq->lock); 504e705c121SKalle Valo 505e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 506e705c121SKalle Valo rxq->free_count++; 507e705c121SKalle Valo 508e705c121SKalle Valo spin_unlock(&rxq->lock); 509e705c121SKalle Valo } 510e705c121SKalle Valo } 511e705c121SKalle Valo 512ff932f61SGolan Ben Ami void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 513e705c121SKalle Valo { 514e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 515e705c121SKalle Valo int i; 516e705c121SKalle Valo 5177b542436SSara Sharon for (i = 0; i < RX_POOL_SIZE; i++) { 51878485054SSara Sharon if (!trans_pcie->rx_pool[i].page) 519e705c121SKalle Valo continue; 52078485054SSara Sharon dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 521e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 522e705c121SKalle Valo DMA_FROM_DEVICE); 52378485054SSara Sharon __free_pages(trans_pcie->rx_pool[i].page, 52478485054SSara Sharon trans_pcie->rx_page_order); 52578485054SSara Sharon trans_pcie->rx_pool[i].page = NULL; 526e705c121SKalle Valo } 527e705c121SKalle Valo } 528e705c121SKalle Valo 529e705c121SKalle Valo /* 530e705c121SKalle Valo * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 531e705c121SKalle Valo * 532e705c121SKalle Valo * Allocates for each received request 8 pages 533e705c121SKalle Valo * Called as a scheduled work item. 534e705c121SKalle Valo */ 535e705c121SKalle Valo static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 536e705c121SKalle Valo { 537e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 538e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 539e705c121SKalle Valo struct list_head local_empty; 540c6ac9f9fSSara Sharon int pending = atomic_read(&rba->req_pending); 541e705c121SKalle Valo 5426dcdd165SSara Sharon IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending); 543e705c121SKalle Valo 544e705c121SKalle Valo /* If we were scheduled - there is at least one request */ 545e705c121SKalle Valo spin_lock(&rba->lock); 546e705c121SKalle Valo /* swap out the rba->rbd_empty to a local list */ 547e705c121SKalle Valo list_replace_init(&rba->rbd_empty, &local_empty); 548e705c121SKalle Valo spin_unlock(&rba->lock); 549e705c121SKalle Valo 550e705c121SKalle Valo while (pending) { 551e705c121SKalle Valo int i; 5520979a913SJohannes Berg LIST_HEAD(local_allocated); 55378485054SSara Sharon gfp_t gfp_mask = GFP_KERNEL; 55478485054SSara Sharon 55578485054SSara Sharon /* Do not post a warning if there are only a few requests */ 55678485054SSara Sharon if (pending < RX_PENDING_WATERMARK) 55778485054SSara Sharon gfp_mask |= __GFP_NOWARN; 558e705c121SKalle Valo 559e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 560e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 561e705c121SKalle Valo struct page *page; 562e705c121SKalle Valo 563e705c121SKalle Valo /* List should never be empty - each reused RBD is 564e705c121SKalle Valo * returned to the list, and initial pool covers any 565e705c121SKalle Valo * possible gap between the time the page is allocated 566e705c121SKalle Valo * to the time the RBD is added. 567e705c121SKalle Valo */ 568e705c121SKalle Valo BUG_ON(list_empty(&local_empty)); 569e705c121SKalle Valo /* Get the first rxb from the rbd list */ 570e705c121SKalle Valo rxb = list_first_entry(&local_empty, 571e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 572e705c121SKalle Valo BUG_ON(rxb->page); 573e705c121SKalle Valo 574e705c121SKalle Valo /* Alloc a new receive buffer */ 57578485054SSara Sharon page = iwl_pcie_rx_alloc_page(trans, gfp_mask); 576e705c121SKalle Valo if (!page) 577e705c121SKalle Valo continue; 578e705c121SKalle Valo rxb->page = page; 579e705c121SKalle Valo 580e705c121SKalle Valo /* Get physical address of the RB */ 581e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, page, 0, 582e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 583e705c121SKalle Valo DMA_FROM_DEVICE); 584e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 585e705c121SKalle Valo rxb->page = NULL; 586e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 587e705c121SKalle Valo continue; 588e705c121SKalle Valo } 589e705c121SKalle Valo 590e705c121SKalle Valo /* move the allocated entry to the out list */ 591e705c121SKalle Valo list_move(&rxb->list, &local_allocated); 592e705c121SKalle Valo i++; 593e705c121SKalle Valo } 594e705c121SKalle Valo 595c6ac9f9fSSara Sharon atomic_dec(&rba->req_pending); 596e705c121SKalle Valo pending--; 597c6ac9f9fSSara Sharon 598e705c121SKalle Valo if (!pending) { 599c6ac9f9fSSara Sharon pending = atomic_read(&rba->req_pending); 6006dcdd165SSara Sharon if (pending) 6016dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 602c6ac9f9fSSara Sharon "Got more pending allocation requests = %d\n", 603e705c121SKalle Valo pending); 604e705c121SKalle Valo } 605e705c121SKalle Valo 606e705c121SKalle Valo spin_lock(&rba->lock); 607e705c121SKalle Valo /* add the allocated rbds to the allocator allocated list */ 608e705c121SKalle Valo list_splice_tail(&local_allocated, &rba->rbd_allocated); 609e705c121SKalle Valo /* get more empty RBDs for current pending requests */ 610e705c121SKalle Valo list_splice_tail_init(&rba->rbd_empty, &local_empty); 611e705c121SKalle Valo spin_unlock(&rba->lock); 612e705c121SKalle Valo 613e705c121SKalle Valo atomic_inc(&rba->req_ready); 614c6ac9f9fSSara Sharon 615e705c121SKalle Valo } 616e705c121SKalle Valo 617e705c121SKalle Valo spin_lock(&rba->lock); 618e705c121SKalle Valo /* return unused rbds to the allocator empty list */ 619e705c121SKalle Valo list_splice_tail(&local_empty, &rba->rbd_empty); 620e705c121SKalle Valo spin_unlock(&rba->lock); 621c6ac9f9fSSara Sharon 6226dcdd165SSara Sharon IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__); 623e705c121SKalle Valo } 624e705c121SKalle Valo 625e705c121SKalle Valo /* 626d56daea4SSara Sharon * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 627e705c121SKalle Valo .* 628e705c121SKalle Valo .* Called by queue when the queue posted allocation request and 629e705c121SKalle Valo * has freed 8 RBDs in order to restock itself. 630d56daea4SSara Sharon * This function directly moves the allocated RBs to the queue's ownership 631d56daea4SSara Sharon * and updates the relevant counters. 632e705c121SKalle Valo */ 633d56daea4SSara Sharon static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 634d56daea4SSara Sharon struct iwl_rxq *rxq) 635e705c121SKalle Valo { 636e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 637e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 638e705c121SKalle Valo int i; 639e705c121SKalle Valo 640d56daea4SSara Sharon lockdep_assert_held(&rxq->lock); 641d56daea4SSara Sharon 642e705c121SKalle Valo /* 643e705c121SKalle Valo * atomic_dec_if_positive returns req_ready - 1 for any scenario. 644e705c121SKalle Valo * If req_ready is 0 atomic_dec_if_positive will return -1 and this 645d56daea4SSara Sharon * function will return early, as there are no ready requests. 646e705c121SKalle Valo * atomic_dec_if_positive will perofrm the *actual* decrement only if 647e705c121SKalle Valo * req_ready > 0, i.e. - there are ready requests and the function 648e705c121SKalle Valo * hands one request to the caller. 649e705c121SKalle Valo */ 650e705c121SKalle Valo if (atomic_dec_if_positive(&rba->req_ready) < 0) 651d56daea4SSara Sharon return; 652e705c121SKalle Valo 653e705c121SKalle Valo spin_lock(&rba->lock); 654e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 655e705c121SKalle Valo /* Get next free Rx buffer, remove it from free list */ 656d56daea4SSara Sharon struct iwl_rx_mem_buffer *rxb = 657d56daea4SSara Sharon list_first_entry(&rba->rbd_allocated, 658e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 659d56daea4SSara Sharon 660d56daea4SSara Sharon list_move(&rxb->list, &rxq->rx_free); 661e705c121SKalle Valo } 662e705c121SKalle Valo spin_unlock(&rba->lock); 663e705c121SKalle Valo 664d56daea4SSara Sharon rxq->used_count -= RX_CLAIM_REQ_ALLOC; 665d56daea4SSara Sharon rxq->free_count += RX_CLAIM_REQ_ALLOC; 666e705c121SKalle Valo } 667e705c121SKalle Valo 66810a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data) 669e705c121SKalle Valo { 670e705c121SKalle Valo struct iwl_rb_allocator *rba_p = 671e705c121SKalle Valo container_of(data, struct iwl_rb_allocator, rx_alloc); 672e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 673e705c121SKalle Valo container_of(rba_p, struct iwl_trans_pcie, rba); 674e705c121SKalle Valo 675e705c121SKalle Valo iwl_pcie_rx_allocator(trans_pcie->trans); 676e705c121SKalle Valo } 677e705c121SKalle Valo 6780307c839SGolan Ben Ami static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td) 6790307c839SGolan Ben Ami { 6800307c839SGolan Ben Ami struct iwl_rx_transfer_desc *rx_td; 6810307c839SGolan Ben Ami 6820307c839SGolan Ben Ami if (use_rx_td) 6830307c839SGolan Ben Ami return sizeof(*rx_td); 6840307c839SGolan Ben Ami else 6850307c839SGolan Ben Ami return trans->cfg->mq_rx_supported ? sizeof(__le64) : 6860307c839SGolan Ben Ami sizeof(__le32); 6870307c839SGolan Ben Ami } 6880307c839SGolan Ben Ami 6891b493e30SGolan Ben Ami static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 6901b493e30SGolan Ben Ami struct iwl_rxq *rxq) 6911b493e30SGolan Ben Ami { 6921b493e30SGolan Ben Ami struct device *dev = trans->dev; 6930307c839SGolan Ben Ami bool use_rx_td = (trans->cfg->device_family >= 6940307c839SGolan Ben Ami IWL_DEVICE_FAMILY_22560); 6950307c839SGolan Ben Ami int free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 6961b493e30SGolan Ben Ami 6971b493e30SGolan Ben Ami if (rxq->bd) 6980307c839SGolan Ben Ami dma_free_coherent(trans->dev, 6990307c839SGolan Ben Ami free_size * rxq->queue_size, 7001b493e30SGolan Ben Ami rxq->bd, rxq->bd_dma); 7011b493e30SGolan Ben Ami rxq->bd_dma = 0; 7021b493e30SGolan Ben Ami rxq->bd = NULL; 7031b493e30SGolan Ben Ami 7041b493e30SGolan Ben Ami rxq->rb_stts_dma = 0; 7051b493e30SGolan Ben Ami rxq->rb_stts = NULL; 7061b493e30SGolan Ben Ami 7071b493e30SGolan Ben Ami if (rxq->used_bd) 7080307c839SGolan Ben Ami dma_free_coherent(trans->dev, 709b2a58c97SSara Sharon (use_rx_td ? sizeof(*rxq->cd) : 7100307c839SGolan Ben Ami sizeof(__le32)) * rxq->queue_size, 7111b493e30SGolan Ben Ami rxq->used_bd, rxq->used_bd_dma); 7121b493e30SGolan Ben Ami rxq->used_bd_dma = 0; 7131b493e30SGolan Ben Ami rxq->used_bd = NULL; 7141b493e30SGolan Ben Ami 7151b493e30SGolan Ben Ami if (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) 7161b493e30SGolan Ben Ami return; 7171b493e30SGolan Ben Ami 7181b493e30SGolan Ben Ami if (rxq->tr_tail) 7191b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 7201b493e30SGolan Ben Ami rxq->tr_tail, rxq->tr_tail_dma); 7211b493e30SGolan Ben Ami rxq->tr_tail_dma = 0; 7221b493e30SGolan Ben Ami rxq->tr_tail = NULL; 7231b493e30SGolan Ben Ami 7241b493e30SGolan Ben Ami if (rxq->cr_tail) 7251b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 7261b493e30SGolan Ben Ami rxq->cr_tail, rxq->cr_tail_dma); 7271b493e30SGolan Ben Ami rxq->cr_tail_dma = 0; 7281b493e30SGolan Ben Ami rxq->cr_tail = NULL; 7291b493e30SGolan Ben Ami } 7301b493e30SGolan Ben Ami 7311b493e30SGolan Ben Ami static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 7321b493e30SGolan Ben Ami struct iwl_rxq *rxq) 733e705c121SKalle Valo { 734e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 735e705c121SKalle Valo struct device *dev = trans->dev; 73678485054SSara Sharon int i; 7370307c839SGolan Ben Ami int free_size; 7380307c839SGolan Ben Ami bool use_rx_td = (trans->cfg->device_family >= 7390307c839SGolan Ben Ami IWL_DEVICE_FAMILY_22560); 7406cc6ba3aSTriebitz size_t rb_stts_size = use_rx_td ? sizeof(__le16) : 7416cc6ba3aSTriebitz sizeof(struct iwl_rb_status); 742e705c121SKalle Valo 74378485054SSara Sharon spin_lock_init(&rxq->lock); 74496a6497bSSara Sharon if (trans->cfg->mq_rx_supported) 74596a6497bSSara Sharon rxq->queue_size = MQ_RX_TABLE_SIZE; 74696a6497bSSara Sharon else 74796a6497bSSara Sharon rxq->queue_size = RX_QUEUE_SIZE; 74896a6497bSSara Sharon 7490307c839SGolan Ben Ami free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 7500307c839SGolan Ben Ami 75178485054SSara Sharon /* 75278485054SSara Sharon * Allocate the circular buffer of Read Buffer Descriptors 75378485054SSara Sharon * (RBDs) 75478485054SSara Sharon */ 755750afb08SLuis Chamberlain rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size, 756e705c121SKalle Valo &rxq->bd_dma, GFP_KERNEL); 757e705c121SKalle Valo if (!rxq->bd) 75878485054SSara Sharon goto err; 75978485054SSara Sharon 76096a6497bSSara Sharon if (trans->cfg->mq_rx_supported) { 761750afb08SLuis Chamberlain rxq->used_bd = dma_alloc_coherent(dev, 762750afb08SLuis Chamberlain (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size, 76396a6497bSSara Sharon &rxq->used_bd_dma, 76496a6497bSSara Sharon GFP_KERNEL); 76596a6497bSSara Sharon if (!rxq->used_bd) 76696a6497bSSara Sharon goto err; 76796a6497bSSara Sharon } 768e705c121SKalle Valo 7696cc6ba3aSTriebitz rxq->rb_stts = trans_pcie->base_rb_stts + rxq->id * rb_stts_size; 7706cc6ba3aSTriebitz rxq->rb_stts_dma = 7716cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size; 7721b493e30SGolan Ben Ami 7730307c839SGolan Ben Ami if (!use_rx_td) 7741b493e30SGolan Ben Ami return 0; 7751b493e30SGolan Ben Ami 7761b493e30SGolan Ben Ami /* Allocate the driver's pointer to TR tail */ 777750afb08SLuis Chamberlain rxq->tr_tail = dma_alloc_coherent(dev, sizeof(__le16), 778750afb08SLuis Chamberlain &rxq->tr_tail_dma, GFP_KERNEL); 7791b493e30SGolan Ben Ami if (!rxq->tr_tail) 7801b493e30SGolan Ben Ami goto err; 7811b493e30SGolan Ben Ami 7821b493e30SGolan Ben Ami /* Allocate the driver's pointer to CR tail */ 783750afb08SLuis Chamberlain rxq->cr_tail = dma_alloc_coherent(dev, sizeof(__le16), 784750afb08SLuis Chamberlain &rxq->cr_tail_dma, GFP_KERNEL); 7851b493e30SGolan Ben Ami if (!rxq->cr_tail) 7861b493e30SGolan Ben Ami goto err; 7870307c839SGolan Ben Ami /* 7880307c839SGolan Ben Ami * W/A 22560 device step Z0 must be non zero bug 7890307c839SGolan Ben Ami * TODO: remove this when stop supporting Z0 7900307c839SGolan Ben Ami */ 7910307c839SGolan Ben Ami *rxq->cr_tail = cpu_to_le16(500); 7921b493e30SGolan Ben Ami 793e705c121SKalle Valo return 0; 794e705c121SKalle Valo 79578485054SSara Sharon err: 79678485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 79778485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 79878485054SSara Sharon 7991b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 80078485054SSara Sharon } 80196a6497bSSara Sharon 802e705c121SKalle Valo return -ENOMEM; 803e705c121SKalle Valo } 804e705c121SKalle Valo 80589d5e833SGolan Ben Ami int iwl_pcie_rx_alloc(struct iwl_trans *trans) 8061b493e30SGolan Ben Ami { 8071b493e30SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 8081b493e30SGolan Ben Ami struct iwl_rb_allocator *rba = &trans_pcie->rba; 8091b493e30SGolan Ben Ami int i, ret; 8106cc6ba3aSTriebitz size_t rb_stts_size = trans->cfg->device_family >= 8116cc6ba3aSTriebitz IWL_DEVICE_FAMILY_22560 ? 8126cc6ba3aSTriebitz sizeof(__le16) : sizeof(struct iwl_rb_status); 8131b493e30SGolan Ben Ami 8141b493e30SGolan Ben Ami if (WARN_ON(trans_pcie->rxq)) 8151b493e30SGolan Ben Ami return -EINVAL; 8161b493e30SGolan Ben Ami 8171b493e30SGolan Ben Ami trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 8181b493e30SGolan Ben Ami GFP_KERNEL); 8191b493e30SGolan Ben Ami if (!trans_pcie->rxq) 8206cc6ba3aSTriebitz return -ENOMEM; 8211b493e30SGolan Ben Ami 8221b493e30SGolan Ben Ami spin_lock_init(&rba->lock); 8231b493e30SGolan Ben Ami 8246cc6ba3aSTriebitz /* 8256cc6ba3aSTriebitz * Allocate the driver's pointer to receive buffer status. 8266cc6ba3aSTriebitz * Allocate for all queues continuously (HW requirement). 8276cc6ba3aSTriebitz */ 8286cc6ba3aSTriebitz trans_pcie->base_rb_stts = 8296cc6ba3aSTriebitz dma_alloc_coherent(trans->dev, 8306cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 8316cc6ba3aSTriebitz &trans_pcie->base_rb_stts_dma, 8326cc6ba3aSTriebitz GFP_KERNEL); 8336cc6ba3aSTriebitz if (!trans_pcie->base_rb_stts) { 8346cc6ba3aSTriebitz ret = -ENOMEM; 8356cc6ba3aSTriebitz goto err; 8366cc6ba3aSTriebitz } 8376cc6ba3aSTriebitz 8381b493e30SGolan Ben Ami for (i = 0; i < trans->num_rx_queues; i++) { 8391b493e30SGolan Ben Ami struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 8401b493e30SGolan Ben Ami 8416cc6ba3aSTriebitz rxq->id = i; 8421b493e30SGolan Ben Ami ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 8431b493e30SGolan Ben Ami if (ret) 8446cc6ba3aSTriebitz goto err; 8451b493e30SGolan Ben Ami } 8461b493e30SGolan Ben Ami return 0; 8476cc6ba3aSTriebitz 8486cc6ba3aSTriebitz err: 8496cc6ba3aSTriebitz if (trans_pcie->base_rb_stts) { 8506cc6ba3aSTriebitz dma_free_coherent(trans->dev, 8516cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 8526cc6ba3aSTriebitz trans_pcie->base_rb_stts, 8536cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma); 8546cc6ba3aSTriebitz trans_pcie->base_rb_stts = NULL; 8556cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma = 0; 8566cc6ba3aSTriebitz } 8576cc6ba3aSTriebitz kfree(trans_pcie->rxq); 8586cc6ba3aSTriebitz 8596cc6ba3aSTriebitz return ret; 8601b493e30SGolan Ben Ami } 8611b493e30SGolan Ben Ami 862e705c121SKalle Valo static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 863e705c121SKalle Valo { 864e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 865e705c121SKalle Valo u32 rb_size; 866dfcfeef9SSara Sharon unsigned long flags; 867e705c121SKalle Valo const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 868e705c121SKalle Valo 8696c4fbcbcSEmmanuel Grumbach switch (trans_pcie->rx_buf_size) { 8706c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 871e705c121SKalle Valo rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8726c4fbcbcSEmmanuel Grumbach break; 8736c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 8746c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 8756c4fbcbcSEmmanuel Grumbach break; 8766c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 8776c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 8786c4fbcbcSEmmanuel Grumbach break; 8796c4fbcbcSEmmanuel Grumbach default: 8806c4fbcbcSEmmanuel Grumbach WARN_ON(1); 8816c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8826c4fbcbcSEmmanuel Grumbach } 883e705c121SKalle Valo 884dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 885dfcfeef9SSara Sharon return; 886dfcfeef9SSara Sharon 887e705c121SKalle Valo /* Stop Rx DMA */ 888dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 889e705c121SKalle Valo /* reset and flush pointers */ 890dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 891dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 892dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 893e705c121SKalle Valo 894e705c121SKalle Valo /* Reset driver's Rx queue write index */ 895dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 896e705c121SKalle Valo 897e705c121SKalle Valo /* Tell device where to find RBD circular buffer in DRAM */ 898dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 899e705c121SKalle Valo (u32)(rxq->bd_dma >> 8)); 900e705c121SKalle Valo 901e705c121SKalle Valo /* Tell device where in DRAM to update its Rx status */ 902dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 903e705c121SKalle Valo rxq->rb_stts_dma >> 4); 904e705c121SKalle Valo 905e705c121SKalle Valo /* Enable Rx DMA 906e705c121SKalle Valo * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 907e705c121SKalle Valo * the credit mechanism in 5000 HW RX FIFO 908e705c121SKalle Valo * Direct rx interrupts to hosts 9096c4fbcbcSEmmanuel Grumbach * Rx buffer size 4 or 8k or 12k 910e705c121SKalle Valo * RB timeout 0x10 911e705c121SKalle Valo * 256 RBDs 912e705c121SKalle Valo */ 913dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 914e705c121SKalle Valo FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 915e705c121SKalle Valo FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 916e705c121SKalle Valo FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 917e705c121SKalle Valo rb_size | 918e705c121SKalle Valo (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 919e705c121SKalle Valo (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 920e705c121SKalle Valo 921dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 922dfcfeef9SSara Sharon 923e705c121SKalle Valo /* Set interrupt coalescing timer to default (2048 usecs) */ 924e705c121SKalle Valo iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 925e705c121SKalle Valo 926e705c121SKalle Valo /* W/A for interrupt coalescing bug in 7260 and 3160 */ 927e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) 928e705c121SKalle Valo iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 929e705c121SKalle Valo } 930e705c121SKalle Valo 931bce97731SSara Sharon static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 93296a6497bSSara Sharon { 93396a6497bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 93496a6497bSSara Sharon u32 rb_size, enabled = 0; 935dfcfeef9SSara Sharon unsigned long flags; 93696a6497bSSara Sharon int i; 93796a6497bSSara Sharon 93896a6497bSSara Sharon switch (trans_pcie->rx_buf_size) { 9391a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 9401a4968d1SGolan Ben Ami rb_size = RFH_RXF_DMA_RB_SIZE_2K; 9411a4968d1SGolan Ben Ami break; 94296a6497bSSara Sharon case IWL_AMSDU_4K: 94396a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 94496a6497bSSara Sharon break; 94596a6497bSSara Sharon case IWL_AMSDU_8K: 94696a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_8K; 94796a6497bSSara Sharon break; 94896a6497bSSara Sharon case IWL_AMSDU_12K: 94996a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_12K; 95096a6497bSSara Sharon break; 95196a6497bSSara Sharon default: 95296a6497bSSara Sharon WARN_ON(1); 95396a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 95496a6497bSSara Sharon } 95596a6497bSSara Sharon 956dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 957dfcfeef9SSara Sharon return; 958dfcfeef9SSara Sharon 95996a6497bSSara Sharon /* Stop Rx DMA */ 960dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 96196a6497bSSara Sharon /* disable free amd used rx queue operation */ 962dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 96396a6497bSSara Sharon 96496a6497bSSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 96596a6497bSSara Sharon /* Tell device where to find RBD free table in DRAM */ 96612a17458SSara Sharon iwl_write_prph64_no_grab(trans, 967dfcfeef9SSara Sharon RFH_Q_FRBDCB_BA_LSB(i), 968dfcfeef9SSara Sharon trans_pcie->rxq[i].bd_dma); 96996a6497bSSara Sharon /* Tell device where to find RBD used table in DRAM */ 97012a17458SSara Sharon iwl_write_prph64_no_grab(trans, 971dfcfeef9SSara Sharon RFH_Q_URBDCB_BA_LSB(i), 972dfcfeef9SSara Sharon trans_pcie->rxq[i].used_bd_dma); 97396a6497bSSara Sharon /* Tell device where in DRAM to update its Rx status */ 97412a17458SSara Sharon iwl_write_prph64_no_grab(trans, 975dfcfeef9SSara Sharon RFH_Q_URBD_STTS_WPTR_LSB(i), 976bce97731SSara Sharon trans_pcie->rxq[i].rb_stts_dma); 97796a6497bSSara Sharon /* Reset device indice tables */ 978dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 979dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 980dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 98196a6497bSSara Sharon 98296a6497bSSara Sharon enabled |= BIT(i) | BIT(i + 16); 98396a6497bSSara Sharon } 98496a6497bSSara Sharon 98596a6497bSSara Sharon /* 98696a6497bSSara Sharon * Enable Rx DMA 98796a6497bSSara Sharon * Rx buffer size 4 or 8k or 12k 98896a6497bSSara Sharon * Min RB size 4 or 8 98988076015SSara Sharon * Drop frames that exceed RB size 99096a6497bSSara Sharon * 512 RBDs 99196a6497bSSara Sharon */ 992dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 99363044335SSara Sharon RFH_DMA_EN_ENABLE_VAL | rb_size | 99496a6497bSSara Sharon RFH_RXF_DMA_MIN_RB_4_8 | 99588076015SSara Sharon RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 99696a6497bSSara Sharon RFH_RXF_DMA_RBDCB_SIZE_512); 99796a6497bSSara Sharon 99888076015SSara Sharon /* 99988076015SSara Sharon * Activate DMA snooping. 1000b0262f07SSara Sharon * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 100188076015SSara Sharon * Default queue is 0 100288076015SSara Sharon */ 1003f3779f47SJohannes Berg iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 1004f3779f47SJohannes Berg RFH_GEN_CFG_RFH_DMA_SNOOP | 1005f3779f47SJohannes Berg RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 1006b0262f07SSara Sharon RFH_GEN_CFG_SERVICE_DMA_SNOOP | 1007f3779f47SJohannes Berg RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 1008f3779f47SJohannes Berg trans->cfg->integrated ? 1009b0262f07SSara Sharon RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 1010f3779f47SJohannes Berg RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 101188076015SSara Sharon /* Enable the relevant rx queues */ 1012dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 1013dfcfeef9SSara Sharon 1014dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 101596a6497bSSara Sharon 101696a6497bSSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 101796a6497bSSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 101896a6497bSSara Sharon } 101996a6497bSSara Sharon 1020ff932f61SGolan Ben Ami void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 1021e705c121SKalle Valo { 1022e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 1023e705c121SKalle Valo 1024e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_free); 1025e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_used); 1026e705c121SKalle Valo rxq->free_count = 0; 1027e705c121SKalle Valo rxq->used_count = 0; 1028e705c121SKalle Valo } 1029e705c121SKalle Valo 1030ff932f61SGolan Ben Ami int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) 1031bce97731SSara Sharon { 1032bce97731SSara Sharon WARN_ON(1); 1033bce97731SSara Sharon return 0; 1034bce97731SSara Sharon } 1035bce97731SSara Sharon 103689d5e833SGolan Ben Ami int _iwl_pcie_rx_init(struct iwl_trans *trans) 1037e705c121SKalle Valo { 1038e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 103978485054SSara Sharon struct iwl_rxq *def_rxq; 1040e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 10417b542436SSara Sharon int i, err, queue_size, allocator_pool_size, num_alloc; 1042e705c121SKalle Valo 104378485054SSara Sharon if (!trans_pcie->rxq) { 1044e705c121SKalle Valo err = iwl_pcie_rx_alloc(trans); 1045e705c121SKalle Valo if (err) 1046e705c121SKalle Valo return err; 1047e705c121SKalle Valo } 104878485054SSara Sharon def_rxq = trans_pcie->rxq; 1049e705c121SKalle Valo 10500f22e400SShaul Triebitz cancel_work_sync(&rba->rx_alloc); 10510f22e400SShaul Triebitz 1052e705c121SKalle Valo spin_lock(&rba->lock); 1053e705c121SKalle Valo atomic_set(&rba->req_pending, 0); 1054e705c121SKalle Valo atomic_set(&rba->req_ready, 0); 105596a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_allocated); 105696a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_empty); 1057e705c121SKalle Valo spin_unlock(&rba->lock); 1058e705c121SKalle Valo 1059e705c121SKalle Valo /* free all first - we might be reconfigured for a different size */ 106078485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1061e705c121SKalle Valo 1062e705c121SKalle Valo for (i = 0; i < RX_QUEUE_SIZE; i++) 106378485054SSara Sharon def_rxq->queue[i] = NULL; 1064e705c121SKalle Valo 106578485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 106678485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1067e705c121SKalle Valo 1068e705c121SKalle Valo spin_lock(&rxq->lock); 106978485054SSara Sharon /* 107078485054SSara Sharon * Set read write pointer to reflect that we have processed 107178485054SSara Sharon * and used all buffers, but have not restocked the Rx queue 107278485054SSara Sharon * with fresh buffers 107378485054SSara Sharon */ 107478485054SSara Sharon rxq->read = 0; 107578485054SSara Sharon rxq->write = 0; 107678485054SSara Sharon rxq->write_actual = 0; 10770307c839SGolan Ben Ami memset(rxq->rb_stts, 0, 10780307c839SGolan Ben Ami (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ? 10790307c839SGolan Ben Ami sizeof(__le16) : sizeof(struct iwl_rb_status)); 108078485054SSara Sharon 108178485054SSara Sharon iwl_pcie_rx_init_rxb_lists(rxq); 108278485054SSara Sharon 1083bce97731SSara Sharon if (!rxq->napi.poll) 1084bce97731SSara Sharon netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 1085bce97731SSara Sharon iwl_pcie_dummy_napi_poll, 64); 1086bce97731SSara Sharon 1087e705c121SKalle Valo spin_unlock(&rxq->lock); 108878485054SSara Sharon } 108978485054SSara Sharon 109096a6497bSSara Sharon /* move the pool to the default queue and allocator ownerships */ 10917b542436SSara Sharon queue_size = trans->cfg->mq_rx_supported ? 10927b542436SSara Sharon MQ_RX_NUM_RBDS : RX_QUEUE_SIZE; 109396a6497bSSara Sharon allocator_pool_size = trans->num_rx_queues * 109496a6497bSSara Sharon (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 10957b542436SSara Sharon num_alloc = queue_size + allocator_pool_size; 109643146925SSara Sharon BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) != 109743146925SSara Sharon ARRAY_SIZE(trans_pcie->rx_pool)); 10987b542436SSara Sharon for (i = 0; i < num_alloc; i++) { 109996a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 110096a6497bSSara Sharon 110196a6497bSSara Sharon if (i < allocator_pool_size) 110296a6497bSSara Sharon list_add(&rxb->list, &rba->rbd_empty); 110396a6497bSSara Sharon else 110496a6497bSSara Sharon list_add(&rxb->list, &def_rxq->rx_used); 110596a6497bSSara Sharon trans_pcie->global_table[i] = rxb; 1106e25d65f2SSara Sharon rxb->vid = (u16)(i + 1); 1107b1753c62SSara Sharon rxb->invalid = true; 110896a6497bSSara Sharon } 110978485054SSara Sharon 111078485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 11112047fa54SSara Sharon 1112eda50cdeSSara Sharon return 0; 1113eda50cdeSSara Sharon } 1114eda50cdeSSara Sharon 1115eda50cdeSSara Sharon int iwl_pcie_rx_init(struct iwl_trans *trans) 1116eda50cdeSSara Sharon { 1117eda50cdeSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1118eda50cdeSSara Sharon int ret = _iwl_pcie_rx_init(trans); 1119eda50cdeSSara Sharon 1120eda50cdeSSara Sharon if (ret) 1121eda50cdeSSara Sharon return ret; 1122eda50cdeSSara Sharon 11232047fa54SSara Sharon if (trans->cfg->mq_rx_supported) 1124bce97731SSara Sharon iwl_pcie_rx_mq_hw_init(trans); 11252047fa54SSara Sharon else 1126eda50cdeSSara Sharon iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 11272047fa54SSara Sharon 1128eda50cdeSSara Sharon iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 112978485054SSara Sharon 1130eda50cdeSSara Sharon spin_lock(&trans_pcie->rxq->lock); 1131eda50cdeSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 1132eda50cdeSSara Sharon spin_unlock(&trans_pcie->rxq->lock); 1133e705c121SKalle Valo 1134e705c121SKalle Valo return 0; 1135e705c121SKalle Valo } 1136e705c121SKalle Valo 1137eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1138eda50cdeSSara Sharon { 1139e506b481SSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 1140e506b481SSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1141e506b481SSara Sharon 1142eda50cdeSSara Sharon /* 1143eda50cdeSSara Sharon * We don't configure the RFH. 1144eda50cdeSSara Sharon * Restock will be done at alive, after firmware configured the RFH. 1145eda50cdeSSara Sharon */ 1146eda50cdeSSara Sharon return _iwl_pcie_rx_init(trans); 1147eda50cdeSSara Sharon } 1148eda50cdeSSara Sharon 1149e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans) 1150e705c121SKalle Valo { 1151e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1152e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 115378485054SSara Sharon int i; 11546cc6ba3aSTriebitz size_t rb_stts_size = trans->cfg->device_family >= 11556cc6ba3aSTriebitz IWL_DEVICE_FAMILY_22560 ? 11566cc6ba3aSTriebitz sizeof(__le16) : sizeof(struct iwl_rb_status); 1157e705c121SKalle Valo 115878485054SSara Sharon /* 115978485054SSara Sharon * if rxq is NULL, it means that nothing has been allocated, 116078485054SSara Sharon * exit now 116178485054SSara Sharon */ 116278485054SSara Sharon if (!trans_pcie->rxq) { 1163e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1164e705c121SKalle Valo return; 1165e705c121SKalle Valo } 1166e705c121SKalle Valo 1167e705c121SKalle Valo cancel_work_sync(&rba->rx_alloc); 1168e705c121SKalle Valo 116978485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1170e705c121SKalle Valo 11716cc6ba3aSTriebitz if (trans_pcie->base_rb_stts) { 11726cc6ba3aSTriebitz dma_free_coherent(trans->dev, 11736cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 11746cc6ba3aSTriebitz trans_pcie->base_rb_stts, 11756cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma); 11766cc6ba3aSTriebitz trans_pcie->base_rb_stts = NULL; 11776cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma = 0; 11786cc6ba3aSTriebitz } 11796cc6ba3aSTriebitz 118078485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 118178485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 118278485054SSara Sharon 11831b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 1184bce97731SSara Sharon 1185bce97731SSara Sharon if (rxq->napi.poll) 1186bce97731SSara Sharon netif_napi_del(&rxq->napi); 118796a6497bSSara Sharon } 118878485054SSara Sharon kfree(trans_pcie->rxq); 1189e705c121SKalle Valo } 1190e705c121SKalle Valo 1191868a1e86SShaul Triebitz static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq, 1192868a1e86SShaul Triebitz struct iwl_rb_allocator *rba) 1193868a1e86SShaul Triebitz { 1194868a1e86SShaul Triebitz spin_lock(&rba->lock); 1195868a1e86SShaul Triebitz list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1196868a1e86SShaul Triebitz spin_unlock(&rba->lock); 1197868a1e86SShaul Triebitz } 1198868a1e86SShaul Triebitz 1199e705c121SKalle Valo /* 1200e705c121SKalle Valo * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1201e705c121SKalle Valo * 1202e705c121SKalle Valo * Called when a RBD can be reused. The RBD is transferred to the allocator. 1203e705c121SKalle Valo * When there are 2 empty RBDs - a request for allocation is posted 1204e705c121SKalle Valo */ 1205e705c121SKalle Valo static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1206e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 1207e705c121SKalle Valo struct iwl_rxq *rxq, bool emergency) 1208e705c121SKalle Valo { 1209e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1210e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 1211e705c121SKalle Valo 1212e705c121SKalle Valo /* Move the RBD to the used list, will be moved to allocator in batches 1213e705c121SKalle Valo * before claiming or posting a request*/ 1214e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_used); 1215e705c121SKalle Valo 1216e705c121SKalle Valo if (unlikely(emergency)) 1217e705c121SKalle Valo return; 1218e705c121SKalle Valo 1219e705c121SKalle Valo /* Count the allocator owned RBDs */ 1220e705c121SKalle Valo rxq->used_count++; 1221e705c121SKalle Valo 1222e705c121SKalle Valo /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1223e705c121SKalle Valo * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1224e705c121SKalle Valo * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1225e705c121SKalle Valo * after but we still need to post another request. 1226e705c121SKalle Valo */ 1227e705c121SKalle Valo if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1228e705c121SKalle Valo /* Move the 2 RBDs to the allocator ownership. 1229e705c121SKalle Valo Allocator has another 6 from pool for the request completion*/ 1230868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1231e705c121SKalle Valo 1232e705c121SKalle Valo atomic_inc(&rba->req_pending); 1233e705c121SKalle Valo queue_work(rba->alloc_wq, &rba->rx_alloc); 1234e705c121SKalle Valo } 1235e705c121SKalle Valo } 1236e705c121SKalle Valo 1237e705c121SKalle Valo static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 123878485054SSara Sharon struct iwl_rxq *rxq, 1239e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 12407891965dSSara Sharon bool emergency, 12417891965dSSara Sharon int i) 1242e705c121SKalle Valo { 1243e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1244b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1245e705c121SKalle Valo bool page_stolen = false; 1246e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 1247e705c121SKalle Valo u32 offset = 0; 1248e705c121SKalle Valo 1249e705c121SKalle Valo if (WARN_ON(!rxb)) 1250e705c121SKalle Valo return; 1251e705c121SKalle Valo 1252e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1253e705c121SKalle Valo 1254e705c121SKalle Valo while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1255e705c121SKalle Valo struct iwl_rx_packet *pkt; 1256e705c121SKalle Valo u16 sequence; 1257e705c121SKalle Valo bool reclaim; 1258e705c121SKalle Valo int index, cmd_index, len; 1259e705c121SKalle Valo struct iwl_rx_cmd_buffer rxcb = { 1260e705c121SKalle Valo ._offset = offset, 1261e705c121SKalle Valo ._rx_page_order = trans_pcie->rx_page_order, 1262e705c121SKalle Valo ._page = rxb->page, 1263e705c121SKalle Valo ._page_stolen = false, 1264e705c121SKalle Valo .truesize = max_len, 1265e705c121SKalle Valo }; 1266e705c121SKalle Valo 1267e705c121SKalle Valo pkt = rxb_addr(&rxcb); 1268e705c121SKalle Valo 12693bfdee76SJohannes Berg if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 12703bfdee76SJohannes Berg IWL_DEBUG_RX(trans, 12713bfdee76SJohannes Berg "Q %d: RB end marker at offset %d\n", 12723bfdee76SJohannes Berg rxq->id, offset); 1273e705c121SKalle Valo break; 12743bfdee76SJohannes Berg } 1275e705c121SKalle Valo 1276a395058eSJohannes Berg WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1277a395058eSJohannes Berg FH_RSCSR_RXQ_POS != rxq->id, 1278a395058eSJohannes Berg "frame on invalid queue - is on %d and indicates %d\n", 1279a395058eSJohannes Berg rxq->id, 1280a395058eSJohannes Berg (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1281a395058eSJohannes Berg FH_RSCSR_RXQ_POS); 1282ab2e696bSSara Sharon 1283e705c121SKalle Valo IWL_DEBUG_RX(trans, 12843bfdee76SJohannes Berg "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 12853bfdee76SJohannes Berg rxq->id, offset, 128639bdb17eSSharon Dvir iwl_get_cmd_string(trans, 128739bdb17eSSharon Dvir iwl_cmd_id(pkt->hdr.cmd, 128839bdb17eSSharon Dvir pkt->hdr.group_id, 128939bdb17eSSharon Dvir 0)), 129035177c99SSara Sharon pkt->hdr.group_id, pkt->hdr.cmd, 129135177c99SSara Sharon le16_to_cpu(pkt->hdr.sequence)); 1292e705c121SKalle Valo 1293e705c121SKalle Valo len = iwl_rx_packet_len(pkt); 1294e705c121SKalle Valo len += sizeof(u32); /* account for status word */ 1295e705c121SKalle Valo trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1296e705c121SKalle Valo trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1297e705c121SKalle Valo 1298e705c121SKalle Valo /* Reclaim a command buffer only if this packet is a response 1299e705c121SKalle Valo * to a (driver-originated) command. 1300e705c121SKalle Valo * If the packet (e.g. Rx frame) originated from uCode, 1301e705c121SKalle Valo * there is no command buffer to reclaim. 1302e705c121SKalle Valo * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1303e705c121SKalle Valo * but apparently a few don't get set; catch them here. */ 1304e705c121SKalle Valo reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1305d8a130b0SJohannes Berg if (reclaim && !pkt->hdr.group_id) { 1306e705c121SKalle Valo int i; 1307e705c121SKalle Valo 1308e705c121SKalle Valo for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1309e705c121SKalle Valo if (trans_pcie->no_reclaim_cmds[i] == 1310e705c121SKalle Valo pkt->hdr.cmd) { 1311e705c121SKalle Valo reclaim = false; 1312e705c121SKalle Valo break; 1313e705c121SKalle Valo } 1314e705c121SKalle Valo } 1315e705c121SKalle Valo } 1316e705c121SKalle Valo 1317e705c121SKalle Valo sequence = le16_to_cpu(pkt->hdr.sequence); 1318e705c121SKalle Valo index = SEQ_TO_INDEX(sequence); 13194ecab561SEmmanuel Grumbach cmd_index = iwl_pcie_get_cmd_index(txq, index); 1320e705c121SKalle Valo 13219416560eSGolan Ben Ami if (rxq->id == trans_pcie->def_rx_queue) 1322bce97731SSara Sharon iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1323bce97731SSara Sharon &rxcb); 1324bce97731SSara Sharon else 1325bce97731SSara Sharon iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1326bce97731SSara Sharon &rxcb, rxq->id); 1327e705c121SKalle Valo 1328e705c121SKalle Valo if (reclaim) { 1329e705c121SKalle Valo kzfree(txq->entries[cmd_index].free_buf); 1330e705c121SKalle Valo txq->entries[cmd_index].free_buf = NULL; 1331e705c121SKalle Valo } 1332e705c121SKalle Valo 1333e705c121SKalle Valo /* 1334e705c121SKalle Valo * After here, we should always check rxcb._page_stolen, 1335e705c121SKalle Valo * if it is true then one of the handlers took the page. 1336e705c121SKalle Valo */ 1337e705c121SKalle Valo 1338e705c121SKalle Valo if (reclaim) { 1339e705c121SKalle Valo /* Invoke any callbacks, transfer the buffer to caller, 1340e705c121SKalle Valo * and fire off the (possibly) blocking 1341e705c121SKalle Valo * iwl_trans_send_cmd() 1342e705c121SKalle Valo * as we reclaim the driver command queue */ 1343e705c121SKalle Valo if (!rxcb._page_stolen) 1344e705c121SKalle Valo iwl_pcie_hcmd_complete(trans, &rxcb); 1345e705c121SKalle Valo else 1346e705c121SKalle Valo IWL_WARN(trans, "Claim null rxb?\n"); 1347e705c121SKalle Valo } 1348e705c121SKalle Valo 1349e705c121SKalle Valo page_stolen |= rxcb._page_stolen; 13500307c839SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 13510307c839SGolan Ben Ami break; 1352e705c121SKalle Valo offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1353e705c121SKalle Valo } 1354e705c121SKalle Valo 1355e705c121SKalle Valo /* page was stolen from us -- free our reference */ 1356e705c121SKalle Valo if (page_stolen) { 1357e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1358e705c121SKalle Valo rxb->page = NULL; 1359e705c121SKalle Valo } 1360e705c121SKalle Valo 1361e705c121SKalle Valo /* Reuse the page if possible. For notification packets and 1362e705c121SKalle Valo * SKBs that fail to Rx correctly, add them back into the 1363e705c121SKalle Valo * rx_free list for reuse later. */ 1364e705c121SKalle Valo if (rxb->page != NULL) { 1365e705c121SKalle Valo rxb->page_dma = 1366e705c121SKalle Valo dma_map_page(trans->dev, rxb->page, 0, 1367e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 1368e705c121SKalle Valo DMA_FROM_DEVICE); 1369e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1370e705c121SKalle Valo /* 1371e705c121SKalle Valo * free the page(s) as well to not break 1372e705c121SKalle Valo * the invariant that the items on the used 1373e705c121SKalle Valo * list have no page(s) 1374e705c121SKalle Valo */ 1375e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1376e705c121SKalle Valo rxb->page = NULL; 1377e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1378e705c121SKalle Valo } else { 1379e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 1380e705c121SKalle Valo rxq->free_count++; 1381e705c121SKalle Valo } 1382e705c121SKalle Valo } else 1383e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1384e705c121SKalle Valo } 1385e705c121SKalle Valo 13861b4bbe8bSSara Sharon static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans, 13871b4bbe8bSSara Sharon struct iwl_rxq *rxq, int i) 13881b4bbe8bSSara Sharon { 13891b4bbe8bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13901b4bbe8bSSara Sharon struct iwl_rx_mem_buffer *rxb; 13911b4bbe8bSSara Sharon u16 vid; 13921b4bbe8bSSara Sharon 1393f826faaaSJohannes Berg BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32); 1394f826faaaSJohannes Berg 13951b4bbe8bSSara Sharon if (!trans->cfg->mq_rx_supported) { 13961b4bbe8bSSara Sharon rxb = rxq->queue[i]; 13971b4bbe8bSSara Sharon rxq->queue[i] = NULL; 13981b4bbe8bSSara Sharon return rxb; 13991b4bbe8bSSara Sharon } 14001b4bbe8bSSara Sharon 14011b4bbe8bSSara Sharon /* used_bd is a 32/16 bit but only 12 are used to retrieve the vid */ 14021b4bbe8bSSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 14031b4bbe8bSSara Sharon vid = le16_to_cpu(rxq->cd[i].rbid) & 0x0FFF; 14041b4bbe8bSSara Sharon else 14051b4bbe8bSSara Sharon vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; 14061b4bbe8bSSara Sharon 14071b4bbe8bSSara Sharon if (!vid || vid > ARRAY_SIZE(trans_pcie->global_table)) 14081b4bbe8bSSara Sharon goto out_err; 14091b4bbe8bSSara Sharon 14101b4bbe8bSSara Sharon rxb = trans_pcie->global_table[vid - 1]; 14111b4bbe8bSSara Sharon if (rxb->invalid) 14121b4bbe8bSSara Sharon goto out_err; 14131b4bbe8bSSara Sharon 141485d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid); 141585d78bb1SSara Sharon 14161b4bbe8bSSara Sharon rxb->invalid = true; 14171b4bbe8bSSara Sharon 14181b4bbe8bSSara Sharon return rxb; 14191b4bbe8bSSara Sharon 14201b4bbe8bSSara Sharon out_err: 14211b4bbe8bSSara Sharon WARN(1, "Invalid rxb from HW %u\n", (u32)vid); 14221b4bbe8bSSara Sharon iwl_force_nmi(trans); 14231b4bbe8bSSara Sharon return NULL; 14241b4bbe8bSSara Sharon } 14251b4bbe8bSSara Sharon 1426e705c121SKalle Valo /* 1427e705c121SKalle Valo * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1428e705c121SKalle Valo */ 14292e5d4a8fSHaim Dreyfuss static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue) 1430e705c121SKalle Valo { 1431e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 143230f24eabSJohannes Berg struct iwl_rxq *rxq; 1433d56daea4SSara Sharon u32 r, i, count = 0; 1434e705c121SKalle Valo bool emergency = false; 1435e705c121SKalle Valo 143630f24eabSJohannes Berg if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd)) 143730f24eabSJohannes Berg return; 143830f24eabSJohannes Berg 143930f24eabSJohannes Berg rxq = &trans_pcie->rxq[queue]; 144030f24eabSJohannes Berg 1441e705c121SKalle Valo restart: 1442e705c121SKalle Valo spin_lock(&rxq->lock); 1443e705c121SKalle Valo /* uCode's read index (stored in shared DRAM) indicates the last Rx 1444e705c121SKalle Valo * buffer that the driver may process (last buffer filled by ucode). */ 14450307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1446e705c121SKalle Valo i = rxq->read; 1447e705c121SKalle Valo 14485eae443eSSara Sharon /* W/A 9000 device step A0 wrap-around bug */ 14495eae443eSSara Sharon r &= (rxq->queue_size - 1); 14505eae443eSSara Sharon 1451e705c121SKalle Valo /* Rx interrupt, but nothing sent from uCode */ 1452e705c121SKalle Valo if (i == r) 14535eae443eSSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1454e705c121SKalle Valo 1455e705c121SKalle Valo while (i != r) { 1456868a1e86SShaul Triebitz struct iwl_rb_allocator *rba = &trans_pcie->rba; 1457e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 1458868a1e86SShaul Triebitz /* number of RBDs still waiting for page allocation */ 1459868a1e86SShaul Triebitz u32 rb_pending_alloc = 1460868a1e86SShaul Triebitz atomic_read(&trans_pcie->rba.req_pending) * 1461868a1e86SShaul Triebitz RX_CLAIM_REQ_ALLOC; 1462e705c121SKalle Valo 1463868a1e86SShaul Triebitz if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 && 1464868a1e86SShaul Triebitz !emergency)) { 1465868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1466e705c121SKalle Valo emergency = true; 14676dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 14686dcdd165SSara Sharon "RX path is in emergency. Pending allocations %d\n", 14696dcdd165SSara Sharon rb_pending_alloc); 1470868a1e86SShaul Triebitz } 1471e705c121SKalle Valo 147285d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 147385d78bb1SSara Sharon 14741b4bbe8bSSara Sharon rxb = iwl_pcie_get_rxb(trans, rxq, i); 14751b4bbe8bSSara Sharon if (!rxb) 14765eae443eSSara Sharon goto out; 1477e705c121SKalle Valo 14787891965dSSara Sharon iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i); 1479e705c121SKalle Valo 148096a6497bSSara Sharon i = (i + 1) & (rxq->queue_size - 1); 1481e705c121SKalle Valo 1482d56daea4SSara Sharon /* 1483d56daea4SSara Sharon * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1484d56daea4SSara Sharon * try to claim the pre-allocated buffers from the allocator. 1485d56daea4SSara Sharon * If not ready - will try to reclaim next time. 1486d56daea4SSara Sharon * There is no need to reschedule work - allocator exits only 1487d56daea4SSara Sharon * on success 1488e705c121SKalle Valo */ 1489d56daea4SSara Sharon if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1490d56daea4SSara Sharon iwl_pcie_rx_allocator_get(trans, rxq); 1491e705c121SKalle Valo 1492d56daea4SSara Sharon if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1493d56daea4SSara Sharon /* Add the remaining empty RBDs for allocator use */ 1494868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1495d56daea4SSara Sharon } else if (emergency) { 1496e705c121SKalle Valo count++; 1497e705c121SKalle Valo if (count == 8) { 1498e705c121SKalle Valo count = 0; 14996dcdd165SSara Sharon if (rb_pending_alloc < rxq->queue_size / 3) { 15006dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 15016dcdd165SSara Sharon "RX path exited emergency. Pending allocations %d\n", 15026dcdd165SSara Sharon rb_pending_alloc); 1503e705c121SKalle Valo emergency = false; 15046dcdd165SSara Sharon } 1505e0e168dcSGregory Greenman 1506e705c121SKalle Valo rxq->read = i; 1507e705c121SKalle Valo spin_unlock(&rxq->lock); 1508e0e168dcSGregory Greenman iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 150978485054SSara Sharon iwl_pcie_rxq_restock(trans, rxq); 1510e705c121SKalle Valo goto restart; 1511e705c121SKalle Valo } 1512e705c121SKalle Valo } 1513e0e168dcSGregory Greenman } 15145eae443eSSara Sharon out: 1515e705c121SKalle Valo /* Backtrack one entry */ 1516e705c121SKalle Valo rxq->read = i; 15170307c839SGolan Ben Ami /* update cr tail with the rxq read pointer */ 15180307c839SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 15190307c839SGolan Ben Ami *rxq->cr_tail = cpu_to_le16(r); 1520e705c121SKalle Valo spin_unlock(&rxq->lock); 1521e705c121SKalle Valo 1522e705c121SKalle Valo /* 1523e705c121SKalle Valo * handle a case where in emergency there are some unallocated RBDs. 1524e705c121SKalle Valo * those RBDs are in the used list, but are not tracked by the queue's 1525e705c121SKalle Valo * used_count which counts allocator owned RBDs. 1526e705c121SKalle Valo * unallocated emergency RBDs must be allocated on exit, otherwise 1527e705c121SKalle Valo * when called again the function may not be in emergency mode and 1528e705c121SKalle Valo * they will be handed to the allocator with no tracking in the RBD 1529e705c121SKalle Valo * allocator counters, which will lead to them never being claimed back 1530e705c121SKalle Valo * by the queue. 1531e705c121SKalle Valo * by allocating them here, they are now in the queue free list, and 1532e705c121SKalle Valo * will be restocked by the next call of iwl_pcie_rxq_restock. 1533e705c121SKalle Valo */ 1534e705c121SKalle Valo if (unlikely(emergency && count)) 153578485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1536e705c121SKalle Valo 1537bce97731SSara Sharon if (rxq->napi.poll) 1538bce97731SSara Sharon napi_gro_flush(&rxq->napi, false); 1539e0e168dcSGregory Greenman 1540e0e168dcSGregory Greenman iwl_pcie_rxq_restock(trans, rxq); 1541e705c121SKalle Valo } 1542e705c121SKalle Valo 15432e5d4a8fSHaim Dreyfuss static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 15442e5d4a8fSHaim Dreyfuss { 15452e5d4a8fSHaim Dreyfuss u8 queue = entry->entry; 15462e5d4a8fSHaim Dreyfuss struct msix_entry *entries = entry - queue; 15472e5d4a8fSHaim Dreyfuss 15482e5d4a8fSHaim Dreyfuss return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 15492e5d4a8fSHaim Dreyfuss } 15502e5d4a8fSHaim Dreyfuss 15512e5d4a8fSHaim Dreyfuss /* 15522e5d4a8fSHaim Dreyfuss * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 15532e5d4a8fSHaim Dreyfuss * This interrupt handler should be used with RSS queue only. 15542e5d4a8fSHaim Dreyfuss */ 15552e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 15562e5d4a8fSHaim Dreyfuss { 15572e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 15582e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 15592e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 15602e5d4a8fSHaim Dreyfuss 1561c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1562c42ff65dSJohannes Berg 15635eae443eSSara Sharon if (WARN_ON(entry->entry >= trans->num_rx_queues)) 15645eae443eSSara Sharon return IRQ_NONE; 15655eae443eSSara Sharon 15662e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 15672e5d4a8fSHaim Dreyfuss 15682e5d4a8fSHaim Dreyfuss local_bh_disable(); 15692e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, entry->entry); 15702e5d4a8fSHaim Dreyfuss local_bh_enable(); 15712e5d4a8fSHaim Dreyfuss 15722e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 15732e5d4a8fSHaim Dreyfuss 15742e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 15752e5d4a8fSHaim Dreyfuss 15762e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 15772e5d4a8fSHaim Dreyfuss } 15782e5d4a8fSHaim Dreyfuss 1579e705c121SKalle Valo /* 1580e705c121SKalle Valo * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1581e705c121SKalle Valo */ 1582e705c121SKalle Valo static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1583e705c121SKalle Valo { 1584e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1585e705c121SKalle Valo int i; 1586e705c121SKalle Valo 1587e705c121SKalle Valo /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1588e705c121SKalle Valo if (trans->cfg->internal_wimax_coex && 1589e705c121SKalle Valo !trans->cfg->apmg_not_supported && 1590e705c121SKalle Valo (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1591e705c121SKalle Valo APMS_CLK_VAL_MRB_FUNC_MODE) || 1592e705c121SKalle Valo (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1593e705c121SKalle Valo APMG_PS_CTRL_VAL_RESET_REQ))) { 1594e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1595e705c121SKalle Valo iwl_op_mode_wimax_active(trans->op_mode); 1596e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1597e705c121SKalle Valo return; 1598e705c121SKalle Valo } 1599e705c121SKalle Valo 160013a3a390SSara Sharon for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 160113a3a390SSara Sharon if (!trans_pcie->txq[i]) 160213a3a390SSara Sharon continue; 1603b2a3b1c1SSara Sharon del_timer(&trans_pcie->txq[i]->stuck_timer); 160413a3a390SSara Sharon } 1605e705c121SKalle Valo 16067d75f32eSEmmanuel Grumbach /* The STATUS_FW_ERROR bit is set in this function. This must happen 16077d75f32eSEmmanuel Grumbach * before we wake up the command caller, to ensure a proper cleanup. */ 16087d75f32eSEmmanuel Grumbach iwl_trans_fw_error(trans); 16097d75f32eSEmmanuel Grumbach 1610e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1611e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1612e705c121SKalle Valo } 1613e705c121SKalle Valo 1614e705c121SKalle Valo static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1615e705c121SKalle Valo { 1616e705c121SKalle Valo u32 inta; 1617e705c121SKalle Valo 1618e705c121SKalle Valo lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1619e705c121SKalle Valo 1620e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1621e705c121SKalle Valo 1622e705c121SKalle Valo /* Discover which interrupts are active/pending */ 1623e705c121SKalle Valo inta = iwl_read32(trans, CSR_INT); 1624e705c121SKalle Valo 1625e705c121SKalle Valo /* the thread will service interrupts and re-enable them */ 1626e705c121SKalle Valo return inta; 1627e705c121SKalle Valo } 1628e705c121SKalle Valo 1629e705c121SKalle Valo /* a device (PCI-E) page is 4096 bytes long */ 1630e705c121SKalle Valo #define ICT_SHIFT 12 1631e705c121SKalle Valo #define ICT_SIZE (1 << ICT_SHIFT) 1632e705c121SKalle Valo #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1633e705c121SKalle Valo 1634e705c121SKalle Valo /* interrupt handler using ict table, with this interrupt driver will 1635e705c121SKalle Valo * stop using INTA register to get device's interrupt, reading this register 1636e705c121SKalle Valo * is expensive, device will write interrupts in ICT dram table, increment 1637e705c121SKalle Valo * index then will fire interrupt to driver, driver will OR all ICT table 1638e705c121SKalle Valo * entries from current index up to table entry with 0 value. the result is 1639e705c121SKalle Valo * the interrupt we need to service, driver will set the entries back to 0 and 1640e705c121SKalle Valo * set index. 1641e705c121SKalle Valo */ 1642e705c121SKalle Valo static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1643e705c121SKalle Valo { 1644e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1645e705c121SKalle Valo u32 inta; 1646e705c121SKalle Valo u32 val = 0; 1647e705c121SKalle Valo u32 read; 1648e705c121SKalle Valo 1649e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1650e705c121SKalle Valo 1651e705c121SKalle Valo /* Ignore interrupt if there's nothing in NIC to service. 1652e705c121SKalle Valo * This may be due to IRQ shared with another device, 1653e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. */ 1654e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1655e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1656e705c121SKalle Valo if (!read) 1657e705c121SKalle Valo return 0; 1658e705c121SKalle Valo 1659e705c121SKalle Valo /* 1660e705c121SKalle Valo * Collect all entries up to the first 0, starting from ict_index; 1661e705c121SKalle Valo * note we already read at ict_index. 1662e705c121SKalle Valo */ 1663e705c121SKalle Valo do { 1664e705c121SKalle Valo val |= read; 1665e705c121SKalle Valo IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1666e705c121SKalle Valo trans_pcie->ict_index, read); 1667e705c121SKalle Valo trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1668e705c121SKalle Valo trans_pcie->ict_index = 1669e705c121SKalle Valo ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1670e705c121SKalle Valo 1671e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1672e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1673e705c121SKalle Valo read); 1674e705c121SKalle Valo } while (read); 1675e705c121SKalle Valo 1676e705c121SKalle Valo /* We should not get this value, just ignore it. */ 1677e705c121SKalle Valo if (val == 0xffffffff) 1678e705c121SKalle Valo val = 0; 1679e705c121SKalle Valo 1680e705c121SKalle Valo /* 1681e705c121SKalle Valo * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1682e705c121SKalle Valo * (bit 15 before shifting it to 31) to clear when using interrupt 1683e705c121SKalle Valo * coalescing. fortunately, bits 18 and 19 stay set when this happens 1684e705c121SKalle Valo * so we use them to decide on the real state of the Rx bit. 1685e705c121SKalle Valo * In order words, bit 15 is set if bit 18 or bit 19 are set. 1686e705c121SKalle Valo */ 1687e705c121SKalle Valo if (val & 0xC0000) 1688e705c121SKalle Valo val |= 0x8000; 1689e705c121SKalle Valo 1690e705c121SKalle Valo inta = (0xff & val) | ((0xff00 & val) << 16); 1691e705c121SKalle Valo return inta; 1692e705c121SKalle Valo } 1693e705c121SKalle Valo 1694fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 16953a6e168bSJohannes Berg { 16963a6e168bSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16973a6e168bSJohannes Berg struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1698326477e4SJohannes Berg bool hw_rfkill, prev, report; 16993a6e168bSJohannes Berg 17003a6e168bSJohannes Berg mutex_lock(&trans_pcie->mutex); 1701326477e4SJohannes Berg prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 17023a6e168bSJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1703326477e4SJohannes Berg if (hw_rfkill) { 1704326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1705326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1706326477e4SJohannes Berg } 1707326477e4SJohannes Berg if (trans_pcie->opmode_down) 1708326477e4SJohannes Berg report = hw_rfkill; 1709326477e4SJohannes Berg else 1710326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 17113a6e168bSJohannes Berg 17123a6e168bSJohannes Berg IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 17133a6e168bSJohannes Berg hw_rfkill ? "disable radio" : "enable radio"); 17143a6e168bSJohannes Berg 17153a6e168bSJohannes Berg isr_stats->rfkill++; 17163a6e168bSJohannes Berg 1717326477e4SJohannes Berg if (prev != report) 1718326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 17193a6e168bSJohannes Berg mutex_unlock(&trans_pcie->mutex); 17203a6e168bSJohannes Berg 17213a6e168bSJohannes Berg if (hw_rfkill) { 17223a6e168bSJohannes Berg if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 17233a6e168bSJohannes Berg &trans->status)) 17243a6e168bSJohannes Berg IWL_DEBUG_RF_KILL(trans, 17253a6e168bSJohannes Berg "Rfkill while SYNC HCMD in flight\n"); 17263a6e168bSJohannes Berg wake_up(&trans_pcie->wait_command_queue); 17273a6e168bSJohannes Berg } else { 1728326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1729326477e4SJohannes Berg if (trans_pcie->opmode_down) 1730326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 17313a6e168bSJohannes Berg } 17323a6e168bSJohannes Berg } 17333a6e168bSJohannes Berg 1734e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1735e705c121SKalle Valo { 1736e705c121SKalle Valo struct iwl_trans *trans = dev_id; 1737e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1738e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1739e705c121SKalle Valo u32 inta = 0; 1740e705c121SKalle Valo u32 handled = 0; 1741e705c121SKalle Valo 1742e705c121SKalle Valo lock_map_acquire(&trans->sync_cmd_lockdep_map); 1743e705c121SKalle Valo 1744e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1745e705c121SKalle Valo 1746e705c121SKalle Valo /* dram interrupt table not set yet, 1747e705c121SKalle Valo * use legacy interrupt. 1748e705c121SKalle Valo */ 1749e705c121SKalle Valo if (likely(trans_pcie->use_ict)) 1750e705c121SKalle Valo inta = iwl_pcie_int_cause_ict(trans); 1751e705c121SKalle Valo else 1752e705c121SKalle Valo inta = iwl_pcie_int_cause_non_ict(trans); 1753e705c121SKalle Valo 1754e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1755e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1756e705c121SKalle Valo "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1757e705c121SKalle Valo inta, trans_pcie->inta_mask, 1758e705c121SKalle Valo iwl_read32(trans, CSR_INT_MASK), 1759e705c121SKalle Valo iwl_read32(trans, CSR_FH_INT_STATUS)); 1760e705c121SKalle Valo if (inta & (~trans_pcie->inta_mask)) 1761e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1762e705c121SKalle Valo "We got a masked interrupt (0x%08x)\n", 1763e705c121SKalle Valo inta & (~trans_pcie->inta_mask)); 1764e705c121SKalle Valo } 1765e705c121SKalle Valo 1766e705c121SKalle Valo inta &= trans_pcie->inta_mask; 1767e705c121SKalle Valo 1768e705c121SKalle Valo /* 1769e705c121SKalle Valo * Ignore interrupt if there's nothing in NIC to service. 1770e705c121SKalle Valo * This may be due to IRQ shared with another device, 1771e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. 1772e705c121SKalle Valo */ 1773e705c121SKalle Valo if (unlikely(!inta)) { 1774e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1775e705c121SKalle Valo /* 1776e705c121SKalle Valo * Re-enable interrupts here since we don't 1777e705c121SKalle Valo * have anything to service 1778e705c121SKalle Valo */ 1779e705c121SKalle Valo if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1780f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 1781e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1782e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1783e705c121SKalle Valo return IRQ_NONE; 1784e705c121SKalle Valo } 1785e705c121SKalle Valo 1786e705c121SKalle Valo if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1787e705c121SKalle Valo /* 1788e705c121SKalle Valo * Hardware disappeared. It might have 1789e705c121SKalle Valo * already raised an interrupt. 1790e705c121SKalle Valo */ 1791e705c121SKalle Valo IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1792e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1793e705c121SKalle Valo goto out; 1794e705c121SKalle Valo } 1795e705c121SKalle Valo 1796e705c121SKalle Valo /* Ack/clear/reset pending uCode interrupts. 1797e705c121SKalle Valo * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1798e705c121SKalle Valo */ 1799e705c121SKalle Valo /* There is a hardware bug in the interrupt mask function that some 1800e705c121SKalle Valo * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1801e705c121SKalle Valo * they are disabled in the CSR_INT_MASK register. Furthermore the 1802e705c121SKalle Valo * ICT interrupt handling mechanism has another bug that might cause 1803e705c121SKalle Valo * these unmasked interrupts fail to be detected. We workaround the 1804e705c121SKalle Valo * hardware bugs here by ACKing all the possible interrupts so that 1805e705c121SKalle Valo * interrupt coalescing can still be achieved. 1806e705c121SKalle Valo */ 1807e705c121SKalle Valo iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1808e705c121SKalle Valo 1809e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) 1810e705c121SKalle Valo IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1811e705c121SKalle Valo inta, iwl_read32(trans, CSR_INT_MASK)); 1812e705c121SKalle Valo 1813e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1814e705c121SKalle Valo 1815e705c121SKalle Valo /* Now service all interrupt bits discovered above. */ 1816e705c121SKalle Valo if (inta & CSR_INT_BIT_HW_ERR) { 1817e705c121SKalle Valo IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1818e705c121SKalle Valo 1819e705c121SKalle Valo /* Tell the device to stop sending interrupts */ 1820e705c121SKalle Valo iwl_disable_interrupts(trans); 1821e705c121SKalle Valo 1822e705c121SKalle Valo isr_stats->hw++; 1823e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1824e705c121SKalle Valo 1825e705c121SKalle Valo handled |= CSR_INT_BIT_HW_ERR; 1826e705c121SKalle Valo 1827e705c121SKalle Valo goto out; 1828e705c121SKalle Valo } 1829e705c121SKalle Valo 1830e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1831e705c121SKalle Valo /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1832e705c121SKalle Valo if (inta & CSR_INT_BIT_SCD) { 1833e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1834e705c121SKalle Valo "Scheduler finished to transmit the frame/frames.\n"); 1835e705c121SKalle Valo isr_stats->sch++; 1836e705c121SKalle Valo } 1837e705c121SKalle Valo 1838e705c121SKalle Valo /* Alive notification via Rx interrupt will do the real work */ 1839e705c121SKalle Valo if (inta & CSR_INT_BIT_ALIVE) { 1840e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1841e705c121SKalle Valo isr_stats->alive++; 1842eda50cdeSSara Sharon if (trans->cfg->gen2) { 1843eda50cdeSSara Sharon /* 1844eda50cdeSSara Sharon * We can restock, since firmware configured 1845eda50cdeSSara Sharon * the RFH 1846eda50cdeSSara Sharon */ 1847eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1848eda50cdeSSara Sharon } 1849e705c121SKalle Valo } 1850e705c121SKalle Valo } 1851e705c121SKalle Valo 1852e705c121SKalle Valo /* Safely ignore these bits for debug checks below */ 1853e705c121SKalle Valo inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1854e705c121SKalle Valo 1855e705c121SKalle Valo /* HW RF KILL switch toggled */ 1856e705c121SKalle Valo if (inta & CSR_INT_BIT_RF_KILL) { 18573a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 1858e705c121SKalle Valo handled |= CSR_INT_BIT_RF_KILL; 1859e705c121SKalle Valo } 1860e705c121SKalle Valo 1861e705c121SKalle Valo /* Chip got too hot and stopped itself */ 1862e705c121SKalle Valo if (inta & CSR_INT_BIT_CT_KILL) { 1863e705c121SKalle Valo IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1864e705c121SKalle Valo isr_stats->ctkill++; 1865e705c121SKalle Valo handled |= CSR_INT_BIT_CT_KILL; 1866e705c121SKalle Valo } 1867e705c121SKalle Valo 1868e705c121SKalle Valo /* Error detected by uCode */ 1869e705c121SKalle Valo if (inta & CSR_INT_BIT_SW_ERR) { 1870e705c121SKalle Valo IWL_ERR(trans, "Microcode SW error detected. " 1871e705c121SKalle Valo " Restarting 0x%X.\n", inta); 1872e705c121SKalle Valo isr_stats->sw++; 1873e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1874e705c121SKalle Valo handled |= CSR_INT_BIT_SW_ERR; 1875e705c121SKalle Valo } 1876e705c121SKalle Valo 1877e705c121SKalle Valo /* uCode wakes up after power-down sleep */ 1878e705c121SKalle Valo if (inta & CSR_INT_BIT_WAKEUP) { 1879e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1880e705c121SKalle Valo iwl_pcie_rxq_check_wrptr(trans); 1881e705c121SKalle Valo iwl_pcie_txq_check_wrptrs(trans); 1882e705c121SKalle Valo 1883e705c121SKalle Valo isr_stats->wakeup++; 1884e705c121SKalle Valo 1885e705c121SKalle Valo handled |= CSR_INT_BIT_WAKEUP; 1886e705c121SKalle Valo } 1887e705c121SKalle Valo 1888e705c121SKalle Valo /* All uCode command responses, including Tx command responses, 1889e705c121SKalle Valo * Rx "responses" (frame-received notification), and other 1890e705c121SKalle Valo * notifications from uCode come through here*/ 1891e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1892e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC)) { 1893e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1894e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1895e705c121SKalle Valo handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1896e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 1897e705c121SKalle Valo CSR_FH_INT_RX_MASK); 1898e705c121SKalle Valo } 1899e705c121SKalle Valo if (inta & CSR_INT_BIT_RX_PERIODIC) { 1900e705c121SKalle Valo handled |= CSR_INT_BIT_RX_PERIODIC; 1901e705c121SKalle Valo iwl_write32(trans, 1902e705c121SKalle Valo CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1903e705c121SKalle Valo } 1904e705c121SKalle Valo /* Sending RX interrupt require many steps to be done in the 1905e705c121SKalle Valo * the device: 1906e705c121SKalle Valo * 1- write interrupt to current index in ICT table. 1907e705c121SKalle Valo * 2- dma RX frame. 1908e705c121SKalle Valo * 3- update RX shared data to indicate last write index. 1909e705c121SKalle Valo * 4- send interrupt. 1910e705c121SKalle Valo * This could lead to RX race, driver could receive RX interrupt 1911e705c121SKalle Valo * but the shared data changes does not reflect this; 1912e705c121SKalle Valo * periodic interrupt will detect any dangling Rx activity. 1913e705c121SKalle Valo */ 1914e705c121SKalle Valo 1915e705c121SKalle Valo /* Disable periodic interrupt; we use it as just a one-shot. */ 1916e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1917e705c121SKalle Valo CSR_INT_PERIODIC_DIS); 1918e705c121SKalle Valo 1919e705c121SKalle Valo /* 1920e705c121SKalle Valo * Enable periodic interrupt in 8 msec only if we received 1921e705c121SKalle Valo * real RX interrupt (instead of just periodic int), to catch 1922e705c121SKalle Valo * any dangling Rx interrupt. If it was just the periodic 1923e705c121SKalle Valo * interrupt, there was no dangling Rx activity, and no need 1924e705c121SKalle Valo * to extend the periodic interrupt; one-shot is enough. 1925e705c121SKalle Valo */ 1926e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1927e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1928e705c121SKalle Valo CSR_INT_PERIODIC_ENA); 1929e705c121SKalle Valo 1930e705c121SKalle Valo isr_stats->rx++; 1931e705c121SKalle Valo 1932e705c121SKalle Valo local_bh_disable(); 19332e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, 0); 1934e705c121SKalle Valo local_bh_enable(); 1935e705c121SKalle Valo } 1936e705c121SKalle Valo 1937e705c121SKalle Valo /* This "Tx" DMA channel is used only for loading uCode */ 1938e705c121SKalle Valo if (inta & CSR_INT_BIT_FH_TX) { 1939e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1940e705c121SKalle Valo IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1941e705c121SKalle Valo isr_stats->tx++; 1942e705c121SKalle Valo handled |= CSR_INT_BIT_FH_TX; 1943e705c121SKalle Valo /* Wake up uCode load routine, now that load is complete */ 1944e705c121SKalle Valo trans_pcie->ucode_write_complete = true; 1945e705c121SKalle Valo wake_up(&trans_pcie->ucode_write_waitq); 1946e705c121SKalle Valo } 1947e705c121SKalle Valo 1948e705c121SKalle Valo if (inta & ~handled) { 1949e705c121SKalle Valo IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 1950e705c121SKalle Valo isr_stats->unhandled++; 1951e705c121SKalle Valo } 1952e705c121SKalle Valo 1953e705c121SKalle Valo if (inta & ~(trans_pcie->inta_mask)) { 1954e705c121SKalle Valo IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 1955e705c121SKalle Valo inta & ~trans_pcie->inta_mask); 1956e705c121SKalle Valo } 1957e705c121SKalle Valo 1958f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 1959a6bd005fSEmmanuel Grumbach /* only Re-enable all interrupt if disabled by irq */ 1960f16c3ebfSEmmanuel Grumbach if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1961f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 1962f16c3ebfSEmmanuel Grumbach /* we are loading the firmware, enable FH_TX interrupt only */ 1963f16c3ebfSEmmanuel Grumbach else if (handled & CSR_INT_BIT_FH_TX) 1964f16c3ebfSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1965e705c121SKalle Valo /* Re-enable RF_KILL if it occurred */ 1966e705c121SKalle Valo else if (handled & CSR_INT_BIT_RF_KILL) 1967e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1968f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 1969e705c121SKalle Valo 1970e705c121SKalle Valo out: 1971e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1972e705c121SKalle Valo return IRQ_HANDLED; 1973e705c121SKalle Valo } 1974e705c121SKalle Valo 1975e705c121SKalle Valo /****************************************************************************** 1976e705c121SKalle Valo * 1977e705c121SKalle Valo * ICT functions 1978e705c121SKalle Valo * 1979e705c121SKalle Valo ******************************************************************************/ 1980e705c121SKalle Valo 1981e705c121SKalle Valo /* Free dram table */ 1982e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans) 1983e705c121SKalle Valo { 1984e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1985e705c121SKalle Valo 1986e705c121SKalle Valo if (trans_pcie->ict_tbl) { 1987e705c121SKalle Valo dma_free_coherent(trans->dev, ICT_SIZE, 1988e705c121SKalle Valo trans_pcie->ict_tbl, 1989e705c121SKalle Valo trans_pcie->ict_tbl_dma); 1990e705c121SKalle Valo trans_pcie->ict_tbl = NULL; 1991e705c121SKalle Valo trans_pcie->ict_tbl_dma = 0; 1992e705c121SKalle Valo } 1993e705c121SKalle Valo } 1994e705c121SKalle Valo 1995e705c121SKalle Valo /* 1996e705c121SKalle Valo * allocate dram shared table, it is an aligned memory 1997e705c121SKalle Valo * block of ICT_SIZE. 1998e705c121SKalle Valo * also reset all data related to ICT table interrupt. 1999e705c121SKalle Valo */ 2000e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans) 2001e705c121SKalle Valo { 2002e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2003e705c121SKalle Valo 2004e705c121SKalle Valo trans_pcie->ict_tbl = 2005750afb08SLuis Chamberlain dma_alloc_coherent(trans->dev, ICT_SIZE, 2006750afb08SLuis Chamberlain &trans_pcie->ict_tbl_dma, GFP_KERNEL); 2007e705c121SKalle Valo if (!trans_pcie->ict_tbl) 2008e705c121SKalle Valo return -ENOMEM; 2009e705c121SKalle Valo 2010e705c121SKalle Valo /* just an API sanity check ... it is guaranteed to be aligned */ 2011e705c121SKalle Valo if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 2012e705c121SKalle Valo iwl_pcie_free_ict(trans); 2013e705c121SKalle Valo return -EINVAL; 2014e705c121SKalle Valo } 2015e705c121SKalle Valo 2016e705c121SKalle Valo return 0; 2017e705c121SKalle Valo } 2018e705c121SKalle Valo 2019e705c121SKalle Valo /* Device is going up inform it about using ICT interrupt table, 2020e705c121SKalle Valo * also we need to tell the driver to start using ICT interrupt. 2021e705c121SKalle Valo */ 2022e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans) 2023e705c121SKalle Valo { 2024e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2025e705c121SKalle Valo u32 val; 2026e705c121SKalle Valo 2027e705c121SKalle Valo if (!trans_pcie->ict_tbl) 2028e705c121SKalle Valo return; 2029e705c121SKalle Valo 2030e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 2031f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 2032e705c121SKalle Valo 2033e705c121SKalle Valo memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 2034e705c121SKalle Valo 2035e705c121SKalle Valo val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 2036e705c121SKalle Valo 2037e705c121SKalle Valo val |= CSR_DRAM_INT_TBL_ENABLE | 2038e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRAP_CHECK | 2039e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRITE_POINTER; 2040e705c121SKalle Valo 2041e705c121SKalle Valo IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 2042e705c121SKalle Valo 2043e705c121SKalle Valo iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 2044e705c121SKalle Valo trans_pcie->use_ict = true; 2045e705c121SKalle Valo trans_pcie->ict_index = 0; 2046e705c121SKalle Valo iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 2047f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 2048e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 2049e705c121SKalle Valo } 2050e705c121SKalle Valo 2051e705c121SKalle Valo /* Device is going down disable ict interrupt usage */ 2052e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans) 2053e705c121SKalle Valo { 2054e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2055e705c121SKalle Valo 2056e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 2057e705c121SKalle Valo trans_pcie->use_ict = false; 2058e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 2059e705c121SKalle Valo } 2060e705c121SKalle Valo 2061e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data) 2062e705c121SKalle Valo { 2063e705c121SKalle Valo struct iwl_trans *trans = data; 2064e705c121SKalle Valo 2065e705c121SKalle Valo if (!trans) 2066e705c121SKalle Valo return IRQ_NONE; 2067e705c121SKalle Valo 2068e705c121SKalle Valo /* Disable (but don't clear!) interrupts here to avoid 2069e705c121SKalle Valo * back-to-back ISRs and sporadic interrupts from our NIC. 2070e705c121SKalle Valo * If we have something to service, the tasklet will re-enable ints. 2071e705c121SKalle Valo * If we *don't* have something, we'll re-enable before leaving here. 2072e705c121SKalle Valo */ 2073e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2074e705c121SKalle Valo 2075e705c121SKalle Valo return IRQ_WAKE_THREAD; 2076e705c121SKalle Valo } 20772e5d4a8fSHaim Dreyfuss 20782e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 20792e5d4a8fSHaim Dreyfuss { 20802e5d4a8fSHaim Dreyfuss return IRQ_WAKE_THREAD; 20812e5d4a8fSHaim Dreyfuss } 20822e5d4a8fSHaim Dreyfuss 20832e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 20842e5d4a8fSHaim Dreyfuss { 20852e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 20862e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 20872e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 208846167a8fSColin Ian King struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 20892e5d4a8fSHaim Dreyfuss u32 inta_fh, inta_hw; 20902e5d4a8fSHaim Dreyfuss 20912e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 20922e5d4a8fSHaim Dreyfuss 20932e5d4a8fSHaim Dreyfuss spin_lock(&trans_pcie->irq_lock); 20947ef3dd26SHaim Dreyfuss inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 20957ef3dd26SHaim Dreyfuss inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 20962e5d4a8fSHaim Dreyfuss /* 20972e5d4a8fSHaim Dreyfuss * Clear causes registers to avoid being handling the same cause. 20982e5d4a8fSHaim Dreyfuss */ 20997ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 21007ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 21012e5d4a8fSHaim Dreyfuss spin_unlock(&trans_pcie->irq_lock); 21022e5d4a8fSHaim Dreyfuss 2103c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2104c42ff65dSJohannes Berg 21052e5d4a8fSHaim Dreyfuss if (unlikely(!(inta_fh | inta_hw))) { 21062e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 21072e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 21082e5d4a8fSHaim Dreyfuss return IRQ_NONE; 21092e5d4a8fSHaim Dreyfuss } 21102e5d4a8fSHaim Dreyfuss 21112e5d4a8fSHaim Dreyfuss if (iwl_have_debug_level(IWL_DL_ISR)) 21122e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "ISR inta_fh 0x%08x, enabled 0x%08x\n", 21132e5d4a8fSHaim Dreyfuss inta_fh, 21142e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 21152e5d4a8fSHaim Dreyfuss 2116496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2117496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2118496d83caSHaim Dreyfuss local_bh_disable(); 2119496d83caSHaim Dreyfuss iwl_pcie_rx_handle(trans, 0); 2120496d83caSHaim Dreyfuss local_bh_enable(); 2121496d83caSHaim Dreyfuss } 2122496d83caSHaim Dreyfuss 2123496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2124496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2125496d83caSHaim Dreyfuss local_bh_disable(); 2126496d83caSHaim Dreyfuss iwl_pcie_rx_handle(trans, 1); 2127496d83caSHaim Dreyfuss local_bh_enable(); 2128496d83caSHaim Dreyfuss } 2129496d83caSHaim Dreyfuss 21302e5d4a8fSHaim Dreyfuss /* This "Tx" DMA channel is used only for loading uCode */ 21312e5d4a8fSHaim Dreyfuss if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 21322e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 21332e5d4a8fSHaim Dreyfuss isr_stats->tx++; 21342e5d4a8fSHaim Dreyfuss /* 21352e5d4a8fSHaim Dreyfuss * Wake up uCode load routine, 21362e5d4a8fSHaim Dreyfuss * now that load is complete 21372e5d4a8fSHaim Dreyfuss */ 21382e5d4a8fSHaim Dreyfuss trans_pcie->ucode_write_complete = true; 21392e5d4a8fSHaim Dreyfuss wake_up(&trans_pcie->ucode_write_waitq); 21402e5d4a8fSHaim Dreyfuss } 21412e5d4a8fSHaim Dreyfuss 21422e5d4a8fSHaim Dreyfuss /* Error detected by uCode */ 21432e5d4a8fSHaim Dreyfuss if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 21449b58419eSGolan Ben Ami (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) || 21459b58419eSGolan Ben Ami (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_V2)) { 21462e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 21472e5d4a8fSHaim Dreyfuss "Microcode SW error detected. Restarting 0x%X.\n", 21482e5d4a8fSHaim Dreyfuss inta_fh); 21492e5d4a8fSHaim Dreyfuss isr_stats->sw++; 21502e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 21512e5d4a8fSHaim Dreyfuss } 21522e5d4a8fSHaim Dreyfuss 21532e5d4a8fSHaim Dreyfuss /* After checking FH register check HW register */ 21542e5d4a8fSHaim Dreyfuss if (iwl_have_debug_level(IWL_DL_ISR)) 21552e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, 21562e5d4a8fSHaim Dreyfuss "ISR inta_hw 0x%08x, enabled 0x%08x\n", 21572e5d4a8fSHaim Dreyfuss inta_hw, 21582e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 21592e5d4a8fSHaim Dreyfuss 21602e5d4a8fSHaim Dreyfuss /* Alive notification via Rx interrupt will do the real work */ 21612e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 21622e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 21632e5d4a8fSHaim Dreyfuss isr_stats->alive++; 2164eda50cdeSSara Sharon if (trans->cfg->gen2) { 2165eda50cdeSSara Sharon /* We can restock, since firmware configured the RFH */ 2166eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2167eda50cdeSSara Sharon } 21682e5d4a8fSHaim Dreyfuss } 21692e5d4a8fSHaim Dreyfuss 2170ff911dcaSShaul Triebitz if (trans->cfg->device_family == IWL_DEVICE_FAMILY_22560 && 21719b58419eSGolan Ben Ami inta_hw & MSIX_HW_INT_CAUSES_REG_IPC) { 21729b58419eSGolan Ben Ami /* Reflect IML transfer status */ 21739b58419eSGolan Ben Ami int res = iwl_read32(trans, CSR_IML_RESP_ADDR); 21749b58419eSGolan Ben Ami 21759b58419eSGolan Ben Ami IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res); 21769b58419eSGolan Ben Ami if (res == IWL_IMAGE_RESP_FAIL) { 21779b58419eSGolan Ben Ami isr_stats->sw++; 21789b58419eSGolan Ben Ami iwl_pcie_irq_handle_error(trans); 21799b58419eSGolan Ben Ami } 21809b58419eSGolan Ben Ami } else if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 21812e5d4a8fSHaim Dreyfuss /* uCode wakes up after power-down sleep */ 21822e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 21832e5d4a8fSHaim Dreyfuss iwl_pcie_rxq_check_wrptr(trans); 21842e5d4a8fSHaim Dreyfuss iwl_pcie_txq_check_wrptrs(trans); 21852e5d4a8fSHaim Dreyfuss 21862e5d4a8fSHaim Dreyfuss isr_stats->wakeup++; 21872e5d4a8fSHaim Dreyfuss } 21882e5d4a8fSHaim Dreyfuss 2189ff911dcaSShaul Triebitz if (inta_hw & MSIX_HW_INT_CAUSES_REG_IML) { 2190ff911dcaSShaul Triebitz /* Reflect IML transfer status */ 2191ff911dcaSShaul Triebitz int res = iwl_read32(trans, CSR_IML_RESP_ADDR); 2192ff911dcaSShaul Triebitz 2193ff911dcaSShaul Triebitz IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res); 2194ff911dcaSShaul Triebitz if (res == IWL_IMAGE_RESP_FAIL) { 2195ff911dcaSShaul Triebitz isr_stats->sw++; 2196ff911dcaSShaul Triebitz iwl_pcie_irq_handle_error(trans); 2197ff911dcaSShaul Triebitz } 2198ff911dcaSShaul Triebitz } 2199ff911dcaSShaul Triebitz 22002e5d4a8fSHaim Dreyfuss /* Chip got too hot and stopped itself */ 22012e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 22022e5d4a8fSHaim Dreyfuss IWL_ERR(trans, "Microcode CT kill error detected.\n"); 22032e5d4a8fSHaim Dreyfuss isr_stats->ctkill++; 22042e5d4a8fSHaim Dreyfuss } 22052e5d4a8fSHaim Dreyfuss 22062e5d4a8fSHaim Dreyfuss /* HW RF KILL switch toggled */ 22073a6e168bSJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 22083a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 22092e5d4a8fSHaim Dreyfuss 22102e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 22112e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 22122e5d4a8fSHaim Dreyfuss "Hardware error detected. Restarting.\n"); 22132e5d4a8fSHaim Dreyfuss 22142e5d4a8fSHaim Dreyfuss isr_stats->hw++; 22154b1831e4SShahar S Matityahu trans->hw_error = true; 22162e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 22172e5d4a8fSHaim Dreyfuss } 22182e5d4a8fSHaim Dreyfuss 22192e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 22202e5d4a8fSHaim Dreyfuss 22212e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 22222e5d4a8fSHaim Dreyfuss 22232e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 22242e5d4a8fSHaim Dreyfuss } 2225