18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 38e99ea8dSJohannes Berg * Copyright (C) 2003-2014, 2018-2020 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #include <linux/sched.h> 8e705c121SKalle Valo #include <linux/wait.h> 9e705c121SKalle Valo #include <linux/gfp.h> 10e705c121SKalle Valo 11e705c121SKalle Valo #include "iwl-prph.h" 12e705c121SKalle Valo #include "iwl-io.h" 13e705c121SKalle Valo #include "internal.h" 14e705c121SKalle Valo #include "iwl-op-mode.h" 159b58419eSGolan Ben Ami #include "iwl-context-info-gen3.h" 16e705c121SKalle Valo 17e705c121SKalle Valo /****************************************************************************** 18e705c121SKalle Valo * 19e705c121SKalle Valo * RX path functions 20e705c121SKalle Valo * 21e705c121SKalle Valo ******************************************************************************/ 22e705c121SKalle Valo 23e705c121SKalle Valo /* 24e705c121SKalle Valo * Rx theory of operation 25e705c121SKalle Valo * 26e705c121SKalle Valo * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 27e705c121SKalle Valo * each of which point to Receive Buffers to be filled by the NIC. These get 28e705c121SKalle Valo * used not only for Rx frames, but for any command response or notification 29e705c121SKalle Valo * from the NIC. The driver and NIC manage the Rx buffers by means 30e705c121SKalle Valo * of indexes into the circular buffer. 31e705c121SKalle Valo * 32e705c121SKalle Valo * Rx Queue Indexes 33e705c121SKalle Valo * The host/firmware share two index registers for managing the Rx buffers. 34e705c121SKalle Valo * 35e705c121SKalle Valo * The READ index maps to the first position that the firmware may be writing 36e705c121SKalle Valo * to -- the driver can read up to (but not including) this position and get 37e705c121SKalle Valo * good data. 38e705c121SKalle Valo * The READ index is managed by the firmware once the card is enabled. 39e705c121SKalle Valo * 40e705c121SKalle Valo * The WRITE index maps to the last position the driver has read from -- the 41e705c121SKalle Valo * position preceding WRITE is the last slot the firmware can place a packet. 42e705c121SKalle Valo * 43e705c121SKalle Valo * The queue is empty (no good data) if WRITE = READ - 1, and is full if 44e705c121SKalle Valo * WRITE = READ. 45e705c121SKalle Valo * 46e705c121SKalle Valo * During initialization, the host sets up the READ queue position to the first 47e705c121SKalle Valo * INDEX position, and WRITE to the last (READ - 1 wrapped) 48e705c121SKalle Valo * 49e705c121SKalle Valo * When the firmware places a packet in a buffer, it will advance the READ index 50e705c121SKalle Valo * and fire the RX interrupt. The driver can then query the READ index and 51e705c121SKalle Valo * process as many packets as possible, moving the WRITE index forward as it 52e705c121SKalle Valo * resets the Rx queue buffers with new memory. 53e705c121SKalle Valo * 54e705c121SKalle Valo * The management in the driver is as follows: 55e705c121SKalle Valo * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 56e705c121SKalle Valo * When the interrupt handler is called, the request is processed. 57e705c121SKalle Valo * The page is either stolen - transferred to the upper layer 58e705c121SKalle Valo * or reused - added immediately to the iwl->rxq->rx_free list. 59e705c121SKalle Valo * + When the page is stolen - the driver updates the matching queue's used 60e705c121SKalle Valo * count, detaches the RBD and transfers it to the queue used list. 61e705c121SKalle Valo * When there are two used RBDs - they are transferred to the allocator empty 62e705c121SKalle Valo * list. Work is then scheduled for the allocator to start allocating 63e705c121SKalle Valo * eight buffers. 64e705c121SKalle Valo * When there are another 6 used RBDs - they are transferred to the allocator 65e705c121SKalle Valo * empty list and the driver tries to claim the pre-allocated buffers and 66e705c121SKalle Valo * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 67e705c121SKalle Valo * until ready. 68e705c121SKalle Valo * When there are 8+ buffers in the free list - either from allocation or from 69e705c121SKalle Valo * 8 reused unstolen pages - restock is called to update the FW and indexes. 70e705c121SKalle Valo * + In order to make sure the allocator always has RBDs to use for allocation 71e705c121SKalle Valo * the allocator has initial pool in the size of num_queues*(8-2) - the 72e705c121SKalle Valo * maximum missing RBDs per allocation request (request posted with 2 73e705c121SKalle Valo * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 74e705c121SKalle Valo * The queues supplies the recycle of the rest of the RBDs. 75e705c121SKalle Valo * + A received packet is processed and handed to the kernel network stack, 76e705c121SKalle Valo * detached from the iwl->rxq. The driver 'processed' index is updated. 77e705c121SKalle Valo * + If there are no allocated buffers in iwl->rxq->rx_free, 78e705c121SKalle Valo * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 79e705c121SKalle Valo * If there were enough free buffers and RX_STALLED is set it is cleared. 80e705c121SKalle Valo * 81e705c121SKalle Valo * 82e705c121SKalle Valo * Driver sequence: 83e705c121SKalle Valo * 84e705c121SKalle Valo * iwl_rxq_alloc() Allocates rx_free 85e705c121SKalle Valo * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 86e705c121SKalle Valo * iwl_pcie_rxq_restock. 87e705c121SKalle Valo * Used only during initialization. 88e705c121SKalle Valo * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 89e705c121SKalle Valo * queue, updates firmware pointers, and updates 90e705c121SKalle Valo * the WRITE index. 91e705c121SKalle Valo * iwl_pcie_rx_allocator() Background work for allocating pages. 92e705c121SKalle Valo * 93e705c121SKalle Valo * -- enable interrupts -- 94e705c121SKalle Valo * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 95e705c121SKalle Valo * READ INDEX, detaching the SKB from the pool. 96e705c121SKalle Valo * Moves the packet buffer from queue to rx_used. 97e705c121SKalle Valo * Posts and claims requests to the allocator. 98e705c121SKalle Valo * Calls iwl_pcie_rxq_restock to refill any empty 99e705c121SKalle Valo * slots. 100e705c121SKalle Valo * 101e705c121SKalle Valo * RBD life-cycle: 102e705c121SKalle Valo * 103e705c121SKalle Valo * Init: 104e705c121SKalle Valo * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 105e705c121SKalle Valo * 106e705c121SKalle Valo * Regular Receive interrupt: 107e705c121SKalle Valo * Page Stolen: 108e705c121SKalle Valo * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 109e705c121SKalle Valo * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 110e705c121SKalle Valo * Page not Stolen: 111e705c121SKalle Valo * rxq.queue -> rxq.rx_free -> rxq.queue 112e705c121SKalle Valo * ... 113e705c121SKalle Valo * 114e705c121SKalle Valo */ 115e705c121SKalle Valo 116e705c121SKalle Valo /* 117e705c121SKalle Valo * iwl_rxq_space - Return number of free slots available in queue. 118e705c121SKalle Valo */ 119e705c121SKalle Valo static int iwl_rxq_space(const struct iwl_rxq *rxq) 120e705c121SKalle Valo { 12196a6497bSSara Sharon /* Make sure rx queue size is a power of 2 */ 12296a6497bSSara Sharon WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 123e705c121SKalle Valo 124e705c121SKalle Valo /* 125e705c121SKalle Valo * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 126e705c121SKalle Valo * between empty and completely full queues. 127e705c121SKalle Valo * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 128e705c121SKalle Valo * defined for negative dividends. 129e705c121SKalle Valo */ 13096a6497bSSara Sharon return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 131e705c121SKalle Valo } 132e705c121SKalle Valo 133e705c121SKalle Valo /* 134e705c121SKalle Valo * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 135e705c121SKalle Valo */ 136e705c121SKalle Valo static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 137e705c121SKalle Valo { 138e705c121SKalle Valo return cpu_to_le32((u32)(dma_addr >> 8)); 139e705c121SKalle Valo } 140e705c121SKalle Valo 141e705c121SKalle Valo /* 142e705c121SKalle Valo * iwl_pcie_rx_stop - stops the Rx DMA 143e705c121SKalle Valo */ 144e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans) 145e705c121SKalle Valo { 1463681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1473681021fSJohannes Berg /* TODO: remove this once fw does it */ 148ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 149ea695b7cSShaul Triebitz return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3, 150d0158235SGolan Ben Ami RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 151286ca8ebSLuca Coelho } else if (trans->trans_cfg->mq_rx_supported) { 152d7fdd0e5SSara Sharon iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 153d7fdd0e5SSara Sharon return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 154d7fdd0e5SSara Sharon RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 155d7fdd0e5SSara Sharon } else { 156e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 157e705c121SKalle Valo return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 158d7fdd0e5SSara Sharon FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 159d7fdd0e5SSara Sharon 1000); 160d7fdd0e5SSara Sharon } 161e705c121SKalle Valo } 162e705c121SKalle Valo 163e705c121SKalle Valo /* 164e705c121SKalle Valo * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 165e705c121SKalle Valo */ 16678485054SSara Sharon static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 16778485054SSara Sharon struct iwl_rxq *rxq) 168e705c121SKalle Valo { 169e705c121SKalle Valo u32 reg; 170e705c121SKalle Valo 171e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 172e705c121SKalle Valo 173e705c121SKalle Valo /* 174e705c121SKalle Valo * explicitly wake up the NIC if: 175e705c121SKalle Valo * 1. shadow registers aren't enabled 176e705c121SKalle Valo * 2. there is a chance that the NIC is asleep 177e705c121SKalle Valo */ 178286ca8ebSLuca Coelho if (!trans->trans_cfg->base_params->shadow_reg_enable && 179e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 180e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 181e705c121SKalle Valo 182e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 183e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 184e705c121SKalle Valo reg); 185e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 1866dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 187e705c121SKalle Valo rxq->need_update = true; 188e705c121SKalle Valo return; 189e705c121SKalle Valo } 190e705c121SKalle Valo } 191e705c121SKalle Valo 192e705c121SKalle Valo rxq->write_actual = round_down(rxq->write, 8); 1933681021fSJohannes Berg if (trans->trans_cfg->mq_rx_supported) 1941554ed20SSara Sharon iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 19596a6497bSSara Sharon rxq->write_actual); 1961316d595SSara Sharon else 197e705c121SKalle Valo iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 198e705c121SKalle Valo } 199e705c121SKalle Valo 200e705c121SKalle Valo static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 201e705c121SKalle Valo { 202e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20378485054SSara Sharon int i; 204e705c121SKalle Valo 20578485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 20678485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 207e705c121SKalle Valo 208e705c121SKalle Valo if (!rxq->need_update) 20978485054SSara Sharon continue; 21025edc8f2SJohannes Berg spin_lock_bh(&rxq->lock); 21178485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 212e705c121SKalle Valo rxq->need_update = false; 21325edc8f2SJohannes Berg spin_unlock_bh(&rxq->lock); 214e705c121SKalle Valo } 21578485054SSara Sharon } 216e705c121SKalle Valo 2170307c839SGolan Ben Ami static void iwl_pcie_restock_bd(struct iwl_trans *trans, 2180307c839SGolan Ben Ami struct iwl_rxq *rxq, 2190307c839SGolan Ben Ami struct iwl_rx_mem_buffer *rxb) 2200307c839SGolan Ben Ami { 2213681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 2220307c839SGolan Ben Ami struct iwl_rx_transfer_desc *bd = rxq->bd; 2230307c839SGolan Ben Ami 224f826faaaSJohannes Berg BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64)); 225f826faaaSJohannes Berg 2260307c839SGolan Ben Ami bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 2270307c839SGolan Ben Ami bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 2280307c839SGolan Ben Ami } else { 2290307c839SGolan Ben Ami __le64 *bd = rxq->bd; 2300307c839SGolan Ben Ami 2310307c839SGolan Ben Ami bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 2320307c839SGolan Ben Ami } 23385d78bb1SSara Sharon 23485d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n", 23585d78bb1SSara Sharon (u32)rxb->vid, rxq->id, rxq->write); 2360307c839SGolan Ben Ami } 2370307c839SGolan Ben Ami 238e0e168dcSGregory Greenman /* 2392047fa54SSara Sharon * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 240e0e168dcSGregory Greenman */ 2412047fa54SSara Sharon static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 24296a6497bSSara Sharon struct iwl_rxq *rxq) 24396a6497bSSara Sharon { 244cfdc20efSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 24596a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb; 24696a6497bSSara Sharon 24796a6497bSSara Sharon /* 24896a6497bSSara Sharon * If the device isn't enabled - no need to try to add buffers... 24996a6497bSSara Sharon * This can happen when we stop the device and still have an interrupt 25096a6497bSSara Sharon * pending. We stop the APM before we sync the interrupts because we 25196a6497bSSara Sharon * have to (see comment there). On the other hand, since the APM is 25296a6497bSSara Sharon * stopped, we cannot access the HW (in particular not prph). 25396a6497bSSara Sharon * So don't try to restock if the APM has been already stopped. 25496a6497bSSara Sharon */ 25596a6497bSSara Sharon if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 25696a6497bSSara Sharon return; 25796a6497bSSara Sharon 25825edc8f2SJohannes Berg spin_lock_bh(&rxq->lock); 25996a6497bSSara Sharon while (rxq->free_count) { 26096a6497bSSara Sharon /* Get next free Rx buffer, remove from free list */ 26196a6497bSSara Sharon rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 26296a6497bSSara Sharon list); 26396a6497bSSara Sharon list_del(&rxb->list); 264b1753c62SSara Sharon rxb->invalid = false; 265cfdc20efSJohannes Berg /* some low bits are expected to be unset (depending on hw) */ 266cfdc20efSJohannes Berg WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask); 26796a6497bSSara Sharon /* Point to Rx buffer via next RBD in circular buffer */ 2680307c839SGolan Ben Ami iwl_pcie_restock_bd(trans, rxq, rxb); 2695661925aSJohannes Berg rxq->write = (rxq->write + 1) & (rxq->queue_size - 1); 27096a6497bSSara Sharon rxq->free_count--; 27196a6497bSSara Sharon } 27225edc8f2SJohannes Berg spin_unlock_bh(&rxq->lock); 27396a6497bSSara Sharon 27496a6497bSSara Sharon /* 27596a6497bSSara Sharon * If we've added more space for the firmware to place data, tell it. 27696a6497bSSara Sharon * Increment device's write pointer in multiples of 8. 27796a6497bSSara Sharon */ 27896a6497bSSara Sharon if (rxq->write_actual != (rxq->write & ~0x7)) { 27925edc8f2SJohannes Berg spin_lock_bh(&rxq->lock); 28096a6497bSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 28125edc8f2SJohannes Berg spin_unlock_bh(&rxq->lock); 28296a6497bSSara Sharon } 28396a6497bSSara Sharon } 28496a6497bSSara Sharon 285e705c121SKalle Valo /* 2862047fa54SSara Sharon * iwl_pcie_rxsq_restock - restock implementation for single queue rx 287e705c121SKalle Valo */ 2882047fa54SSara Sharon static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 289e0e168dcSGregory Greenman struct iwl_rxq *rxq) 290e705c121SKalle Valo { 291e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 292e705c121SKalle Valo 293e705c121SKalle Valo /* 294e705c121SKalle Valo * If the device isn't enabled - not need to try to add buffers... 295e705c121SKalle Valo * This can happen when we stop the device and still have an interrupt 296e705c121SKalle Valo * pending. We stop the APM before we sync the interrupts because we 297e705c121SKalle Valo * have to (see comment there). On the other hand, since the APM is 298e705c121SKalle Valo * stopped, we cannot access the HW (in particular not prph). 299e705c121SKalle Valo * So don't try to restock if the APM has been already stopped. 300e705c121SKalle Valo */ 301e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 302e705c121SKalle Valo return; 303e705c121SKalle Valo 304e705c121SKalle Valo spin_lock(&rxq->lock); 305e705c121SKalle Valo while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 30696a6497bSSara Sharon __le32 *bd = (__le32 *)rxq->bd; 307e705c121SKalle Valo /* The overwritten rxb must be a used one */ 308e705c121SKalle Valo rxb = rxq->queue[rxq->write]; 309e705c121SKalle Valo BUG_ON(rxb && rxb->page); 310e705c121SKalle Valo 311e705c121SKalle Valo /* Get next free Rx buffer, remove from free list */ 312e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 313e705c121SKalle Valo list); 314e705c121SKalle Valo list_del(&rxb->list); 315b1753c62SSara Sharon rxb->invalid = false; 316e705c121SKalle Valo 317e705c121SKalle Valo /* Point to Rx buffer via next RBD in circular buffer */ 31896a6497bSSara Sharon bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 319e705c121SKalle Valo rxq->queue[rxq->write] = rxb; 320e705c121SKalle Valo rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 321e705c121SKalle Valo rxq->free_count--; 322e705c121SKalle Valo } 323e705c121SKalle Valo spin_unlock(&rxq->lock); 324e705c121SKalle Valo 325e705c121SKalle Valo /* If we've added more space for the firmware to place data, tell it. 326e705c121SKalle Valo * Increment device's write pointer in multiples of 8. */ 327e705c121SKalle Valo if (rxq->write_actual != (rxq->write & ~0x7)) { 328e705c121SKalle Valo spin_lock(&rxq->lock); 32978485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 330e705c121SKalle Valo spin_unlock(&rxq->lock); 331e705c121SKalle Valo } 332e705c121SKalle Valo } 333e705c121SKalle Valo 334e705c121SKalle Valo /* 335e0e168dcSGregory Greenman * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 336e0e168dcSGregory Greenman * 337e0e168dcSGregory Greenman * If there are slots in the RX queue that need to be restocked, 338e0e168dcSGregory Greenman * and we have free pre-allocated buffers, fill the ranks as much 339e0e168dcSGregory Greenman * as we can, pulling from rx_free. 340e0e168dcSGregory Greenman * 341e0e168dcSGregory Greenman * This moves the 'write' index forward to catch up with 'processed', and 342e0e168dcSGregory Greenman * also updates the memory address in the firmware to reference the new 343e0e168dcSGregory Greenman * target buffer. 344e0e168dcSGregory Greenman */ 345e0e168dcSGregory Greenman static 346e0e168dcSGregory Greenman void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 347e0e168dcSGregory Greenman { 348286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 3492047fa54SSara Sharon iwl_pcie_rxmq_restock(trans, rxq); 350e0e168dcSGregory Greenman else 3512047fa54SSara Sharon iwl_pcie_rxsq_restock(trans, rxq); 352e0e168dcSGregory Greenman } 353e0e168dcSGregory Greenman 354e0e168dcSGregory Greenman /* 355e705c121SKalle Valo * iwl_pcie_rx_alloc_page - allocates and returns a page. 356e705c121SKalle Valo * 357e705c121SKalle Valo */ 358e705c121SKalle Valo static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 359cfdc20efSJohannes Berg u32 *offset, gfp_t priority) 360e705c121SKalle Valo { 361e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 362cfdc20efSJohannes Berg unsigned int rbsize = iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 363cfdc20efSJohannes Berg unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order; 364e705c121SKalle Valo struct page *page; 365e705c121SKalle Valo gfp_t gfp_mask = priority; 366e705c121SKalle Valo 367e705c121SKalle Valo if (trans_pcie->rx_page_order > 0) 368e705c121SKalle Valo gfp_mask |= __GFP_COMP; 369e705c121SKalle Valo 370cfdc20efSJohannes Berg if (trans_pcie->alloc_page) { 371cfdc20efSJohannes Berg spin_lock_bh(&trans_pcie->alloc_page_lock); 372cfdc20efSJohannes Berg /* recheck */ 373cfdc20efSJohannes Berg if (trans_pcie->alloc_page) { 374cfdc20efSJohannes Berg *offset = trans_pcie->alloc_page_used; 375cfdc20efSJohannes Berg page = trans_pcie->alloc_page; 376cfdc20efSJohannes Berg trans_pcie->alloc_page_used += rbsize; 377cfdc20efSJohannes Berg if (trans_pcie->alloc_page_used >= allocsize) 378cfdc20efSJohannes Berg trans_pcie->alloc_page = NULL; 379cfdc20efSJohannes Berg else 380cfdc20efSJohannes Berg get_page(page); 381cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 382cfdc20efSJohannes Berg return page; 383cfdc20efSJohannes Berg } 384cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 385cfdc20efSJohannes Berg } 386cfdc20efSJohannes Berg 387e705c121SKalle Valo /* Alloc a new receive buffer */ 388e705c121SKalle Valo page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 389e705c121SKalle Valo if (!page) { 390e705c121SKalle Valo if (net_ratelimit()) 391e705c121SKalle Valo IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 392e705c121SKalle Valo trans_pcie->rx_page_order); 39378485054SSara Sharon /* 39478485054SSara Sharon * Issue an error if we don't have enough pre-allocated 39578485054SSara Sharon * buffers. 3961da3823dSLuca Coelho */ 39778485054SSara Sharon if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 398e705c121SKalle Valo IWL_CRIT(trans, 39978485054SSara Sharon "Failed to alloc_pages\n"); 400e705c121SKalle Valo return NULL; 401e705c121SKalle Valo } 402cfdc20efSJohannes Berg 403cfdc20efSJohannes Berg if (2 * rbsize <= allocsize) { 404cfdc20efSJohannes Berg spin_lock_bh(&trans_pcie->alloc_page_lock); 405cfdc20efSJohannes Berg if (!trans_pcie->alloc_page) { 406cfdc20efSJohannes Berg get_page(page); 407cfdc20efSJohannes Berg trans_pcie->alloc_page = page; 408cfdc20efSJohannes Berg trans_pcie->alloc_page_used = rbsize; 409cfdc20efSJohannes Berg } 410cfdc20efSJohannes Berg spin_unlock_bh(&trans_pcie->alloc_page_lock); 411cfdc20efSJohannes Berg } 412cfdc20efSJohannes Berg 413cfdc20efSJohannes Berg *offset = 0; 414e705c121SKalle Valo return page; 415e705c121SKalle Valo } 416e705c121SKalle Valo 417e705c121SKalle Valo /* 418e705c121SKalle Valo * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 419e705c121SKalle Valo * 420e705c121SKalle Valo * A used RBD is an Rx buffer that has been given to the stack. To use it again 421e705c121SKalle Valo * a page must be allocated and the RBD must point to the page. This function 422e705c121SKalle Valo * doesn't change the HW pointer but handles the list of pages that is used by 423e705c121SKalle Valo * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 424e705c121SKalle Valo * allocated buffers. 425e705c121SKalle Valo */ 426ff932f61SGolan Ben Ami void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 42778485054SSara Sharon struct iwl_rxq *rxq) 428e705c121SKalle Valo { 429e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 430e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 431e705c121SKalle Valo struct page *page; 432e705c121SKalle Valo 433e705c121SKalle Valo while (1) { 434cfdc20efSJohannes Berg unsigned int offset; 435cfdc20efSJohannes Berg 436e705c121SKalle Valo spin_lock(&rxq->lock); 437e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 438e705c121SKalle Valo spin_unlock(&rxq->lock); 439e705c121SKalle Valo return; 440e705c121SKalle Valo } 441e705c121SKalle Valo spin_unlock(&rxq->lock); 442e705c121SKalle Valo 443cfdc20efSJohannes Berg page = iwl_pcie_rx_alloc_page(trans, &offset, priority); 444e705c121SKalle Valo if (!page) 445e705c121SKalle Valo return; 446e705c121SKalle Valo 447e705c121SKalle Valo spin_lock(&rxq->lock); 448e705c121SKalle Valo 449e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 450e705c121SKalle Valo spin_unlock(&rxq->lock); 451e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 452e705c121SKalle Valo return; 453e705c121SKalle Valo } 454e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 455e705c121SKalle Valo list); 456e705c121SKalle Valo list_del(&rxb->list); 457e705c121SKalle Valo spin_unlock(&rxq->lock); 458e705c121SKalle Valo 459e705c121SKalle Valo BUG_ON(rxb->page); 460e705c121SKalle Valo rxb->page = page; 461cfdc20efSJohannes Berg rxb->offset = offset; 462e705c121SKalle Valo /* Get physical address of the RB */ 463e705c121SKalle Valo rxb->page_dma = 464cfdc20efSJohannes Berg dma_map_page(trans->dev, page, rxb->offset, 46580084e35SJohannes Berg trans_pcie->rx_buf_bytes, 466e705c121SKalle Valo DMA_FROM_DEVICE); 467e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 468e705c121SKalle Valo rxb->page = NULL; 469e705c121SKalle Valo spin_lock(&rxq->lock); 470e705c121SKalle Valo list_add(&rxb->list, &rxq->rx_used); 471e705c121SKalle Valo spin_unlock(&rxq->lock); 472e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 473e705c121SKalle Valo return; 474e705c121SKalle Valo } 475e705c121SKalle Valo 476e705c121SKalle Valo spin_lock(&rxq->lock); 477e705c121SKalle Valo 478e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 479e705c121SKalle Valo rxq->free_count++; 480e705c121SKalle Valo 481e705c121SKalle Valo spin_unlock(&rxq->lock); 482e705c121SKalle Valo } 483e705c121SKalle Valo } 484e705c121SKalle Valo 485ff932f61SGolan Ben Ami void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 486e705c121SKalle Valo { 487e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 488e705c121SKalle Valo int i; 489e705c121SKalle Valo 490c042f0c7SJohannes Berg for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) { 49178485054SSara Sharon if (!trans_pcie->rx_pool[i].page) 492e705c121SKalle Valo continue; 49378485054SSara Sharon dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 49480084e35SJohannes Berg trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE); 49578485054SSara Sharon __free_pages(trans_pcie->rx_pool[i].page, 49678485054SSara Sharon trans_pcie->rx_page_order); 49778485054SSara Sharon trans_pcie->rx_pool[i].page = NULL; 498e705c121SKalle Valo } 499e705c121SKalle Valo } 500e705c121SKalle Valo 501e705c121SKalle Valo /* 502e705c121SKalle Valo * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 503e705c121SKalle Valo * 504e705c121SKalle Valo * Allocates for each received request 8 pages 505e705c121SKalle Valo * Called as a scheduled work item. 506e705c121SKalle Valo */ 507e705c121SKalle Valo static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 508e705c121SKalle Valo { 509e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 510e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 511e705c121SKalle Valo struct list_head local_empty; 512c6ac9f9fSSara Sharon int pending = atomic_read(&rba->req_pending); 513e705c121SKalle Valo 5146dcdd165SSara Sharon IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending); 515e705c121SKalle Valo 516e705c121SKalle Valo /* If we were scheduled - there is at least one request */ 51725edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 518e705c121SKalle Valo /* swap out the rba->rbd_empty to a local list */ 519e705c121SKalle Valo list_replace_init(&rba->rbd_empty, &local_empty); 52025edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 521e705c121SKalle Valo 522e705c121SKalle Valo while (pending) { 523e705c121SKalle Valo int i; 5240979a913SJohannes Berg LIST_HEAD(local_allocated); 52578485054SSara Sharon gfp_t gfp_mask = GFP_KERNEL; 52678485054SSara Sharon 52778485054SSara Sharon /* Do not post a warning if there are only a few requests */ 52878485054SSara Sharon if (pending < RX_PENDING_WATERMARK) 52978485054SSara Sharon gfp_mask |= __GFP_NOWARN; 530e705c121SKalle Valo 531e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 532e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 533e705c121SKalle Valo struct page *page; 534e705c121SKalle Valo 535e705c121SKalle Valo /* List should never be empty - each reused RBD is 536e705c121SKalle Valo * returned to the list, and initial pool covers any 537e705c121SKalle Valo * possible gap between the time the page is allocated 538e705c121SKalle Valo * to the time the RBD is added. 539e705c121SKalle Valo */ 540e705c121SKalle Valo BUG_ON(list_empty(&local_empty)); 541e705c121SKalle Valo /* Get the first rxb from the rbd list */ 542e705c121SKalle Valo rxb = list_first_entry(&local_empty, 543e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 544e705c121SKalle Valo BUG_ON(rxb->page); 545e705c121SKalle Valo 546e705c121SKalle Valo /* Alloc a new receive buffer */ 547cfdc20efSJohannes Berg page = iwl_pcie_rx_alloc_page(trans, &rxb->offset, 548cfdc20efSJohannes Berg gfp_mask); 549e705c121SKalle Valo if (!page) 550e705c121SKalle Valo continue; 551e705c121SKalle Valo rxb->page = page; 552e705c121SKalle Valo 553e705c121SKalle Valo /* Get physical address of the RB */ 554cfdc20efSJohannes Berg rxb->page_dma = dma_map_page(trans->dev, page, 555cfdc20efSJohannes Berg rxb->offset, 55680084e35SJohannes Berg trans_pcie->rx_buf_bytes, 557e705c121SKalle Valo DMA_FROM_DEVICE); 558e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 559e705c121SKalle Valo rxb->page = NULL; 560e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 561e705c121SKalle Valo continue; 562e705c121SKalle Valo } 563e705c121SKalle Valo 564e705c121SKalle Valo /* move the allocated entry to the out list */ 565e705c121SKalle Valo list_move(&rxb->list, &local_allocated); 566e705c121SKalle Valo i++; 567e705c121SKalle Valo } 568e705c121SKalle Valo 569c6ac9f9fSSara Sharon atomic_dec(&rba->req_pending); 570e705c121SKalle Valo pending--; 571c6ac9f9fSSara Sharon 572e705c121SKalle Valo if (!pending) { 573c6ac9f9fSSara Sharon pending = atomic_read(&rba->req_pending); 5746dcdd165SSara Sharon if (pending) 5756dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 576c6ac9f9fSSara Sharon "Got more pending allocation requests = %d\n", 577e705c121SKalle Valo pending); 578e705c121SKalle Valo } 579e705c121SKalle Valo 58025edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 581e705c121SKalle Valo /* add the allocated rbds to the allocator allocated list */ 582e705c121SKalle Valo list_splice_tail(&local_allocated, &rba->rbd_allocated); 583e705c121SKalle Valo /* get more empty RBDs for current pending requests */ 584e705c121SKalle Valo list_splice_tail_init(&rba->rbd_empty, &local_empty); 58525edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 586e705c121SKalle Valo 587e705c121SKalle Valo atomic_inc(&rba->req_ready); 588c6ac9f9fSSara Sharon 589e705c121SKalle Valo } 590e705c121SKalle Valo 59125edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 592e705c121SKalle Valo /* return unused rbds to the allocator empty list */ 593e705c121SKalle Valo list_splice_tail(&local_empty, &rba->rbd_empty); 59425edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 595c6ac9f9fSSara Sharon 5966dcdd165SSara Sharon IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__); 597e705c121SKalle Valo } 598e705c121SKalle Valo 599e705c121SKalle Valo /* 600d56daea4SSara Sharon * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 601e705c121SKalle Valo .* 602e705c121SKalle Valo .* Called by queue when the queue posted allocation request and 603e705c121SKalle Valo * has freed 8 RBDs in order to restock itself. 604d56daea4SSara Sharon * This function directly moves the allocated RBs to the queue's ownership 605d56daea4SSara Sharon * and updates the relevant counters. 606e705c121SKalle Valo */ 607d56daea4SSara Sharon static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 608d56daea4SSara Sharon struct iwl_rxq *rxq) 609e705c121SKalle Valo { 610e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 611e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 612e705c121SKalle Valo int i; 613e705c121SKalle Valo 614d56daea4SSara Sharon lockdep_assert_held(&rxq->lock); 615d56daea4SSara Sharon 616e705c121SKalle Valo /* 617e705c121SKalle Valo * atomic_dec_if_positive returns req_ready - 1 for any scenario. 618e705c121SKalle Valo * If req_ready is 0 atomic_dec_if_positive will return -1 and this 619d56daea4SSara Sharon * function will return early, as there are no ready requests. 620e705c121SKalle Valo * atomic_dec_if_positive will perofrm the *actual* decrement only if 621e705c121SKalle Valo * req_ready > 0, i.e. - there are ready requests and the function 622e705c121SKalle Valo * hands one request to the caller. 623e705c121SKalle Valo */ 624e705c121SKalle Valo if (atomic_dec_if_positive(&rba->req_ready) < 0) 625d56daea4SSara Sharon return; 626e705c121SKalle Valo 627e705c121SKalle Valo spin_lock(&rba->lock); 628e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 629e705c121SKalle Valo /* Get next free Rx buffer, remove it from free list */ 630d56daea4SSara Sharon struct iwl_rx_mem_buffer *rxb = 631d56daea4SSara Sharon list_first_entry(&rba->rbd_allocated, 632e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 633d56daea4SSara Sharon 634d56daea4SSara Sharon list_move(&rxb->list, &rxq->rx_free); 635e705c121SKalle Valo } 636e705c121SKalle Valo spin_unlock(&rba->lock); 637e705c121SKalle Valo 638d56daea4SSara Sharon rxq->used_count -= RX_CLAIM_REQ_ALLOC; 639d56daea4SSara Sharon rxq->free_count += RX_CLAIM_REQ_ALLOC; 640e705c121SKalle Valo } 641e705c121SKalle Valo 64210a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data) 643e705c121SKalle Valo { 644e705c121SKalle Valo struct iwl_rb_allocator *rba_p = 645e705c121SKalle Valo container_of(data, struct iwl_rb_allocator, rx_alloc); 646e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 647e705c121SKalle Valo container_of(rba_p, struct iwl_trans_pcie, rba); 648e705c121SKalle Valo 649e705c121SKalle Valo iwl_pcie_rx_allocator(trans_pcie->trans); 650e705c121SKalle Valo } 651e705c121SKalle Valo 6520307c839SGolan Ben Ami static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td) 6530307c839SGolan Ben Ami { 6540307c839SGolan Ben Ami struct iwl_rx_transfer_desc *rx_td; 6550307c839SGolan Ben Ami 6560307c839SGolan Ben Ami if (use_rx_td) 6570307c839SGolan Ben Ami return sizeof(*rx_td); 6580307c839SGolan Ben Ami else 659286ca8ebSLuca Coelho return trans->trans_cfg->mq_rx_supported ? sizeof(__le64) : 6600307c839SGolan Ben Ami sizeof(__le32); 6610307c839SGolan Ben Ami } 6620307c839SGolan Ben Ami 6631b493e30SGolan Ben Ami static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 6641b493e30SGolan Ben Ami struct iwl_rxq *rxq) 6651b493e30SGolan Ben Ami { 6661b493e30SGolan Ben Ami struct device *dev = trans->dev; 667286ca8ebSLuca Coelho bool use_rx_td = (trans->trans_cfg->device_family >= 6683681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210); 6690307c839SGolan Ben Ami int free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 6701b493e30SGolan Ben Ami 6711b493e30SGolan Ben Ami if (rxq->bd) 6720307c839SGolan Ben Ami dma_free_coherent(trans->dev, 6730307c839SGolan Ben Ami free_size * rxq->queue_size, 6741b493e30SGolan Ben Ami rxq->bd, rxq->bd_dma); 6751b493e30SGolan Ben Ami rxq->bd_dma = 0; 6761b493e30SGolan Ben Ami rxq->bd = NULL; 6771b493e30SGolan Ben Ami 6781b493e30SGolan Ben Ami rxq->rb_stts_dma = 0; 6791b493e30SGolan Ben Ami rxq->rb_stts = NULL; 6801b493e30SGolan Ben Ami 6811b493e30SGolan Ben Ami if (rxq->used_bd) 6820307c839SGolan Ben Ami dma_free_coherent(trans->dev, 683b2a58c97SSara Sharon (use_rx_td ? sizeof(*rxq->cd) : 6840307c839SGolan Ben Ami sizeof(__le32)) * rxq->queue_size, 6851b493e30SGolan Ben Ami rxq->used_bd, rxq->used_bd_dma); 6861b493e30SGolan Ben Ami rxq->used_bd_dma = 0; 6871b493e30SGolan Ben Ami rxq->used_bd = NULL; 6881b493e30SGolan Ben Ami 6893681021fSJohannes Berg if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 6901b493e30SGolan Ben Ami return; 6911b493e30SGolan Ben Ami 6921b493e30SGolan Ben Ami if (rxq->tr_tail) 6931b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 6941b493e30SGolan Ben Ami rxq->tr_tail, rxq->tr_tail_dma); 6951b493e30SGolan Ben Ami rxq->tr_tail_dma = 0; 6961b493e30SGolan Ben Ami rxq->tr_tail = NULL; 6971b493e30SGolan Ben Ami 6981b493e30SGolan Ben Ami if (rxq->cr_tail) 6991b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 7001b493e30SGolan Ben Ami rxq->cr_tail, rxq->cr_tail_dma); 7011b493e30SGolan Ben Ami rxq->cr_tail_dma = 0; 7021b493e30SGolan Ben Ami rxq->cr_tail = NULL; 7031b493e30SGolan Ben Ami } 7041b493e30SGolan Ben Ami 7051b493e30SGolan Ben Ami static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 7061b493e30SGolan Ben Ami struct iwl_rxq *rxq) 707e705c121SKalle Valo { 708e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 709e705c121SKalle Valo struct device *dev = trans->dev; 71078485054SSara Sharon int i; 7110307c839SGolan Ben Ami int free_size; 712286ca8ebSLuca Coelho bool use_rx_td = (trans->trans_cfg->device_family >= 7133681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210); 7146cc6ba3aSTriebitz size_t rb_stts_size = use_rx_td ? sizeof(__le16) : 7156cc6ba3aSTriebitz sizeof(struct iwl_rb_status); 716e705c121SKalle Valo 71778485054SSara Sharon spin_lock_init(&rxq->lock); 718286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 719c042f0c7SJohannes Berg rxq->queue_size = trans->cfg->num_rbds; 72096a6497bSSara Sharon else 72196a6497bSSara Sharon rxq->queue_size = RX_QUEUE_SIZE; 72296a6497bSSara Sharon 7230307c839SGolan Ben Ami free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 7240307c839SGolan Ben Ami 72578485054SSara Sharon /* 72678485054SSara Sharon * Allocate the circular buffer of Read Buffer Descriptors 72778485054SSara Sharon * (RBDs) 72878485054SSara Sharon */ 729750afb08SLuis Chamberlain rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size, 730e705c121SKalle Valo &rxq->bd_dma, GFP_KERNEL); 731e705c121SKalle Valo if (!rxq->bd) 73278485054SSara Sharon goto err; 73378485054SSara Sharon 734286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) { 735750afb08SLuis Chamberlain rxq->used_bd = dma_alloc_coherent(dev, 736750afb08SLuis Chamberlain (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size, 73796a6497bSSara Sharon &rxq->used_bd_dma, 73896a6497bSSara Sharon GFP_KERNEL); 73996a6497bSSara Sharon if (!rxq->used_bd) 74096a6497bSSara Sharon goto err; 74196a6497bSSara Sharon } 742e705c121SKalle Valo 7436cc6ba3aSTriebitz rxq->rb_stts = trans_pcie->base_rb_stts + rxq->id * rb_stts_size; 7446cc6ba3aSTriebitz rxq->rb_stts_dma = 7456cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size; 7461b493e30SGolan Ben Ami 7470307c839SGolan Ben Ami if (!use_rx_td) 7481b493e30SGolan Ben Ami return 0; 7491b493e30SGolan Ben Ami 7501b493e30SGolan Ben Ami /* Allocate the driver's pointer to TR tail */ 751750afb08SLuis Chamberlain rxq->tr_tail = dma_alloc_coherent(dev, sizeof(__le16), 752750afb08SLuis Chamberlain &rxq->tr_tail_dma, GFP_KERNEL); 7531b493e30SGolan Ben Ami if (!rxq->tr_tail) 7541b493e30SGolan Ben Ami goto err; 7551b493e30SGolan Ben Ami 7561b493e30SGolan Ben Ami /* Allocate the driver's pointer to CR tail */ 757750afb08SLuis Chamberlain rxq->cr_tail = dma_alloc_coherent(dev, sizeof(__le16), 758750afb08SLuis Chamberlain &rxq->cr_tail_dma, GFP_KERNEL); 7591b493e30SGolan Ben Ami if (!rxq->cr_tail) 7601b493e30SGolan Ben Ami goto err; 7611b493e30SGolan Ben Ami 762e705c121SKalle Valo return 0; 763e705c121SKalle Valo 76478485054SSara Sharon err: 76578485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 76678485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 76778485054SSara Sharon 7681b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 76978485054SSara Sharon } 77096a6497bSSara Sharon 771e705c121SKalle Valo return -ENOMEM; 772e705c121SKalle Valo } 773e705c121SKalle Valo 774ab393cb1SJohannes Berg static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 7751b493e30SGolan Ben Ami { 7761b493e30SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 7771b493e30SGolan Ben Ami struct iwl_rb_allocator *rba = &trans_pcie->rba; 7781b493e30SGolan Ben Ami int i, ret; 779286ca8ebSLuca Coelho size_t rb_stts_size = trans->trans_cfg->device_family >= 7803681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210 ? 7816cc6ba3aSTriebitz sizeof(__le16) : sizeof(struct iwl_rb_status); 7821b493e30SGolan Ben Ami 7831b493e30SGolan Ben Ami if (WARN_ON(trans_pcie->rxq)) 7841b493e30SGolan Ben Ami return -EINVAL; 7851b493e30SGolan Ben Ami 7861b493e30SGolan Ben Ami trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 7871b493e30SGolan Ben Ami GFP_KERNEL); 788c042f0c7SJohannes Berg trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 789c042f0c7SJohannes Berg sizeof(trans_pcie->rx_pool[0]), 790c042f0c7SJohannes Berg GFP_KERNEL); 791c042f0c7SJohannes Berg trans_pcie->global_table = 792c042f0c7SJohannes Berg kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs), 793c042f0c7SJohannes Berg sizeof(trans_pcie->global_table[0]), 794c042f0c7SJohannes Berg GFP_KERNEL); 795c042f0c7SJohannes Berg if (!trans_pcie->rxq || !trans_pcie->rx_pool || 796c042f0c7SJohannes Berg !trans_pcie->global_table) { 797c042f0c7SJohannes Berg ret = -ENOMEM; 798c042f0c7SJohannes Berg goto err; 799c042f0c7SJohannes Berg } 8001b493e30SGolan Ben Ami 8011b493e30SGolan Ben Ami spin_lock_init(&rba->lock); 8021b493e30SGolan Ben Ami 8036cc6ba3aSTriebitz /* 8046cc6ba3aSTriebitz * Allocate the driver's pointer to receive buffer status. 8056cc6ba3aSTriebitz * Allocate for all queues continuously (HW requirement). 8066cc6ba3aSTriebitz */ 8076cc6ba3aSTriebitz trans_pcie->base_rb_stts = 8086cc6ba3aSTriebitz dma_alloc_coherent(trans->dev, 8096cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 8106cc6ba3aSTriebitz &trans_pcie->base_rb_stts_dma, 8116cc6ba3aSTriebitz GFP_KERNEL); 8126cc6ba3aSTriebitz if (!trans_pcie->base_rb_stts) { 8136cc6ba3aSTriebitz ret = -ENOMEM; 8146cc6ba3aSTriebitz goto err; 8156cc6ba3aSTriebitz } 8166cc6ba3aSTriebitz 8171b493e30SGolan Ben Ami for (i = 0; i < trans->num_rx_queues; i++) { 8181b493e30SGolan Ben Ami struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 8191b493e30SGolan Ben Ami 8206cc6ba3aSTriebitz rxq->id = i; 8211b493e30SGolan Ben Ami ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 8221b493e30SGolan Ben Ami if (ret) 8236cc6ba3aSTriebitz goto err; 8241b493e30SGolan Ben Ami } 8251b493e30SGolan Ben Ami return 0; 8266cc6ba3aSTriebitz 8276cc6ba3aSTriebitz err: 8286cc6ba3aSTriebitz if (trans_pcie->base_rb_stts) { 8296cc6ba3aSTriebitz dma_free_coherent(trans->dev, 8306cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 8316cc6ba3aSTriebitz trans_pcie->base_rb_stts, 8326cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma); 8336cc6ba3aSTriebitz trans_pcie->base_rb_stts = NULL; 8346cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma = 0; 8356cc6ba3aSTriebitz } 836c042f0c7SJohannes Berg kfree(trans_pcie->rx_pool); 837c042f0c7SJohannes Berg kfree(trans_pcie->global_table); 8386cc6ba3aSTriebitz kfree(trans_pcie->rxq); 8396cc6ba3aSTriebitz 8406cc6ba3aSTriebitz return ret; 8411b493e30SGolan Ben Ami } 8421b493e30SGolan Ben Ami 843e705c121SKalle Valo static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 844e705c121SKalle Valo { 845e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 846e705c121SKalle Valo u32 rb_size; 847dfcfeef9SSara Sharon unsigned long flags; 848e705c121SKalle Valo const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 849e705c121SKalle Valo 8506c4fbcbcSEmmanuel Grumbach switch (trans_pcie->rx_buf_size) { 8516c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 852e705c121SKalle Valo rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8536c4fbcbcSEmmanuel Grumbach break; 8546c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 8556c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 8566c4fbcbcSEmmanuel Grumbach break; 8576c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 8586c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 8596c4fbcbcSEmmanuel Grumbach break; 8606c4fbcbcSEmmanuel Grumbach default: 8616c4fbcbcSEmmanuel Grumbach WARN_ON(1); 8626c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8636c4fbcbcSEmmanuel Grumbach } 864e705c121SKalle Valo 865dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 866dfcfeef9SSara Sharon return; 867dfcfeef9SSara Sharon 868e705c121SKalle Valo /* Stop Rx DMA */ 869dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 870e705c121SKalle Valo /* reset and flush pointers */ 871dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 872dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 873dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 874e705c121SKalle Valo 875e705c121SKalle Valo /* Reset driver's Rx queue write index */ 876dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 877e705c121SKalle Valo 878e705c121SKalle Valo /* Tell device where to find RBD circular buffer in DRAM */ 879dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 880e705c121SKalle Valo (u32)(rxq->bd_dma >> 8)); 881e705c121SKalle Valo 882e705c121SKalle Valo /* Tell device where in DRAM to update its Rx status */ 883dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 884e705c121SKalle Valo rxq->rb_stts_dma >> 4); 885e705c121SKalle Valo 886e705c121SKalle Valo /* Enable Rx DMA 887e705c121SKalle Valo * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 888e705c121SKalle Valo * the credit mechanism in 5000 HW RX FIFO 889e705c121SKalle Valo * Direct rx interrupts to hosts 8906c4fbcbcSEmmanuel Grumbach * Rx buffer size 4 or 8k or 12k 891e705c121SKalle Valo * RB timeout 0x10 892e705c121SKalle Valo * 256 RBDs 893e705c121SKalle Valo */ 894dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 895e705c121SKalle Valo FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 896e705c121SKalle Valo FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 897e705c121SKalle Valo FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 898e705c121SKalle Valo rb_size | 899e705c121SKalle Valo (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 900e705c121SKalle Valo (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 901e705c121SKalle Valo 902dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 903dfcfeef9SSara Sharon 904e705c121SKalle Valo /* Set interrupt coalescing timer to default (2048 usecs) */ 905e705c121SKalle Valo iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 906e705c121SKalle Valo 907e705c121SKalle Valo /* W/A for interrupt coalescing bug in 7260 and 3160 */ 908e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) 909e705c121SKalle Valo iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 910e705c121SKalle Valo } 911e705c121SKalle Valo 912bce97731SSara Sharon static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 91396a6497bSSara Sharon { 91496a6497bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 91596a6497bSSara Sharon u32 rb_size, enabled = 0; 916dfcfeef9SSara Sharon unsigned long flags; 91796a6497bSSara Sharon int i; 91896a6497bSSara Sharon 91996a6497bSSara Sharon switch (trans_pcie->rx_buf_size) { 9201a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 9211a4968d1SGolan Ben Ami rb_size = RFH_RXF_DMA_RB_SIZE_2K; 9221a4968d1SGolan Ben Ami break; 92396a6497bSSara Sharon case IWL_AMSDU_4K: 92496a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 92596a6497bSSara Sharon break; 92696a6497bSSara Sharon case IWL_AMSDU_8K: 92796a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_8K; 92896a6497bSSara Sharon break; 92996a6497bSSara Sharon case IWL_AMSDU_12K: 93096a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_12K; 93196a6497bSSara Sharon break; 93296a6497bSSara Sharon default: 93396a6497bSSara Sharon WARN_ON(1); 93496a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 93596a6497bSSara Sharon } 93696a6497bSSara Sharon 937dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 938dfcfeef9SSara Sharon return; 939dfcfeef9SSara Sharon 94096a6497bSSara Sharon /* Stop Rx DMA */ 941dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 94296a6497bSSara Sharon /* disable free amd used rx queue operation */ 943dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 94496a6497bSSara Sharon 94596a6497bSSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 94696a6497bSSara Sharon /* Tell device where to find RBD free table in DRAM */ 94712a17458SSara Sharon iwl_write_prph64_no_grab(trans, 948dfcfeef9SSara Sharon RFH_Q_FRBDCB_BA_LSB(i), 949dfcfeef9SSara Sharon trans_pcie->rxq[i].bd_dma); 95096a6497bSSara Sharon /* Tell device where to find RBD used table in DRAM */ 95112a17458SSara Sharon iwl_write_prph64_no_grab(trans, 952dfcfeef9SSara Sharon RFH_Q_URBDCB_BA_LSB(i), 953dfcfeef9SSara Sharon trans_pcie->rxq[i].used_bd_dma); 95496a6497bSSara Sharon /* Tell device where in DRAM to update its Rx status */ 95512a17458SSara Sharon iwl_write_prph64_no_grab(trans, 956dfcfeef9SSara Sharon RFH_Q_URBD_STTS_WPTR_LSB(i), 957bce97731SSara Sharon trans_pcie->rxq[i].rb_stts_dma); 95896a6497bSSara Sharon /* Reset device indice tables */ 959dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 960dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 961dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 96296a6497bSSara Sharon 96396a6497bSSara Sharon enabled |= BIT(i) | BIT(i + 16); 96496a6497bSSara Sharon } 96596a6497bSSara Sharon 96696a6497bSSara Sharon /* 96796a6497bSSara Sharon * Enable Rx DMA 96896a6497bSSara Sharon * Rx buffer size 4 or 8k or 12k 96996a6497bSSara Sharon * Min RB size 4 or 8 97088076015SSara Sharon * Drop frames that exceed RB size 97196a6497bSSara Sharon * 512 RBDs 97296a6497bSSara Sharon */ 973dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 97463044335SSara Sharon RFH_DMA_EN_ENABLE_VAL | rb_size | 97596a6497bSSara Sharon RFH_RXF_DMA_MIN_RB_4_8 | 97688076015SSara Sharon RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 97796a6497bSSara Sharon RFH_RXF_DMA_RBDCB_SIZE_512); 97896a6497bSSara Sharon 97988076015SSara Sharon /* 98088076015SSara Sharon * Activate DMA snooping. 981b0262f07SSara Sharon * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 98288076015SSara Sharon * Default queue is 0 98388076015SSara Sharon */ 984f3779f47SJohannes Berg iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 985f3779f47SJohannes Berg RFH_GEN_CFG_RFH_DMA_SNOOP | 986f3779f47SJohannes Berg RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 987b0262f07SSara Sharon RFH_GEN_CFG_SERVICE_DMA_SNOOP | 988f3779f47SJohannes Berg RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 9897897dfa2SLuca Coelho trans->trans_cfg->integrated ? 990b0262f07SSara Sharon RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 991f3779f47SJohannes Berg RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 99288076015SSara Sharon /* Enable the relevant rx queues */ 993dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 994dfcfeef9SSara Sharon 995dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 99696a6497bSSara Sharon 99796a6497bSSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 99896a6497bSSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 99996a6497bSSara Sharon } 100096a6497bSSara Sharon 1001ff932f61SGolan Ben Ami void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 1002e705c121SKalle Valo { 1003e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 1004e705c121SKalle Valo 1005e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_free); 1006e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_used); 1007e705c121SKalle Valo rxq->free_count = 0; 1008e705c121SKalle Valo rxq->used_count = 0; 1009e705c121SKalle Valo } 1010e705c121SKalle Valo 101125edc8f2SJohannes Berg static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget); 101225edc8f2SJohannes Berg 101325edc8f2SJohannes Berg static int iwl_pcie_napi_poll(struct napi_struct *napi, int budget) 1014bce97731SSara Sharon { 101525edc8f2SJohannes Berg struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 101625edc8f2SJohannes Berg struct iwl_trans_pcie *trans_pcie; 101725edc8f2SJohannes Berg struct iwl_trans *trans; 101825edc8f2SJohannes Berg int ret; 101925edc8f2SJohannes Berg 102025edc8f2SJohannes Berg trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 102125edc8f2SJohannes Berg trans = trans_pcie->trans; 102225edc8f2SJohannes Berg 102325edc8f2SJohannes Berg ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 102425edc8f2SJohannes Berg 102525edc8f2SJohannes Berg if (ret < budget) { 102625edc8f2SJohannes Berg spin_lock(&trans_pcie->irq_lock); 102725edc8f2SJohannes Berg if (test_bit(STATUS_INT_ENABLED, &trans->status)) 102825edc8f2SJohannes Berg _iwl_enable_interrupts(trans); 102925edc8f2SJohannes Berg spin_unlock(&trans_pcie->irq_lock); 103025edc8f2SJohannes Berg 103125edc8f2SJohannes Berg napi_complete_done(&rxq->napi, ret); 103225edc8f2SJohannes Berg } 103325edc8f2SJohannes Berg 103425edc8f2SJohannes Berg return ret; 103525edc8f2SJohannes Berg } 103625edc8f2SJohannes Berg 103725edc8f2SJohannes Berg static int iwl_pcie_napi_poll_msix(struct napi_struct *napi, int budget) 103825edc8f2SJohannes Berg { 103925edc8f2SJohannes Berg struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 104025edc8f2SJohannes Berg struct iwl_trans_pcie *trans_pcie; 104125edc8f2SJohannes Berg struct iwl_trans *trans; 104225edc8f2SJohannes Berg int ret; 104325edc8f2SJohannes Berg 104425edc8f2SJohannes Berg trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 104525edc8f2SJohannes Berg trans = trans_pcie->trans; 104625edc8f2SJohannes Berg 104725edc8f2SJohannes Berg ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 104825edc8f2SJohannes Berg 104925edc8f2SJohannes Berg if (ret < budget) { 105025edc8f2SJohannes Berg spin_lock(&trans_pcie->irq_lock); 105125edc8f2SJohannes Berg iwl_pcie_clear_irq(trans, rxq->id); 105225edc8f2SJohannes Berg spin_unlock(&trans_pcie->irq_lock); 105325edc8f2SJohannes Berg 105425edc8f2SJohannes Berg napi_complete_done(&rxq->napi, ret); 105525edc8f2SJohannes Berg } 105625edc8f2SJohannes Berg 105725edc8f2SJohannes Berg return ret; 105825edc8f2SJohannes Berg } 105925edc8f2SJohannes Berg 106025edc8f2SJohannes Berg static int iwl_pcie_napi_poll_msix_shared(struct napi_struct *napi, int budget) 106125edc8f2SJohannes Berg { 106225edc8f2SJohannes Berg struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi); 106325edc8f2SJohannes Berg struct iwl_trans_pcie *trans_pcie; 106425edc8f2SJohannes Berg struct iwl_trans *trans; 106525edc8f2SJohannes Berg int ret; 106625edc8f2SJohannes Berg 106725edc8f2SJohannes Berg trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev); 106825edc8f2SJohannes Berg trans = trans_pcie->trans; 106925edc8f2SJohannes Berg 107025edc8f2SJohannes Berg ret = iwl_pcie_rx_handle(trans, rxq->id, budget); 107125edc8f2SJohannes Berg 107225edc8f2SJohannes Berg if (ret < budget) { 107325edc8f2SJohannes Berg spin_lock(&trans_pcie->irq_lock); 107425edc8f2SJohannes Berg iwl_pcie_clear_irq(trans, 0); 107525edc8f2SJohannes Berg spin_unlock(&trans_pcie->irq_lock); 107625edc8f2SJohannes Berg 107725edc8f2SJohannes Berg napi_complete_done(&rxq->napi, ret); 107825edc8f2SJohannes Berg } 107925edc8f2SJohannes Berg 108025edc8f2SJohannes Berg return ret; 1081bce97731SSara Sharon } 1082bce97731SSara Sharon 1083ab393cb1SJohannes Berg static int _iwl_pcie_rx_init(struct iwl_trans *trans) 1084e705c121SKalle Valo { 1085e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 108678485054SSara Sharon struct iwl_rxq *def_rxq; 1087e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 10887b542436SSara Sharon int i, err, queue_size, allocator_pool_size, num_alloc; 1089e705c121SKalle Valo 109078485054SSara Sharon if (!trans_pcie->rxq) { 1091e705c121SKalle Valo err = iwl_pcie_rx_alloc(trans); 1092e705c121SKalle Valo if (err) 1093e705c121SKalle Valo return err; 1094e705c121SKalle Valo } 109578485054SSara Sharon def_rxq = trans_pcie->rxq; 1096e705c121SKalle Valo 10970f22e400SShaul Triebitz cancel_work_sync(&rba->rx_alloc); 10980f22e400SShaul Triebitz 109925edc8f2SJohannes Berg spin_lock_bh(&rba->lock); 1100e705c121SKalle Valo atomic_set(&rba->req_pending, 0); 1101e705c121SKalle Valo atomic_set(&rba->req_ready, 0); 110296a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_allocated); 110396a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_empty); 110425edc8f2SJohannes Berg spin_unlock_bh(&rba->lock); 1105e705c121SKalle Valo 1106e705c121SKalle Valo /* free all first - we might be reconfigured for a different size */ 110778485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1108e705c121SKalle Valo 1109e705c121SKalle Valo for (i = 0; i < RX_QUEUE_SIZE; i++) 111078485054SSara Sharon def_rxq->queue[i] = NULL; 1111e705c121SKalle Valo 111278485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 111378485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1114e705c121SKalle Valo 1115e705c121SKalle Valo spin_lock(&rxq->lock); 111678485054SSara Sharon /* 111778485054SSara Sharon * Set read write pointer to reflect that we have processed 111878485054SSara Sharon * and used all buffers, but have not restocked the Rx queue 111978485054SSara Sharon * with fresh buffers 112078485054SSara Sharon */ 112178485054SSara Sharon rxq->read = 0; 112278485054SSara Sharon rxq->write = 0; 112378485054SSara Sharon rxq->write_actual = 0; 11243681021fSJohannes Berg memset(rxq->rb_stts, 0, 11253681021fSJohannes Berg (trans->trans_cfg->device_family >= 11263681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210) ? 11270307c839SGolan Ben Ami sizeof(__le16) : sizeof(struct iwl_rb_status)); 112878485054SSara Sharon 112978485054SSara Sharon iwl_pcie_rx_init_rxb_lists(rxq); 113078485054SSara Sharon 113125edc8f2SJohannes Berg if (!rxq->napi.poll) { 113225edc8f2SJohannes Berg int (*poll)(struct napi_struct *, int) = iwl_pcie_napi_poll; 113325edc8f2SJohannes Berg 113425edc8f2SJohannes Berg if (trans_pcie->msix_enabled) { 113525edc8f2SJohannes Berg poll = iwl_pcie_napi_poll_msix; 113625edc8f2SJohannes Berg 113725edc8f2SJohannes Berg if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX && 113825edc8f2SJohannes Berg i == 0) 113925edc8f2SJohannes Berg poll = iwl_pcie_napi_poll_msix_shared; 114025edc8f2SJohannes Berg 114125edc8f2SJohannes Berg if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS && 114225edc8f2SJohannes Berg i == 1) 114325edc8f2SJohannes Berg poll = iwl_pcie_napi_poll_msix_shared; 114425edc8f2SJohannes Berg } 114525edc8f2SJohannes Berg 1146bce97731SSara Sharon netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 114725edc8f2SJohannes Berg poll, NAPI_POLL_WEIGHT); 114825edc8f2SJohannes Berg napi_enable(&rxq->napi); 114925edc8f2SJohannes Berg } 1150bce97731SSara Sharon 1151e705c121SKalle Valo spin_unlock(&rxq->lock); 115278485054SSara Sharon } 115378485054SSara Sharon 115496a6497bSSara Sharon /* move the pool to the default queue and allocator ownerships */ 1155286ca8ebSLuca Coelho queue_size = trans->trans_cfg->mq_rx_supported ? 1156c042f0c7SJohannes Berg trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE; 115796a6497bSSara Sharon allocator_pool_size = trans->num_rx_queues * 115896a6497bSSara Sharon (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 11597b542436SSara Sharon num_alloc = queue_size + allocator_pool_size; 1160c042f0c7SJohannes Berg 11617b542436SSara Sharon for (i = 0; i < num_alloc; i++) { 116296a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 116396a6497bSSara Sharon 116496a6497bSSara Sharon if (i < allocator_pool_size) 116596a6497bSSara Sharon list_add(&rxb->list, &rba->rbd_empty); 116696a6497bSSara Sharon else 116796a6497bSSara Sharon list_add(&rxb->list, &def_rxq->rx_used); 116896a6497bSSara Sharon trans_pcie->global_table[i] = rxb; 1169e25d65f2SSara Sharon rxb->vid = (u16)(i + 1); 1170b1753c62SSara Sharon rxb->invalid = true; 117196a6497bSSara Sharon } 117278485054SSara Sharon 117378485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 11742047fa54SSara Sharon 1175eda50cdeSSara Sharon return 0; 1176eda50cdeSSara Sharon } 1177eda50cdeSSara Sharon 1178eda50cdeSSara Sharon int iwl_pcie_rx_init(struct iwl_trans *trans) 1179eda50cdeSSara Sharon { 1180eda50cdeSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1181eda50cdeSSara Sharon int ret = _iwl_pcie_rx_init(trans); 1182eda50cdeSSara Sharon 1183eda50cdeSSara Sharon if (ret) 1184eda50cdeSSara Sharon return ret; 1185eda50cdeSSara Sharon 1186286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported) 1187bce97731SSara Sharon iwl_pcie_rx_mq_hw_init(trans); 11882047fa54SSara Sharon else 1189eda50cdeSSara Sharon iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 11902047fa54SSara Sharon 1191eda50cdeSSara Sharon iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 119278485054SSara Sharon 1193eda50cdeSSara Sharon spin_lock(&trans_pcie->rxq->lock); 1194eda50cdeSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 1195eda50cdeSSara Sharon spin_unlock(&trans_pcie->rxq->lock); 1196e705c121SKalle Valo 1197e705c121SKalle Valo return 0; 1198e705c121SKalle Valo } 1199e705c121SKalle Valo 1200eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1201eda50cdeSSara Sharon { 1202e506b481SSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 1203e506b481SSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 1204e506b481SSara Sharon 1205eda50cdeSSara Sharon /* 1206eda50cdeSSara Sharon * We don't configure the RFH. 1207eda50cdeSSara Sharon * Restock will be done at alive, after firmware configured the RFH. 1208eda50cdeSSara Sharon */ 1209eda50cdeSSara Sharon return _iwl_pcie_rx_init(trans); 1210eda50cdeSSara Sharon } 1211eda50cdeSSara Sharon 1212e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans) 1213e705c121SKalle Valo { 1214e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1215e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 121678485054SSara Sharon int i; 1217286ca8ebSLuca Coelho size_t rb_stts_size = trans->trans_cfg->device_family >= 12183681021fSJohannes Berg IWL_DEVICE_FAMILY_AX210 ? 12196cc6ba3aSTriebitz sizeof(__le16) : sizeof(struct iwl_rb_status); 1220e705c121SKalle Valo 122178485054SSara Sharon /* 122278485054SSara Sharon * if rxq is NULL, it means that nothing has been allocated, 122378485054SSara Sharon * exit now 122478485054SSara Sharon */ 122578485054SSara Sharon if (!trans_pcie->rxq) { 1226e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1227e705c121SKalle Valo return; 1228e705c121SKalle Valo } 1229e705c121SKalle Valo 1230e705c121SKalle Valo cancel_work_sync(&rba->rx_alloc); 1231e705c121SKalle Valo 123278485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1233e705c121SKalle Valo 12346cc6ba3aSTriebitz if (trans_pcie->base_rb_stts) { 12356cc6ba3aSTriebitz dma_free_coherent(trans->dev, 12366cc6ba3aSTriebitz rb_stts_size * trans->num_rx_queues, 12376cc6ba3aSTriebitz trans_pcie->base_rb_stts, 12386cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma); 12396cc6ba3aSTriebitz trans_pcie->base_rb_stts = NULL; 12406cc6ba3aSTriebitz trans_pcie->base_rb_stts_dma = 0; 12416cc6ba3aSTriebitz } 12426cc6ba3aSTriebitz 124378485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 124478485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 124578485054SSara Sharon 12461b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 1247bce97731SSara Sharon 124825edc8f2SJohannes Berg if (rxq->napi.poll) { 124925edc8f2SJohannes Berg napi_disable(&rxq->napi); 1250bce97731SSara Sharon netif_napi_del(&rxq->napi); 125196a6497bSSara Sharon } 125225edc8f2SJohannes Berg } 1253c042f0c7SJohannes Berg kfree(trans_pcie->rx_pool); 1254c042f0c7SJohannes Berg kfree(trans_pcie->global_table); 125578485054SSara Sharon kfree(trans_pcie->rxq); 1256cfdc20efSJohannes Berg 1257cfdc20efSJohannes Berg if (trans_pcie->alloc_page) 1258cfdc20efSJohannes Berg __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order); 1259e705c121SKalle Valo } 1260e705c121SKalle Valo 1261868a1e86SShaul Triebitz static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq, 1262868a1e86SShaul Triebitz struct iwl_rb_allocator *rba) 1263868a1e86SShaul Triebitz { 1264868a1e86SShaul Triebitz spin_lock(&rba->lock); 1265868a1e86SShaul Triebitz list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1266868a1e86SShaul Triebitz spin_unlock(&rba->lock); 1267868a1e86SShaul Triebitz } 1268868a1e86SShaul Triebitz 1269e705c121SKalle Valo /* 1270e705c121SKalle Valo * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1271e705c121SKalle Valo * 1272e705c121SKalle Valo * Called when a RBD can be reused. The RBD is transferred to the allocator. 1273e705c121SKalle Valo * When there are 2 empty RBDs - a request for allocation is posted 1274e705c121SKalle Valo */ 1275e705c121SKalle Valo static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1276e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 1277e705c121SKalle Valo struct iwl_rxq *rxq, bool emergency) 1278e705c121SKalle Valo { 1279e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1280e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 1281e705c121SKalle Valo 1282e705c121SKalle Valo /* Move the RBD to the used list, will be moved to allocator in batches 1283e705c121SKalle Valo * before claiming or posting a request*/ 1284e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_used); 1285e705c121SKalle Valo 1286e705c121SKalle Valo if (unlikely(emergency)) 1287e705c121SKalle Valo return; 1288e705c121SKalle Valo 1289e705c121SKalle Valo /* Count the allocator owned RBDs */ 1290e705c121SKalle Valo rxq->used_count++; 1291e705c121SKalle Valo 1292e705c121SKalle Valo /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1293e705c121SKalle Valo * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1294e705c121SKalle Valo * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1295e705c121SKalle Valo * after but we still need to post another request. 1296e705c121SKalle Valo */ 1297e705c121SKalle Valo if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1298e705c121SKalle Valo /* Move the 2 RBDs to the allocator ownership. 1299e705c121SKalle Valo Allocator has another 6 from pool for the request completion*/ 1300868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1301e705c121SKalle Valo 1302e705c121SKalle Valo atomic_inc(&rba->req_pending); 1303e705c121SKalle Valo queue_work(rba->alloc_wq, &rba->rx_alloc); 1304e705c121SKalle Valo } 1305e705c121SKalle Valo } 1306e705c121SKalle Valo 1307e705c121SKalle Valo static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 130878485054SSara Sharon struct iwl_rxq *rxq, 1309e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 13107891965dSSara Sharon bool emergency, 13117891965dSSara Sharon int i) 1312e705c121SKalle Valo { 1313e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13144f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id]; 1315e705c121SKalle Valo bool page_stolen = false; 131680084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 1317e705c121SKalle Valo u32 offset = 0; 1318e705c121SKalle Valo 1319e705c121SKalle Valo if (WARN_ON(!rxb)) 1320e705c121SKalle Valo return; 1321e705c121SKalle Valo 1322e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1323e705c121SKalle Valo 1324e705c121SKalle Valo while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1325e705c121SKalle Valo struct iwl_rx_packet *pkt; 1326e705c121SKalle Valo bool reclaim; 1327e4475583SJohannes Berg int len; 1328e705c121SKalle Valo struct iwl_rx_cmd_buffer rxcb = { 1329cfdc20efSJohannes Berg ._offset = rxb->offset + offset, 1330e705c121SKalle Valo ._rx_page_order = trans_pcie->rx_page_order, 1331e705c121SKalle Valo ._page = rxb->page, 1332e705c121SKalle Valo ._page_stolen = false, 1333e705c121SKalle Valo .truesize = max_len, 1334e705c121SKalle Valo }; 1335e705c121SKalle Valo 1336e705c121SKalle Valo pkt = rxb_addr(&rxcb); 1337e705c121SKalle Valo 13383bfdee76SJohannes Berg if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 13393bfdee76SJohannes Berg IWL_DEBUG_RX(trans, 13403bfdee76SJohannes Berg "Q %d: RB end marker at offset %d\n", 13413bfdee76SJohannes Berg rxq->id, offset); 1342e705c121SKalle Valo break; 13433bfdee76SJohannes Berg } 1344e705c121SKalle Valo 1345a395058eSJohannes Berg WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1346a395058eSJohannes Berg FH_RSCSR_RXQ_POS != rxq->id, 1347a395058eSJohannes Berg "frame on invalid queue - is on %d and indicates %d\n", 1348a395058eSJohannes Berg rxq->id, 1349a395058eSJohannes Berg (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1350a395058eSJohannes Berg FH_RSCSR_RXQ_POS); 1351ab2e696bSSara Sharon 1352e705c121SKalle Valo IWL_DEBUG_RX(trans, 13533bfdee76SJohannes Berg "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 13543bfdee76SJohannes Berg rxq->id, offset, 135539bdb17eSSharon Dvir iwl_get_cmd_string(trans, 135639bdb17eSSharon Dvir iwl_cmd_id(pkt->hdr.cmd, 135739bdb17eSSharon Dvir pkt->hdr.group_id, 135839bdb17eSSharon Dvir 0)), 135935177c99SSara Sharon pkt->hdr.group_id, pkt->hdr.cmd, 136035177c99SSara Sharon le16_to_cpu(pkt->hdr.sequence)); 1361e705c121SKalle Valo 1362e705c121SKalle Valo len = iwl_rx_packet_len(pkt); 1363e705c121SKalle Valo len += sizeof(u32); /* account for status word */ 1364df72138dSJohannes Berg 1365df72138dSJohannes Berg offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1366df72138dSJohannes Berg 1367df72138dSJohannes Berg /* check that what the device tells us made sense */ 1368df72138dSJohannes Berg if (offset > max_len) 1369df72138dSJohannes Berg break; 1370df72138dSJohannes Berg 1371e705c121SKalle Valo trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1372e705c121SKalle Valo trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1373e705c121SKalle Valo 1374e705c121SKalle Valo /* Reclaim a command buffer only if this packet is a response 1375e705c121SKalle Valo * to a (driver-originated) command. 1376e705c121SKalle Valo * If the packet (e.g. Rx frame) originated from uCode, 1377e705c121SKalle Valo * there is no command buffer to reclaim. 1378e705c121SKalle Valo * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1379e705c121SKalle Valo * but apparently a few don't get set; catch them here. */ 1380e705c121SKalle Valo reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1381d8a130b0SJohannes Berg if (reclaim && !pkt->hdr.group_id) { 1382e705c121SKalle Valo int i; 1383e705c121SKalle Valo 1384e705c121SKalle Valo for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1385e705c121SKalle Valo if (trans_pcie->no_reclaim_cmds[i] == 1386e705c121SKalle Valo pkt->hdr.cmd) { 1387e705c121SKalle Valo reclaim = false; 1388e705c121SKalle Valo break; 1389e705c121SKalle Valo } 1390e705c121SKalle Valo } 1391e705c121SKalle Valo } 1392e705c121SKalle Valo 13939416560eSGolan Ben Ami if (rxq->id == trans_pcie->def_rx_queue) 1394bce97731SSara Sharon iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1395bce97731SSara Sharon &rxcb); 1396bce97731SSara Sharon else 1397bce97731SSara Sharon iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1398bce97731SSara Sharon &rxcb, rxq->id); 1399e705c121SKalle Valo 1400e705c121SKalle Valo /* 1401e705c121SKalle Valo * After here, we should always check rxcb._page_stolen, 1402e705c121SKalle Valo * if it is true then one of the handlers took the page. 1403e705c121SKalle Valo */ 1404e705c121SKalle Valo 1405e705c121SKalle Valo if (reclaim) { 1406e4475583SJohannes Berg u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1407e4475583SJohannes Berg int index = SEQ_TO_INDEX(sequence); 1408e4475583SJohannes Berg int cmd_index = iwl_txq_get_cmd_index(txq, index); 1409e4475583SJohannes Berg 1410e4475583SJohannes Berg kfree_sensitive(txq->entries[cmd_index].free_buf); 1411e4475583SJohannes Berg txq->entries[cmd_index].free_buf = NULL; 1412e4475583SJohannes Berg 1413e705c121SKalle Valo /* Invoke any callbacks, transfer the buffer to caller, 1414e705c121SKalle Valo * and fire off the (possibly) blocking 1415e705c121SKalle Valo * iwl_trans_send_cmd() 1416e705c121SKalle Valo * as we reclaim the driver command queue */ 1417e705c121SKalle Valo if (!rxcb._page_stolen) 1418e705c121SKalle Valo iwl_pcie_hcmd_complete(trans, &rxcb); 1419e705c121SKalle Valo else 1420e705c121SKalle Valo IWL_WARN(trans, "Claim null rxb?\n"); 1421e705c121SKalle Valo } 1422e705c121SKalle Valo 1423e705c121SKalle Valo page_stolen |= rxcb._page_stolen; 14243681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 14250307c839SGolan Ben Ami break; 1426e705c121SKalle Valo } 1427e705c121SKalle Valo 1428e705c121SKalle Valo /* page was stolen from us -- free our reference */ 1429e705c121SKalle Valo if (page_stolen) { 1430e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1431e705c121SKalle Valo rxb->page = NULL; 1432e705c121SKalle Valo } 1433e705c121SKalle Valo 1434e705c121SKalle Valo /* Reuse the page if possible. For notification packets and 1435e705c121SKalle Valo * SKBs that fail to Rx correctly, add them back into the 1436e705c121SKalle Valo * rx_free list for reuse later. */ 1437e705c121SKalle Valo if (rxb->page != NULL) { 1438e705c121SKalle Valo rxb->page_dma = 1439cfdc20efSJohannes Berg dma_map_page(trans->dev, rxb->page, rxb->offset, 144080084e35SJohannes Berg trans_pcie->rx_buf_bytes, 1441e705c121SKalle Valo DMA_FROM_DEVICE); 1442e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1443e705c121SKalle Valo /* 1444e705c121SKalle Valo * free the page(s) as well to not break 1445e705c121SKalle Valo * the invariant that the items on the used 1446e705c121SKalle Valo * list have no page(s) 1447e705c121SKalle Valo */ 1448e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1449e705c121SKalle Valo rxb->page = NULL; 1450e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1451e705c121SKalle Valo } else { 1452e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 1453e705c121SKalle Valo rxq->free_count++; 1454e705c121SKalle Valo } 1455e705c121SKalle Valo } else 1456e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1457e705c121SKalle Valo } 1458e705c121SKalle Valo 14591b4bbe8bSSara Sharon static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans, 1460b1c860f6SJohannes Berg struct iwl_rxq *rxq, int i, 1461b1c860f6SJohannes Berg bool *join) 14621b4bbe8bSSara Sharon { 14631b4bbe8bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 14641b4bbe8bSSara Sharon struct iwl_rx_mem_buffer *rxb; 14651b4bbe8bSSara Sharon u16 vid; 14661b4bbe8bSSara Sharon 1467f826faaaSJohannes Berg BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32); 1468f826faaaSJohannes Berg 1469286ca8ebSLuca Coelho if (!trans->trans_cfg->mq_rx_supported) { 14701b4bbe8bSSara Sharon rxb = rxq->queue[i]; 14711b4bbe8bSSara Sharon rxq->queue[i] = NULL; 14721b4bbe8bSSara Sharon return rxb; 14731b4bbe8bSSara Sharon } 14741b4bbe8bSSara Sharon 1475b1c860f6SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1476c042f0c7SJohannes Berg vid = le16_to_cpu(rxq->cd[i].rbid); 1477b1c860f6SJohannes Berg *join = rxq->cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED; 1478b1c860f6SJohannes Berg } else { 1479c042f0c7SJohannes Berg vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; /* 12-bit VID */ 1480b1c860f6SJohannes Berg } 14811b4bbe8bSSara Sharon 1482c042f0c7SJohannes Berg if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs)) 14831b4bbe8bSSara Sharon goto out_err; 14841b4bbe8bSSara Sharon 14851b4bbe8bSSara Sharon rxb = trans_pcie->global_table[vid - 1]; 14861b4bbe8bSSara Sharon if (rxb->invalid) 14871b4bbe8bSSara Sharon goto out_err; 14881b4bbe8bSSara Sharon 148985d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid); 149085d78bb1SSara Sharon 14911b4bbe8bSSara Sharon rxb->invalid = true; 14921b4bbe8bSSara Sharon 14931b4bbe8bSSara Sharon return rxb; 14941b4bbe8bSSara Sharon 14951b4bbe8bSSara Sharon out_err: 14961b4bbe8bSSara Sharon WARN(1, "Invalid rxb from HW %u\n", (u32)vid); 14971b4bbe8bSSara Sharon iwl_force_nmi(trans); 14981b4bbe8bSSara Sharon return NULL; 14991b4bbe8bSSara Sharon } 15001b4bbe8bSSara Sharon 1501e705c121SKalle Valo /* 1502e705c121SKalle Valo * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1503e705c121SKalle Valo */ 150425edc8f2SJohannes Berg static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget) 1505e705c121SKalle Valo { 1506e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 150730f24eabSJohannes Berg struct iwl_rxq *rxq; 150825edc8f2SJohannes Berg u32 r, i, count = 0, handled = 0; 1509e705c121SKalle Valo bool emergency = false; 1510e705c121SKalle Valo 151130f24eabSJohannes Berg if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd)) 151225edc8f2SJohannes Berg return budget; 151330f24eabSJohannes Berg 151430f24eabSJohannes Berg rxq = &trans_pcie->rxq[queue]; 151530f24eabSJohannes Berg 1516e705c121SKalle Valo restart: 1517e705c121SKalle Valo spin_lock(&rxq->lock); 1518e705c121SKalle Valo /* uCode's read index (stored in shared DRAM) indicates the last Rx 1519e705c121SKalle Valo * buffer that the driver may process (last buffer filled by ucode). */ 15200307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1521e705c121SKalle Valo i = rxq->read; 1522e705c121SKalle Valo 15235eae443eSSara Sharon /* W/A 9000 device step A0 wrap-around bug */ 15245eae443eSSara Sharon r &= (rxq->queue_size - 1); 15255eae443eSSara Sharon 1526e705c121SKalle Valo /* Rx interrupt, but nothing sent from uCode */ 1527e705c121SKalle Valo if (i == r) 15285eae443eSSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1529e705c121SKalle Valo 153025edc8f2SJohannes Berg while (i != r && ++handled < budget) { 1531868a1e86SShaul Triebitz struct iwl_rb_allocator *rba = &trans_pcie->rba; 1532e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 1533868a1e86SShaul Triebitz /* number of RBDs still waiting for page allocation */ 1534868a1e86SShaul Triebitz u32 rb_pending_alloc = 1535868a1e86SShaul Triebitz atomic_read(&trans_pcie->rba.req_pending) * 1536868a1e86SShaul Triebitz RX_CLAIM_REQ_ALLOC; 1537b1c860f6SJohannes Berg bool join = false; 1538e705c121SKalle Valo 1539868a1e86SShaul Triebitz if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 && 1540868a1e86SShaul Triebitz !emergency)) { 1541868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1542e705c121SKalle Valo emergency = true; 15436dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 15446dcdd165SSara Sharon "RX path is in emergency. Pending allocations %d\n", 15456dcdd165SSara Sharon rb_pending_alloc); 1546868a1e86SShaul Triebitz } 1547e705c121SKalle Valo 154885d78bb1SSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 154985d78bb1SSara Sharon 1550b1c860f6SJohannes Berg rxb = iwl_pcie_get_rxb(trans, rxq, i, &join); 15511b4bbe8bSSara Sharon if (!rxb) 15525eae443eSSara Sharon goto out; 1553e705c121SKalle Valo 1554b1c860f6SJohannes Berg if (unlikely(join || rxq->next_rb_is_fragment)) { 1555b1c860f6SJohannes Berg rxq->next_rb_is_fragment = join; 1556b1c860f6SJohannes Berg /* 1557b1c860f6SJohannes Berg * We can only get a multi-RB in the following cases: 1558b1c860f6SJohannes Berg * - firmware issue, sending a too big notification 1559b1c860f6SJohannes Berg * - sniffer mode with a large A-MSDU 1560b1c860f6SJohannes Berg * - large MTU frames (>2k) 1561b1c860f6SJohannes Berg * since the multi-RB functionality is limited to newer 1562b1c860f6SJohannes Berg * hardware that cannot put multiple entries into a 1563b1c860f6SJohannes Berg * single RB. 1564b1c860f6SJohannes Berg * 1565b1c860f6SJohannes Berg * Right now, the higher layers aren't set up to deal 1566b1c860f6SJohannes Berg * with that, so discard all of these. 1567b1c860f6SJohannes Berg */ 1568b1c860f6SJohannes Berg list_add_tail(&rxb->list, &rxq->rx_free); 1569b1c860f6SJohannes Berg rxq->free_count++; 1570b1c860f6SJohannes Berg } else { 15717891965dSSara Sharon iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i); 1572b1c860f6SJohannes Berg } 1573e705c121SKalle Valo 157496a6497bSSara Sharon i = (i + 1) & (rxq->queue_size - 1); 1575e705c121SKalle Valo 1576d56daea4SSara Sharon /* 1577d56daea4SSara Sharon * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1578d56daea4SSara Sharon * try to claim the pre-allocated buffers from the allocator. 1579d56daea4SSara Sharon * If not ready - will try to reclaim next time. 1580d56daea4SSara Sharon * There is no need to reschedule work - allocator exits only 1581d56daea4SSara Sharon * on success 1582e705c121SKalle Valo */ 1583d56daea4SSara Sharon if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1584d56daea4SSara Sharon iwl_pcie_rx_allocator_get(trans, rxq); 1585e705c121SKalle Valo 1586d56daea4SSara Sharon if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1587d56daea4SSara Sharon /* Add the remaining empty RBDs for allocator use */ 1588868a1e86SShaul Triebitz iwl_pcie_rx_move_to_allocator(rxq, rba); 1589d56daea4SSara Sharon } else if (emergency) { 1590e705c121SKalle Valo count++; 1591e705c121SKalle Valo if (count == 8) { 1592e705c121SKalle Valo count = 0; 15936dcdd165SSara Sharon if (rb_pending_alloc < rxq->queue_size / 3) { 15946dcdd165SSara Sharon IWL_DEBUG_TPT(trans, 15956dcdd165SSara Sharon "RX path exited emergency. Pending allocations %d\n", 15966dcdd165SSara Sharon rb_pending_alloc); 1597e705c121SKalle Valo emergency = false; 15986dcdd165SSara Sharon } 1599e0e168dcSGregory Greenman 1600e705c121SKalle Valo rxq->read = i; 1601e705c121SKalle Valo spin_unlock(&rxq->lock); 1602e0e168dcSGregory Greenman iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 160378485054SSara Sharon iwl_pcie_rxq_restock(trans, rxq); 1604e705c121SKalle Valo goto restart; 1605e705c121SKalle Valo } 1606e705c121SKalle Valo } 1607e0e168dcSGregory Greenman } 16085eae443eSSara Sharon out: 1609e705c121SKalle Valo /* Backtrack one entry */ 1610e705c121SKalle Valo rxq->read = i; 16110307c839SGolan Ben Ami /* update cr tail with the rxq read pointer */ 16123681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 16130307c839SGolan Ben Ami *rxq->cr_tail = cpu_to_le16(r); 1614e705c121SKalle Valo spin_unlock(&rxq->lock); 1615e705c121SKalle Valo 1616e705c121SKalle Valo /* 1617e705c121SKalle Valo * handle a case where in emergency there are some unallocated RBDs. 1618e705c121SKalle Valo * those RBDs are in the used list, but are not tracked by the queue's 1619e705c121SKalle Valo * used_count which counts allocator owned RBDs. 1620e705c121SKalle Valo * unallocated emergency RBDs must be allocated on exit, otherwise 1621e705c121SKalle Valo * when called again the function may not be in emergency mode and 1622e705c121SKalle Valo * they will be handed to the allocator with no tracking in the RBD 1623e705c121SKalle Valo * allocator counters, which will lead to them never being claimed back 1624e705c121SKalle Valo * by the queue. 1625e705c121SKalle Valo * by allocating them here, they are now in the queue free list, and 1626e705c121SKalle Valo * will be restocked by the next call of iwl_pcie_rxq_restock. 1627e705c121SKalle Valo */ 1628e705c121SKalle Valo if (unlikely(emergency && count)) 162978485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1630e705c121SKalle Valo 1631e0e168dcSGregory Greenman iwl_pcie_rxq_restock(trans, rxq); 163225edc8f2SJohannes Berg 163325edc8f2SJohannes Berg return handled; 1634e705c121SKalle Valo } 1635e705c121SKalle Valo 16362e5d4a8fSHaim Dreyfuss static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 16372e5d4a8fSHaim Dreyfuss { 16382e5d4a8fSHaim Dreyfuss u8 queue = entry->entry; 16392e5d4a8fSHaim Dreyfuss struct msix_entry *entries = entry - queue; 16402e5d4a8fSHaim Dreyfuss 16412e5d4a8fSHaim Dreyfuss return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 16422e5d4a8fSHaim Dreyfuss } 16432e5d4a8fSHaim Dreyfuss 16442e5d4a8fSHaim Dreyfuss /* 16452e5d4a8fSHaim Dreyfuss * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 16462e5d4a8fSHaim Dreyfuss * This interrupt handler should be used with RSS queue only. 16472e5d4a8fSHaim Dreyfuss */ 16482e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 16492e5d4a8fSHaim Dreyfuss { 16502e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 16512e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 16522e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 165325edc8f2SJohannes Berg struct iwl_rxq *rxq = &trans_pcie->rxq[entry->entry]; 16542e5d4a8fSHaim Dreyfuss 1655c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1656c42ff65dSJohannes Berg 16575eae443eSSara Sharon if (WARN_ON(entry->entry >= trans->num_rx_queues)) 16585eae443eSSara Sharon return IRQ_NONE; 16595eae443eSSara Sharon 16602e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 16612e5d4a8fSHaim Dreyfuss 16622e5d4a8fSHaim Dreyfuss local_bh_disable(); 166325edc8f2SJohannes Berg if (napi_schedule_prep(&rxq->napi)) 166425edc8f2SJohannes Berg __napi_schedule(&rxq->napi); 166525edc8f2SJohannes Berg else 166625edc8f2SJohannes Berg iwl_pcie_clear_irq(trans, entry->entry); 16672e5d4a8fSHaim Dreyfuss local_bh_enable(); 16682e5d4a8fSHaim Dreyfuss 16692e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 16702e5d4a8fSHaim Dreyfuss 16712e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 16722e5d4a8fSHaim Dreyfuss } 16732e5d4a8fSHaim Dreyfuss 1674e705c121SKalle Valo /* 1675e705c121SKalle Valo * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1676e705c121SKalle Valo */ 1677e705c121SKalle Valo static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1678e705c121SKalle Valo { 1679e705c121SKalle Valo int i; 1680e705c121SKalle Valo 1681e705c121SKalle Valo /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1682e705c121SKalle Valo if (trans->cfg->internal_wimax_coex && 1683e705c121SKalle Valo !trans->cfg->apmg_not_supported && 1684e705c121SKalle Valo (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1685e705c121SKalle Valo APMS_CLK_VAL_MRB_FUNC_MODE) || 1686e705c121SKalle Valo (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1687e705c121SKalle Valo APMG_PS_CTRL_VAL_RESET_REQ))) { 1688e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1689e705c121SKalle Valo iwl_op_mode_wimax_active(trans->op_mode); 1690*13f028b4SMordechay Goodstein wake_up(&trans->wait_command_queue); 1691e705c121SKalle Valo return; 1692e705c121SKalle Valo } 1693e705c121SKalle Valo 1694286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 16954f4822b7SMordechay Goodstein if (!trans->txqs.txq[i]) 169613a3a390SSara Sharon continue; 16974f4822b7SMordechay Goodstein del_timer(&trans->txqs.txq[i]->stuck_timer); 169813a3a390SSara Sharon } 1699e705c121SKalle Valo 17007d75f32eSEmmanuel Grumbach /* The STATUS_FW_ERROR bit is set in this function. This must happen 17017d75f32eSEmmanuel Grumbach * before we wake up the command caller, to ensure a proper cleanup. */ 17027d75f32eSEmmanuel Grumbach iwl_trans_fw_error(trans); 17037d75f32eSEmmanuel Grumbach 1704e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1705*13f028b4SMordechay Goodstein wake_up(&trans->wait_command_queue); 1706e705c121SKalle Valo } 1707e705c121SKalle Valo 1708e705c121SKalle Valo static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1709e705c121SKalle Valo { 1710e705c121SKalle Valo u32 inta; 1711e705c121SKalle Valo 1712e705c121SKalle Valo lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1713e705c121SKalle Valo 1714e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1715e705c121SKalle Valo 1716e705c121SKalle Valo /* Discover which interrupts are active/pending */ 1717e705c121SKalle Valo inta = iwl_read32(trans, CSR_INT); 1718e705c121SKalle Valo 1719e705c121SKalle Valo /* the thread will service interrupts and re-enable them */ 1720e705c121SKalle Valo return inta; 1721e705c121SKalle Valo } 1722e705c121SKalle Valo 1723e705c121SKalle Valo /* a device (PCI-E) page is 4096 bytes long */ 1724e705c121SKalle Valo #define ICT_SHIFT 12 1725e705c121SKalle Valo #define ICT_SIZE (1 << ICT_SHIFT) 1726e705c121SKalle Valo #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1727e705c121SKalle Valo 1728e705c121SKalle Valo /* interrupt handler using ict table, with this interrupt driver will 1729e705c121SKalle Valo * stop using INTA register to get device's interrupt, reading this register 1730e705c121SKalle Valo * is expensive, device will write interrupts in ICT dram table, increment 1731e705c121SKalle Valo * index then will fire interrupt to driver, driver will OR all ICT table 1732e705c121SKalle Valo * entries from current index up to table entry with 0 value. the result is 1733e705c121SKalle Valo * the interrupt we need to service, driver will set the entries back to 0 and 1734e705c121SKalle Valo * set index. 1735e705c121SKalle Valo */ 1736e705c121SKalle Valo static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1737e705c121SKalle Valo { 1738e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1739e705c121SKalle Valo u32 inta; 1740e705c121SKalle Valo u32 val = 0; 1741e705c121SKalle Valo u32 read; 1742e705c121SKalle Valo 1743e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1744e705c121SKalle Valo 1745e705c121SKalle Valo /* Ignore interrupt if there's nothing in NIC to service. 1746e705c121SKalle Valo * This may be due to IRQ shared with another device, 1747e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. */ 1748e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1749e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1750e705c121SKalle Valo if (!read) 1751e705c121SKalle Valo return 0; 1752e705c121SKalle Valo 1753e705c121SKalle Valo /* 1754e705c121SKalle Valo * Collect all entries up to the first 0, starting from ict_index; 1755e705c121SKalle Valo * note we already read at ict_index. 1756e705c121SKalle Valo */ 1757e705c121SKalle Valo do { 1758e705c121SKalle Valo val |= read; 1759e705c121SKalle Valo IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1760e705c121SKalle Valo trans_pcie->ict_index, read); 1761e705c121SKalle Valo trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1762e705c121SKalle Valo trans_pcie->ict_index = 1763e705c121SKalle Valo ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1764e705c121SKalle Valo 1765e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1766e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1767e705c121SKalle Valo read); 1768e705c121SKalle Valo } while (read); 1769e705c121SKalle Valo 1770e705c121SKalle Valo /* We should not get this value, just ignore it. */ 1771e705c121SKalle Valo if (val == 0xffffffff) 1772e705c121SKalle Valo val = 0; 1773e705c121SKalle Valo 1774e705c121SKalle Valo /* 1775e705c121SKalle Valo * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1776e705c121SKalle Valo * (bit 15 before shifting it to 31) to clear when using interrupt 1777e705c121SKalle Valo * coalescing. fortunately, bits 18 and 19 stay set when this happens 1778e705c121SKalle Valo * so we use them to decide on the real state of the Rx bit. 1779e705c121SKalle Valo * In order words, bit 15 is set if bit 18 or bit 19 are set. 1780e705c121SKalle Valo */ 1781e705c121SKalle Valo if (val & 0xC0000) 1782e705c121SKalle Valo val |= 0x8000; 1783e705c121SKalle Valo 1784e705c121SKalle Valo inta = (0xff & val) | ((0xff00 & val) << 16); 1785e705c121SKalle Valo return inta; 1786e705c121SKalle Valo } 1787e705c121SKalle Valo 1788fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 17893a6e168bSJohannes Berg { 17903a6e168bSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17913a6e168bSJohannes Berg struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1792326477e4SJohannes Berg bool hw_rfkill, prev, report; 17933a6e168bSJohannes Berg 17943a6e168bSJohannes Berg mutex_lock(&trans_pcie->mutex); 1795326477e4SJohannes Berg prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 17963a6e168bSJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1797326477e4SJohannes Berg if (hw_rfkill) { 1798326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1799326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1800326477e4SJohannes Berg } 1801326477e4SJohannes Berg if (trans_pcie->opmode_down) 1802326477e4SJohannes Berg report = hw_rfkill; 1803326477e4SJohannes Berg else 1804326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 18053a6e168bSJohannes Berg 18063a6e168bSJohannes Berg IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 18073a6e168bSJohannes Berg hw_rfkill ? "disable radio" : "enable radio"); 18083a6e168bSJohannes Berg 18093a6e168bSJohannes Berg isr_stats->rfkill++; 18103a6e168bSJohannes Berg 1811326477e4SJohannes Berg if (prev != report) 1812326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 18133a6e168bSJohannes Berg mutex_unlock(&trans_pcie->mutex); 18143a6e168bSJohannes Berg 18153a6e168bSJohannes Berg if (hw_rfkill) { 18163a6e168bSJohannes Berg if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 18173a6e168bSJohannes Berg &trans->status)) 18183a6e168bSJohannes Berg IWL_DEBUG_RF_KILL(trans, 18193a6e168bSJohannes Berg "Rfkill while SYNC HCMD in flight\n"); 1820*13f028b4SMordechay Goodstein wake_up(&trans->wait_command_queue); 18213a6e168bSJohannes Berg } else { 1822326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1823326477e4SJohannes Berg if (trans_pcie->opmode_down) 1824326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 18253a6e168bSJohannes Berg } 18263a6e168bSJohannes Berg } 18273a6e168bSJohannes Berg 1828e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1829e705c121SKalle Valo { 1830e705c121SKalle Valo struct iwl_trans *trans = dev_id; 1831e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1832e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1833e705c121SKalle Valo u32 inta = 0; 1834e705c121SKalle Valo u32 handled = 0; 183525edc8f2SJohannes Berg bool polling = false; 1836e705c121SKalle Valo 1837e705c121SKalle Valo lock_map_acquire(&trans->sync_cmd_lockdep_map); 1838e705c121SKalle Valo 183925edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 1840e705c121SKalle Valo 1841e705c121SKalle Valo /* dram interrupt table not set yet, 1842e705c121SKalle Valo * use legacy interrupt. 1843e705c121SKalle Valo */ 1844e705c121SKalle Valo if (likely(trans_pcie->use_ict)) 1845e705c121SKalle Valo inta = iwl_pcie_int_cause_ict(trans); 1846e705c121SKalle Valo else 1847e705c121SKalle Valo inta = iwl_pcie_int_cause_non_ict(trans); 1848e705c121SKalle Valo 1849e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1850e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1851e705c121SKalle Valo "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1852e705c121SKalle Valo inta, trans_pcie->inta_mask, 1853e705c121SKalle Valo iwl_read32(trans, CSR_INT_MASK), 1854e705c121SKalle Valo iwl_read32(trans, CSR_FH_INT_STATUS)); 1855e705c121SKalle Valo if (inta & (~trans_pcie->inta_mask)) 1856e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1857e705c121SKalle Valo "We got a masked interrupt (0x%08x)\n", 1858e705c121SKalle Valo inta & (~trans_pcie->inta_mask)); 1859e705c121SKalle Valo } 1860e705c121SKalle Valo 1861e705c121SKalle Valo inta &= trans_pcie->inta_mask; 1862e705c121SKalle Valo 1863e705c121SKalle Valo /* 1864e705c121SKalle Valo * Ignore interrupt if there's nothing in NIC to service. 1865e705c121SKalle Valo * This may be due to IRQ shared with another device, 1866e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. 1867e705c121SKalle Valo */ 1868e705c121SKalle Valo if (unlikely(!inta)) { 1869e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1870e705c121SKalle Valo /* 1871e705c121SKalle Valo * Re-enable interrupts here since we don't 1872e705c121SKalle Valo * have anything to service 1873e705c121SKalle Valo */ 1874e705c121SKalle Valo if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1875f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 187625edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 1877e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1878e705c121SKalle Valo return IRQ_NONE; 1879e705c121SKalle Valo } 1880e705c121SKalle Valo 1881e705c121SKalle Valo if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1882e705c121SKalle Valo /* 1883e705c121SKalle Valo * Hardware disappeared. It might have 1884e705c121SKalle Valo * already raised an interrupt. 1885e705c121SKalle Valo */ 1886e705c121SKalle Valo IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 188725edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 1888e705c121SKalle Valo goto out; 1889e705c121SKalle Valo } 1890e705c121SKalle Valo 1891e705c121SKalle Valo /* Ack/clear/reset pending uCode interrupts. 1892e705c121SKalle Valo * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1893e705c121SKalle Valo */ 1894e705c121SKalle Valo /* There is a hardware bug in the interrupt mask function that some 1895e705c121SKalle Valo * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1896e705c121SKalle Valo * they are disabled in the CSR_INT_MASK register. Furthermore the 1897e705c121SKalle Valo * ICT interrupt handling mechanism has another bug that might cause 1898e705c121SKalle Valo * these unmasked interrupts fail to be detected. We workaround the 1899e705c121SKalle Valo * hardware bugs here by ACKing all the possible interrupts so that 1900e705c121SKalle Valo * interrupt coalescing can still be achieved. 1901e705c121SKalle Valo */ 1902e705c121SKalle Valo iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1903e705c121SKalle Valo 1904e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) 1905e705c121SKalle Valo IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1906e705c121SKalle Valo inta, iwl_read32(trans, CSR_INT_MASK)); 1907e705c121SKalle Valo 190825edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 1909e705c121SKalle Valo 1910e705c121SKalle Valo /* Now service all interrupt bits discovered above. */ 1911e705c121SKalle Valo if (inta & CSR_INT_BIT_HW_ERR) { 1912e705c121SKalle Valo IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1913e705c121SKalle Valo 1914e705c121SKalle Valo /* Tell the device to stop sending interrupts */ 1915e705c121SKalle Valo iwl_disable_interrupts(trans); 1916e705c121SKalle Valo 1917e705c121SKalle Valo isr_stats->hw++; 1918e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1919e705c121SKalle Valo 1920e705c121SKalle Valo handled |= CSR_INT_BIT_HW_ERR; 1921e705c121SKalle Valo 1922e705c121SKalle Valo goto out; 1923e705c121SKalle Valo } 1924e705c121SKalle Valo 1925e705c121SKalle Valo /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1926e705c121SKalle Valo if (inta & CSR_INT_BIT_SCD) { 1927e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1928e705c121SKalle Valo "Scheduler finished to transmit the frame/frames.\n"); 1929e705c121SKalle Valo isr_stats->sch++; 1930e705c121SKalle Valo } 1931e705c121SKalle Valo 1932e705c121SKalle Valo /* Alive notification via Rx interrupt will do the real work */ 1933e705c121SKalle Valo if (inta & CSR_INT_BIT_ALIVE) { 1934e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1935e705c121SKalle Valo isr_stats->alive++; 1936286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) { 1937eda50cdeSSara Sharon /* 1938eda50cdeSSara Sharon * We can restock, since firmware configured 1939eda50cdeSSara Sharon * the RFH 1940eda50cdeSSara Sharon */ 1941eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1942eda50cdeSSara Sharon } 1943ed3e4c6dSEmmanuel Grumbach 1944ed3e4c6dSEmmanuel Grumbach handled |= CSR_INT_BIT_ALIVE; 1945e705c121SKalle Valo } 1946e705c121SKalle Valo 1947e705c121SKalle Valo /* Safely ignore these bits for debug checks below */ 1948e705c121SKalle Valo inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1949e705c121SKalle Valo 1950e705c121SKalle Valo /* HW RF KILL switch toggled */ 1951e705c121SKalle Valo if (inta & CSR_INT_BIT_RF_KILL) { 19523a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 1953e705c121SKalle Valo handled |= CSR_INT_BIT_RF_KILL; 1954e705c121SKalle Valo } 1955e705c121SKalle Valo 1956e705c121SKalle Valo /* Chip got too hot and stopped itself */ 1957e705c121SKalle Valo if (inta & CSR_INT_BIT_CT_KILL) { 1958e705c121SKalle Valo IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1959e705c121SKalle Valo isr_stats->ctkill++; 1960e705c121SKalle Valo handled |= CSR_INT_BIT_CT_KILL; 1961e705c121SKalle Valo } 1962e705c121SKalle Valo 1963e705c121SKalle Valo /* Error detected by uCode */ 1964e705c121SKalle Valo if (inta & CSR_INT_BIT_SW_ERR) { 1965e705c121SKalle Valo IWL_ERR(trans, "Microcode SW error detected. " 1966e705c121SKalle Valo " Restarting 0x%X.\n", inta); 1967e705c121SKalle Valo isr_stats->sw++; 1968e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1969e705c121SKalle Valo handled |= CSR_INT_BIT_SW_ERR; 1970e705c121SKalle Valo } 1971e705c121SKalle Valo 1972e705c121SKalle Valo /* uCode wakes up after power-down sleep */ 1973e705c121SKalle Valo if (inta & CSR_INT_BIT_WAKEUP) { 1974e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1975e705c121SKalle Valo iwl_pcie_rxq_check_wrptr(trans); 1976e705c121SKalle Valo iwl_pcie_txq_check_wrptrs(trans); 1977e705c121SKalle Valo 1978e705c121SKalle Valo isr_stats->wakeup++; 1979e705c121SKalle Valo 1980e705c121SKalle Valo handled |= CSR_INT_BIT_WAKEUP; 1981e705c121SKalle Valo } 1982e705c121SKalle Valo 1983e705c121SKalle Valo /* All uCode command responses, including Tx command responses, 1984e705c121SKalle Valo * Rx "responses" (frame-received notification), and other 1985e705c121SKalle Valo * notifications from uCode come through here*/ 1986e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1987e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC)) { 1988e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1989e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1990e705c121SKalle Valo handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1991e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 1992e705c121SKalle Valo CSR_FH_INT_RX_MASK); 1993e705c121SKalle Valo } 1994e705c121SKalle Valo if (inta & CSR_INT_BIT_RX_PERIODIC) { 1995e705c121SKalle Valo handled |= CSR_INT_BIT_RX_PERIODIC; 1996e705c121SKalle Valo iwl_write32(trans, 1997e705c121SKalle Valo CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1998e705c121SKalle Valo } 1999e705c121SKalle Valo /* Sending RX interrupt require many steps to be done in the 2000e705c121SKalle Valo * the device: 2001e705c121SKalle Valo * 1- write interrupt to current index in ICT table. 2002e705c121SKalle Valo * 2- dma RX frame. 2003e705c121SKalle Valo * 3- update RX shared data to indicate last write index. 2004e705c121SKalle Valo * 4- send interrupt. 2005e705c121SKalle Valo * This could lead to RX race, driver could receive RX interrupt 2006e705c121SKalle Valo * but the shared data changes does not reflect this; 2007e705c121SKalle Valo * periodic interrupt will detect any dangling Rx activity. 2008e705c121SKalle Valo */ 2009e705c121SKalle Valo 2010e705c121SKalle Valo /* Disable periodic interrupt; we use it as just a one-shot. */ 2011e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 2012e705c121SKalle Valo CSR_INT_PERIODIC_DIS); 2013e705c121SKalle Valo 2014e705c121SKalle Valo /* 2015e705c121SKalle Valo * Enable periodic interrupt in 8 msec only if we received 2016e705c121SKalle Valo * real RX interrupt (instead of just periodic int), to catch 2017e705c121SKalle Valo * any dangling Rx interrupt. If it was just the periodic 2018e705c121SKalle Valo * interrupt, there was no dangling Rx activity, and no need 2019e705c121SKalle Valo * to extend the periodic interrupt; one-shot is enough. 2020e705c121SKalle Valo */ 2021e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 2022e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 2023e705c121SKalle Valo CSR_INT_PERIODIC_ENA); 2024e705c121SKalle Valo 2025e705c121SKalle Valo isr_stats->rx++; 2026e705c121SKalle Valo 2027e705c121SKalle Valo local_bh_disable(); 202825edc8f2SJohannes Berg if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 202925edc8f2SJohannes Berg polling = true; 203025edc8f2SJohannes Berg __napi_schedule(&trans_pcie->rxq[0].napi); 203125edc8f2SJohannes Berg } 2032e705c121SKalle Valo local_bh_enable(); 2033e705c121SKalle Valo } 2034e705c121SKalle Valo 2035e705c121SKalle Valo /* This "Tx" DMA channel is used only for loading uCode */ 2036e705c121SKalle Valo if (inta & CSR_INT_BIT_FH_TX) { 2037e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 2038e705c121SKalle Valo IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 2039e705c121SKalle Valo isr_stats->tx++; 2040e705c121SKalle Valo handled |= CSR_INT_BIT_FH_TX; 2041e705c121SKalle Valo /* Wake up uCode load routine, now that load is complete */ 2042e705c121SKalle Valo trans_pcie->ucode_write_complete = true; 2043e705c121SKalle Valo wake_up(&trans_pcie->ucode_write_waitq); 2044e705c121SKalle Valo } 2045e705c121SKalle Valo 2046e705c121SKalle Valo if (inta & ~handled) { 2047e705c121SKalle Valo IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 2048e705c121SKalle Valo isr_stats->unhandled++; 2049e705c121SKalle Valo } 2050e705c121SKalle Valo 2051e705c121SKalle Valo if (inta & ~(trans_pcie->inta_mask)) { 2052e705c121SKalle Valo IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 2053e705c121SKalle Valo inta & ~trans_pcie->inta_mask); 2054e705c121SKalle Valo } 2055e705c121SKalle Valo 205625edc8f2SJohannes Berg if (!polling) { 205725edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 2058a6bd005fSEmmanuel Grumbach /* only Re-enable all interrupt if disabled by irq */ 2059f16c3ebfSEmmanuel Grumbach if (test_bit(STATUS_INT_ENABLED, &trans->status)) 2060f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 2061f16c3ebfSEmmanuel Grumbach /* we are loading the firmware, enable FH_TX interrupt only */ 2062f16c3ebfSEmmanuel Grumbach else if (handled & CSR_INT_BIT_FH_TX) 2063f16c3ebfSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 2064e705c121SKalle Valo /* Re-enable RF_KILL if it occurred */ 2065e705c121SKalle Valo else if (handled & CSR_INT_BIT_RF_KILL) 2066e705c121SKalle Valo iwl_enable_rfkill_int(trans); 2067ed3e4c6dSEmmanuel Grumbach /* Re-enable the ALIVE / Rx interrupt if it occurred */ 2068ed3e4c6dSEmmanuel Grumbach else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX)) 2069ed3e4c6dSEmmanuel Grumbach iwl_enable_fw_load_int_ctx_info(trans); 207025edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 207125edc8f2SJohannes Berg } 2072e705c121SKalle Valo 2073e705c121SKalle Valo out: 2074e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 2075e705c121SKalle Valo return IRQ_HANDLED; 2076e705c121SKalle Valo } 2077e705c121SKalle Valo 2078e705c121SKalle Valo /****************************************************************************** 2079e705c121SKalle Valo * 2080e705c121SKalle Valo * ICT functions 2081e705c121SKalle Valo * 2082e705c121SKalle Valo ******************************************************************************/ 2083e705c121SKalle Valo 2084e705c121SKalle Valo /* Free dram table */ 2085e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans) 2086e705c121SKalle Valo { 2087e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2088e705c121SKalle Valo 2089e705c121SKalle Valo if (trans_pcie->ict_tbl) { 2090e705c121SKalle Valo dma_free_coherent(trans->dev, ICT_SIZE, 2091e705c121SKalle Valo trans_pcie->ict_tbl, 2092e705c121SKalle Valo trans_pcie->ict_tbl_dma); 2093e705c121SKalle Valo trans_pcie->ict_tbl = NULL; 2094e705c121SKalle Valo trans_pcie->ict_tbl_dma = 0; 2095e705c121SKalle Valo } 2096e705c121SKalle Valo } 2097e705c121SKalle Valo 2098e705c121SKalle Valo /* 2099e705c121SKalle Valo * allocate dram shared table, it is an aligned memory 2100e705c121SKalle Valo * block of ICT_SIZE. 2101e705c121SKalle Valo * also reset all data related to ICT table interrupt. 2102e705c121SKalle Valo */ 2103e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans) 2104e705c121SKalle Valo { 2105e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2106e705c121SKalle Valo 2107e705c121SKalle Valo trans_pcie->ict_tbl = 2108750afb08SLuis Chamberlain dma_alloc_coherent(trans->dev, ICT_SIZE, 2109750afb08SLuis Chamberlain &trans_pcie->ict_tbl_dma, GFP_KERNEL); 2110e705c121SKalle Valo if (!trans_pcie->ict_tbl) 2111e705c121SKalle Valo return -ENOMEM; 2112e705c121SKalle Valo 2113e705c121SKalle Valo /* just an API sanity check ... it is guaranteed to be aligned */ 2114e705c121SKalle Valo if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 2115e705c121SKalle Valo iwl_pcie_free_ict(trans); 2116e705c121SKalle Valo return -EINVAL; 2117e705c121SKalle Valo } 2118e705c121SKalle Valo 2119e705c121SKalle Valo return 0; 2120e705c121SKalle Valo } 2121e705c121SKalle Valo 2122e705c121SKalle Valo /* Device is going up inform it about using ICT interrupt table, 2123e705c121SKalle Valo * also we need to tell the driver to start using ICT interrupt. 2124e705c121SKalle Valo */ 2125e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans) 2126e705c121SKalle Valo { 2127e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2128e705c121SKalle Valo u32 val; 2129e705c121SKalle Valo 2130e705c121SKalle Valo if (!trans_pcie->ict_tbl) 2131e705c121SKalle Valo return; 2132e705c121SKalle Valo 213325edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 2134f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 2135e705c121SKalle Valo 2136e705c121SKalle Valo memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 2137e705c121SKalle Valo 2138e705c121SKalle Valo val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 2139e705c121SKalle Valo 2140e705c121SKalle Valo val |= CSR_DRAM_INT_TBL_ENABLE | 2141e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRAP_CHECK | 2142e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRITE_POINTER; 2143e705c121SKalle Valo 2144e705c121SKalle Valo IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 2145e705c121SKalle Valo 2146e705c121SKalle Valo iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 2147e705c121SKalle Valo trans_pcie->use_ict = true; 2148e705c121SKalle Valo trans_pcie->ict_index = 0; 2149e705c121SKalle Valo iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 2150f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 215125edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 2152e705c121SKalle Valo } 2153e705c121SKalle Valo 2154e705c121SKalle Valo /* Device is going down disable ict interrupt usage */ 2155e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans) 2156e705c121SKalle Valo { 2157e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2158e705c121SKalle Valo 215925edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 2160e705c121SKalle Valo trans_pcie->use_ict = false; 216125edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 2162e705c121SKalle Valo } 2163e705c121SKalle Valo 2164e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data) 2165e705c121SKalle Valo { 2166e705c121SKalle Valo struct iwl_trans *trans = data; 2167e705c121SKalle Valo 2168e705c121SKalle Valo if (!trans) 2169e705c121SKalle Valo return IRQ_NONE; 2170e705c121SKalle Valo 2171e705c121SKalle Valo /* Disable (but don't clear!) interrupts here to avoid 2172e705c121SKalle Valo * back-to-back ISRs and sporadic interrupts from our NIC. 2173e705c121SKalle Valo * If we have something to service, the tasklet will re-enable ints. 2174e705c121SKalle Valo * If we *don't* have something, we'll re-enable before leaving here. 2175e705c121SKalle Valo */ 2176e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2177e705c121SKalle Valo 2178e705c121SKalle Valo return IRQ_WAKE_THREAD; 2179e705c121SKalle Valo } 21802e5d4a8fSHaim Dreyfuss 21812e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 21822e5d4a8fSHaim Dreyfuss { 21832e5d4a8fSHaim Dreyfuss return IRQ_WAKE_THREAD; 21842e5d4a8fSHaim Dreyfuss } 21852e5d4a8fSHaim Dreyfuss 21862e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 21872e5d4a8fSHaim Dreyfuss { 21882e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 21892e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 21902e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 219146167a8fSColin Ian King struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 21922e5d4a8fSHaim Dreyfuss u32 inta_fh, inta_hw; 219325edc8f2SJohannes Berg bool polling = false; 21942e5d4a8fSHaim Dreyfuss 21952e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 21962e5d4a8fSHaim Dreyfuss 219725edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 21987ef3dd26SHaim Dreyfuss inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 21997ef3dd26SHaim Dreyfuss inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 22002e5d4a8fSHaim Dreyfuss /* 22012e5d4a8fSHaim Dreyfuss * Clear causes registers to avoid being handling the same cause. 22022e5d4a8fSHaim Dreyfuss */ 22037ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 22047ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 220525edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 22062e5d4a8fSHaim Dreyfuss 2207c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2208c42ff65dSJohannes Berg 22092e5d4a8fSHaim Dreyfuss if (unlikely(!(inta_fh | inta_hw))) { 22102e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 22112e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 22122e5d4a8fSHaim Dreyfuss return IRQ_NONE; 22132e5d4a8fSHaim Dreyfuss } 22142e5d4a8fSHaim Dreyfuss 22153b57a10cSEmmanuel Grumbach if (iwl_have_debug_level(IWL_DL_ISR)) { 22163b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 22173b57a10cSEmmanuel Grumbach "ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 22183b57a10cSEmmanuel Grumbach inta_fh, trans_pcie->fh_mask, 22192e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 22203b57a10cSEmmanuel Grumbach if (inta_fh & ~trans_pcie->fh_mask) 22213b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 22223b57a10cSEmmanuel Grumbach "We got a masked interrupt (0x%08x)\n", 22233b57a10cSEmmanuel Grumbach inta_fh & ~trans_pcie->fh_mask); 22243b57a10cSEmmanuel Grumbach } 22253b57a10cSEmmanuel Grumbach 22263b57a10cSEmmanuel Grumbach inta_fh &= trans_pcie->fh_mask; 22272e5d4a8fSHaim Dreyfuss 2228496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2229496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2230496d83caSHaim Dreyfuss local_bh_disable(); 223125edc8f2SJohannes Berg if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) { 223225edc8f2SJohannes Berg polling = true; 223325edc8f2SJohannes Berg __napi_schedule(&trans_pcie->rxq[0].napi); 223425edc8f2SJohannes Berg } 2235496d83caSHaim Dreyfuss local_bh_enable(); 2236496d83caSHaim Dreyfuss } 2237496d83caSHaim Dreyfuss 2238496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2239496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2240496d83caSHaim Dreyfuss local_bh_disable(); 224125edc8f2SJohannes Berg if (napi_schedule_prep(&trans_pcie->rxq[1].napi)) { 224225edc8f2SJohannes Berg polling = true; 224325edc8f2SJohannes Berg __napi_schedule(&trans_pcie->rxq[1].napi); 224425edc8f2SJohannes Berg } 2245496d83caSHaim Dreyfuss local_bh_enable(); 2246496d83caSHaim Dreyfuss } 2247496d83caSHaim Dreyfuss 22482e5d4a8fSHaim Dreyfuss /* This "Tx" DMA channel is used only for loading uCode */ 22492e5d4a8fSHaim Dreyfuss if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 22502e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 22512e5d4a8fSHaim Dreyfuss isr_stats->tx++; 22522e5d4a8fSHaim Dreyfuss /* 22532e5d4a8fSHaim Dreyfuss * Wake up uCode load routine, 22542e5d4a8fSHaim Dreyfuss * now that load is complete 22552e5d4a8fSHaim Dreyfuss */ 22562e5d4a8fSHaim Dreyfuss trans_pcie->ucode_write_complete = true; 22572e5d4a8fSHaim Dreyfuss wake_up(&trans_pcie->ucode_write_waitq); 22582e5d4a8fSHaim Dreyfuss } 22592e5d4a8fSHaim Dreyfuss 22602e5d4a8fSHaim Dreyfuss /* Error detected by uCode */ 22612e5d4a8fSHaim Dreyfuss if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 22623681021fSJohannes Berg (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) { 22632e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 22642e5d4a8fSHaim Dreyfuss "Microcode SW error detected. Restarting 0x%X.\n", 22652e5d4a8fSHaim Dreyfuss inta_fh); 22662e5d4a8fSHaim Dreyfuss isr_stats->sw++; 22672e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 22682e5d4a8fSHaim Dreyfuss } 22692e5d4a8fSHaim Dreyfuss 22702e5d4a8fSHaim Dreyfuss /* After checking FH register check HW register */ 22713b57a10cSEmmanuel Grumbach if (iwl_have_debug_level(IWL_DL_ISR)) { 22722e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, 22733b57a10cSEmmanuel Grumbach "ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n", 22743b57a10cSEmmanuel Grumbach inta_hw, trans_pcie->hw_mask, 22752e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 22763b57a10cSEmmanuel Grumbach if (inta_hw & ~trans_pcie->hw_mask) 22773b57a10cSEmmanuel Grumbach IWL_DEBUG_ISR(trans, 22783b57a10cSEmmanuel Grumbach "We got a masked interrupt 0x%08x\n", 22793b57a10cSEmmanuel Grumbach inta_hw & ~trans_pcie->hw_mask); 22803b57a10cSEmmanuel Grumbach } 22813b57a10cSEmmanuel Grumbach 22823b57a10cSEmmanuel Grumbach inta_hw &= trans_pcie->hw_mask; 22832e5d4a8fSHaim Dreyfuss 22842e5d4a8fSHaim Dreyfuss /* Alive notification via Rx interrupt will do the real work */ 22852e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 22862e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 22872e5d4a8fSHaim Dreyfuss isr_stats->alive++; 2288286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) { 2289eda50cdeSSara Sharon /* We can restock, since firmware configured the RFH */ 2290eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2291eda50cdeSSara Sharon } 22922e5d4a8fSHaim Dreyfuss } 22932e5d4a8fSHaim Dreyfuss 22943681021fSJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 2295e5f3f215SHaim Dreyfuss u32 sleep_notif = 2296e5f3f215SHaim Dreyfuss le32_to_cpu(trans_pcie->prph_info->sleep_notif); 2297e5f3f215SHaim Dreyfuss if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND || 2298e5f3f215SHaim Dreyfuss sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) { 2299e5f3f215SHaim Dreyfuss IWL_DEBUG_ISR(trans, 2300e5f3f215SHaim Dreyfuss "Sx interrupt: sleep notification = 0x%x\n", 2301e5f3f215SHaim Dreyfuss sleep_notif); 2302e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = true; 2303e5f3f215SHaim Dreyfuss wake_up(&trans_pcie->sx_waitq); 2304e5f3f215SHaim Dreyfuss } else { 23052e5d4a8fSHaim Dreyfuss /* uCode wakes up after power-down sleep */ 23062e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 23072e5d4a8fSHaim Dreyfuss iwl_pcie_rxq_check_wrptr(trans); 23082e5d4a8fSHaim Dreyfuss iwl_pcie_txq_check_wrptrs(trans); 23092e5d4a8fSHaim Dreyfuss 23102e5d4a8fSHaim Dreyfuss isr_stats->wakeup++; 23112e5d4a8fSHaim Dreyfuss } 2312e5f3f215SHaim Dreyfuss } 23132e5d4a8fSHaim Dreyfuss 23142e5d4a8fSHaim Dreyfuss /* Chip got too hot and stopped itself */ 23152e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 23162e5d4a8fSHaim Dreyfuss IWL_ERR(trans, "Microcode CT kill error detected.\n"); 23172e5d4a8fSHaim Dreyfuss isr_stats->ctkill++; 23182e5d4a8fSHaim Dreyfuss } 23192e5d4a8fSHaim Dreyfuss 23202e5d4a8fSHaim Dreyfuss /* HW RF KILL switch toggled */ 23213a6e168bSJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 23223a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 23232e5d4a8fSHaim Dreyfuss 23242e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 23252e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 23262e5d4a8fSHaim Dreyfuss "Hardware error detected. Restarting.\n"); 23272e5d4a8fSHaim Dreyfuss 23282e5d4a8fSHaim Dreyfuss isr_stats->hw++; 232991c28b83SShahar S Matityahu trans->dbg.hw_error = true; 23302e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 23312e5d4a8fSHaim Dreyfuss } 23322e5d4a8fSHaim Dreyfuss 2333906d4eb8SJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE) { 2334906d4eb8SJohannes Berg IWL_DEBUG_ISR(trans, "Reset flow completed\n"); 2335906d4eb8SJohannes Berg trans_pcie->fw_reset_done = true; 2336906d4eb8SJohannes Berg wake_up(&trans_pcie->fw_reset_waitq); 2337906d4eb8SJohannes Berg } 2338906d4eb8SJohannes Berg 233925edc8f2SJohannes Berg if (!polling) 234025edc8f2SJohannes Berg iwl_pcie_clear_irq(trans, entry->entry); 23412e5d4a8fSHaim Dreyfuss 23422e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 23432e5d4a8fSHaim Dreyfuss 23442e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 23452e5d4a8fSHaim Dreyfuss } 2346