1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 4e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 7e705c121SKalle Valo * 8e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 9e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 10e705c121SKalle Valo * 11e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 12e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 13e705c121SKalle Valo * published by the Free Software Foundation. 14e705c121SKalle Valo * 15e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 16e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18e705c121SKalle Valo * more details. 19e705c121SKalle Valo * 20e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 219b58419eSGolan Ben Ami * this program. 22e705c121SKalle Valo * 23e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 24e705c121SKalle Valo * file called LICENSE. 25e705c121SKalle Valo * 26e705c121SKalle Valo * Contact Information: 27d01c5366SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 28e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29e705c121SKalle Valo * 30e705c121SKalle Valo *****************************************************************************/ 31e705c121SKalle Valo #include <linux/sched.h> 32e705c121SKalle Valo #include <linux/wait.h> 33e705c121SKalle Valo #include <linux/gfp.h> 34e705c121SKalle Valo 35e705c121SKalle Valo #include "iwl-prph.h" 36e705c121SKalle Valo #include "iwl-io.h" 37e705c121SKalle Valo #include "internal.h" 38e705c121SKalle Valo #include "iwl-op-mode.h" 399b58419eSGolan Ben Ami #include "iwl-context-info-gen3.h" 40e705c121SKalle Valo 41e705c121SKalle Valo /****************************************************************************** 42e705c121SKalle Valo * 43e705c121SKalle Valo * RX path functions 44e705c121SKalle Valo * 45e705c121SKalle Valo ******************************************************************************/ 46e705c121SKalle Valo 47e705c121SKalle Valo /* 48e705c121SKalle Valo * Rx theory of operation 49e705c121SKalle Valo * 50e705c121SKalle Valo * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), 51e705c121SKalle Valo * each of which point to Receive Buffers to be filled by the NIC. These get 52e705c121SKalle Valo * used not only for Rx frames, but for any command response or notification 53e705c121SKalle Valo * from the NIC. The driver and NIC manage the Rx buffers by means 54e705c121SKalle Valo * of indexes into the circular buffer. 55e705c121SKalle Valo * 56e705c121SKalle Valo * Rx Queue Indexes 57e705c121SKalle Valo * The host/firmware share two index registers for managing the Rx buffers. 58e705c121SKalle Valo * 59e705c121SKalle Valo * The READ index maps to the first position that the firmware may be writing 60e705c121SKalle Valo * to -- the driver can read up to (but not including) this position and get 61e705c121SKalle Valo * good data. 62e705c121SKalle Valo * The READ index is managed by the firmware once the card is enabled. 63e705c121SKalle Valo * 64e705c121SKalle Valo * The WRITE index maps to the last position the driver has read from -- the 65e705c121SKalle Valo * position preceding WRITE is the last slot the firmware can place a packet. 66e705c121SKalle Valo * 67e705c121SKalle Valo * The queue is empty (no good data) if WRITE = READ - 1, and is full if 68e705c121SKalle Valo * WRITE = READ. 69e705c121SKalle Valo * 70e705c121SKalle Valo * During initialization, the host sets up the READ queue position to the first 71e705c121SKalle Valo * INDEX position, and WRITE to the last (READ - 1 wrapped) 72e705c121SKalle Valo * 73e705c121SKalle Valo * When the firmware places a packet in a buffer, it will advance the READ index 74e705c121SKalle Valo * and fire the RX interrupt. The driver can then query the READ index and 75e705c121SKalle Valo * process as many packets as possible, moving the WRITE index forward as it 76e705c121SKalle Valo * resets the Rx queue buffers with new memory. 77e705c121SKalle Valo * 78e705c121SKalle Valo * The management in the driver is as follows: 79e705c121SKalle Valo * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free. 80e705c121SKalle Valo * When the interrupt handler is called, the request is processed. 81e705c121SKalle Valo * The page is either stolen - transferred to the upper layer 82e705c121SKalle Valo * or reused - added immediately to the iwl->rxq->rx_free list. 83e705c121SKalle Valo * + When the page is stolen - the driver updates the matching queue's used 84e705c121SKalle Valo * count, detaches the RBD and transfers it to the queue used list. 85e705c121SKalle Valo * When there are two used RBDs - they are transferred to the allocator empty 86e705c121SKalle Valo * list. Work is then scheduled for the allocator to start allocating 87e705c121SKalle Valo * eight buffers. 88e705c121SKalle Valo * When there are another 6 used RBDs - they are transferred to the allocator 89e705c121SKalle Valo * empty list and the driver tries to claim the pre-allocated buffers and 90e705c121SKalle Valo * add them to iwl->rxq->rx_free. If it fails - it continues to claim them 91e705c121SKalle Valo * until ready. 92e705c121SKalle Valo * When there are 8+ buffers in the free list - either from allocation or from 93e705c121SKalle Valo * 8 reused unstolen pages - restock is called to update the FW and indexes. 94e705c121SKalle Valo * + In order to make sure the allocator always has RBDs to use for allocation 95e705c121SKalle Valo * the allocator has initial pool in the size of num_queues*(8-2) - the 96e705c121SKalle Valo * maximum missing RBDs per allocation request (request posted with 2 97e705c121SKalle Valo * empty RBDs, there is no guarantee when the other 6 RBDs are supplied). 98e705c121SKalle Valo * The queues supplies the recycle of the rest of the RBDs. 99e705c121SKalle Valo * + A received packet is processed and handed to the kernel network stack, 100e705c121SKalle Valo * detached from the iwl->rxq. The driver 'processed' index is updated. 101e705c121SKalle Valo * + If there are no allocated buffers in iwl->rxq->rx_free, 102e705c121SKalle Valo * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set. 103e705c121SKalle Valo * If there were enough free buffers and RX_STALLED is set it is cleared. 104e705c121SKalle Valo * 105e705c121SKalle Valo * 106e705c121SKalle Valo * Driver sequence: 107e705c121SKalle Valo * 108e705c121SKalle Valo * iwl_rxq_alloc() Allocates rx_free 109e705c121SKalle Valo * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls 110e705c121SKalle Valo * iwl_pcie_rxq_restock. 111e705c121SKalle Valo * Used only during initialization. 112e705c121SKalle Valo * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx 113e705c121SKalle Valo * queue, updates firmware pointers, and updates 114e705c121SKalle Valo * the WRITE index. 115e705c121SKalle Valo * iwl_pcie_rx_allocator() Background work for allocating pages. 116e705c121SKalle Valo * 117e705c121SKalle Valo * -- enable interrupts -- 118e705c121SKalle Valo * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the 119e705c121SKalle Valo * READ INDEX, detaching the SKB from the pool. 120e705c121SKalle Valo * Moves the packet buffer from queue to rx_used. 121e705c121SKalle Valo * Posts and claims requests to the allocator. 122e705c121SKalle Valo * Calls iwl_pcie_rxq_restock to refill any empty 123e705c121SKalle Valo * slots. 124e705c121SKalle Valo * 125e705c121SKalle Valo * RBD life-cycle: 126e705c121SKalle Valo * 127e705c121SKalle Valo * Init: 128e705c121SKalle Valo * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue 129e705c121SKalle Valo * 130e705c121SKalle Valo * Regular Receive interrupt: 131e705c121SKalle Valo * Page Stolen: 132e705c121SKalle Valo * rxq.queue -> rxq.rx_used -> allocator.rbd_empty -> 133e705c121SKalle Valo * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue 134e705c121SKalle Valo * Page not Stolen: 135e705c121SKalle Valo * rxq.queue -> rxq.rx_free -> rxq.queue 136e705c121SKalle Valo * ... 137e705c121SKalle Valo * 138e705c121SKalle Valo */ 139e705c121SKalle Valo 140e705c121SKalle Valo /* 141e705c121SKalle Valo * iwl_rxq_space - Return number of free slots available in queue. 142e705c121SKalle Valo */ 143e705c121SKalle Valo static int iwl_rxq_space(const struct iwl_rxq *rxq) 144e705c121SKalle Valo { 14596a6497bSSara Sharon /* Make sure rx queue size is a power of 2 */ 14696a6497bSSara Sharon WARN_ON(rxq->queue_size & (rxq->queue_size - 1)); 147e705c121SKalle Valo 148e705c121SKalle Valo /* 149e705c121SKalle Valo * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity 150e705c121SKalle Valo * between empty and completely full queues. 151e705c121SKalle Valo * The following is equivalent to modulo by RX_QUEUE_SIZE and is well 152e705c121SKalle Valo * defined for negative dividends. 153e705c121SKalle Valo */ 15496a6497bSSara Sharon return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1); 155e705c121SKalle Valo } 156e705c121SKalle Valo 157e705c121SKalle Valo /* 158e705c121SKalle Valo * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 159e705c121SKalle Valo */ 160e705c121SKalle Valo static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr) 161e705c121SKalle Valo { 162e705c121SKalle Valo return cpu_to_le32((u32)(dma_addr >> 8)); 163e705c121SKalle Valo } 164e705c121SKalle Valo 165e705c121SKalle Valo /* 166e705c121SKalle Valo * iwl_pcie_rx_stop - stops the Rx DMA 167e705c121SKalle Valo */ 168e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans) 169e705c121SKalle Valo { 170d0158235SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 171d0158235SGolan Ben Ami /* TODO: remove this for 22560 once fw does it */ 172d0158235SGolan Ben Ami iwl_write_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0); 173d0158235SGolan Ben Ami return iwl_poll_prph_bit(trans, RFH_GEN_STATUS_GEN3, 174d0158235SGolan Ben Ami RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 175d0158235SGolan Ben Ami } else if (trans->cfg->mq_rx_supported) { 176d7fdd0e5SSara Sharon iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0); 177d7fdd0e5SSara Sharon return iwl_poll_prph_bit(trans, RFH_GEN_STATUS, 178d7fdd0e5SSara Sharon RXF_DMA_IDLE, RXF_DMA_IDLE, 1000); 179d7fdd0e5SSara Sharon } else { 180e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 181e705c121SKalle Valo return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, 182d7fdd0e5SSara Sharon FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 183d7fdd0e5SSara Sharon 1000); 184d7fdd0e5SSara Sharon } 185e705c121SKalle Valo } 186e705c121SKalle Valo 187e705c121SKalle Valo /* 188e705c121SKalle Valo * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue 189e705c121SKalle Valo */ 19078485054SSara Sharon static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, 19178485054SSara Sharon struct iwl_rxq *rxq) 192e705c121SKalle Valo { 193e705c121SKalle Valo u32 reg; 194e705c121SKalle Valo 195e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 196e705c121SKalle Valo 197e705c121SKalle Valo /* 198e705c121SKalle Valo * explicitly wake up the NIC if: 199e705c121SKalle Valo * 1. shadow registers aren't enabled 200e705c121SKalle Valo * 2. there is a chance that the NIC is asleep 201e705c121SKalle Valo */ 202e705c121SKalle Valo if (!trans->cfg->base_params->shadow_reg_enable && 203e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 204e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 205e705c121SKalle Valo 206e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 207e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n", 208e705c121SKalle Valo reg); 209e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 210a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 211e705c121SKalle Valo rxq->need_update = true; 212e705c121SKalle Valo return; 213e705c121SKalle Valo } 214e705c121SKalle Valo } 215e705c121SKalle Valo 216e705c121SKalle Valo rxq->write_actual = round_down(rxq->write, 8); 2171b493e30SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 2181b493e30SGolan Ben Ami iwl_write32(trans, HBUS_TARG_WRPTR, 2191b493e30SGolan Ben Ami (rxq->write_actual | 2201b493e30SGolan Ben Ami ((FIRST_RX_QUEUE + rxq->id) << 16))); 2211b493e30SGolan Ben Ami else if (trans->cfg->mq_rx_supported) 2221554ed20SSara Sharon iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id), 22396a6497bSSara Sharon rxq->write_actual); 2241316d595SSara Sharon else 225e705c121SKalle Valo iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual); 226e705c121SKalle Valo } 227e705c121SKalle Valo 228e705c121SKalle Valo static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans) 229e705c121SKalle Valo { 230e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 23178485054SSara Sharon int i; 232e705c121SKalle Valo 23378485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 23478485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 235e705c121SKalle Valo 236e705c121SKalle Valo if (!rxq->need_update) 23778485054SSara Sharon continue; 23878485054SSara Sharon spin_lock(&rxq->lock); 23978485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 240e705c121SKalle Valo rxq->need_update = false; 241e705c121SKalle Valo spin_unlock(&rxq->lock); 242e705c121SKalle Valo } 24378485054SSara Sharon } 244e705c121SKalle Valo 2450307c839SGolan Ben Ami static void iwl_pcie_restock_bd(struct iwl_trans *trans, 2460307c839SGolan Ben Ami struct iwl_rxq *rxq, 2470307c839SGolan Ben Ami struct iwl_rx_mem_buffer *rxb) 2480307c839SGolan Ben Ami { 2490307c839SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 2500307c839SGolan Ben Ami struct iwl_rx_transfer_desc *bd = rxq->bd; 2510307c839SGolan Ben Ami 2520307c839SGolan Ben Ami bd[rxq->write].type_n_size = 2530307c839SGolan Ben Ami cpu_to_le32((IWL_RX_TD_TYPE & IWL_RX_TD_TYPE_MSK) | 2540307c839SGolan Ben Ami ((IWL_RX_TD_SIZE_2K >> 8) & IWL_RX_TD_SIZE_MSK)); 2550307c839SGolan Ben Ami bd[rxq->write].addr = cpu_to_le64(rxb->page_dma); 2560307c839SGolan Ben Ami bd[rxq->write].rbid = cpu_to_le16(rxb->vid); 2570307c839SGolan Ben Ami } else { 2580307c839SGolan Ben Ami __le64 *bd = rxq->bd; 2590307c839SGolan Ben Ami 2600307c839SGolan Ben Ami bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid); 2610307c839SGolan Ben Ami } 2620307c839SGolan Ben Ami } 2630307c839SGolan Ben Ami 264e0e168dcSGregory Greenman /* 2652047fa54SSara Sharon * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx 266e0e168dcSGregory Greenman */ 2672047fa54SSara Sharon static void iwl_pcie_rxmq_restock(struct iwl_trans *trans, 26896a6497bSSara Sharon struct iwl_rxq *rxq) 26996a6497bSSara Sharon { 27096a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb; 27196a6497bSSara Sharon 27296a6497bSSara Sharon /* 27396a6497bSSara Sharon * If the device isn't enabled - no need to try to add buffers... 27496a6497bSSara Sharon * This can happen when we stop the device and still have an interrupt 27596a6497bSSara Sharon * pending. We stop the APM before we sync the interrupts because we 27696a6497bSSara Sharon * have to (see comment there). On the other hand, since the APM is 27796a6497bSSara Sharon * stopped, we cannot access the HW (in particular not prph). 27896a6497bSSara Sharon * So don't try to restock if the APM has been already stopped. 27996a6497bSSara Sharon */ 28096a6497bSSara Sharon if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 28196a6497bSSara Sharon return; 28296a6497bSSara Sharon 28396a6497bSSara Sharon spin_lock(&rxq->lock); 28496a6497bSSara Sharon while (rxq->free_count) { 28596a6497bSSara Sharon /* Get next free Rx buffer, remove from free list */ 28696a6497bSSara Sharon rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 28796a6497bSSara Sharon list); 28896a6497bSSara Sharon list_del(&rxb->list); 289b1753c62SSara Sharon rxb->invalid = false; 29096a6497bSSara Sharon /* 12 first bits are expected to be empty */ 29196a6497bSSara Sharon WARN_ON(rxb->page_dma & DMA_BIT_MASK(12)); 29296a6497bSSara Sharon /* Point to Rx buffer via next RBD in circular buffer */ 2930307c839SGolan Ben Ami iwl_pcie_restock_bd(trans, rxq, rxb); 29496a6497bSSara Sharon rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK; 29596a6497bSSara Sharon rxq->free_count--; 29696a6497bSSara Sharon } 29796a6497bSSara Sharon spin_unlock(&rxq->lock); 29896a6497bSSara Sharon 29996a6497bSSara Sharon /* 30096a6497bSSara Sharon * If we've added more space for the firmware to place data, tell it. 30196a6497bSSara Sharon * Increment device's write pointer in multiples of 8. 30296a6497bSSara Sharon */ 30396a6497bSSara Sharon if (rxq->write_actual != (rxq->write & ~0x7)) { 30496a6497bSSara Sharon spin_lock(&rxq->lock); 30596a6497bSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 30696a6497bSSara Sharon spin_unlock(&rxq->lock); 30796a6497bSSara Sharon } 30896a6497bSSara Sharon } 30996a6497bSSara Sharon 310e705c121SKalle Valo /* 3112047fa54SSara Sharon * iwl_pcie_rxsq_restock - restock implementation for single queue rx 312e705c121SKalle Valo */ 3132047fa54SSara Sharon static void iwl_pcie_rxsq_restock(struct iwl_trans *trans, 314e0e168dcSGregory Greenman struct iwl_rxq *rxq) 315e705c121SKalle Valo { 316e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 317e705c121SKalle Valo 318e705c121SKalle Valo /* 319e705c121SKalle Valo * If the device isn't enabled - not need to try to add buffers... 320e705c121SKalle Valo * This can happen when we stop the device and still have an interrupt 321e705c121SKalle Valo * pending. We stop the APM before we sync the interrupts because we 322e705c121SKalle Valo * have to (see comment there). On the other hand, since the APM is 323e705c121SKalle Valo * stopped, we cannot access the HW (in particular not prph). 324e705c121SKalle Valo * So don't try to restock if the APM has been already stopped. 325e705c121SKalle Valo */ 326e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 327e705c121SKalle Valo return; 328e705c121SKalle Valo 329e705c121SKalle Valo spin_lock(&rxq->lock); 330e705c121SKalle Valo while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) { 33196a6497bSSara Sharon __le32 *bd = (__le32 *)rxq->bd; 332e705c121SKalle Valo /* The overwritten rxb must be a used one */ 333e705c121SKalle Valo rxb = rxq->queue[rxq->write]; 334e705c121SKalle Valo BUG_ON(rxb && rxb->page); 335e705c121SKalle Valo 336e705c121SKalle Valo /* Get next free Rx buffer, remove from free list */ 337e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer, 338e705c121SKalle Valo list); 339e705c121SKalle Valo list_del(&rxb->list); 340b1753c62SSara Sharon rxb->invalid = false; 341e705c121SKalle Valo 342e705c121SKalle Valo /* Point to Rx buffer via next RBD in circular buffer */ 34396a6497bSSara Sharon bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma); 344e705c121SKalle Valo rxq->queue[rxq->write] = rxb; 345e705c121SKalle Valo rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 346e705c121SKalle Valo rxq->free_count--; 347e705c121SKalle Valo } 348e705c121SKalle Valo spin_unlock(&rxq->lock); 349e705c121SKalle Valo 350e705c121SKalle Valo /* If we've added more space for the firmware to place data, tell it. 351e705c121SKalle Valo * Increment device's write pointer in multiples of 8. */ 352e705c121SKalle Valo if (rxq->write_actual != (rxq->write & ~0x7)) { 353e705c121SKalle Valo spin_lock(&rxq->lock); 35478485054SSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, rxq); 355e705c121SKalle Valo spin_unlock(&rxq->lock); 356e705c121SKalle Valo } 357e705c121SKalle Valo } 358e705c121SKalle Valo 359e705c121SKalle Valo /* 360e0e168dcSGregory Greenman * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool 361e0e168dcSGregory Greenman * 362e0e168dcSGregory Greenman * If there are slots in the RX queue that need to be restocked, 363e0e168dcSGregory Greenman * and we have free pre-allocated buffers, fill the ranks as much 364e0e168dcSGregory Greenman * as we can, pulling from rx_free. 365e0e168dcSGregory Greenman * 366e0e168dcSGregory Greenman * This moves the 'write' index forward to catch up with 'processed', and 367e0e168dcSGregory Greenman * also updates the memory address in the firmware to reference the new 368e0e168dcSGregory Greenman * target buffer. 369e0e168dcSGregory Greenman */ 370e0e168dcSGregory Greenman static 371e0e168dcSGregory Greenman void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq) 372e0e168dcSGregory Greenman { 373e0e168dcSGregory Greenman if (trans->cfg->mq_rx_supported) 3742047fa54SSara Sharon iwl_pcie_rxmq_restock(trans, rxq); 375e0e168dcSGregory Greenman else 3762047fa54SSara Sharon iwl_pcie_rxsq_restock(trans, rxq); 377e0e168dcSGregory Greenman } 378e0e168dcSGregory Greenman 379e0e168dcSGregory Greenman /* 380e705c121SKalle Valo * iwl_pcie_rx_alloc_page - allocates and returns a page. 381e705c121SKalle Valo * 382e705c121SKalle Valo */ 383e705c121SKalle Valo static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans, 384e705c121SKalle Valo gfp_t priority) 385e705c121SKalle Valo { 386e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 387e705c121SKalle Valo struct page *page; 388e705c121SKalle Valo gfp_t gfp_mask = priority; 389e705c121SKalle Valo 390e705c121SKalle Valo if (trans_pcie->rx_page_order > 0) 391e705c121SKalle Valo gfp_mask |= __GFP_COMP; 392e705c121SKalle Valo 393e705c121SKalle Valo /* Alloc a new receive buffer */ 394e705c121SKalle Valo page = alloc_pages(gfp_mask, trans_pcie->rx_page_order); 395e705c121SKalle Valo if (!page) { 396e705c121SKalle Valo if (net_ratelimit()) 397e705c121SKalle Valo IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n", 398e705c121SKalle Valo trans_pcie->rx_page_order); 39978485054SSara Sharon /* 40078485054SSara Sharon * Issue an error if we don't have enough pre-allocated 40178485054SSara Sharon * buffers. 402e705c121SKalle Valo ` */ 40378485054SSara Sharon if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit()) 404e705c121SKalle Valo IWL_CRIT(trans, 40578485054SSara Sharon "Failed to alloc_pages\n"); 406e705c121SKalle Valo return NULL; 407e705c121SKalle Valo } 408e705c121SKalle Valo return page; 409e705c121SKalle Valo } 410e705c121SKalle Valo 411e705c121SKalle Valo /* 412e705c121SKalle Valo * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD 413e705c121SKalle Valo * 414e705c121SKalle Valo * A used RBD is an Rx buffer that has been given to the stack. To use it again 415e705c121SKalle Valo * a page must be allocated and the RBD must point to the page. This function 416e705c121SKalle Valo * doesn't change the HW pointer but handles the list of pages that is used by 417e705c121SKalle Valo * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly 418e705c121SKalle Valo * allocated buffers. 419e705c121SKalle Valo */ 42078485054SSara Sharon static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 42178485054SSara Sharon struct iwl_rxq *rxq) 422e705c121SKalle Valo { 423e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 424e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 425e705c121SKalle Valo struct page *page; 426e705c121SKalle Valo 427e705c121SKalle Valo while (1) { 428e705c121SKalle Valo spin_lock(&rxq->lock); 429e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 430e705c121SKalle Valo spin_unlock(&rxq->lock); 431e705c121SKalle Valo return; 432e705c121SKalle Valo } 433e705c121SKalle Valo spin_unlock(&rxq->lock); 434e705c121SKalle Valo 435e705c121SKalle Valo /* Alloc a new receive buffer */ 436e705c121SKalle Valo page = iwl_pcie_rx_alloc_page(trans, priority); 437e705c121SKalle Valo if (!page) 438e705c121SKalle Valo return; 439e705c121SKalle Valo 440e705c121SKalle Valo spin_lock(&rxq->lock); 441e705c121SKalle Valo 442e705c121SKalle Valo if (list_empty(&rxq->rx_used)) { 443e705c121SKalle Valo spin_unlock(&rxq->lock); 444e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 445e705c121SKalle Valo return; 446e705c121SKalle Valo } 447e705c121SKalle Valo rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer, 448e705c121SKalle Valo list); 449e705c121SKalle Valo list_del(&rxb->list); 450e705c121SKalle Valo spin_unlock(&rxq->lock); 451e705c121SKalle Valo 452e705c121SKalle Valo BUG_ON(rxb->page); 453e705c121SKalle Valo rxb->page = page; 454e705c121SKalle Valo /* Get physical address of the RB */ 455e705c121SKalle Valo rxb->page_dma = 456e705c121SKalle Valo dma_map_page(trans->dev, page, 0, 457e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 458e705c121SKalle Valo DMA_FROM_DEVICE); 459e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 460e705c121SKalle Valo rxb->page = NULL; 461e705c121SKalle Valo spin_lock(&rxq->lock); 462e705c121SKalle Valo list_add(&rxb->list, &rxq->rx_used); 463e705c121SKalle Valo spin_unlock(&rxq->lock); 464e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 465e705c121SKalle Valo return; 466e705c121SKalle Valo } 467e705c121SKalle Valo 468e705c121SKalle Valo spin_lock(&rxq->lock); 469e705c121SKalle Valo 470e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 471e705c121SKalle Valo rxq->free_count++; 472e705c121SKalle Valo 473e705c121SKalle Valo spin_unlock(&rxq->lock); 474e705c121SKalle Valo } 475e705c121SKalle Valo } 476e705c121SKalle Valo 47778485054SSara Sharon static void iwl_pcie_free_rbs_pool(struct iwl_trans *trans) 478e705c121SKalle Valo { 479e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 480e705c121SKalle Valo int i; 481e705c121SKalle Valo 4827b542436SSara Sharon for (i = 0; i < RX_POOL_SIZE; i++) { 48378485054SSara Sharon if (!trans_pcie->rx_pool[i].page) 484e705c121SKalle Valo continue; 48578485054SSara Sharon dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma, 486e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 487e705c121SKalle Valo DMA_FROM_DEVICE); 48878485054SSara Sharon __free_pages(trans_pcie->rx_pool[i].page, 48978485054SSara Sharon trans_pcie->rx_page_order); 49078485054SSara Sharon trans_pcie->rx_pool[i].page = NULL; 491e705c121SKalle Valo } 492e705c121SKalle Valo } 493e705c121SKalle Valo 494e705c121SKalle Valo /* 495e705c121SKalle Valo * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues 496e705c121SKalle Valo * 497e705c121SKalle Valo * Allocates for each received request 8 pages 498e705c121SKalle Valo * Called as a scheduled work item. 499e705c121SKalle Valo */ 500e705c121SKalle Valo static void iwl_pcie_rx_allocator(struct iwl_trans *trans) 501e705c121SKalle Valo { 502e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 503e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 504e705c121SKalle Valo struct list_head local_empty; 505e705c121SKalle Valo int pending = atomic_xchg(&rba->req_pending, 0); 506e705c121SKalle Valo 507e705c121SKalle Valo IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending); 508e705c121SKalle Valo 509e705c121SKalle Valo /* If we were scheduled - there is at least one request */ 510e705c121SKalle Valo spin_lock(&rba->lock); 511e705c121SKalle Valo /* swap out the rba->rbd_empty to a local list */ 512e705c121SKalle Valo list_replace_init(&rba->rbd_empty, &local_empty); 513e705c121SKalle Valo spin_unlock(&rba->lock); 514e705c121SKalle Valo 515e705c121SKalle Valo while (pending) { 516e705c121SKalle Valo int i; 5170979a913SJohannes Berg LIST_HEAD(local_allocated); 51878485054SSara Sharon gfp_t gfp_mask = GFP_KERNEL; 51978485054SSara Sharon 52078485054SSara Sharon /* Do not post a warning if there are only a few requests */ 52178485054SSara Sharon if (pending < RX_PENDING_WATERMARK) 52278485054SSara Sharon gfp_mask |= __GFP_NOWARN; 523e705c121SKalle Valo 524e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC;) { 525e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 526e705c121SKalle Valo struct page *page; 527e705c121SKalle Valo 528e705c121SKalle Valo /* List should never be empty - each reused RBD is 529e705c121SKalle Valo * returned to the list, and initial pool covers any 530e705c121SKalle Valo * possible gap between the time the page is allocated 531e705c121SKalle Valo * to the time the RBD is added. 532e705c121SKalle Valo */ 533e705c121SKalle Valo BUG_ON(list_empty(&local_empty)); 534e705c121SKalle Valo /* Get the first rxb from the rbd list */ 535e705c121SKalle Valo rxb = list_first_entry(&local_empty, 536e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 537e705c121SKalle Valo BUG_ON(rxb->page); 538e705c121SKalle Valo 539e705c121SKalle Valo /* Alloc a new receive buffer */ 54078485054SSara Sharon page = iwl_pcie_rx_alloc_page(trans, gfp_mask); 541e705c121SKalle Valo if (!page) 542e705c121SKalle Valo continue; 543e705c121SKalle Valo rxb->page = page; 544e705c121SKalle Valo 545e705c121SKalle Valo /* Get physical address of the RB */ 546e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, page, 0, 547e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 548e705c121SKalle Valo DMA_FROM_DEVICE); 549e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 550e705c121SKalle Valo rxb->page = NULL; 551e705c121SKalle Valo __free_pages(page, trans_pcie->rx_page_order); 552e705c121SKalle Valo continue; 553e705c121SKalle Valo } 554e705c121SKalle Valo 555e705c121SKalle Valo /* move the allocated entry to the out list */ 556e705c121SKalle Valo list_move(&rxb->list, &local_allocated); 557e705c121SKalle Valo i++; 558e705c121SKalle Valo } 559e705c121SKalle Valo 560e705c121SKalle Valo pending--; 561e705c121SKalle Valo if (!pending) { 562e705c121SKalle Valo pending = atomic_xchg(&rba->req_pending, 0); 563e705c121SKalle Valo IWL_DEBUG_RX(trans, 564e705c121SKalle Valo "Pending allocation requests = %d\n", 565e705c121SKalle Valo pending); 566e705c121SKalle Valo } 567e705c121SKalle Valo 568e705c121SKalle Valo spin_lock(&rba->lock); 569e705c121SKalle Valo /* add the allocated rbds to the allocator allocated list */ 570e705c121SKalle Valo list_splice_tail(&local_allocated, &rba->rbd_allocated); 571e705c121SKalle Valo /* get more empty RBDs for current pending requests */ 572e705c121SKalle Valo list_splice_tail_init(&rba->rbd_empty, &local_empty); 573e705c121SKalle Valo spin_unlock(&rba->lock); 574e705c121SKalle Valo 575e705c121SKalle Valo atomic_inc(&rba->req_ready); 576e705c121SKalle Valo } 577e705c121SKalle Valo 578e705c121SKalle Valo spin_lock(&rba->lock); 579e705c121SKalle Valo /* return unused rbds to the allocator empty list */ 580e705c121SKalle Valo list_splice_tail(&local_empty, &rba->rbd_empty); 581e705c121SKalle Valo spin_unlock(&rba->lock); 582e705c121SKalle Valo } 583e705c121SKalle Valo 584e705c121SKalle Valo /* 585d56daea4SSara Sharon * iwl_pcie_rx_allocator_get - returns the pre-allocated pages 586e705c121SKalle Valo .* 587e705c121SKalle Valo .* Called by queue when the queue posted allocation request and 588e705c121SKalle Valo * has freed 8 RBDs in order to restock itself. 589d56daea4SSara Sharon * This function directly moves the allocated RBs to the queue's ownership 590d56daea4SSara Sharon * and updates the relevant counters. 591e705c121SKalle Valo */ 592d56daea4SSara Sharon static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans, 593d56daea4SSara Sharon struct iwl_rxq *rxq) 594e705c121SKalle Valo { 595e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 596e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 597e705c121SKalle Valo int i; 598e705c121SKalle Valo 599d56daea4SSara Sharon lockdep_assert_held(&rxq->lock); 600d56daea4SSara Sharon 601e705c121SKalle Valo /* 602e705c121SKalle Valo * atomic_dec_if_positive returns req_ready - 1 for any scenario. 603e705c121SKalle Valo * If req_ready is 0 atomic_dec_if_positive will return -1 and this 604d56daea4SSara Sharon * function will return early, as there are no ready requests. 605e705c121SKalle Valo * atomic_dec_if_positive will perofrm the *actual* decrement only if 606e705c121SKalle Valo * req_ready > 0, i.e. - there are ready requests and the function 607e705c121SKalle Valo * hands one request to the caller. 608e705c121SKalle Valo */ 609e705c121SKalle Valo if (atomic_dec_if_positive(&rba->req_ready) < 0) 610d56daea4SSara Sharon return; 611e705c121SKalle Valo 612e705c121SKalle Valo spin_lock(&rba->lock); 613e705c121SKalle Valo for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) { 614e705c121SKalle Valo /* Get next free Rx buffer, remove it from free list */ 615d56daea4SSara Sharon struct iwl_rx_mem_buffer *rxb = 616d56daea4SSara Sharon list_first_entry(&rba->rbd_allocated, 617e705c121SKalle Valo struct iwl_rx_mem_buffer, list); 618d56daea4SSara Sharon 619d56daea4SSara Sharon list_move(&rxb->list, &rxq->rx_free); 620e705c121SKalle Valo } 621e705c121SKalle Valo spin_unlock(&rba->lock); 622e705c121SKalle Valo 623d56daea4SSara Sharon rxq->used_count -= RX_CLAIM_REQ_ALLOC; 624d56daea4SSara Sharon rxq->free_count += RX_CLAIM_REQ_ALLOC; 625e705c121SKalle Valo } 626e705c121SKalle Valo 62710a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data) 628e705c121SKalle Valo { 629e705c121SKalle Valo struct iwl_rb_allocator *rba_p = 630e705c121SKalle Valo container_of(data, struct iwl_rb_allocator, rx_alloc); 631e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 632e705c121SKalle Valo container_of(rba_p, struct iwl_trans_pcie, rba); 633e705c121SKalle Valo 634e705c121SKalle Valo iwl_pcie_rx_allocator(trans_pcie->trans); 635e705c121SKalle Valo } 636e705c121SKalle Valo 6370307c839SGolan Ben Ami static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td) 6380307c839SGolan Ben Ami { 6390307c839SGolan Ben Ami struct iwl_rx_transfer_desc *rx_td; 6400307c839SGolan Ben Ami 6410307c839SGolan Ben Ami if (use_rx_td) 6420307c839SGolan Ben Ami return sizeof(*rx_td); 6430307c839SGolan Ben Ami else 6440307c839SGolan Ben Ami return trans->cfg->mq_rx_supported ? sizeof(__le64) : 6450307c839SGolan Ben Ami sizeof(__le32); 6460307c839SGolan Ben Ami } 6470307c839SGolan Ben Ami 6481b493e30SGolan Ben Ami static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans, 6491b493e30SGolan Ben Ami struct iwl_rxq *rxq) 6501b493e30SGolan Ben Ami { 6511b493e30SGolan Ben Ami struct device *dev = trans->dev; 6520307c839SGolan Ben Ami struct iwl_rx_completion_desc *rx_cd; 6530307c839SGolan Ben Ami bool use_rx_td = (trans->cfg->device_family >= 6540307c839SGolan Ben Ami IWL_DEVICE_FAMILY_22560); 6550307c839SGolan Ben Ami int free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 6561b493e30SGolan Ben Ami 6571b493e30SGolan Ben Ami if (rxq->bd) 6580307c839SGolan Ben Ami dma_free_coherent(trans->dev, 6590307c839SGolan Ben Ami free_size * rxq->queue_size, 6601b493e30SGolan Ben Ami rxq->bd, rxq->bd_dma); 6611b493e30SGolan Ben Ami rxq->bd_dma = 0; 6621b493e30SGolan Ben Ami rxq->bd = NULL; 6631b493e30SGolan Ben Ami 6641b493e30SGolan Ben Ami if (rxq->rb_stts) 6651b493e30SGolan Ben Ami dma_free_coherent(trans->dev, 6660307c839SGolan Ben Ami use_rx_td ? sizeof(__le16) : 6671b493e30SGolan Ben Ami sizeof(struct iwl_rb_status), 6681b493e30SGolan Ben Ami rxq->rb_stts, rxq->rb_stts_dma); 6691b493e30SGolan Ben Ami rxq->rb_stts_dma = 0; 6701b493e30SGolan Ben Ami rxq->rb_stts = NULL; 6711b493e30SGolan Ben Ami 6721b493e30SGolan Ben Ami if (rxq->used_bd) 6730307c839SGolan Ben Ami dma_free_coherent(trans->dev, 6740307c839SGolan Ben Ami (use_rx_td ? sizeof(*rx_cd) : 6750307c839SGolan Ben Ami sizeof(__le32)) * rxq->queue_size, 6761b493e30SGolan Ben Ami rxq->used_bd, rxq->used_bd_dma); 6771b493e30SGolan Ben Ami rxq->used_bd_dma = 0; 6781b493e30SGolan Ben Ami rxq->used_bd = NULL; 6791b493e30SGolan Ben Ami 6801b493e30SGolan Ben Ami if (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) 6811b493e30SGolan Ben Ami return; 6821b493e30SGolan Ben Ami 6831b493e30SGolan Ben Ami if (rxq->tr_tail) 6841b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 6851b493e30SGolan Ben Ami rxq->tr_tail, rxq->tr_tail_dma); 6861b493e30SGolan Ben Ami rxq->tr_tail_dma = 0; 6871b493e30SGolan Ben Ami rxq->tr_tail = NULL; 6881b493e30SGolan Ben Ami 6891b493e30SGolan Ben Ami if (rxq->cr_tail) 6901b493e30SGolan Ben Ami dma_free_coherent(dev, sizeof(__le16), 6911b493e30SGolan Ben Ami rxq->cr_tail, rxq->cr_tail_dma); 6921b493e30SGolan Ben Ami rxq->cr_tail_dma = 0; 6931b493e30SGolan Ben Ami rxq->cr_tail = NULL; 6941b493e30SGolan Ben Ami } 6951b493e30SGolan Ben Ami 6961b493e30SGolan Ben Ami static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans, 6971b493e30SGolan Ben Ami struct iwl_rxq *rxq) 698e705c121SKalle Valo { 699e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 700e705c121SKalle Valo struct device *dev = trans->dev; 7010307c839SGolan Ben Ami struct iwl_rx_completion_desc *rx_cd; 70278485054SSara Sharon int i; 7030307c839SGolan Ben Ami int free_size; 7040307c839SGolan Ben Ami bool use_rx_td = (trans->cfg->device_family >= 7050307c839SGolan Ben Ami IWL_DEVICE_FAMILY_22560); 706e705c121SKalle Valo 70778485054SSara Sharon spin_lock_init(&rxq->lock); 70896a6497bSSara Sharon if (trans->cfg->mq_rx_supported) 70996a6497bSSara Sharon rxq->queue_size = MQ_RX_TABLE_SIZE; 71096a6497bSSara Sharon else 71196a6497bSSara Sharon rxq->queue_size = RX_QUEUE_SIZE; 71296a6497bSSara Sharon 7130307c839SGolan Ben Ami free_size = iwl_pcie_free_bd_size(trans, use_rx_td); 7140307c839SGolan Ben Ami 71578485054SSara Sharon /* 71678485054SSara Sharon * Allocate the circular buffer of Read Buffer Descriptors 71778485054SSara Sharon * (RBDs) 71878485054SSara Sharon */ 71978485054SSara Sharon rxq->bd = dma_zalloc_coherent(dev, 72096a6497bSSara Sharon free_size * rxq->queue_size, 721e705c121SKalle Valo &rxq->bd_dma, GFP_KERNEL); 722e705c121SKalle Valo if (!rxq->bd) 72378485054SSara Sharon goto err; 72478485054SSara Sharon 72596a6497bSSara Sharon if (trans->cfg->mq_rx_supported) { 72696a6497bSSara Sharon rxq->used_bd = dma_zalloc_coherent(dev, 7270307c839SGolan Ben Ami (use_rx_td ? 7280307c839SGolan Ben Ami sizeof(*rx_cd) : 7290307c839SGolan Ben Ami sizeof(__le32)) * 73096a6497bSSara Sharon rxq->queue_size, 73196a6497bSSara Sharon &rxq->used_bd_dma, 73296a6497bSSara Sharon GFP_KERNEL); 73396a6497bSSara Sharon if (!rxq->used_bd) 73496a6497bSSara Sharon goto err; 73596a6497bSSara Sharon } 736e705c121SKalle Valo 737e705c121SKalle Valo /* Allocate the driver's pointer to receive buffer status */ 7380307c839SGolan Ben Ami rxq->rb_stts = dma_zalloc_coherent(dev, use_rx_td ? 7390307c839SGolan Ben Ami sizeof(__le16) : 7400307c839SGolan Ben Ami sizeof(struct iwl_rb_status), 74178485054SSara Sharon &rxq->rb_stts_dma, 74278485054SSara Sharon GFP_KERNEL); 743e705c121SKalle Valo if (!rxq->rb_stts) 74478485054SSara Sharon goto err; 7451b493e30SGolan Ben Ami 7460307c839SGolan Ben Ami if (!use_rx_td) 7471b493e30SGolan Ben Ami return 0; 7481b493e30SGolan Ben Ami 7491b493e30SGolan Ben Ami /* Allocate the driver's pointer to TR tail */ 7501b493e30SGolan Ben Ami rxq->tr_tail = dma_zalloc_coherent(dev, sizeof(__le16), 7511b493e30SGolan Ben Ami &rxq->tr_tail_dma, 7521b493e30SGolan Ben Ami GFP_KERNEL); 7531b493e30SGolan Ben Ami if (!rxq->tr_tail) 7541b493e30SGolan Ben Ami goto err; 7551b493e30SGolan Ben Ami 7561b493e30SGolan Ben Ami /* Allocate the driver's pointer to CR tail */ 7571b493e30SGolan Ben Ami rxq->cr_tail = dma_zalloc_coherent(dev, sizeof(__le16), 7581b493e30SGolan Ben Ami &rxq->cr_tail_dma, 7591b493e30SGolan Ben Ami GFP_KERNEL); 7601b493e30SGolan Ben Ami if (!rxq->cr_tail) 7611b493e30SGolan Ben Ami goto err; 7620307c839SGolan Ben Ami /* 7630307c839SGolan Ben Ami * W/A 22560 device step Z0 must be non zero bug 7640307c839SGolan Ben Ami * TODO: remove this when stop supporting Z0 7650307c839SGolan Ben Ami */ 7660307c839SGolan Ben Ami *rxq->cr_tail = cpu_to_le16(500); 7671b493e30SGolan Ben Ami 768e705c121SKalle Valo return 0; 769e705c121SKalle Valo 77078485054SSara Sharon err: 77178485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 77278485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 77378485054SSara Sharon 7741b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 77578485054SSara Sharon } 77678485054SSara Sharon kfree(trans_pcie->rxq); 77796a6497bSSara Sharon 778e705c121SKalle Valo return -ENOMEM; 779e705c121SKalle Valo } 780e705c121SKalle Valo 7811b493e30SGolan Ben Ami static int iwl_pcie_rx_alloc(struct iwl_trans *trans) 7821b493e30SGolan Ben Ami { 7831b493e30SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 7841b493e30SGolan Ben Ami struct iwl_rb_allocator *rba = &trans_pcie->rba; 7851b493e30SGolan Ben Ami int i, ret; 7861b493e30SGolan Ben Ami 7871b493e30SGolan Ben Ami if (WARN_ON(trans_pcie->rxq)) 7881b493e30SGolan Ben Ami return -EINVAL; 7891b493e30SGolan Ben Ami 7901b493e30SGolan Ben Ami trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq), 7911b493e30SGolan Ben Ami GFP_KERNEL); 7921b493e30SGolan Ben Ami if (!trans_pcie->rxq) 7931b493e30SGolan Ben Ami return -EINVAL; 7941b493e30SGolan Ben Ami 7951b493e30SGolan Ben Ami spin_lock_init(&rba->lock); 7961b493e30SGolan Ben Ami 7971b493e30SGolan Ben Ami for (i = 0; i < trans->num_rx_queues; i++) { 7981b493e30SGolan Ben Ami struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 7991b493e30SGolan Ben Ami 8001b493e30SGolan Ben Ami ret = iwl_pcie_alloc_rxq_dma(trans, rxq); 8011b493e30SGolan Ben Ami if (ret) 8021b493e30SGolan Ben Ami return ret; 8031b493e30SGolan Ben Ami } 8041b493e30SGolan Ben Ami return 0; 8051b493e30SGolan Ben Ami } 8061b493e30SGolan Ben Ami 807e705c121SKalle Valo static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq) 808e705c121SKalle Valo { 809e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 810e705c121SKalle Valo u32 rb_size; 811dfcfeef9SSara Sharon unsigned long flags; 812e705c121SKalle Valo const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 813e705c121SKalle Valo 8146c4fbcbcSEmmanuel Grumbach switch (trans_pcie->rx_buf_size) { 8156c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 816e705c121SKalle Valo rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8176c4fbcbcSEmmanuel Grumbach break; 8186c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 8196c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 8206c4fbcbcSEmmanuel Grumbach break; 8216c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 8226c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K; 8236c4fbcbcSEmmanuel Grumbach break; 8246c4fbcbcSEmmanuel Grumbach default: 8256c4fbcbcSEmmanuel Grumbach WARN_ON(1); 8266c4fbcbcSEmmanuel Grumbach rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 8276c4fbcbcSEmmanuel Grumbach } 828e705c121SKalle Valo 829dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 830dfcfeef9SSara Sharon return; 831dfcfeef9SSara Sharon 832e705c121SKalle Valo /* Stop Rx DMA */ 833dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 834e705c121SKalle Valo /* reset and flush pointers */ 835dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 836dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 837dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0); 838e705c121SKalle Valo 839e705c121SKalle Valo /* Reset driver's Rx queue write index */ 840dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 841e705c121SKalle Valo 842e705c121SKalle Valo /* Tell device where to find RBD circular buffer in DRAM */ 843dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 844e705c121SKalle Valo (u32)(rxq->bd_dma >> 8)); 845e705c121SKalle Valo 846e705c121SKalle Valo /* Tell device where in DRAM to update its Rx status */ 847dfcfeef9SSara Sharon iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, 848e705c121SKalle Valo rxq->rb_stts_dma >> 4); 849e705c121SKalle Valo 850e705c121SKalle Valo /* Enable Rx DMA 851e705c121SKalle Valo * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 852e705c121SKalle Valo * the credit mechanism in 5000 HW RX FIFO 853e705c121SKalle Valo * Direct rx interrupts to hosts 8546c4fbcbcSEmmanuel Grumbach * Rx buffer size 4 or 8k or 12k 855e705c121SKalle Valo * RB timeout 0x10 856e705c121SKalle Valo * 256 RBDs 857e705c121SKalle Valo */ 858dfcfeef9SSara Sharon iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 859e705c121SKalle Valo FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 860e705c121SKalle Valo FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 861e705c121SKalle Valo FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 862e705c121SKalle Valo rb_size | 863e705c121SKalle Valo (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 864e705c121SKalle Valo (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 865e705c121SKalle Valo 866dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 867dfcfeef9SSara Sharon 868e705c121SKalle Valo /* Set interrupt coalescing timer to default (2048 usecs) */ 869e705c121SKalle Valo iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 870e705c121SKalle Valo 871e705c121SKalle Valo /* W/A for interrupt coalescing bug in 7260 and 3160 */ 872e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) 873e705c121SKalle Valo iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE); 874e705c121SKalle Valo } 875e705c121SKalle Valo 8761316d595SSara Sharon void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable) 8771316d595SSara Sharon { 878565291c6SJohannes Berg if (trans->cfg->device_family != IWL_DEVICE_FAMILY_9000) 879565291c6SJohannes Berg return; 880565291c6SJohannes Berg 881565291c6SJohannes Berg if (CSR_HW_REV_STEP(trans->hw_rev) != SILICON_A_STEP) 882565291c6SJohannes Berg return; 883565291c6SJohannes Berg 884565291c6SJohannes Berg if (!trans->cfg->integrated) 885565291c6SJohannes Berg return; 886565291c6SJohannes Berg 8871316d595SSara Sharon /* 8881316d595SSara Sharon * Turn on the chicken-bits that cause MAC wakeup for RX-related 8891316d595SSara Sharon * values. 8901316d595SSara Sharon * This costs some power, but needed for W/A 9000 integrated A-step 8911316d595SSara Sharon * bug where shadow registers are not in the retention list and their 8921316d595SSara Sharon * value is lost when NIC powers down 8931316d595SSara Sharon */ 8941316d595SSara Sharon iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 8951316d595SSara Sharon CSR_MAC_SHADOW_REG_CTRL_RX_WAKE); 8961316d595SSara Sharon iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTL2, 8971316d595SSara Sharon CSR_MAC_SHADOW_REG_CTL2_RX_WAKE); 8981316d595SSara Sharon } 8991316d595SSara Sharon 900bce97731SSara Sharon static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 90196a6497bSSara Sharon { 90296a6497bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 90396a6497bSSara Sharon u32 rb_size, enabled = 0; 904dfcfeef9SSara Sharon unsigned long flags; 90596a6497bSSara Sharon int i; 90696a6497bSSara Sharon 90796a6497bSSara Sharon switch (trans_pcie->rx_buf_size) { 9081a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 9091a4968d1SGolan Ben Ami rb_size = RFH_RXF_DMA_RB_SIZE_2K; 9101a4968d1SGolan Ben Ami break; 91196a6497bSSara Sharon case IWL_AMSDU_4K: 91296a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 91396a6497bSSara Sharon break; 91496a6497bSSara Sharon case IWL_AMSDU_8K: 91596a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_8K; 91696a6497bSSara Sharon break; 91796a6497bSSara Sharon case IWL_AMSDU_12K: 91896a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_12K; 91996a6497bSSara Sharon break; 92096a6497bSSara Sharon default: 92196a6497bSSara Sharon WARN_ON(1); 92296a6497bSSara Sharon rb_size = RFH_RXF_DMA_RB_SIZE_4K; 92396a6497bSSara Sharon } 92496a6497bSSara Sharon 925dfcfeef9SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 926dfcfeef9SSara Sharon return; 927dfcfeef9SSara Sharon 92896a6497bSSara Sharon /* Stop Rx DMA */ 929dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0); 93096a6497bSSara Sharon /* disable free amd used rx queue operation */ 931dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0); 93296a6497bSSara Sharon 93396a6497bSSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 93496a6497bSSara Sharon /* Tell device where to find RBD free table in DRAM */ 93512a17458SSara Sharon iwl_write_prph64_no_grab(trans, 936dfcfeef9SSara Sharon RFH_Q_FRBDCB_BA_LSB(i), 937dfcfeef9SSara Sharon trans_pcie->rxq[i].bd_dma); 93896a6497bSSara Sharon /* Tell device where to find RBD used table in DRAM */ 93912a17458SSara Sharon iwl_write_prph64_no_grab(trans, 940dfcfeef9SSara Sharon RFH_Q_URBDCB_BA_LSB(i), 941dfcfeef9SSara Sharon trans_pcie->rxq[i].used_bd_dma); 94296a6497bSSara Sharon /* Tell device where in DRAM to update its Rx status */ 94312a17458SSara Sharon iwl_write_prph64_no_grab(trans, 944dfcfeef9SSara Sharon RFH_Q_URBD_STTS_WPTR_LSB(i), 945bce97731SSara Sharon trans_pcie->rxq[i].rb_stts_dma); 94696a6497bSSara Sharon /* Reset device indice tables */ 947dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0); 948dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0); 949dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0); 95096a6497bSSara Sharon 95196a6497bSSara Sharon enabled |= BIT(i) | BIT(i + 16); 95296a6497bSSara Sharon } 95396a6497bSSara Sharon 95496a6497bSSara Sharon /* 95596a6497bSSara Sharon * Enable Rx DMA 95696a6497bSSara Sharon * Rx buffer size 4 or 8k or 12k 95796a6497bSSara Sharon * Min RB size 4 or 8 95888076015SSara Sharon * Drop frames that exceed RB size 95996a6497bSSara Sharon * 512 RBDs 96096a6497bSSara Sharon */ 961dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 96263044335SSara Sharon RFH_DMA_EN_ENABLE_VAL | rb_size | 96396a6497bSSara Sharon RFH_RXF_DMA_MIN_RB_4_8 | 96488076015SSara Sharon RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 96596a6497bSSara Sharon RFH_RXF_DMA_RBDCB_SIZE_512); 96696a6497bSSara Sharon 96788076015SSara Sharon /* 96888076015SSara Sharon * Activate DMA snooping. 969b0262f07SSara Sharon * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe 97088076015SSara Sharon * Default queue is 0 97188076015SSara Sharon */ 972f3779f47SJohannes Berg iwl_write_prph_no_grab(trans, RFH_GEN_CFG, 973f3779f47SJohannes Berg RFH_GEN_CFG_RFH_DMA_SNOOP | 974f3779f47SJohannes Berg RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) | 975b0262f07SSara Sharon RFH_GEN_CFG_SERVICE_DMA_SNOOP | 976f3779f47SJohannes Berg RFH_GEN_CFG_VAL(RB_CHUNK_SIZE, 977f3779f47SJohannes Berg trans->cfg->integrated ? 978b0262f07SSara Sharon RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 979f3779f47SJohannes Berg RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 98088076015SSara Sharon /* Enable the relevant rx queues */ 981dfcfeef9SSara Sharon iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled); 982dfcfeef9SSara Sharon 983dfcfeef9SSara Sharon iwl_trans_release_nic_access(trans, &flags); 98496a6497bSSara Sharon 98596a6497bSSara Sharon /* Set interrupt coalescing timer to default (2048 usecs) */ 98696a6497bSSara Sharon iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 9871316d595SSara Sharon 9881316d595SSara Sharon iwl_pcie_enable_rx_wake(trans, true); 98996a6497bSSara Sharon } 99096a6497bSSara Sharon 991e705c121SKalle Valo static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq) 992e705c121SKalle Valo { 993e705c121SKalle Valo lockdep_assert_held(&rxq->lock); 994e705c121SKalle Valo 995e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_free); 996e705c121SKalle Valo INIT_LIST_HEAD(&rxq->rx_used); 997e705c121SKalle Valo rxq->free_count = 0; 998e705c121SKalle Valo rxq->used_count = 0; 999e705c121SKalle Valo } 1000e705c121SKalle Valo 1001bce97731SSara Sharon static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) 1002bce97731SSara Sharon { 1003bce97731SSara Sharon WARN_ON(1); 1004bce97731SSara Sharon return 0; 1005bce97731SSara Sharon } 1006bce97731SSara Sharon 1007eda50cdeSSara Sharon static int _iwl_pcie_rx_init(struct iwl_trans *trans) 1008e705c121SKalle Valo { 1009e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 101078485054SSara Sharon struct iwl_rxq *def_rxq; 1011e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 10127b542436SSara Sharon int i, err, queue_size, allocator_pool_size, num_alloc; 1013e705c121SKalle Valo 101478485054SSara Sharon if (!trans_pcie->rxq) { 1015e705c121SKalle Valo err = iwl_pcie_rx_alloc(trans); 1016e705c121SKalle Valo if (err) 1017e705c121SKalle Valo return err; 1018e705c121SKalle Valo } 101978485054SSara Sharon def_rxq = trans_pcie->rxq; 1020e705c121SKalle Valo 10210f22e400SShaul Triebitz cancel_work_sync(&rba->rx_alloc); 10220f22e400SShaul Triebitz 1023e705c121SKalle Valo spin_lock(&rba->lock); 1024e705c121SKalle Valo atomic_set(&rba->req_pending, 0); 1025e705c121SKalle Valo atomic_set(&rba->req_ready, 0); 102696a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_allocated); 102796a6497bSSara Sharon INIT_LIST_HEAD(&rba->rbd_empty); 1028e705c121SKalle Valo spin_unlock(&rba->lock); 1029e705c121SKalle Valo 1030e705c121SKalle Valo /* free all first - we might be reconfigured for a different size */ 103178485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1032e705c121SKalle Valo 1033e705c121SKalle Valo for (i = 0; i < RX_QUEUE_SIZE; i++) 103478485054SSara Sharon def_rxq->queue[i] = NULL; 1035e705c121SKalle Valo 103678485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 103778485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 1038e705c121SKalle Valo 103996a6497bSSara Sharon rxq->id = i; 104096a6497bSSara Sharon 1041e705c121SKalle Valo spin_lock(&rxq->lock); 104278485054SSara Sharon /* 104378485054SSara Sharon * Set read write pointer to reflect that we have processed 104478485054SSara Sharon * and used all buffers, but have not restocked the Rx queue 104578485054SSara Sharon * with fresh buffers 104678485054SSara Sharon */ 104778485054SSara Sharon rxq->read = 0; 104878485054SSara Sharon rxq->write = 0; 104978485054SSara Sharon rxq->write_actual = 0; 10500307c839SGolan Ben Ami memset(rxq->rb_stts, 0, 10510307c839SGolan Ben Ami (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ? 10520307c839SGolan Ben Ami sizeof(__le16) : sizeof(struct iwl_rb_status)); 105378485054SSara Sharon 105478485054SSara Sharon iwl_pcie_rx_init_rxb_lists(rxq); 105578485054SSara Sharon 1056bce97731SSara Sharon if (!rxq->napi.poll) 1057bce97731SSara Sharon netif_napi_add(&trans_pcie->napi_dev, &rxq->napi, 1058bce97731SSara Sharon iwl_pcie_dummy_napi_poll, 64); 1059bce97731SSara Sharon 1060e705c121SKalle Valo spin_unlock(&rxq->lock); 106178485054SSara Sharon } 106278485054SSara Sharon 106396a6497bSSara Sharon /* move the pool to the default queue and allocator ownerships */ 10647b542436SSara Sharon queue_size = trans->cfg->mq_rx_supported ? 10657b542436SSara Sharon MQ_RX_NUM_RBDS : RX_QUEUE_SIZE; 106696a6497bSSara Sharon allocator_pool_size = trans->num_rx_queues * 106796a6497bSSara Sharon (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC); 10687b542436SSara Sharon num_alloc = queue_size + allocator_pool_size; 106943146925SSara Sharon BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) != 107043146925SSara Sharon ARRAY_SIZE(trans_pcie->rx_pool)); 10717b542436SSara Sharon for (i = 0; i < num_alloc; i++) { 107296a6497bSSara Sharon struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i]; 107396a6497bSSara Sharon 107496a6497bSSara Sharon if (i < allocator_pool_size) 107596a6497bSSara Sharon list_add(&rxb->list, &rba->rbd_empty); 107696a6497bSSara Sharon else 107796a6497bSSara Sharon list_add(&rxb->list, &def_rxq->rx_used); 107896a6497bSSara Sharon trans_pcie->global_table[i] = rxb; 1079e25d65f2SSara Sharon rxb->vid = (u16)(i + 1); 1080b1753c62SSara Sharon rxb->invalid = true; 108196a6497bSSara Sharon } 108278485054SSara Sharon 108378485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq); 10842047fa54SSara Sharon 1085eda50cdeSSara Sharon return 0; 1086eda50cdeSSara Sharon } 1087eda50cdeSSara Sharon 1088eda50cdeSSara Sharon int iwl_pcie_rx_init(struct iwl_trans *trans) 1089eda50cdeSSara Sharon { 1090eda50cdeSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1091eda50cdeSSara Sharon int ret = _iwl_pcie_rx_init(trans); 1092eda50cdeSSara Sharon 1093eda50cdeSSara Sharon if (ret) 1094eda50cdeSSara Sharon return ret; 1095eda50cdeSSara Sharon 10962047fa54SSara Sharon if (trans->cfg->mq_rx_supported) 1097bce97731SSara Sharon iwl_pcie_rx_mq_hw_init(trans); 10982047fa54SSara Sharon else 1099eda50cdeSSara Sharon iwl_pcie_rx_hw_init(trans, trans_pcie->rxq); 11002047fa54SSara Sharon 1101eda50cdeSSara Sharon iwl_pcie_rxq_restock(trans, trans_pcie->rxq); 110278485054SSara Sharon 1103eda50cdeSSara Sharon spin_lock(&trans_pcie->rxq->lock); 1104eda50cdeSSara Sharon iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq); 1105eda50cdeSSara Sharon spin_unlock(&trans_pcie->rxq->lock); 1106e705c121SKalle Valo 1107e705c121SKalle Valo return 0; 1108e705c121SKalle Valo } 1109e705c121SKalle Valo 1110eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans) 1111eda50cdeSSara Sharon { 1112eda50cdeSSara Sharon /* 1113eda50cdeSSara Sharon * We don't configure the RFH. 1114eda50cdeSSara Sharon * Restock will be done at alive, after firmware configured the RFH. 1115eda50cdeSSara Sharon */ 1116eda50cdeSSara Sharon return _iwl_pcie_rx_init(trans); 1117eda50cdeSSara Sharon } 1118eda50cdeSSara Sharon 1119e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans) 1120e705c121SKalle Valo { 1121e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1122e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 112378485054SSara Sharon int i; 1124e705c121SKalle Valo 112578485054SSara Sharon /* 112678485054SSara Sharon * if rxq is NULL, it means that nothing has been allocated, 112778485054SSara Sharon * exit now 112878485054SSara Sharon */ 112978485054SSara Sharon if (!trans_pcie->rxq) { 1130e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); 1131e705c121SKalle Valo return; 1132e705c121SKalle Valo } 1133e705c121SKalle Valo 1134e705c121SKalle Valo cancel_work_sync(&rba->rx_alloc); 1135e705c121SKalle Valo 113678485054SSara Sharon iwl_pcie_free_rbs_pool(trans); 1137e705c121SKalle Valo 113878485054SSara Sharon for (i = 0; i < trans->num_rx_queues; i++) { 113978485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 114078485054SSara Sharon 11411b493e30SGolan Ben Ami iwl_pcie_free_rxq_dma(trans, rxq); 1142bce97731SSara Sharon 1143bce97731SSara Sharon if (rxq->napi.poll) 1144bce97731SSara Sharon netif_napi_del(&rxq->napi); 114596a6497bSSara Sharon } 114678485054SSara Sharon kfree(trans_pcie->rxq); 1147e705c121SKalle Valo } 1148e705c121SKalle Valo 1149e705c121SKalle Valo /* 1150e705c121SKalle Valo * iwl_pcie_rx_reuse_rbd - Recycle used RBDs 1151e705c121SKalle Valo * 1152e705c121SKalle Valo * Called when a RBD can be reused. The RBD is transferred to the allocator. 1153e705c121SKalle Valo * When there are 2 empty RBDs - a request for allocation is posted 1154e705c121SKalle Valo */ 1155e705c121SKalle Valo static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans, 1156e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 1157e705c121SKalle Valo struct iwl_rxq *rxq, bool emergency) 1158e705c121SKalle Valo { 1159e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1160e705c121SKalle Valo struct iwl_rb_allocator *rba = &trans_pcie->rba; 1161e705c121SKalle Valo 1162e705c121SKalle Valo /* Move the RBD to the used list, will be moved to allocator in batches 1163e705c121SKalle Valo * before claiming or posting a request*/ 1164e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_used); 1165e705c121SKalle Valo 1166e705c121SKalle Valo if (unlikely(emergency)) 1167e705c121SKalle Valo return; 1168e705c121SKalle Valo 1169e705c121SKalle Valo /* Count the allocator owned RBDs */ 1170e705c121SKalle Valo rxq->used_count++; 1171e705c121SKalle Valo 1172e705c121SKalle Valo /* If we have RX_POST_REQ_ALLOC new released rx buffers - 1173e705c121SKalle Valo * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is 1174e705c121SKalle Valo * used for the case we failed to claim RX_CLAIM_REQ_ALLOC, 1175e705c121SKalle Valo * after but we still need to post another request. 1176e705c121SKalle Valo */ 1177e705c121SKalle Valo if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) { 1178e705c121SKalle Valo /* Move the 2 RBDs to the allocator ownership. 1179e705c121SKalle Valo Allocator has another 6 from pool for the request completion*/ 1180e705c121SKalle Valo spin_lock(&rba->lock); 1181e705c121SKalle Valo list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1182e705c121SKalle Valo spin_unlock(&rba->lock); 1183e705c121SKalle Valo 1184e705c121SKalle Valo atomic_inc(&rba->req_pending); 1185e705c121SKalle Valo queue_work(rba->alloc_wq, &rba->rx_alloc); 1186e705c121SKalle Valo } 1187e705c121SKalle Valo } 1188e705c121SKalle Valo 1189e705c121SKalle Valo static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans, 119078485054SSara Sharon struct iwl_rxq *rxq, 1191e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb, 1192e705c121SKalle Valo bool emergency) 1193e705c121SKalle Valo { 1194e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1195b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1196e705c121SKalle Valo bool page_stolen = false; 1197e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 1198e705c121SKalle Valo u32 offset = 0; 1199e705c121SKalle Valo 1200e705c121SKalle Valo if (WARN_ON(!rxb)) 1201e705c121SKalle Valo return; 1202e705c121SKalle Valo 1203e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE); 1204e705c121SKalle Valo 1205e705c121SKalle Valo while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) { 1206e705c121SKalle Valo struct iwl_rx_packet *pkt; 1207e705c121SKalle Valo u16 sequence; 1208e705c121SKalle Valo bool reclaim; 1209e705c121SKalle Valo int index, cmd_index, len; 1210e705c121SKalle Valo struct iwl_rx_cmd_buffer rxcb = { 1211e705c121SKalle Valo ._offset = offset, 1212e705c121SKalle Valo ._rx_page_order = trans_pcie->rx_page_order, 1213e705c121SKalle Valo ._page = rxb->page, 1214e705c121SKalle Valo ._page_stolen = false, 1215e705c121SKalle Valo .truesize = max_len, 1216e705c121SKalle Valo }; 1217e705c121SKalle Valo 1218e705c121SKalle Valo pkt = rxb_addr(&rxcb); 1219e705c121SKalle Valo 12203bfdee76SJohannes Berg if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) { 12213bfdee76SJohannes Berg IWL_DEBUG_RX(trans, 12223bfdee76SJohannes Berg "Q %d: RB end marker at offset %d\n", 12233bfdee76SJohannes Berg rxq->id, offset); 1224e705c121SKalle Valo break; 12253bfdee76SJohannes Berg } 1226e705c121SKalle Valo 1227a395058eSJohannes Berg WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1228a395058eSJohannes Berg FH_RSCSR_RXQ_POS != rxq->id, 1229a395058eSJohannes Berg "frame on invalid queue - is on %d and indicates %d\n", 1230a395058eSJohannes Berg rxq->id, 1231a395058eSJohannes Berg (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >> 1232a395058eSJohannes Berg FH_RSCSR_RXQ_POS); 1233ab2e696bSSara Sharon 1234e705c121SKalle Valo IWL_DEBUG_RX(trans, 12353bfdee76SJohannes Berg "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n", 12363bfdee76SJohannes Berg rxq->id, offset, 123739bdb17eSSharon Dvir iwl_get_cmd_string(trans, 123839bdb17eSSharon Dvir iwl_cmd_id(pkt->hdr.cmd, 123939bdb17eSSharon Dvir pkt->hdr.group_id, 124039bdb17eSSharon Dvir 0)), 124135177c99SSara Sharon pkt->hdr.group_id, pkt->hdr.cmd, 124235177c99SSara Sharon le16_to_cpu(pkt->hdr.sequence)); 1243e705c121SKalle Valo 1244e705c121SKalle Valo len = iwl_rx_packet_len(pkt); 1245e705c121SKalle Valo len += sizeof(u32); /* account for status word */ 1246e705c121SKalle Valo trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len); 1247e705c121SKalle Valo trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len); 1248e705c121SKalle Valo 1249e705c121SKalle Valo /* Reclaim a command buffer only if this packet is a response 1250e705c121SKalle Valo * to a (driver-originated) command. 1251e705c121SKalle Valo * If the packet (e.g. Rx frame) originated from uCode, 1252e705c121SKalle Valo * there is no command buffer to reclaim. 1253e705c121SKalle Valo * Ucode should set SEQ_RX_FRAME bit if ucode-originated, 1254e705c121SKalle Valo * but apparently a few don't get set; catch them here. */ 1255e705c121SKalle Valo reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME); 1256d8a130b0SJohannes Berg if (reclaim && !pkt->hdr.group_id) { 1257e705c121SKalle Valo int i; 1258e705c121SKalle Valo 1259e705c121SKalle Valo for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) { 1260e705c121SKalle Valo if (trans_pcie->no_reclaim_cmds[i] == 1261e705c121SKalle Valo pkt->hdr.cmd) { 1262e705c121SKalle Valo reclaim = false; 1263e705c121SKalle Valo break; 1264e705c121SKalle Valo } 1265e705c121SKalle Valo } 1266e705c121SKalle Valo } 1267e705c121SKalle Valo 1268e705c121SKalle Valo sequence = le16_to_cpu(pkt->hdr.sequence); 1269e705c121SKalle Valo index = SEQ_TO_INDEX(sequence); 12704ecab561SEmmanuel Grumbach cmd_index = iwl_pcie_get_cmd_index(txq, index); 1271e705c121SKalle Valo 1272bce97731SSara Sharon if (rxq->id == 0) 1273bce97731SSara Sharon iwl_op_mode_rx(trans->op_mode, &rxq->napi, 1274bce97731SSara Sharon &rxcb); 1275bce97731SSara Sharon else 1276bce97731SSara Sharon iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi, 1277bce97731SSara Sharon &rxcb, rxq->id); 1278e705c121SKalle Valo 1279e705c121SKalle Valo if (reclaim) { 1280e705c121SKalle Valo kzfree(txq->entries[cmd_index].free_buf); 1281e705c121SKalle Valo txq->entries[cmd_index].free_buf = NULL; 1282e705c121SKalle Valo } 1283e705c121SKalle Valo 1284e705c121SKalle Valo /* 1285e705c121SKalle Valo * After here, we should always check rxcb._page_stolen, 1286e705c121SKalle Valo * if it is true then one of the handlers took the page. 1287e705c121SKalle Valo */ 1288e705c121SKalle Valo 1289e705c121SKalle Valo if (reclaim) { 1290e705c121SKalle Valo /* Invoke any callbacks, transfer the buffer to caller, 1291e705c121SKalle Valo * and fire off the (possibly) blocking 1292e705c121SKalle Valo * iwl_trans_send_cmd() 1293e705c121SKalle Valo * as we reclaim the driver command queue */ 1294e705c121SKalle Valo if (!rxcb._page_stolen) 1295e705c121SKalle Valo iwl_pcie_hcmd_complete(trans, &rxcb); 1296e705c121SKalle Valo else 1297e705c121SKalle Valo IWL_WARN(trans, "Claim null rxb?\n"); 1298e705c121SKalle Valo } 1299e705c121SKalle Valo 1300e705c121SKalle Valo page_stolen |= rxcb._page_stolen; 13010307c839SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 13020307c839SGolan Ben Ami break; 1303e705c121SKalle Valo offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN); 1304e705c121SKalle Valo } 1305e705c121SKalle Valo 1306e705c121SKalle Valo /* page was stolen from us -- free our reference */ 1307e705c121SKalle Valo if (page_stolen) { 1308e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1309e705c121SKalle Valo rxb->page = NULL; 1310e705c121SKalle Valo } 1311e705c121SKalle Valo 1312e705c121SKalle Valo /* Reuse the page if possible. For notification packets and 1313e705c121SKalle Valo * SKBs that fail to Rx correctly, add them back into the 1314e705c121SKalle Valo * rx_free list for reuse later. */ 1315e705c121SKalle Valo if (rxb->page != NULL) { 1316e705c121SKalle Valo rxb->page_dma = 1317e705c121SKalle Valo dma_map_page(trans->dev, rxb->page, 0, 1318e705c121SKalle Valo PAGE_SIZE << trans_pcie->rx_page_order, 1319e705c121SKalle Valo DMA_FROM_DEVICE); 1320e705c121SKalle Valo if (dma_mapping_error(trans->dev, rxb->page_dma)) { 1321e705c121SKalle Valo /* 1322e705c121SKalle Valo * free the page(s) as well to not break 1323e705c121SKalle Valo * the invariant that the items on the used 1324e705c121SKalle Valo * list have no page(s) 1325e705c121SKalle Valo */ 1326e705c121SKalle Valo __free_pages(rxb->page, trans_pcie->rx_page_order); 1327e705c121SKalle Valo rxb->page = NULL; 1328e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1329e705c121SKalle Valo } else { 1330e705c121SKalle Valo list_add_tail(&rxb->list, &rxq->rx_free); 1331e705c121SKalle Valo rxq->free_count++; 1332e705c121SKalle Valo } 1333e705c121SKalle Valo } else 1334e705c121SKalle Valo iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency); 1335e705c121SKalle Valo } 1336e705c121SKalle Valo 1337e705c121SKalle Valo /* 1338e705c121SKalle Valo * iwl_pcie_rx_handle - Main entry function for receiving responses from fw 1339e705c121SKalle Valo */ 13402e5d4a8fSHaim Dreyfuss static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue) 1341e705c121SKalle Valo { 1342e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13432e5d4a8fSHaim Dreyfuss struct iwl_rxq *rxq = &trans_pcie->rxq[queue]; 1344d56daea4SSara Sharon u32 r, i, count = 0; 1345e705c121SKalle Valo bool emergency = false; 1346e705c121SKalle Valo 1347e705c121SKalle Valo restart: 1348e705c121SKalle Valo spin_lock(&rxq->lock); 1349e705c121SKalle Valo /* uCode's read index (stored in shared DRAM) indicates the last Rx 1350e705c121SKalle Valo * buffer that the driver may process (last buffer filled by ucode). */ 13510307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 1352e705c121SKalle Valo i = rxq->read; 1353e705c121SKalle Valo 13545eae443eSSara Sharon /* W/A 9000 device step A0 wrap-around bug */ 13555eae443eSSara Sharon r &= (rxq->queue_size - 1); 13565eae443eSSara Sharon 1357e705c121SKalle Valo /* Rx interrupt, but nothing sent from uCode */ 1358e705c121SKalle Valo if (i == r) 13595eae443eSSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r); 1360e705c121SKalle Valo 1361e705c121SKalle Valo while (i != r) { 1362e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb; 1363e705c121SKalle Valo 136496a6497bSSara Sharon if (unlikely(rxq->used_count == rxq->queue_size / 2)) 1365e705c121SKalle Valo emergency = true; 1366e705c121SKalle Valo 136796a6497bSSara Sharon if (trans->cfg->mq_rx_supported) { 13680307c839SGolan Ben Ami u16 vid; 136996a6497bSSara Sharon /* 13700307c839SGolan Ben Ami * used_bd is a 32/16 bit but only 12 are used 13710307c839SGolan Ben Ami * to retrieve the vid 137296a6497bSSara Sharon */ 13730307c839SGolan Ben Ami if (trans->cfg->device_family >= 13740307c839SGolan Ben Ami IWL_DEVICE_FAMILY_22560) { 13750307c839SGolan Ben Ami struct iwl_rx_completion_desc *rx_cd = 13760307c839SGolan Ben Ami &((struct iwl_rx_completion_desc *) 13770307c839SGolan Ben Ami rxq->used_bd)[i]; 13780307c839SGolan Ben Ami 13790307c839SGolan Ben Ami vid = le16_to_cpu(rx_cd->rbid) & 0x0FFF; 13800307c839SGolan Ben Ami } else { 13810307c839SGolan Ben Ami __le32 *used = 13820307c839SGolan Ben Ami &((__le32 *)rxq->used_bd)[i]; 13830307c839SGolan Ben Ami 13840307c839SGolan Ben Ami vid = le32_to_cpu(*used) & 0x0FFF; 13850307c839SGolan Ben Ami } 138696a6497bSSara Sharon 1387e25d65f2SSara Sharon if (WARN(!vid || 1388e25d65f2SSara Sharon vid > ARRAY_SIZE(trans_pcie->global_table), 1389e25d65f2SSara Sharon "Invalid rxb index from HW %u\n", (u32)vid)) { 1390e25d65f2SSara Sharon iwl_force_nmi(trans); 13915eae443eSSara Sharon goto out; 1392e25d65f2SSara Sharon } 1393e25d65f2SSara Sharon rxb = trans_pcie->global_table[vid - 1]; 1394b1753c62SSara Sharon if (WARN(rxb->invalid, 1395b1753c62SSara Sharon "Invalid rxb from HW %u\n", (u32)vid)) { 1396b1753c62SSara Sharon iwl_force_nmi(trans); 1397b1753c62SSara Sharon goto out; 1398b1753c62SSara Sharon } 13990307c839SGolan Ben Ami if (trans->cfg->device_family >= 14000307c839SGolan Ben Ami IWL_DEVICE_FAMILY_22560) { 14010307c839SGolan Ben Ami struct iwl_rx_completion_desc *rx_cd = 14020307c839SGolan Ben Ami &((struct iwl_rx_completion_desc *) 14030307c839SGolan Ben Ami rxq->used_bd)[i]; 14040307c839SGolan Ben Ami 14050307c839SGolan Ben Ami rxb->size = le32_to_cpu(rx_cd->size) & 14060307c839SGolan Ben Ami IWL_RX_CD_SIZE; 14070307c839SGolan Ben Ami } 14080307c839SGolan Ben Ami 1409b1753c62SSara Sharon rxb->invalid = true; 141096a6497bSSara Sharon } else { 1411e705c121SKalle Valo rxb = rxq->queue[i]; 1412e705c121SKalle Valo rxq->queue[i] = NULL; 141396a6497bSSara Sharon } 1414e705c121SKalle Valo 14155eae443eSSara Sharon IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i); 141678485054SSara Sharon iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency); 1417e705c121SKalle Valo 141896a6497bSSara Sharon i = (i + 1) & (rxq->queue_size - 1); 1419e705c121SKalle Valo 1420d56daea4SSara Sharon /* 1421d56daea4SSara Sharon * If we have RX_CLAIM_REQ_ALLOC released rx buffers - 1422d56daea4SSara Sharon * try to claim the pre-allocated buffers from the allocator. 1423d56daea4SSara Sharon * If not ready - will try to reclaim next time. 1424d56daea4SSara Sharon * There is no need to reschedule work - allocator exits only 1425d56daea4SSara Sharon * on success 1426e705c121SKalle Valo */ 1427d56daea4SSara Sharon if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) 1428d56daea4SSara Sharon iwl_pcie_rx_allocator_get(trans, rxq); 1429e705c121SKalle Valo 1430d56daea4SSara Sharon if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) { 1431d56daea4SSara Sharon struct iwl_rb_allocator *rba = &trans_pcie->rba; 1432d56daea4SSara Sharon 1433d56daea4SSara Sharon /* Add the remaining empty RBDs for allocator use */ 1434d56daea4SSara Sharon spin_lock(&rba->lock); 1435d56daea4SSara Sharon list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty); 1436d56daea4SSara Sharon spin_unlock(&rba->lock); 1437d56daea4SSara Sharon } else if (emergency) { 1438e705c121SKalle Valo count++; 1439e705c121SKalle Valo if (count == 8) { 1440e705c121SKalle Valo count = 0; 144196a6497bSSara Sharon if (rxq->used_count < rxq->queue_size / 3) 1442e705c121SKalle Valo emergency = false; 1443e0e168dcSGregory Greenman 1444e705c121SKalle Valo rxq->read = i; 1445e705c121SKalle Valo spin_unlock(&rxq->lock); 1446e0e168dcSGregory Greenman iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 144778485054SSara Sharon iwl_pcie_rxq_restock(trans, rxq); 1448e705c121SKalle Valo goto restart; 1449e705c121SKalle Valo } 1450e705c121SKalle Valo } 1451e0e168dcSGregory Greenman } 14525eae443eSSara Sharon out: 1453e705c121SKalle Valo /* Backtrack one entry */ 1454e705c121SKalle Valo rxq->read = i; 14550307c839SGolan Ben Ami /* update cr tail with the rxq read pointer */ 14560307c839SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 14570307c839SGolan Ben Ami *rxq->cr_tail = cpu_to_le16(r); 1458e705c121SKalle Valo spin_unlock(&rxq->lock); 1459e705c121SKalle Valo 1460e705c121SKalle Valo /* 1461e705c121SKalle Valo * handle a case where in emergency there are some unallocated RBDs. 1462e705c121SKalle Valo * those RBDs are in the used list, but are not tracked by the queue's 1463e705c121SKalle Valo * used_count which counts allocator owned RBDs. 1464e705c121SKalle Valo * unallocated emergency RBDs must be allocated on exit, otherwise 1465e705c121SKalle Valo * when called again the function may not be in emergency mode and 1466e705c121SKalle Valo * they will be handed to the allocator with no tracking in the RBD 1467e705c121SKalle Valo * allocator counters, which will lead to them never being claimed back 1468e705c121SKalle Valo * by the queue. 1469e705c121SKalle Valo * by allocating them here, they are now in the queue free list, and 1470e705c121SKalle Valo * will be restocked by the next call of iwl_pcie_rxq_restock. 1471e705c121SKalle Valo */ 1472e705c121SKalle Valo if (unlikely(emergency && count)) 147378485054SSara Sharon iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq); 1474e705c121SKalle Valo 1475bce97731SSara Sharon if (rxq->napi.poll) 1476bce97731SSara Sharon napi_gro_flush(&rxq->napi, false); 1477e0e168dcSGregory Greenman 1478e0e168dcSGregory Greenman iwl_pcie_rxq_restock(trans, rxq); 1479e705c121SKalle Valo } 1480e705c121SKalle Valo 14812e5d4a8fSHaim Dreyfuss static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry) 14822e5d4a8fSHaim Dreyfuss { 14832e5d4a8fSHaim Dreyfuss u8 queue = entry->entry; 14842e5d4a8fSHaim Dreyfuss struct msix_entry *entries = entry - queue; 14852e5d4a8fSHaim Dreyfuss 14862e5d4a8fSHaim Dreyfuss return container_of(entries, struct iwl_trans_pcie, msix_entries[0]); 14872e5d4a8fSHaim Dreyfuss } 14882e5d4a8fSHaim Dreyfuss 14892e5d4a8fSHaim Dreyfuss static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 14902e5d4a8fSHaim Dreyfuss struct msix_entry *entry) 14912e5d4a8fSHaim Dreyfuss { 14922e5d4a8fSHaim Dreyfuss /* 14932e5d4a8fSHaim Dreyfuss * Before sending the interrupt the HW disables it to prevent 14942e5d4a8fSHaim Dreyfuss * a nested interrupt. This is done by writing 1 to the corresponding 14952e5d4a8fSHaim Dreyfuss * bit in the mask register. After handling the interrupt, it should be 14962e5d4a8fSHaim Dreyfuss * re-enabled by clearing this bit. This register is defined as 14972e5d4a8fSHaim Dreyfuss * write 1 clear (W1C) register, meaning that it's being clear 14982e5d4a8fSHaim Dreyfuss * by writing 1 to the bit. 14992e5d4a8fSHaim Dreyfuss */ 15007ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 15012e5d4a8fSHaim Dreyfuss } 15022e5d4a8fSHaim Dreyfuss 15032e5d4a8fSHaim Dreyfuss /* 15042e5d4a8fSHaim Dreyfuss * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw 15052e5d4a8fSHaim Dreyfuss * This interrupt handler should be used with RSS queue only. 15062e5d4a8fSHaim Dreyfuss */ 15072e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id) 15082e5d4a8fSHaim Dreyfuss { 15092e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 15102e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 15112e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 15122e5d4a8fSHaim Dreyfuss 1513c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0); 1514c42ff65dSJohannes Berg 15155eae443eSSara Sharon if (WARN_ON(entry->entry >= trans->num_rx_queues)) 15165eae443eSSara Sharon return IRQ_NONE; 15175eae443eSSara Sharon 15182e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 15192e5d4a8fSHaim Dreyfuss 15202e5d4a8fSHaim Dreyfuss local_bh_disable(); 15212e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, entry->entry); 15222e5d4a8fSHaim Dreyfuss local_bh_enable(); 15232e5d4a8fSHaim Dreyfuss 15242e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 15252e5d4a8fSHaim Dreyfuss 15262e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 15272e5d4a8fSHaim Dreyfuss 15282e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 15292e5d4a8fSHaim Dreyfuss } 15302e5d4a8fSHaim Dreyfuss 1531e705c121SKalle Valo /* 1532e705c121SKalle Valo * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card 1533e705c121SKalle Valo */ 1534e705c121SKalle Valo static void iwl_pcie_irq_handle_error(struct iwl_trans *trans) 1535e705c121SKalle Valo { 1536e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1537e705c121SKalle Valo int i; 1538e705c121SKalle Valo 1539e705c121SKalle Valo /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 1540e705c121SKalle Valo if (trans->cfg->internal_wimax_coex && 1541e705c121SKalle Valo !trans->cfg->apmg_not_supported && 1542e705c121SKalle Valo (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & 1543e705c121SKalle Valo APMS_CLK_VAL_MRB_FUNC_MODE) || 1544e705c121SKalle Valo (iwl_read_prph(trans, APMG_PS_CTRL_REG) & 1545e705c121SKalle Valo APMG_PS_CTRL_VAL_RESET_REQ))) { 1546e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1547e705c121SKalle Valo iwl_op_mode_wimax_active(trans->op_mode); 1548e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1549e705c121SKalle Valo return; 1550e705c121SKalle Valo } 1551e705c121SKalle Valo 155213a3a390SSara Sharon for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 155313a3a390SSara Sharon if (!trans_pcie->txq[i]) 155413a3a390SSara Sharon continue; 1555b2a3b1c1SSara Sharon del_timer(&trans_pcie->txq[i]->stuck_timer); 155613a3a390SSara Sharon } 1557e705c121SKalle Valo 15587d75f32eSEmmanuel Grumbach /* The STATUS_FW_ERROR bit is set in this function. This must happen 15597d75f32eSEmmanuel Grumbach * before we wake up the command caller, to ensure a proper cleanup. */ 15607d75f32eSEmmanuel Grumbach iwl_trans_fw_error(trans); 15617d75f32eSEmmanuel Grumbach 1562e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1563e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1564e705c121SKalle Valo } 1565e705c121SKalle Valo 1566e705c121SKalle Valo static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans) 1567e705c121SKalle Valo { 1568e705c121SKalle Valo u32 inta; 1569e705c121SKalle Valo 1570e705c121SKalle Valo lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock); 1571e705c121SKalle Valo 1572e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1573e705c121SKalle Valo 1574e705c121SKalle Valo /* Discover which interrupts are active/pending */ 1575e705c121SKalle Valo inta = iwl_read32(trans, CSR_INT); 1576e705c121SKalle Valo 1577e705c121SKalle Valo /* the thread will service interrupts and re-enable them */ 1578e705c121SKalle Valo return inta; 1579e705c121SKalle Valo } 1580e705c121SKalle Valo 1581e705c121SKalle Valo /* a device (PCI-E) page is 4096 bytes long */ 1582e705c121SKalle Valo #define ICT_SHIFT 12 1583e705c121SKalle Valo #define ICT_SIZE (1 << ICT_SHIFT) 1584e705c121SKalle Valo #define ICT_COUNT (ICT_SIZE / sizeof(u32)) 1585e705c121SKalle Valo 1586e705c121SKalle Valo /* interrupt handler using ict table, with this interrupt driver will 1587e705c121SKalle Valo * stop using INTA register to get device's interrupt, reading this register 1588e705c121SKalle Valo * is expensive, device will write interrupts in ICT dram table, increment 1589e705c121SKalle Valo * index then will fire interrupt to driver, driver will OR all ICT table 1590e705c121SKalle Valo * entries from current index up to table entry with 0 value. the result is 1591e705c121SKalle Valo * the interrupt we need to service, driver will set the entries back to 0 and 1592e705c121SKalle Valo * set index. 1593e705c121SKalle Valo */ 1594e705c121SKalle Valo static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans) 1595e705c121SKalle Valo { 1596e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1597e705c121SKalle Valo u32 inta; 1598e705c121SKalle Valo u32 val = 0; 1599e705c121SKalle Valo u32 read; 1600e705c121SKalle Valo 1601e705c121SKalle Valo trace_iwlwifi_dev_irq(trans->dev); 1602e705c121SKalle Valo 1603e705c121SKalle Valo /* Ignore interrupt if there's nothing in NIC to service. 1604e705c121SKalle Valo * This may be due to IRQ shared with another device, 1605e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. */ 1606e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1607e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read); 1608e705c121SKalle Valo if (!read) 1609e705c121SKalle Valo return 0; 1610e705c121SKalle Valo 1611e705c121SKalle Valo /* 1612e705c121SKalle Valo * Collect all entries up to the first 0, starting from ict_index; 1613e705c121SKalle Valo * note we already read at ict_index. 1614e705c121SKalle Valo */ 1615e705c121SKalle Valo do { 1616e705c121SKalle Valo val |= read; 1617e705c121SKalle Valo IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", 1618e705c121SKalle Valo trans_pcie->ict_index, read); 1619e705c121SKalle Valo trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; 1620e705c121SKalle Valo trans_pcie->ict_index = 1621e705c121SKalle Valo ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1)); 1622e705c121SKalle Valo 1623e705c121SKalle Valo read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); 1624e705c121SKalle Valo trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, 1625e705c121SKalle Valo read); 1626e705c121SKalle Valo } while (read); 1627e705c121SKalle Valo 1628e705c121SKalle Valo /* We should not get this value, just ignore it. */ 1629e705c121SKalle Valo if (val == 0xffffffff) 1630e705c121SKalle Valo val = 0; 1631e705c121SKalle Valo 1632e705c121SKalle Valo /* 1633e705c121SKalle Valo * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit 1634e705c121SKalle Valo * (bit 15 before shifting it to 31) to clear when using interrupt 1635e705c121SKalle Valo * coalescing. fortunately, bits 18 and 19 stay set when this happens 1636e705c121SKalle Valo * so we use them to decide on the real state of the Rx bit. 1637e705c121SKalle Valo * In order words, bit 15 is set if bit 18 or bit 19 are set. 1638e705c121SKalle Valo */ 1639e705c121SKalle Valo if (val & 0xC0000) 1640e705c121SKalle Valo val |= 0x8000; 1641e705c121SKalle Valo 1642e705c121SKalle Valo inta = (0xff & val) | ((0xff00 & val) << 16); 1643e705c121SKalle Valo return inta; 1644e705c121SKalle Valo } 1645e705c121SKalle Valo 1646fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans) 16473a6e168bSJohannes Berg { 16483a6e168bSJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16493a6e168bSJohannes Berg struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1650326477e4SJohannes Berg bool hw_rfkill, prev, report; 16513a6e168bSJohannes Berg 16523a6e168bSJohannes Berg mutex_lock(&trans_pcie->mutex); 1653326477e4SJohannes Berg prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 16543a6e168bSJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1655326477e4SJohannes Berg if (hw_rfkill) { 1656326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1657326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1658326477e4SJohannes Berg } 1659326477e4SJohannes Berg if (trans_pcie->opmode_down) 1660326477e4SJohannes Berg report = hw_rfkill; 1661326477e4SJohannes Berg else 1662326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 16633a6e168bSJohannes Berg 16643a6e168bSJohannes Berg IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", 16653a6e168bSJohannes Berg hw_rfkill ? "disable radio" : "enable radio"); 16663a6e168bSJohannes Berg 16673a6e168bSJohannes Berg isr_stats->rfkill++; 16683a6e168bSJohannes Berg 1669326477e4SJohannes Berg if (prev != report) 1670326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 16713a6e168bSJohannes Berg mutex_unlock(&trans_pcie->mutex); 16723a6e168bSJohannes Berg 16733a6e168bSJohannes Berg if (hw_rfkill) { 16743a6e168bSJohannes Berg if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE, 16753a6e168bSJohannes Berg &trans->status)) 16763a6e168bSJohannes Berg IWL_DEBUG_RF_KILL(trans, 16773a6e168bSJohannes Berg "Rfkill while SYNC HCMD in flight\n"); 16783a6e168bSJohannes Berg wake_up(&trans_pcie->wait_command_queue); 16793a6e168bSJohannes Berg } else { 1680326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1681326477e4SJohannes Berg if (trans_pcie->opmode_down) 1682326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 16833a6e168bSJohannes Berg } 16843a6e168bSJohannes Berg } 16853a6e168bSJohannes Berg 1686e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id) 1687e705c121SKalle Valo { 1688e705c121SKalle Valo struct iwl_trans *trans = dev_id; 1689e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1690e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 1691e705c121SKalle Valo u32 inta = 0; 1692e705c121SKalle Valo u32 handled = 0; 1693e705c121SKalle Valo 1694e705c121SKalle Valo lock_map_acquire(&trans->sync_cmd_lockdep_map); 1695e705c121SKalle Valo 1696e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1697e705c121SKalle Valo 1698e705c121SKalle Valo /* dram interrupt table not set yet, 1699e705c121SKalle Valo * use legacy interrupt. 1700e705c121SKalle Valo */ 1701e705c121SKalle Valo if (likely(trans_pcie->use_ict)) 1702e705c121SKalle Valo inta = iwl_pcie_int_cause_ict(trans); 1703e705c121SKalle Valo else 1704e705c121SKalle Valo inta = iwl_pcie_int_cause_non_ict(trans); 1705e705c121SKalle Valo 1706e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1707e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1708e705c121SKalle Valo "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n", 1709e705c121SKalle Valo inta, trans_pcie->inta_mask, 1710e705c121SKalle Valo iwl_read32(trans, CSR_INT_MASK), 1711e705c121SKalle Valo iwl_read32(trans, CSR_FH_INT_STATUS)); 1712e705c121SKalle Valo if (inta & (~trans_pcie->inta_mask)) 1713e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1714e705c121SKalle Valo "We got a masked interrupt (0x%08x)\n", 1715e705c121SKalle Valo inta & (~trans_pcie->inta_mask)); 1716e705c121SKalle Valo } 1717e705c121SKalle Valo 1718e705c121SKalle Valo inta &= trans_pcie->inta_mask; 1719e705c121SKalle Valo 1720e705c121SKalle Valo /* 1721e705c121SKalle Valo * Ignore interrupt if there's nothing in NIC to service. 1722e705c121SKalle Valo * This may be due to IRQ shared with another device, 1723e705c121SKalle Valo * or due to sporadic interrupts thrown from our NIC. 1724e705c121SKalle Valo */ 1725e705c121SKalle Valo if (unlikely(!inta)) { 1726e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 1727e705c121SKalle Valo /* 1728e705c121SKalle Valo * Re-enable interrupts here since we don't 1729e705c121SKalle Valo * have anything to service 1730e705c121SKalle Valo */ 1731e705c121SKalle Valo if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1732f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 1733e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1734e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1735e705c121SKalle Valo return IRQ_NONE; 1736e705c121SKalle Valo } 1737e705c121SKalle Valo 1738e705c121SKalle Valo if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { 1739e705c121SKalle Valo /* 1740e705c121SKalle Valo * Hardware disappeared. It might have 1741e705c121SKalle Valo * already raised an interrupt. 1742e705c121SKalle Valo */ 1743e705c121SKalle Valo IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); 1744e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1745e705c121SKalle Valo goto out; 1746e705c121SKalle Valo } 1747e705c121SKalle Valo 1748e705c121SKalle Valo /* Ack/clear/reset pending uCode interrupts. 1749e705c121SKalle Valo * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 1750e705c121SKalle Valo */ 1751e705c121SKalle Valo /* There is a hardware bug in the interrupt mask function that some 1752e705c121SKalle Valo * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if 1753e705c121SKalle Valo * they are disabled in the CSR_INT_MASK register. Furthermore the 1754e705c121SKalle Valo * ICT interrupt handling mechanism has another bug that might cause 1755e705c121SKalle Valo * these unmasked interrupts fail to be detected. We workaround the 1756e705c121SKalle Valo * hardware bugs here by ACKing all the possible interrupts so that 1757e705c121SKalle Valo * interrupt coalescing can still be achieved. 1758e705c121SKalle Valo */ 1759e705c121SKalle Valo iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask); 1760e705c121SKalle Valo 1761e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) 1762e705c121SKalle Valo IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n", 1763e705c121SKalle Valo inta, iwl_read32(trans, CSR_INT_MASK)); 1764e705c121SKalle Valo 1765e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1766e705c121SKalle Valo 1767e705c121SKalle Valo /* Now service all interrupt bits discovered above. */ 1768e705c121SKalle Valo if (inta & CSR_INT_BIT_HW_ERR) { 1769e705c121SKalle Valo IWL_ERR(trans, "Hardware error detected. Restarting.\n"); 1770e705c121SKalle Valo 1771e705c121SKalle Valo /* Tell the device to stop sending interrupts */ 1772e705c121SKalle Valo iwl_disable_interrupts(trans); 1773e705c121SKalle Valo 1774e705c121SKalle Valo isr_stats->hw++; 1775e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1776e705c121SKalle Valo 1777e705c121SKalle Valo handled |= CSR_INT_BIT_HW_ERR; 1778e705c121SKalle Valo 1779e705c121SKalle Valo goto out; 1780e705c121SKalle Valo } 1781e705c121SKalle Valo 1782e705c121SKalle Valo if (iwl_have_debug_level(IWL_DL_ISR)) { 1783e705c121SKalle Valo /* NIC fires this, but we don't use it, redundant with WAKEUP */ 1784e705c121SKalle Valo if (inta & CSR_INT_BIT_SCD) { 1785e705c121SKalle Valo IWL_DEBUG_ISR(trans, 1786e705c121SKalle Valo "Scheduler finished to transmit the frame/frames.\n"); 1787e705c121SKalle Valo isr_stats->sch++; 1788e705c121SKalle Valo } 1789e705c121SKalle Valo 1790e705c121SKalle Valo /* Alive notification via Rx interrupt will do the real work */ 1791e705c121SKalle Valo if (inta & CSR_INT_BIT_ALIVE) { 1792e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 1793e705c121SKalle Valo isr_stats->alive++; 1794eda50cdeSSara Sharon if (trans->cfg->gen2) { 1795eda50cdeSSara Sharon /* 1796eda50cdeSSara Sharon * We can restock, since firmware configured 1797eda50cdeSSara Sharon * the RFH 1798eda50cdeSSara Sharon */ 1799eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 1800eda50cdeSSara Sharon } 1801e705c121SKalle Valo } 1802e705c121SKalle Valo } 1803e705c121SKalle Valo 1804e705c121SKalle Valo /* Safely ignore these bits for debug checks below */ 1805e705c121SKalle Valo inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 1806e705c121SKalle Valo 1807e705c121SKalle Valo /* HW RF KILL switch toggled */ 1808e705c121SKalle Valo if (inta & CSR_INT_BIT_RF_KILL) { 18093a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 1810e705c121SKalle Valo handled |= CSR_INT_BIT_RF_KILL; 1811e705c121SKalle Valo } 1812e705c121SKalle Valo 1813e705c121SKalle Valo /* Chip got too hot and stopped itself */ 1814e705c121SKalle Valo if (inta & CSR_INT_BIT_CT_KILL) { 1815e705c121SKalle Valo IWL_ERR(trans, "Microcode CT kill error detected.\n"); 1816e705c121SKalle Valo isr_stats->ctkill++; 1817e705c121SKalle Valo handled |= CSR_INT_BIT_CT_KILL; 1818e705c121SKalle Valo } 1819e705c121SKalle Valo 1820e705c121SKalle Valo /* Error detected by uCode */ 1821e705c121SKalle Valo if (inta & CSR_INT_BIT_SW_ERR) { 1822e705c121SKalle Valo IWL_ERR(trans, "Microcode SW error detected. " 1823e705c121SKalle Valo " Restarting 0x%X.\n", inta); 1824e705c121SKalle Valo isr_stats->sw++; 1825e705c121SKalle Valo iwl_pcie_irq_handle_error(trans); 1826e705c121SKalle Valo handled |= CSR_INT_BIT_SW_ERR; 1827e705c121SKalle Valo } 1828e705c121SKalle Valo 1829e705c121SKalle Valo /* uCode wakes up after power-down sleep */ 1830e705c121SKalle Valo if (inta & CSR_INT_BIT_WAKEUP) { 1831e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 1832e705c121SKalle Valo iwl_pcie_rxq_check_wrptr(trans); 1833e705c121SKalle Valo iwl_pcie_txq_check_wrptrs(trans); 1834e705c121SKalle Valo 1835e705c121SKalle Valo isr_stats->wakeup++; 1836e705c121SKalle Valo 1837e705c121SKalle Valo handled |= CSR_INT_BIT_WAKEUP; 1838e705c121SKalle Valo } 1839e705c121SKalle Valo 1840e705c121SKalle Valo /* All uCode command responses, including Tx command responses, 1841e705c121SKalle Valo * Rx "responses" (frame-received notification), and other 1842e705c121SKalle Valo * notifications from uCode come through here*/ 1843e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | 1844e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC)) { 1845e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1846e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1847e705c121SKalle Valo handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1848e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 1849e705c121SKalle Valo CSR_FH_INT_RX_MASK); 1850e705c121SKalle Valo } 1851e705c121SKalle Valo if (inta & CSR_INT_BIT_RX_PERIODIC) { 1852e705c121SKalle Valo handled |= CSR_INT_BIT_RX_PERIODIC; 1853e705c121SKalle Valo iwl_write32(trans, 1854e705c121SKalle Valo CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1855e705c121SKalle Valo } 1856e705c121SKalle Valo /* Sending RX interrupt require many steps to be done in the 1857e705c121SKalle Valo * the device: 1858e705c121SKalle Valo * 1- write interrupt to current index in ICT table. 1859e705c121SKalle Valo * 2- dma RX frame. 1860e705c121SKalle Valo * 3- update RX shared data to indicate last write index. 1861e705c121SKalle Valo * 4- send interrupt. 1862e705c121SKalle Valo * This could lead to RX race, driver could receive RX interrupt 1863e705c121SKalle Valo * but the shared data changes does not reflect this; 1864e705c121SKalle Valo * periodic interrupt will detect any dangling Rx activity. 1865e705c121SKalle Valo */ 1866e705c121SKalle Valo 1867e705c121SKalle Valo /* Disable periodic interrupt; we use it as just a one-shot. */ 1868e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1869e705c121SKalle Valo CSR_INT_PERIODIC_DIS); 1870e705c121SKalle Valo 1871e705c121SKalle Valo /* 1872e705c121SKalle Valo * Enable periodic interrupt in 8 msec only if we received 1873e705c121SKalle Valo * real RX interrupt (instead of just periodic int), to catch 1874e705c121SKalle Valo * any dangling Rx interrupt. If it was just the periodic 1875e705c121SKalle Valo * interrupt, there was no dangling Rx activity, and no need 1876e705c121SKalle Valo * to extend the periodic interrupt; one-shot is enough. 1877e705c121SKalle Valo */ 1878e705c121SKalle Valo if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1879e705c121SKalle Valo iwl_write8(trans, CSR_INT_PERIODIC_REG, 1880e705c121SKalle Valo CSR_INT_PERIODIC_ENA); 1881e705c121SKalle Valo 1882e705c121SKalle Valo isr_stats->rx++; 1883e705c121SKalle Valo 1884e705c121SKalle Valo local_bh_disable(); 18852e5d4a8fSHaim Dreyfuss iwl_pcie_rx_handle(trans, 0); 1886e705c121SKalle Valo local_bh_enable(); 1887e705c121SKalle Valo } 1888e705c121SKalle Valo 1889e705c121SKalle Valo /* This "Tx" DMA channel is used only for loading uCode */ 1890e705c121SKalle Valo if (inta & CSR_INT_BIT_FH_TX) { 1891e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1892e705c121SKalle Valo IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1893e705c121SKalle Valo isr_stats->tx++; 1894e705c121SKalle Valo handled |= CSR_INT_BIT_FH_TX; 1895e705c121SKalle Valo /* Wake up uCode load routine, now that load is complete */ 1896e705c121SKalle Valo trans_pcie->ucode_write_complete = true; 1897e705c121SKalle Valo wake_up(&trans_pcie->ucode_write_waitq); 1898e705c121SKalle Valo } 1899e705c121SKalle Valo 1900e705c121SKalle Valo if (inta & ~handled) { 1901e705c121SKalle Valo IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); 1902e705c121SKalle Valo isr_stats->unhandled++; 1903e705c121SKalle Valo } 1904e705c121SKalle Valo 1905e705c121SKalle Valo if (inta & ~(trans_pcie->inta_mask)) { 1906e705c121SKalle Valo IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", 1907e705c121SKalle Valo inta & ~trans_pcie->inta_mask); 1908e705c121SKalle Valo } 1909e705c121SKalle Valo 1910f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 1911a6bd005fSEmmanuel Grumbach /* only Re-enable all interrupt if disabled by irq */ 1912f16c3ebfSEmmanuel Grumbach if (test_bit(STATUS_INT_ENABLED, &trans->status)) 1913f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 1914f16c3ebfSEmmanuel Grumbach /* we are loading the firmware, enable FH_TX interrupt only */ 1915f16c3ebfSEmmanuel Grumbach else if (handled & CSR_INT_BIT_FH_TX) 1916f16c3ebfSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1917e705c121SKalle Valo /* Re-enable RF_KILL if it occurred */ 1918e705c121SKalle Valo else if (handled & CSR_INT_BIT_RF_KILL) 1919e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1920f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 1921e705c121SKalle Valo 1922e705c121SKalle Valo out: 1923e705c121SKalle Valo lock_map_release(&trans->sync_cmd_lockdep_map); 1924e705c121SKalle Valo return IRQ_HANDLED; 1925e705c121SKalle Valo } 1926e705c121SKalle Valo 1927e705c121SKalle Valo /****************************************************************************** 1928e705c121SKalle Valo * 1929e705c121SKalle Valo * ICT functions 1930e705c121SKalle Valo * 1931e705c121SKalle Valo ******************************************************************************/ 1932e705c121SKalle Valo 1933e705c121SKalle Valo /* Free dram table */ 1934e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans) 1935e705c121SKalle Valo { 1936e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1937e705c121SKalle Valo 1938e705c121SKalle Valo if (trans_pcie->ict_tbl) { 1939e705c121SKalle Valo dma_free_coherent(trans->dev, ICT_SIZE, 1940e705c121SKalle Valo trans_pcie->ict_tbl, 1941e705c121SKalle Valo trans_pcie->ict_tbl_dma); 1942e705c121SKalle Valo trans_pcie->ict_tbl = NULL; 1943e705c121SKalle Valo trans_pcie->ict_tbl_dma = 0; 1944e705c121SKalle Valo } 1945e705c121SKalle Valo } 1946e705c121SKalle Valo 1947e705c121SKalle Valo /* 1948e705c121SKalle Valo * allocate dram shared table, it is an aligned memory 1949e705c121SKalle Valo * block of ICT_SIZE. 1950e705c121SKalle Valo * also reset all data related to ICT table interrupt. 1951e705c121SKalle Valo */ 1952e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans) 1953e705c121SKalle Valo { 1954e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1955e705c121SKalle Valo 1956e705c121SKalle Valo trans_pcie->ict_tbl = 1957e705c121SKalle Valo dma_zalloc_coherent(trans->dev, ICT_SIZE, 1958e705c121SKalle Valo &trans_pcie->ict_tbl_dma, 1959e705c121SKalle Valo GFP_KERNEL); 1960e705c121SKalle Valo if (!trans_pcie->ict_tbl) 1961e705c121SKalle Valo return -ENOMEM; 1962e705c121SKalle Valo 1963e705c121SKalle Valo /* just an API sanity check ... it is guaranteed to be aligned */ 1964e705c121SKalle Valo if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { 1965e705c121SKalle Valo iwl_pcie_free_ict(trans); 1966e705c121SKalle Valo return -EINVAL; 1967e705c121SKalle Valo } 1968e705c121SKalle Valo 1969e705c121SKalle Valo return 0; 1970e705c121SKalle Valo } 1971e705c121SKalle Valo 1972e705c121SKalle Valo /* Device is going up inform it about using ICT interrupt table, 1973e705c121SKalle Valo * also we need to tell the driver to start using ICT interrupt. 1974e705c121SKalle Valo */ 1975e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans) 1976e705c121SKalle Valo { 1977e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1978e705c121SKalle Valo u32 val; 1979e705c121SKalle Valo 1980e705c121SKalle Valo if (!trans_pcie->ict_tbl) 1981e705c121SKalle Valo return; 1982e705c121SKalle Valo 1983e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1984f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 1985e705c121SKalle Valo 1986e705c121SKalle Valo memset(trans_pcie->ict_tbl, 0, ICT_SIZE); 1987e705c121SKalle Valo 1988e705c121SKalle Valo val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; 1989e705c121SKalle Valo 1990e705c121SKalle Valo val |= CSR_DRAM_INT_TBL_ENABLE | 1991e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRAP_CHECK | 1992e705c121SKalle Valo CSR_DRAM_INIT_TBL_WRITE_POINTER; 1993e705c121SKalle Valo 1994e705c121SKalle Valo IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); 1995e705c121SKalle Valo 1996e705c121SKalle Valo iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); 1997e705c121SKalle Valo trans_pcie->use_ict = true; 1998e705c121SKalle Valo trans_pcie->ict_index = 0; 1999e705c121SKalle Valo iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); 2000f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 2001e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 2002e705c121SKalle Valo } 2003e705c121SKalle Valo 2004e705c121SKalle Valo /* Device is going down disable ict interrupt usage */ 2005e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans) 2006e705c121SKalle Valo { 2007e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2008e705c121SKalle Valo 2009e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 2010e705c121SKalle Valo trans_pcie->use_ict = false; 2011e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 2012e705c121SKalle Valo } 2013e705c121SKalle Valo 2014e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data) 2015e705c121SKalle Valo { 2016e705c121SKalle Valo struct iwl_trans *trans = data; 2017e705c121SKalle Valo 2018e705c121SKalle Valo if (!trans) 2019e705c121SKalle Valo return IRQ_NONE; 2020e705c121SKalle Valo 2021e705c121SKalle Valo /* Disable (but don't clear!) interrupts here to avoid 2022e705c121SKalle Valo * back-to-back ISRs and sporadic interrupts from our NIC. 2023e705c121SKalle Valo * If we have something to service, the tasklet will re-enable ints. 2024e705c121SKalle Valo * If we *don't* have something, we'll re-enable before leaving here. 2025e705c121SKalle Valo */ 2026e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 2027e705c121SKalle Valo 2028e705c121SKalle Valo return IRQ_WAKE_THREAD; 2029e705c121SKalle Valo } 20302e5d4a8fSHaim Dreyfuss 20312e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data) 20322e5d4a8fSHaim Dreyfuss { 20332e5d4a8fSHaim Dreyfuss return IRQ_WAKE_THREAD; 20342e5d4a8fSHaim Dreyfuss } 20352e5d4a8fSHaim Dreyfuss 20362e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id) 20372e5d4a8fSHaim Dreyfuss { 20382e5d4a8fSHaim Dreyfuss struct msix_entry *entry = dev_id; 20392e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry); 20402e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 204146167a8fSColin Ian King struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 20422e5d4a8fSHaim Dreyfuss u32 inta_fh, inta_hw; 20432e5d4a8fSHaim Dreyfuss 20442e5d4a8fSHaim Dreyfuss lock_map_acquire(&trans->sync_cmd_lockdep_map); 20452e5d4a8fSHaim Dreyfuss 20462e5d4a8fSHaim Dreyfuss spin_lock(&trans_pcie->irq_lock); 20477ef3dd26SHaim Dreyfuss inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD); 20487ef3dd26SHaim Dreyfuss inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD); 20492e5d4a8fSHaim Dreyfuss /* 20502e5d4a8fSHaim Dreyfuss * Clear causes registers to avoid being handling the same cause. 20512e5d4a8fSHaim Dreyfuss */ 20527ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 20537ef3dd26SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 20542e5d4a8fSHaim Dreyfuss spin_unlock(&trans_pcie->irq_lock); 20552e5d4a8fSHaim Dreyfuss 2056c42ff65dSJohannes Berg trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw); 2057c42ff65dSJohannes Berg 20582e5d4a8fSHaim Dreyfuss if (unlikely(!(inta_fh | inta_hw))) { 20592e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); 20602e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 20612e5d4a8fSHaim Dreyfuss return IRQ_NONE; 20622e5d4a8fSHaim Dreyfuss } 20632e5d4a8fSHaim Dreyfuss 20642e5d4a8fSHaim Dreyfuss if (iwl_have_debug_level(IWL_DL_ISR)) 20652e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "ISR inta_fh 0x%08x, enabled 0x%08x\n", 20662e5d4a8fSHaim Dreyfuss inta_fh, 20672e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD)); 20682e5d4a8fSHaim Dreyfuss 2069496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) && 2070496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q0) { 2071496d83caSHaim Dreyfuss local_bh_disable(); 2072496d83caSHaim Dreyfuss iwl_pcie_rx_handle(trans, 0); 2073496d83caSHaim Dreyfuss local_bh_enable(); 2074496d83caSHaim Dreyfuss } 2075496d83caSHaim Dreyfuss 2076496d83caSHaim Dreyfuss if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) && 2077496d83caSHaim Dreyfuss inta_fh & MSIX_FH_INT_CAUSES_Q1) { 2078496d83caSHaim Dreyfuss local_bh_disable(); 2079496d83caSHaim Dreyfuss iwl_pcie_rx_handle(trans, 1); 2080496d83caSHaim Dreyfuss local_bh_enable(); 2081496d83caSHaim Dreyfuss } 2082496d83caSHaim Dreyfuss 20832e5d4a8fSHaim Dreyfuss /* This "Tx" DMA channel is used only for loading uCode */ 20842e5d4a8fSHaim Dreyfuss if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 20852e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 20862e5d4a8fSHaim Dreyfuss isr_stats->tx++; 20872e5d4a8fSHaim Dreyfuss /* 20882e5d4a8fSHaim Dreyfuss * Wake up uCode load routine, 20892e5d4a8fSHaim Dreyfuss * now that load is complete 20902e5d4a8fSHaim Dreyfuss */ 20912e5d4a8fSHaim Dreyfuss trans_pcie->ucode_write_complete = true; 20922e5d4a8fSHaim Dreyfuss wake_up(&trans_pcie->ucode_write_waitq); 20932e5d4a8fSHaim Dreyfuss } 20942e5d4a8fSHaim Dreyfuss 20952e5d4a8fSHaim Dreyfuss /* Error detected by uCode */ 20962e5d4a8fSHaim Dreyfuss if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || 20979b58419eSGolan Ben Ami (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) || 20989b58419eSGolan Ben Ami (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_V2)) { 20992e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 21002e5d4a8fSHaim Dreyfuss "Microcode SW error detected. Restarting 0x%X.\n", 21012e5d4a8fSHaim Dreyfuss inta_fh); 21022e5d4a8fSHaim Dreyfuss isr_stats->sw++; 21032e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 21042e5d4a8fSHaim Dreyfuss } 21052e5d4a8fSHaim Dreyfuss 21062e5d4a8fSHaim Dreyfuss /* After checking FH register check HW register */ 21072e5d4a8fSHaim Dreyfuss if (iwl_have_debug_level(IWL_DL_ISR)) 21082e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, 21092e5d4a8fSHaim Dreyfuss "ISR inta_hw 0x%08x, enabled 0x%08x\n", 21102e5d4a8fSHaim Dreyfuss inta_hw, 21112e5d4a8fSHaim Dreyfuss iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD)); 21122e5d4a8fSHaim Dreyfuss 21132e5d4a8fSHaim Dreyfuss /* Alive notification via Rx interrupt will do the real work */ 21142e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) { 21152e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Alive interrupt\n"); 21162e5d4a8fSHaim Dreyfuss isr_stats->alive++; 2117eda50cdeSSara Sharon if (trans->cfg->gen2) { 2118eda50cdeSSara Sharon /* We can restock, since firmware configured the RFH */ 2119eda50cdeSSara Sharon iwl_pcie_rxmq_restock(trans, trans_pcie->rxq); 2120eda50cdeSSara Sharon } 21212e5d4a8fSHaim Dreyfuss } 21222e5d4a8fSHaim Dreyfuss 21239b58419eSGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560 && 21249b58419eSGolan Ben Ami inta_hw & MSIX_HW_INT_CAUSES_REG_IPC) { 21259b58419eSGolan Ben Ami /* Reflect IML transfer status */ 21269b58419eSGolan Ben Ami int res = iwl_read32(trans, CSR_IML_RESP_ADDR); 21279b58419eSGolan Ben Ami 21289b58419eSGolan Ben Ami IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res); 21299b58419eSGolan Ben Ami if (res == IWL_IMAGE_RESP_FAIL) { 21309b58419eSGolan Ben Ami isr_stats->sw++; 21319b58419eSGolan Ben Ami iwl_pcie_irq_handle_error(trans); 21329b58419eSGolan Ben Ami } 21339b58419eSGolan Ben Ami } else if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) { 21342e5d4a8fSHaim Dreyfuss /* uCode wakes up after power-down sleep */ 21352e5d4a8fSHaim Dreyfuss IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); 21362e5d4a8fSHaim Dreyfuss iwl_pcie_rxq_check_wrptr(trans); 21372e5d4a8fSHaim Dreyfuss iwl_pcie_txq_check_wrptrs(trans); 21382e5d4a8fSHaim Dreyfuss 21392e5d4a8fSHaim Dreyfuss isr_stats->wakeup++; 21402e5d4a8fSHaim Dreyfuss } 21412e5d4a8fSHaim Dreyfuss 21422e5d4a8fSHaim Dreyfuss /* Chip got too hot and stopped itself */ 21432e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) { 21442e5d4a8fSHaim Dreyfuss IWL_ERR(trans, "Microcode CT kill error detected.\n"); 21452e5d4a8fSHaim Dreyfuss isr_stats->ctkill++; 21462e5d4a8fSHaim Dreyfuss } 21472e5d4a8fSHaim Dreyfuss 21482e5d4a8fSHaim Dreyfuss /* HW RF KILL switch toggled */ 21493a6e168bSJohannes Berg if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) 21503a6e168bSJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 21512e5d4a8fSHaim Dreyfuss 21522e5d4a8fSHaim Dreyfuss if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) { 21532e5d4a8fSHaim Dreyfuss IWL_ERR(trans, 21542e5d4a8fSHaim Dreyfuss "Hardware error detected. Restarting.\n"); 21552e5d4a8fSHaim Dreyfuss 21562e5d4a8fSHaim Dreyfuss isr_stats->hw++; 21572e5d4a8fSHaim Dreyfuss iwl_pcie_irq_handle_error(trans); 21582e5d4a8fSHaim Dreyfuss } 21592e5d4a8fSHaim Dreyfuss 21602e5d4a8fSHaim Dreyfuss iwl_pcie_clear_irq(trans, entry); 21612e5d4a8fSHaim Dreyfuss 21622e5d4a8fSHaim Dreyfuss lock_map_release(&trans->sync_cmd_lockdep_map); 21632e5d4a8fSHaim Dreyfuss 21642e5d4a8fSHaim Dreyfuss return IRQ_HANDLED; 21652e5d4a8fSHaim Dreyfuss } 2166