1 /****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6 * Copyright(c) 2018 Intel Corporation 7 * 8 * Portions of this file are derived from the ipw3945 project, as well 9 * as portions of the ieee80211 subsystem header files. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * The full GNU General Public License is included in this distribution in the 21 * file called LICENSE. 22 * 23 * Contact Information: 24 * Intel Linux Wireless <linuxwifi@intel.com> 25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 * 27 *****************************************************************************/ 28 #ifndef __iwl_trans_int_pcie_h__ 29 #define __iwl_trans_int_pcie_h__ 30 31 #include <linux/spinlock.h> 32 #include <linux/interrupt.h> 33 #include <linux/skbuff.h> 34 #include <linux/wait.h> 35 #include <linux/pci.h> 36 #include <linux/timer.h> 37 #include <linux/cpu.h> 38 39 #include "iwl-fh.h" 40 #include "iwl-csr.h" 41 #include "iwl-trans.h" 42 #include "iwl-debug.h" 43 #include "iwl-io.h" 44 #include "iwl-op-mode.h" 45 #include "iwl-drv.h" 46 47 /* We need 2 entries for the TX command and header, and another one might 48 * be needed for potential data in the SKB's head. The remaining ones can 49 * be used for frags. 50 */ 51 #define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3) 52 53 /* 54 * RX related structures and functions 55 */ 56 #define RX_NUM_QUEUES 1 57 #define RX_POST_REQ_ALLOC 2 58 #define RX_CLAIM_REQ_ALLOC 8 59 #define RX_PENDING_WATERMARK 16 60 #define FIRST_RX_QUEUE 512 61 62 struct iwl_host_cmd; 63 64 /*This file includes the declaration that are internal to the 65 * trans_pcie layer */ 66 67 /** 68 * struct iwl_rx_mem_buffer 69 * @page_dma: bus address of rxb page 70 * @page: driver's pointer to the rxb page 71 * @invalid: rxb is in driver ownership - not owned by HW 72 * @vid: index of this rxb in the global table 73 * @size: size used from the buffer 74 */ 75 struct iwl_rx_mem_buffer { 76 dma_addr_t page_dma; 77 struct page *page; 78 u16 vid; 79 bool invalid; 80 struct list_head list; 81 u32 size; 82 }; 83 84 /** 85 * struct isr_statistics - interrupt statistics 86 * 87 */ 88 struct isr_statistics { 89 u32 hw; 90 u32 sw; 91 u32 err_code; 92 u32 sch; 93 u32 alive; 94 u32 rfkill; 95 u32 ctkill; 96 u32 wakeup; 97 u32 rx; 98 u32 tx; 99 u32 unhandled; 100 }; 101 102 #define IWL_RX_TD_TYPE_MSK 0xff000000 103 #define IWL_RX_TD_SIZE_MSK 0x00ffffff 104 #define IWL_RX_TD_SIZE_2K BIT(11) 105 #define IWL_RX_TD_TYPE 0 106 107 /** 108 * struct iwl_rx_transfer_desc - transfer descriptor 109 * @type_n_size: buffer type (bit 0: external buff valid, 110 * bit 1: optional footer valid, bit 2-7: reserved) 111 * and buffer size 112 * @addr: ptr to free buffer start address 113 * @rbid: unique tag of the buffer 114 * @reserved: reserved 115 */ 116 struct iwl_rx_transfer_desc { 117 __le32 type_n_size; 118 __le64 addr; 119 __le16 rbid; 120 __le16 reserved; 121 } __packed; 122 123 #define IWL_RX_CD_SIZE 0xffffff00 124 125 /** 126 * struct iwl_rx_completion_desc - completion descriptor 127 * @type: buffer type (bit 0: external buff valid, 128 * bit 1: optional footer valid, bit 2-7: reserved) 129 * @status: status of the completion 130 * @reserved1: reserved 131 * @rbid: unique tag of the received buffer 132 * @size: buffer size, masked by IWL_RX_CD_SIZE 133 * @reserved2: reserved 134 */ 135 struct iwl_rx_completion_desc { 136 u8 type; 137 u8 status; 138 __le16 reserved1; 139 __le16 rbid; 140 __le32 size; 141 u8 reserved2[22]; 142 } __packed; 143 144 /** 145 * struct iwl_rxq - Rx queue 146 * @id: queue index 147 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 148 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 149 * In 22560 devices it is a pointer to a list of iwl_rx_transfer_desc's 150 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 151 * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd) 152 * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd) 153 * @tr_tail: driver's pointer to the transmission ring tail buffer 154 * @tr_tail_dma: physical address of the buffer for the transmission ring tail 155 * @cr_tail: driver's pointer to the completion ring tail buffer 156 * @cr_tail_dma: physical address of the buffer for the completion ring tail 157 * @read: Shared index to newest available Rx buffer 158 * @write: Shared index to oldest written Rx packet 159 * @free_count: Number of pre-allocated buffers in rx_free 160 * @used_count: Number of RBDs handled to allocator to use for allocation 161 * @write_actual: 162 * @rx_free: list of RBDs with allocated RB ready for use 163 * @rx_used: list of RBDs with no RB attached 164 * @need_update: flag to indicate we need to update read/write index 165 * @rb_stts: driver's pointer to receive buffer status 166 * @rb_stts_dma: bus address of receive buffer status 167 * @lock: 168 * @queue: actual rx queue. Not used for multi-rx queue. 169 * 170 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 171 */ 172 struct iwl_rxq { 173 int id; 174 void *bd; 175 dma_addr_t bd_dma; 176 union { 177 void *used_bd; 178 __le32 *bd_32; 179 struct iwl_rx_completion_desc *cd; 180 }; 181 dma_addr_t used_bd_dma; 182 __le16 *tr_tail; 183 dma_addr_t tr_tail_dma; 184 __le16 *cr_tail; 185 dma_addr_t cr_tail_dma; 186 u32 read; 187 u32 write; 188 u32 free_count; 189 u32 used_count; 190 u32 write_actual; 191 u32 queue_size; 192 struct list_head rx_free; 193 struct list_head rx_used; 194 bool need_update; 195 void *rb_stts; 196 dma_addr_t rb_stts_dma; 197 spinlock_t lock; 198 struct napi_struct napi; 199 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 200 }; 201 202 /** 203 * struct iwl_rb_allocator - Rx allocator 204 * @req_pending: number of requests the allcator had not processed yet 205 * @req_ready: number of requests honored and ready for claiming 206 * @rbd_allocated: RBDs with pages allocated and ready to be handled to 207 * the queue. This is a list of &struct iwl_rx_mem_buffer 208 * @rbd_empty: RBDs with no page attached for allocator use. This is a list 209 * of &struct iwl_rx_mem_buffer 210 * @lock: protects the rbd_allocated and rbd_empty lists 211 * @alloc_wq: work queue for background calls 212 * @rx_alloc: work struct for background calls 213 */ 214 struct iwl_rb_allocator { 215 atomic_t req_pending; 216 atomic_t req_ready; 217 struct list_head rbd_allocated; 218 struct list_head rbd_empty; 219 spinlock_t lock; 220 struct workqueue_struct *alloc_wq; 221 struct work_struct rx_alloc; 222 }; 223 224 struct iwl_dma_ptr { 225 dma_addr_t dma; 226 void *addr; 227 size_t size; 228 }; 229 230 /** 231 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 232 * @index -- current index 233 */ 234 static inline int iwl_queue_inc_wrap(struct iwl_trans *trans, int index) 235 { 236 return ++index & (trans->cfg->base_params->max_tfd_queue_size - 1); 237 } 238 239 /** 240 * iwl_get_closed_rb_stts - get closed rb stts from different structs 241 * @rxq - the rxq to get the rb stts from 242 */ 243 static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans, 244 struct iwl_rxq *rxq) 245 { 246 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 247 __le16 *rb_stts = rxq->rb_stts; 248 249 return READ_ONCE(*rb_stts); 250 } else { 251 struct iwl_rb_status *rb_stts = rxq->rb_stts; 252 253 return READ_ONCE(rb_stts->closed_rb_num); 254 } 255 } 256 257 /** 258 * iwl_queue_dec_wrap - decrement queue index, wrap back to end 259 * @index -- current index 260 */ 261 static inline int iwl_queue_dec_wrap(struct iwl_trans *trans, int index) 262 { 263 return --index & (trans->cfg->base_params->max_tfd_queue_size - 1); 264 } 265 266 struct iwl_cmd_meta { 267 /* only for SYNC commands, iff the reply skb is wanted */ 268 struct iwl_host_cmd *source; 269 u32 flags; 270 u32 tbs; 271 }; 272 273 274 #define TFD_TX_CMD_SLOTS 256 275 #define TFD_CMD_SLOTS 32 276 277 /* 278 * The FH will write back to the first TB only, so we need to copy some data 279 * into the buffer regardless of whether it should be mapped or not. 280 * This indicates how big the first TB must be to include the scratch buffer 281 * and the assigned PN. 282 * Since PN location is 8 bytes at offset 12, it's 20 now. 283 * If we make it bigger then allocations will be bigger and copy slower, so 284 * that's probably not useful. 285 */ 286 #define IWL_FIRST_TB_SIZE 20 287 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 288 289 struct iwl_pcie_txq_entry { 290 struct iwl_device_cmd *cmd; 291 struct sk_buff *skb; 292 /* buffer to free after command completes */ 293 const void *free_buf; 294 struct iwl_cmd_meta meta; 295 }; 296 297 struct iwl_pcie_first_tb_buf { 298 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 299 }; 300 301 /** 302 * struct iwl_txq - Tx Queue for DMA 303 * @q: generic Rx/Tx queue descriptor 304 * @tfds: transmit frame descriptors (DMA memory) 305 * @first_tb_bufs: start of command headers, including scratch buffers, for 306 * the writeback -- this is DMA memory and an array holding one buffer 307 * for each command on the queue 308 * @first_tb_dma: DMA address for the first_tb_bufs start 309 * @entries: transmit entries (driver state) 310 * @lock: queue lock 311 * @stuck_timer: timer that fires if queue gets stuck 312 * @trans_pcie: pointer back to transport (for timer) 313 * @need_update: indicates need to update read/write index 314 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 315 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 316 * @frozen: tx stuck queue timer is frozen 317 * @frozen_expiry_remainder: remember how long until the timer fires 318 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 319 * @write_ptr: 1-st empty entry (index) host_w 320 * @read_ptr: last used entry (index) host_r 321 * @dma_addr: physical addr for BD's 322 * @n_window: safe queue window 323 * @id: queue id 324 * @low_mark: low watermark, resume queue if free space more than this 325 * @high_mark: high watermark, stop queue if free space less than this 326 * 327 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 328 * descriptors) and required locking structures. 329 * 330 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 331 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 332 * there might be HW changes in the future). For the normal TX 333 * queues, n_window, which is the size of the software queue data 334 * is also 256; however, for the command queue, n_window is only 335 * 32 since we don't need so many commands pending. Since the HW 336 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 337 * This means that we end up with the following: 338 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 339 * SW entries: | 0 | ... | 31 | 340 * where N is a number between 0 and 7. This means that the SW 341 * data is a window overlayed over the HW queue. 342 */ 343 struct iwl_txq { 344 void *tfds; 345 struct iwl_pcie_first_tb_buf *first_tb_bufs; 346 dma_addr_t first_tb_dma; 347 struct iwl_pcie_txq_entry *entries; 348 spinlock_t lock; 349 unsigned long frozen_expiry_remainder; 350 struct timer_list stuck_timer; 351 struct iwl_trans_pcie *trans_pcie; 352 bool need_update; 353 bool frozen; 354 bool ampdu; 355 int block; 356 unsigned long wd_timeout; 357 struct sk_buff_head overflow_q; 358 struct iwl_dma_ptr bc_tbl; 359 360 int write_ptr; 361 int read_ptr; 362 dma_addr_t dma_addr; 363 int n_window; 364 u32 id; 365 int low_mark; 366 int high_mark; 367 }; 368 369 static inline dma_addr_t 370 iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx) 371 { 372 return txq->first_tb_dma + 373 sizeof(struct iwl_pcie_first_tb_buf) * idx; 374 } 375 376 struct iwl_tso_hdr_page { 377 struct page *page; 378 u8 *pos; 379 }; 380 381 #ifdef CONFIG_IWLWIFI_DEBUGFS 382 /** 383 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data 384 * debugfs file 385 * 386 * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed. 387 * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open. 388 * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is 389 * set the file can no longer be used. 390 */ 391 enum iwl_fw_mon_dbgfs_state { 392 IWL_FW_MON_DBGFS_STATE_CLOSED, 393 IWL_FW_MON_DBGFS_STATE_OPEN, 394 IWL_FW_MON_DBGFS_STATE_DISABLED, 395 }; 396 #endif 397 398 /** 399 * enum iwl_shared_irq_flags - level of sharing for irq 400 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 401 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 402 */ 403 enum iwl_shared_irq_flags { 404 IWL_SHARED_IRQ_NON_RX = BIT(0), 405 IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 406 }; 407 408 /** 409 * enum iwl_image_response_code - image response values 410 * @IWL_IMAGE_RESP_DEF: the default value of the register 411 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully 412 * @IWL_IMAGE_RESP_FAIL: iml reading failed 413 */ 414 enum iwl_image_response_code { 415 IWL_IMAGE_RESP_DEF = 0, 416 IWL_IMAGE_RESP_SUCCESS = 1, 417 IWL_IMAGE_RESP_FAIL = 2, 418 }; 419 420 /** 421 * struct iwl_self_init_dram - dram data used by self init process 422 * @fw: lmac and umac dram data 423 * @fw_cnt: total number of items in array 424 * @paging: paging dram data 425 * @paging_cnt: total number of items in array 426 */ 427 struct iwl_self_init_dram { 428 struct iwl_dram_data *fw; 429 int fw_cnt; 430 struct iwl_dram_data *paging; 431 int paging_cnt; 432 }; 433 434 /** 435 * struct cont_rec: continuous recording data structure 436 * @prev_wr_ptr: the last address that was read in monitor_data 437 * debugfs file 438 * @prev_wrap_cnt: the wrap count that was used during the last read in 439 * monitor_data debugfs file 440 * @state: the state of monitor_data debugfs file as described 441 * in &iwl_fw_mon_dbgfs_state enum 442 * @mutex: locked while reading from monitor_data debugfs file 443 */ 444 #ifdef CONFIG_IWLWIFI_DEBUGFS 445 struct cont_rec { 446 u32 prev_wr_ptr; 447 u32 prev_wrap_cnt; 448 u8 state; 449 /* Used to sync monitor_data debugfs file with driver unload flow */ 450 struct mutex mutex; 451 }; 452 #endif 453 454 /** 455 * struct iwl_trans_pcie - PCIe transport specific data 456 * @rxq: all the RX queue data 457 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 458 * @global_table: table mapping received VID from hw to rxb 459 * @rba: allocator for RX replenishing 460 * @ctxt_info: context information for FW self init 461 * @ctxt_info_gen3: context information for gen3 devices 462 * @prph_info: prph info for self init 463 * @prph_scratch: prph scratch for self init 464 * @ctxt_info_dma_addr: dma addr of context information 465 * @prph_info_dma_addr: dma addr of prph info 466 * @prph_scratch_dma_addr: dma addr of prph scratch 467 * @ctxt_info_dma_addr: dma addr of context information 468 * @init_dram: DRAM data of firmware image (including paging). 469 * Context information addresses will be taken from here. 470 * This is driver's local copy for keeping track of size and 471 * count for allocating and freeing the memory. 472 * @trans: pointer to the generic transport area 473 * @scd_base_addr: scheduler sram base address in SRAM 474 * @scd_bc_tbls: pointer to the byte count table of the scheduler 475 * @kw: keep warm address 476 * @pci_dev: basic pci-network driver stuff 477 * @hw_base: pci hardware address support 478 * @ucode_write_complete: indicates that the ucode has been copied. 479 * @ucode_write_waitq: wait queue for uCode load 480 * @cmd_queue - command queue number 481 * @def_rx_queue - default rx queue number 482 * @rx_buf_size: Rx buffer size 483 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 484 * @scd_set_active: should the transport configure the SCD for HCMD queue 485 * @sw_csum_tx: if true, then the transport will compute the csum of the TXed 486 * frame. 487 * @rx_page_order: page order for receive buffer size 488 * @reg_lock: protect hw register access 489 * @mutex: to protect stop_device / start_fw / start_hw 490 * @cmd_in_flight: true when we have a host command in flight 491 #ifdef CONFIG_IWLWIFI_DEBUGFS 492 * @fw_mon_data: fw continuous recording data 493 #endif 494 * @msix_entries: array of MSI-X entries 495 * @msix_enabled: true if managed to enable MSI-X 496 * @shared_vec_mask: the type of causes the shared vector handles 497 * (see iwl_shared_irq_flags). 498 * @alloc_vecs: the number of interrupt vectors allocated by the OS 499 * @def_irq: default irq for non rx causes 500 * @fh_init_mask: initial unmasked fh causes 501 * @hw_init_mask: initial unmasked hw causes 502 * @fh_mask: current unmasked fh causes 503 * @hw_mask: current unmasked hw causes 504 * @in_rescan: true if we have triggered a device rescan 505 */ 506 struct iwl_trans_pcie { 507 struct iwl_rxq *rxq; 508 struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE]; 509 struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE]; 510 struct iwl_rb_allocator rba; 511 union { 512 struct iwl_context_info *ctxt_info; 513 struct iwl_context_info_gen3 *ctxt_info_gen3; 514 }; 515 struct iwl_prph_info *prph_info; 516 struct iwl_prph_scratch *prph_scratch; 517 dma_addr_t ctxt_info_dma_addr; 518 dma_addr_t prph_info_dma_addr; 519 dma_addr_t prph_scratch_dma_addr; 520 dma_addr_t iml_dma_addr; 521 struct iwl_self_init_dram init_dram; 522 struct iwl_trans *trans; 523 524 struct net_device napi_dev; 525 526 struct __percpu iwl_tso_hdr_page *tso_hdr_page; 527 528 /* INT ICT Table */ 529 __le32 *ict_tbl; 530 dma_addr_t ict_tbl_dma; 531 int ict_index; 532 bool use_ict; 533 bool is_down, opmode_down; 534 bool debug_rfkill; 535 struct isr_statistics isr_stats; 536 537 spinlock_t irq_lock; 538 struct mutex mutex; 539 u32 inta_mask; 540 u32 scd_base_addr; 541 struct iwl_dma_ptr scd_bc_tbls; 542 struct iwl_dma_ptr kw; 543 544 struct iwl_txq *txq_memory; 545 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 546 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 547 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 548 549 /* PCI bus related data */ 550 struct pci_dev *pci_dev; 551 void __iomem *hw_base; 552 553 bool ucode_write_complete; 554 wait_queue_head_t ucode_write_waitq; 555 wait_queue_head_t wait_command_queue; 556 wait_queue_head_t d0i3_waitq; 557 558 u8 page_offs, dev_cmd_offs; 559 560 u8 cmd_queue; 561 u8 def_rx_queue; 562 u8 cmd_fifo; 563 unsigned int cmd_q_wdg_timeout; 564 u8 n_no_reclaim_cmds; 565 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 566 u8 max_tbs; 567 u16 tfd_size; 568 569 enum iwl_amsdu_size rx_buf_size; 570 bool bc_table_dword; 571 bool scd_set_active; 572 bool sw_csum_tx; 573 bool pcie_dbg_dumped_once; 574 u32 rx_page_order; 575 576 /*protect hw register */ 577 spinlock_t reg_lock; 578 bool cmd_hold_nic_awake; 579 bool ref_cmd_in_flight; 580 581 #ifdef CONFIG_IWLWIFI_DEBUGFS 582 struct cont_rec fw_mon_data; 583 #endif 584 585 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 586 bool msix_enabled; 587 u8 shared_vec_mask; 588 u32 alloc_vecs; 589 u32 def_irq; 590 u32 fh_init_mask; 591 u32 hw_init_mask; 592 u32 fh_mask; 593 u32 hw_mask; 594 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 595 u16 tx_cmd_queue_size; 596 bool in_rescan; 597 }; 598 599 static inline struct iwl_trans_pcie * 600 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 601 { 602 return (void *)trans->trans_specific; 603 } 604 605 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 606 struct msix_entry *entry) 607 { 608 /* 609 * Before sending the interrupt the HW disables it to prevent 610 * a nested interrupt. This is done by writing 1 to the corresponding 611 * bit in the mask register. After handling the interrupt, it should be 612 * re-enabled by clearing this bit. This register is defined as 613 * write 1 clear (W1C) register, meaning that it's being clear 614 * by writing 1 to the bit. 615 */ 616 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 617 } 618 619 static inline struct iwl_trans * 620 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 621 { 622 return container_of((void *)trans_pcie, struct iwl_trans, 623 trans_specific); 624 } 625 626 /* 627 * Convention: trans API functions: iwl_trans_pcie_XXX 628 * Other functions: iwl_pcie_XXX 629 */ 630 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 631 const struct pci_device_id *ent, 632 const struct iwl_cfg *cfg); 633 void iwl_trans_pcie_free(struct iwl_trans *trans); 634 635 /***************************************************** 636 * RX 637 ******************************************************/ 638 int _iwl_pcie_rx_init(struct iwl_trans *trans); 639 int iwl_pcie_rx_init(struct iwl_trans *trans); 640 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 641 irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 642 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 643 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 644 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 645 int iwl_pcie_rx_stop(struct iwl_trans *trans); 646 void iwl_pcie_rx_free(struct iwl_trans *trans); 647 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans); 648 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq); 649 int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget); 650 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 651 struct iwl_rxq *rxq); 652 int iwl_pcie_rx_alloc(struct iwl_trans *trans); 653 654 /***************************************************** 655 * ICT - interrupt handling 656 ******************************************************/ 657 irqreturn_t iwl_pcie_isr(int irq, void *data); 658 int iwl_pcie_alloc_ict(struct iwl_trans *trans); 659 void iwl_pcie_free_ict(struct iwl_trans *trans); 660 void iwl_pcie_reset_ict(struct iwl_trans *trans); 661 void iwl_pcie_disable_ict(struct iwl_trans *trans); 662 663 /***************************************************** 664 * TX / HCMD 665 ******************************************************/ 666 int iwl_pcie_tx_init(struct iwl_trans *trans); 667 int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id, 668 int queue_size); 669 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 670 int iwl_pcie_tx_stop(struct iwl_trans *trans); 671 void iwl_pcie_tx_free(struct iwl_trans *trans); 672 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 673 const struct iwl_trans_txq_scd_cfg *cfg, 674 unsigned int wdg_timeout); 675 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 676 bool configure_scd); 677 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 678 bool shared_mode); 679 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, 680 struct iwl_txq *txq); 681 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 682 struct iwl_device_cmd *dev_cmd, int txq_id); 683 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 684 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 685 void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx); 686 void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans, 687 struct iwl_txq *txq); 688 void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 689 struct iwl_rx_cmd_buffer *rxb); 690 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 691 struct sk_buff_head *skbs); 692 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 693 void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans_pcie *trans_pcie, 694 struct iwl_txq *txq, u16 byte_cnt, 695 int num_tbs); 696 697 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd, 698 u8 idx) 699 { 700 if (trans->cfg->use_tfh) { 701 struct iwl_tfh_tfd *tfd = _tfd; 702 struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 703 704 return le16_to_cpu(tb->tb_len); 705 } else { 706 struct iwl_tfd *tfd = _tfd; 707 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 708 709 return le16_to_cpu(tb->hi_n_len) >> 4; 710 } 711 } 712 713 /***************************************************** 714 * Error handling 715 ******************************************************/ 716 void iwl_pcie_dump_csr(struct iwl_trans *trans); 717 718 /***************************************************** 719 * Helpers 720 ******************************************************/ 721 static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 722 { 723 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 724 725 clear_bit(STATUS_INT_ENABLED, &trans->status); 726 if (!trans_pcie->msix_enabled) { 727 /* disable interrupts from uCode/NIC to host */ 728 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 729 730 /* acknowledge/clear/reset any interrupts still pending 731 * from uCode or flow handler (Rx/Tx DMA) */ 732 iwl_write32(trans, CSR_INT, 0xffffffff); 733 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 734 } else { 735 /* disable all the interrupt we might use */ 736 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 737 trans_pcie->fh_init_mask); 738 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 739 trans_pcie->hw_init_mask); 740 } 741 IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 742 } 743 744 #define IWL_NUM_OF_COMPLETION_RINGS 31 745 #define IWL_NUM_OF_TRANSFER_RINGS 527 746 747 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw, 748 int start) 749 { 750 int i = 0; 751 752 while (start < fw->num_sec && 753 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && 754 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { 755 start++; 756 i++; 757 } 758 759 return i; 760 } 761 762 static inline int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans, 763 const struct fw_desc *sec, 764 struct iwl_dram_data *dram) 765 { 766 dram->block = dma_alloc_coherent(trans->dev, sec->len, 767 &dram->physical, 768 GFP_KERNEL); 769 if (!dram->block) 770 return -ENOMEM; 771 772 dram->size = sec->len; 773 memcpy(dram->block, sec->data, sec->len); 774 775 return 0; 776 } 777 778 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans) 779 { 780 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 781 struct iwl_self_init_dram *dram = &trans_pcie->init_dram; 782 int i; 783 784 if (!dram->fw) { 785 WARN_ON(dram->fw_cnt); 786 return; 787 } 788 789 for (i = 0; i < dram->fw_cnt; i++) 790 dma_free_coherent(trans->dev, dram->fw[i].size, 791 dram->fw[i].block, dram->fw[i].physical); 792 793 kfree(dram->fw); 794 dram->fw_cnt = 0; 795 dram->fw = NULL; 796 } 797 798 static inline void iwl_disable_interrupts(struct iwl_trans *trans) 799 { 800 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 801 802 spin_lock(&trans_pcie->irq_lock); 803 _iwl_disable_interrupts(trans); 804 spin_unlock(&trans_pcie->irq_lock); 805 } 806 807 static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 808 { 809 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 810 811 IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 812 set_bit(STATUS_INT_ENABLED, &trans->status); 813 if (!trans_pcie->msix_enabled) { 814 trans_pcie->inta_mask = CSR_INI_SET_MASK; 815 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 816 } else { 817 /* 818 * fh/hw_mask keeps all the unmasked causes. 819 * Unlike msi, in msix cause is enabled when it is unset. 820 */ 821 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 822 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 823 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 824 ~trans_pcie->fh_mask); 825 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 826 ~trans_pcie->hw_mask); 827 } 828 } 829 830 static inline void iwl_enable_interrupts(struct iwl_trans *trans) 831 { 832 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 833 834 spin_lock(&trans_pcie->irq_lock); 835 _iwl_enable_interrupts(trans); 836 spin_unlock(&trans_pcie->irq_lock); 837 } 838 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 839 { 840 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 841 842 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 843 trans_pcie->hw_mask = msk; 844 } 845 846 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 847 { 848 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 849 850 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 851 trans_pcie->fh_mask = msk; 852 } 853 854 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 855 { 856 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 857 858 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 859 if (!trans_pcie->msix_enabled) { 860 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 861 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 862 } else { 863 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 864 trans_pcie->hw_init_mask); 865 iwl_enable_fh_int_msk_msix(trans, 866 MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 867 } 868 } 869 870 static inline u16 iwl_pcie_get_cmd_index(const struct iwl_txq *q, u32 index) 871 { 872 return index & (q->n_window - 1); 873 } 874 875 static inline void *iwl_pcie_get_tfd(struct iwl_trans *trans, 876 struct iwl_txq *txq, int idx) 877 { 878 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 879 880 if (trans->cfg->use_tfh) 881 idx = iwl_pcie_get_cmd_index(txq, idx); 882 883 return txq->tfds + trans_pcie->tfd_size * idx; 884 } 885 886 static inline const char *queue_name(struct device *dev, 887 struct iwl_trans_pcie *trans_p, int i) 888 { 889 if (trans_p->shared_vec_mask) { 890 int vec = trans_p->shared_vec_mask & 891 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 892 893 if (i == 0) 894 return DRV_NAME ": shared IRQ"; 895 896 return devm_kasprintf(dev, GFP_KERNEL, 897 DRV_NAME ": queue %d", i + vec); 898 } 899 if (i == 0) 900 return DRV_NAME ": default queue"; 901 902 if (i == trans_p->alloc_vecs - 1) 903 return DRV_NAME ": exception"; 904 905 return devm_kasprintf(dev, GFP_KERNEL, 906 DRV_NAME ": queue %d", i); 907 } 908 909 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 910 { 911 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 912 913 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 914 if (!trans_pcie->msix_enabled) { 915 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 916 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 917 } else { 918 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 919 trans_pcie->fh_init_mask); 920 iwl_enable_hw_int_msk_msix(trans, 921 MSIX_HW_INT_CAUSES_REG_RF_KILL); 922 } 923 924 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_9000) { 925 /* 926 * On 9000-series devices this bit isn't enabled by default, so 927 * when we power down the device we need set the bit to allow it 928 * to wake up the PCI-E bus for RF-kill interrupts. 929 */ 930 iwl_set_bit(trans, CSR_GP_CNTRL, 931 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 932 } 933 } 934 935 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans); 936 937 static inline void iwl_wake_queue(struct iwl_trans *trans, 938 struct iwl_txq *txq) 939 { 940 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 941 942 if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) { 943 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id); 944 iwl_op_mode_queue_not_full(trans->op_mode, txq->id); 945 } 946 } 947 948 static inline void iwl_stop_queue(struct iwl_trans *trans, 949 struct iwl_txq *txq) 950 { 951 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 952 953 if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) { 954 iwl_op_mode_queue_full(trans->op_mode, txq->id); 955 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id); 956 } else 957 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 958 txq->id); 959 } 960 961 static inline bool iwl_queue_used(const struct iwl_txq *q, int i) 962 { 963 int index = iwl_pcie_get_cmd_index(q, i); 964 int r = iwl_pcie_get_cmd_index(q, q->read_ptr); 965 int w = iwl_pcie_get_cmd_index(q, q->write_ptr); 966 967 return w >= r ? 968 (index >= r && index < w) : 969 !(index < r && index >= w); 970 } 971 972 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 973 { 974 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 975 976 lockdep_assert_held(&trans_pcie->mutex); 977 978 if (trans_pcie->debug_rfkill) 979 return true; 980 981 return !(iwl_read32(trans, CSR_GP_CNTRL) & 982 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 983 } 984 985 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 986 u32 reg, u32 mask, u32 value) 987 { 988 u32 v; 989 990 #ifdef CONFIG_IWLWIFI_DEBUG 991 WARN_ON_ONCE(value & ~mask); 992 #endif 993 994 v = iwl_read32(trans, reg); 995 v &= ~mask; 996 v |= value; 997 iwl_write32(trans, reg, v); 998 } 999 1000 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 1001 u32 reg, u32 mask) 1002 { 1003 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 1004 } 1005 1006 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 1007 u32 reg, u32 mask) 1008 { 1009 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 1010 } 1011 1012 static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans) 1013 { 1014 return (trans->dbg_dest_tlv || trans->ini_valid); 1015 } 1016 1017 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 1018 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans); 1019 1020 #ifdef CONFIG_IWLWIFI_DEBUGFS 1021 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 1022 #else 1023 static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 1024 { 1025 return 0; 1026 } 1027 #endif 1028 1029 int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans); 1030 int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans); 1031 1032 void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable); 1033 1034 void iwl_pcie_rx_allocator_work(struct work_struct *data); 1035 1036 /* common functions that are used by gen2 transport */ 1037 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans); 1038 void iwl_pcie_apm_config(struct iwl_trans *trans); 1039 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 1040 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 1041 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans); 1042 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1043 bool was_in_rfkill); 1044 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq); 1045 int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q); 1046 void iwl_pcie_apm_stop_master(struct iwl_trans *trans); 1047 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 1048 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 1049 int slots_num, bool cmd_queue); 1050 int iwl_pcie_txq_alloc(struct iwl_trans *trans, 1051 struct iwl_txq *txq, int slots_num, bool cmd_queue); 1052 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 1053 struct iwl_dma_ptr *ptr, size_t size); 1054 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr); 1055 void iwl_pcie_apply_destination(struct iwl_trans *trans); 1056 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 1057 struct sk_buff *skb); 1058 #ifdef CONFIG_INET 1059 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len); 1060 #endif 1061 1062 /* common functions that are used by gen3 transport */ 1063 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power); 1064 1065 /* transport gen 2 exported functions */ 1066 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 1067 const struct fw_img *fw, bool run_in_rfkill); 1068 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr); 1069 void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans, 1070 struct iwl_txq *txq); 1071 int iwl_trans_pcie_dyn_txq_alloc_dma(struct iwl_trans *trans, 1072 struct iwl_txq **intxq, int size, 1073 unsigned int timeout); 1074 int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans, 1075 struct iwl_txq *txq, 1076 struct iwl_host_cmd *hcmd); 1077 int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans, 1078 __le16 flags, u8 sta_id, u8 tid, 1079 int cmd_id, int size, 1080 unsigned int timeout); 1081 void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue); 1082 int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb, 1083 struct iwl_device_cmd *dev_cmd, int txq_id); 1084 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 1085 struct iwl_host_cmd *cmd); 1086 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, 1087 bool low_power); 1088 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power); 1089 void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id); 1090 void iwl_pcie_gen2_tx_free(struct iwl_trans *trans); 1091 void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans); 1092 #endif /* __iwl_trans_int_pcie_h__ */ 1093