1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * The full GNU General Public License is included in this distribution in the 23 * file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #ifndef __iwl_trans_int_pcie_h__ 65 #define __iwl_trans_int_pcie_h__ 66 67 #include <linux/spinlock.h> 68 #include <linux/interrupt.h> 69 #include <linux/skbuff.h> 70 #include <linux/wait.h> 71 #include <linux/pci.h> 72 #include <linux/timer.h> 73 #include <linux/cpu.h> 74 75 #include "iwl-fh.h" 76 #include "iwl-csr.h" 77 #include "iwl-trans.h" 78 #include "iwl-debug.h" 79 #include "iwl-io.h" 80 #include "iwl-op-mode.h" 81 #include "iwl-drv.h" 82 83 /* We need 2 entries for the TX command and header, and another one might 84 * be needed for potential data in the SKB's head. The remaining ones can 85 * be used for frags. 86 */ 87 #define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3) 88 89 /* 90 * RX related structures and functions 91 */ 92 #define RX_NUM_QUEUES 1 93 #define RX_POST_REQ_ALLOC 2 94 #define RX_CLAIM_REQ_ALLOC 8 95 #define RX_PENDING_WATERMARK 16 96 #define FIRST_RX_QUEUE 512 97 98 struct iwl_host_cmd; 99 100 /*This file includes the declaration that are internal to the 101 * trans_pcie layer */ 102 103 /** 104 * struct iwl_rx_mem_buffer 105 * @page_dma: bus address of rxb page 106 * @page: driver's pointer to the rxb page 107 * @invalid: rxb is in driver ownership - not owned by HW 108 * @vid: index of this rxb in the global table 109 * @size: size used from the buffer 110 */ 111 struct iwl_rx_mem_buffer { 112 dma_addr_t page_dma; 113 struct page *page; 114 u16 vid; 115 bool invalid; 116 struct list_head list; 117 u32 size; 118 }; 119 120 /** 121 * struct isr_statistics - interrupt statistics 122 * 123 */ 124 struct isr_statistics { 125 u32 hw; 126 u32 sw; 127 u32 err_code; 128 u32 sch; 129 u32 alive; 130 u32 rfkill; 131 u32 ctkill; 132 u32 wakeup; 133 u32 rx; 134 u32 tx; 135 u32 unhandled; 136 }; 137 138 #define IWL_RX_TD_TYPE_MSK 0xff000000 139 #define IWL_RX_TD_SIZE_MSK 0x00ffffff 140 #define IWL_RX_TD_SIZE_2K BIT(11) 141 #define IWL_RX_TD_TYPE 0 142 143 /** 144 * struct iwl_rx_transfer_desc - transfer descriptor 145 * @type_n_size: buffer type (bit 0: external buff valid, 146 * bit 1: optional footer valid, bit 2-7: reserved) 147 * and buffer size 148 * @addr: ptr to free buffer start address 149 * @rbid: unique tag of the buffer 150 * @reserved: reserved 151 */ 152 struct iwl_rx_transfer_desc { 153 __le32 type_n_size; 154 __le64 addr; 155 __le16 rbid; 156 __le16 reserved; 157 } __packed; 158 159 #define IWL_RX_CD_SIZE 0xffffff00 160 161 /** 162 * struct iwl_rx_completion_desc - completion descriptor 163 * @type: buffer type (bit 0: external buff valid, 164 * bit 1: optional footer valid, bit 2-7: reserved) 165 * @status: status of the completion 166 * @reserved1: reserved 167 * @rbid: unique tag of the received buffer 168 * @size: buffer size, masked by IWL_RX_CD_SIZE 169 * @reserved2: reserved 170 */ 171 struct iwl_rx_completion_desc { 172 u8 type; 173 u8 status; 174 __le16 reserved1; 175 __le16 rbid; 176 __le32 size; 177 u8 reserved2[22]; 178 } __packed; 179 180 /** 181 * struct iwl_rxq - Rx queue 182 * @id: queue index 183 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 184 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 185 * In 22560 devices it is a pointer to a list of iwl_rx_transfer_desc's 186 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 187 * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd) 188 * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd) 189 * @tr_tail: driver's pointer to the transmission ring tail buffer 190 * @tr_tail_dma: physical address of the buffer for the transmission ring tail 191 * @cr_tail: driver's pointer to the completion ring tail buffer 192 * @cr_tail_dma: physical address of the buffer for the completion ring tail 193 * @read: Shared index to newest available Rx buffer 194 * @write: Shared index to oldest written Rx packet 195 * @free_count: Number of pre-allocated buffers in rx_free 196 * @used_count: Number of RBDs handled to allocator to use for allocation 197 * @write_actual: 198 * @rx_free: list of RBDs with allocated RB ready for use 199 * @rx_used: list of RBDs with no RB attached 200 * @need_update: flag to indicate we need to update read/write index 201 * @rb_stts: driver's pointer to receive buffer status 202 * @rb_stts_dma: bus address of receive buffer status 203 * @lock: 204 * @queue: actual rx queue. Not used for multi-rx queue. 205 * 206 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 207 */ 208 struct iwl_rxq { 209 int id; 210 void *bd; 211 dma_addr_t bd_dma; 212 union { 213 void *used_bd; 214 __le32 *bd_32; 215 struct iwl_rx_completion_desc *cd; 216 }; 217 dma_addr_t used_bd_dma; 218 __le16 *tr_tail; 219 dma_addr_t tr_tail_dma; 220 __le16 *cr_tail; 221 dma_addr_t cr_tail_dma; 222 u32 read; 223 u32 write; 224 u32 free_count; 225 u32 used_count; 226 u32 write_actual; 227 u32 queue_size; 228 struct list_head rx_free; 229 struct list_head rx_used; 230 bool need_update; 231 void *rb_stts; 232 dma_addr_t rb_stts_dma; 233 spinlock_t lock; 234 struct napi_struct napi; 235 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 236 }; 237 238 /** 239 * struct iwl_rb_allocator - Rx allocator 240 * @req_pending: number of requests the allcator had not processed yet 241 * @req_ready: number of requests honored and ready for claiming 242 * @rbd_allocated: RBDs with pages allocated and ready to be handled to 243 * the queue. This is a list of &struct iwl_rx_mem_buffer 244 * @rbd_empty: RBDs with no page attached for allocator use. This is a list 245 * of &struct iwl_rx_mem_buffer 246 * @lock: protects the rbd_allocated and rbd_empty lists 247 * @alloc_wq: work queue for background calls 248 * @rx_alloc: work struct for background calls 249 */ 250 struct iwl_rb_allocator { 251 atomic_t req_pending; 252 atomic_t req_ready; 253 struct list_head rbd_allocated; 254 struct list_head rbd_empty; 255 spinlock_t lock; 256 struct workqueue_struct *alloc_wq; 257 struct work_struct rx_alloc; 258 }; 259 260 struct iwl_dma_ptr { 261 dma_addr_t dma; 262 void *addr; 263 size_t size; 264 }; 265 266 /** 267 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 268 * @index -- current index 269 */ 270 static inline int iwl_queue_inc_wrap(struct iwl_trans *trans, int index) 271 { 272 return ++index & (trans->cfg->base_params->max_tfd_queue_size - 1); 273 } 274 275 /** 276 * iwl_get_closed_rb_stts - get closed rb stts from different structs 277 * @rxq - the rxq to get the rb stts from 278 */ 279 static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans, 280 struct iwl_rxq *rxq) 281 { 282 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 283 __le16 *rb_stts = rxq->rb_stts; 284 285 return READ_ONCE(*rb_stts); 286 } else { 287 struct iwl_rb_status *rb_stts = rxq->rb_stts; 288 289 return READ_ONCE(rb_stts->closed_rb_num); 290 } 291 } 292 293 /** 294 * iwl_queue_dec_wrap - decrement queue index, wrap back to end 295 * @index -- current index 296 */ 297 static inline int iwl_queue_dec_wrap(struct iwl_trans *trans, int index) 298 { 299 return --index & (trans->cfg->base_params->max_tfd_queue_size - 1); 300 } 301 302 struct iwl_cmd_meta { 303 /* only for SYNC commands, iff the reply skb is wanted */ 304 struct iwl_host_cmd *source; 305 u32 flags; 306 u32 tbs; 307 }; 308 309 310 #define TFD_TX_CMD_SLOTS 256 311 #define TFD_CMD_SLOTS 32 312 313 /* 314 * The FH will write back to the first TB only, so we need to copy some data 315 * into the buffer regardless of whether it should be mapped or not. 316 * This indicates how big the first TB must be to include the scratch buffer 317 * and the assigned PN. 318 * Since PN location is 8 bytes at offset 12, it's 20 now. 319 * If we make it bigger then allocations will be bigger and copy slower, so 320 * that's probably not useful. 321 */ 322 #define IWL_FIRST_TB_SIZE 20 323 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 324 325 struct iwl_pcie_txq_entry { 326 struct iwl_device_cmd *cmd; 327 struct sk_buff *skb; 328 /* buffer to free after command completes */ 329 const void *free_buf; 330 struct iwl_cmd_meta meta; 331 }; 332 333 struct iwl_pcie_first_tb_buf { 334 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 335 }; 336 337 /** 338 * struct iwl_txq - Tx Queue for DMA 339 * @q: generic Rx/Tx queue descriptor 340 * @tfds: transmit frame descriptors (DMA memory) 341 * @first_tb_bufs: start of command headers, including scratch buffers, for 342 * the writeback -- this is DMA memory and an array holding one buffer 343 * for each command on the queue 344 * @first_tb_dma: DMA address for the first_tb_bufs start 345 * @entries: transmit entries (driver state) 346 * @lock: queue lock 347 * @stuck_timer: timer that fires if queue gets stuck 348 * @trans_pcie: pointer back to transport (for timer) 349 * @need_update: indicates need to update read/write index 350 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 351 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 352 * @frozen: tx stuck queue timer is frozen 353 * @frozen_expiry_remainder: remember how long until the timer fires 354 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 355 * @write_ptr: 1-st empty entry (index) host_w 356 * @read_ptr: last used entry (index) host_r 357 * @dma_addr: physical addr for BD's 358 * @n_window: safe queue window 359 * @id: queue id 360 * @low_mark: low watermark, resume queue if free space more than this 361 * @high_mark: high watermark, stop queue if free space less than this 362 * 363 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 364 * descriptors) and required locking structures. 365 * 366 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 367 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 368 * there might be HW changes in the future). For the normal TX 369 * queues, n_window, which is the size of the software queue data 370 * is also 256; however, for the command queue, n_window is only 371 * 32 since we don't need so many commands pending. Since the HW 372 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 373 * This means that we end up with the following: 374 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 375 * SW entries: | 0 | ... | 31 | 376 * where N is a number between 0 and 7. This means that the SW 377 * data is a window overlayed over the HW queue. 378 */ 379 struct iwl_txq { 380 void *tfds; 381 struct iwl_pcie_first_tb_buf *first_tb_bufs; 382 dma_addr_t first_tb_dma; 383 struct iwl_pcie_txq_entry *entries; 384 spinlock_t lock; 385 unsigned long frozen_expiry_remainder; 386 struct timer_list stuck_timer; 387 struct iwl_trans_pcie *trans_pcie; 388 bool need_update; 389 bool frozen; 390 bool ampdu; 391 int block; 392 unsigned long wd_timeout; 393 struct sk_buff_head overflow_q; 394 struct iwl_dma_ptr bc_tbl; 395 396 int write_ptr; 397 int read_ptr; 398 dma_addr_t dma_addr; 399 int n_window; 400 u32 id; 401 int low_mark; 402 int high_mark; 403 404 bool overflow_tx; 405 }; 406 407 static inline dma_addr_t 408 iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx) 409 { 410 return txq->first_tb_dma + 411 sizeof(struct iwl_pcie_first_tb_buf) * idx; 412 } 413 414 struct iwl_tso_hdr_page { 415 struct page *page; 416 u8 *pos; 417 }; 418 419 #ifdef CONFIG_IWLWIFI_DEBUGFS 420 /** 421 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data 422 * debugfs file 423 * 424 * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed. 425 * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open. 426 * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is 427 * set the file can no longer be used. 428 */ 429 enum iwl_fw_mon_dbgfs_state { 430 IWL_FW_MON_DBGFS_STATE_CLOSED, 431 IWL_FW_MON_DBGFS_STATE_OPEN, 432 IWL_FW_MON_DBGFS_STATE_DISABLED, 433 }; 434 #endif 435 436 /** 437 * enum iwl_shared_irq_flags - level of sharing for irq 438 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 439 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 440 */ 441 enum iwl_shared_irq_flags { 442 IWL_SHARED_IRQ_NON_RX = BIT(0), 443 IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 444 }; 445 446 /** 447 * enum iwl_image_response_code - image response values 448 * @IWL_IMAGE_RESP_DEF: the default value of the register 449 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully 450 * @IWL_IMAGE_RESP_FAIL: iml reading failed 451 */ 452 enum iwl_image_response_code { 453 IWL_IMAGE_RESP_DEF = 0, 454 IWL_IMAGE_RESP_SUCCESS = 1, 455 IWL_IMAGE_RESP_FAIL = 2, 456 }; 457 458 /** 459 * struct cont_rec: continuous recording data structure 460 * @prev_wr_ptr: the last address that was read in monitor_data 461 * debugfs file 462 * @prev_wrap_cnt: the wrap count that was used during the last read in 463 * monitor_data debugfs file 464 * @state: the state of monitor_data debugfs file as described 465 * in &iwl_fw_mon_dbgfs_state enum 466 * @mutex: locked while reading from monitor_data debugfs file 467 */ 468 #ifdef CONFIG_IWLWIFI_DEBUGFS 469 struct cont_rec { 470 u32 prev_wr_ptr; 471 u32 prev_wrap_cnt; 472 u8 state; 473 /* Used to sync monitor_data debugfs file with driver unload flow */ 474 struct mutex mutex; 475 }; 476 #endif 477 478 /** 479 * struct iwl_trans_pcie - PCIe transport specific data 480 * @rxq: all the RX queue data 481 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 482 * @global_table: table mapping received VID from hw to rxb 483 * @rba: allocator for RX replenishing 484 * @ctxt_info: context information for FW self init 485 * @ctxt_info_gen3: context information for gen3 devices 486 * @prph_info: prph info for self init 487 * @prph_scratch: prph scratch for self init 488 * @ctxt_info_dma_addr: dma addr of context information 489 * @prph_info_dma_addr: dma addr of prph info 490 * @prph_scratch_dma_addr: dma addr of prph scratch 491 * @ctxt_info_dma_addr: dma addr of context information 492 * @init_dram: DRAM data of firmware image (including paging). 493 * Context information addresses will be taken from here. 494 * This is driver's local copy for keeping track of size and 495 * count for allocating and freeing the memory. 496 * @trans: pointer to the generic transport area 497 * @scd_base_addr: scheduler sram base address in SRAM 498 * @scd_bc_tbls: pointer to the byte count table of the scheduler 499 * @kw: keep warm address 500 * @pci_dev: basic pci-network driver stuff 501 * @hw_base: pci hardware address support 502 * @ucode_write_complete: indicates that the ucode has been copied. 503 * @ucode_write_waitq: wait queue for uCode load 504 * @cmd_queue - command queue number 505 * @def_rx_queue - default rx queue number 506 * @rx_buf_size: Rx buffer size 507 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 508 * @scd_set_active: should the transport configure the SCD for HCMD queue 509 * @sw_csum_tx: if true, then the transport will compute the csum of the TXed 510 * frame. 511 * @rx_page_order: page order for receive buffer size 512 * @reg_lock: protect hw register access 513 * @mutex: to protect stop_device / start_fw / start_hw 514 * @cmd_in_flight: true when we have a host command in flight 515 #ifdef CONFIG_IWLWIFI_DEBUGFS 516 * @fw_mon_data: fw continuous recording data 517 #endif 518 * @msix_entries: array of MSI-X entries 519 * @msix_enabled: true if managed to enable MSI-X 520 * @shared_vec_mask: the type of causes the shared vector handles 521 * (see iwl_shared_irq_flags). 522 * @alloc_vecs: the number of interrupt vectors allocated by the OS 523 * @def_irq: default irq for non rx causes 524 * @fh_init_mask: initial unmasked fh causes 525 * @hw_init_mask: initial unmasked hw causes 526 * @fh_mask: current unmasked fh causes 527 * @hw_mask: current unmasked hw causes 528 * @in_rescan: true if we have triggered a device rescan 529 * @base_rb_stts: base virtual address of receive buffer status for all queues 530 * @base_rb_stts_dma: base physical address of receive buffer status 531 */ 532 struct iwl_trans_pcie { 533 struct iwl_rxq *rxq; 534 struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE]; 535 struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE]; 536 struct iwl_rb_allocator rba; 537 union { 538 struct iwl_context_info *ctxt_info; 539 struct iwl_context_info_gen3 *ctxt_info_gen3; 540 }; 541 struct iwl_prph_info *prph_info; 542 struct iwl_prph_scratch *prph_scratch; 543 dma_addr_t ctxt_info_dma_addr; 544 dma_addr_t prph_info_dma_addr; 545 dma_addr_t prph_scratch_dma_addr; 546 dma_addr_t iml_dma_addr; 547 struct iwl_trans *trans; 548 549 struct net_device napi_dev; 550 551 struct __percpu iwl_tso_hdr_page *tso_hdr_page; 552 553 /* INT ICT Table */ 554 __le32 *ict_tbl; 555 dma_addr_t ict_tbl_dma; 556 int ict_index; 557 bool use_ict; 558 bool is_down, opmode_down; 559 bool debug_rfkill; 560 struct isr_statistics isr_stats; 561 562 spinlock_t irq_lock; 563 struct mutex mutex; 564 u32 inta_mask; 565 u32 scd_base_addr; 566 struct iwl_dma_ptr scd_bc_tbls; 567 struct iwl_dma_ptr kw; 568 569 struct iwl_txq *txq_memory; 570 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 571 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 572 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 573 574 /* PCI bus related data */ 575 struct pci_dev *pci_dev; 576 void __iomem *hw_base; 577 578 bool ucode_write_complete; 579 wait_queue_head_t ucode_write_waitq; 580 wait_queue_head_t wait_command_queue; 581 wait_queue_head_t d0i3_waitq; 582 583 u8 page_offs, dev_cmd_offs; 584 585 u8 cmd_queue; 586 u8 def_rx_queue; 587 u8 cmd_fifo; 588 unsigned int cmd_q_wdg_timeout; 589 u8 n_no_reclaim_cmds; 590 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 591 u8 max_tbs; 592 u16 tfd_size; 593 594 enum iwl_amsdu_size rx_buf_size; 595 bool bc_table_dword; 596 bool scd_set_active; 597 bool sw_csum_tx; 598 bool pcie_dbg_dumped_once; 599 u32 rx_page_order; 600 601 /*protect hw register */ 602 spinlock_t reg_lock; 603 bool cmd_hold_nic_awake; 604 bool ref_cmd_in_flight; 605 606 #ifdef CONFIG_IWLWIFI_DEBUGFS 607 struct cont_rec fw_mon_data; 608 #endif 609 610 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 611 bool msix_enabled; 612 u8 shared_vec_mask; 613 u32 alloc_vecs; 614 u32 def_irq; 615 u32 fh_init_mask; 616 u32 hw_init_mask; 617 u32 fh_mask; 618 u32 hw_mask; 619 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 620 u16 tx_cmd_queue_size; 621 bool in_rescan; 622 623 void *base_rb_stts; 624 dma_addr_t base_rb_stts_dma; 625 }; 626 627 static inline struct iwl_trans_pcie * 628 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 629 { 630 return (void *)trans->trans_specific; 631 } 632 633 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 634 struct msix_entry *entry) 635 { 636 /* 637 * Before sending the interrupt the HW disables it to prevent 638 * a nested interrupt. This is done by writing 1 to the corresponding 639 * bit in the mask register. After handling the interrupt, it should be 640 * re-enabled by clearing this bit. This register is defined as 641 * write 1 clear (W1C) register, meaning that it's being clear 642 * by writing 1 to the bit. 643 */ 644 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 645 } 646 647 static inline struct iwl_trans * 648 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 649 { 650 return container_of((void *)trans_pcie, struct iwl_trans, 651 trans_specific); 652 } 653 654 /* 655 * Convention: trans API functions: iwl_trans_pcie_XXX 656 * Other functions: iwl_pcie_XXX 657 */ 658 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 659 const struct pci_device_id *ent, 660 const struct iwl_cfg *cfg); 661 void iwl_trans_pcie_free(struct iwl_trans *trans); 662 663 /***************************************************** 664 * RX 665 ******************************************************/ 666 int _iwl_pcie_rx_init(struct iwl_trans *trans); 667 int iwl_pcie_rx_init(struct iwl_trans *trans); 668 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 669 irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 670 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 671 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 672 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 673 int iwl_pcie_rx_stop(struct iwl_trans *trans); 674 void iwl_pcie_rx_free(struct iwl_trans *trans); 675 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans); 676 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq); 677 int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget); 678 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 679 struct iwl_rxq *rxq); 680 int iwl_pcie_rx_alloc(struct iwl_trans *trans); 681 682 /***************************************************** 683 * ICT - interrupt handling 684 ******************************************************/ 685 irqreturn_t iwl_pcie_isr(int irq, void *data); 686 int iwl_pcie_alloc_ict(struct iwl_trans *trans); 687 void iwl_pcie_free_ict(struct iwl_trans *trans); 688 void iwl_pcie_reset_ict(struct iwl_trans *trans); 689 void iwl_pcie_disable_ict(struct iwl_trans *trans); 690 691 /***************************************************** 692 * TX / HCMD 693 ******************************************************/ 694 int iwl_pcie_tx_init(struct iwl_trans *trans); 695 int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id, 696 int queue_size); 697 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 698 int iwl_pcie_tx_stop(struct iwl_trans *trans); 699 void iwl_pcie_tx_free(struct iwl_trans *trans); 700 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 701 const struct iwl_trans_txq_scd_cfg *cfg, 702 unsigned int wdg_timeout); 703 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 704 bool configure_scd); 705 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 706 bool shared_mode); 707 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, 708 struct iwl_txq *txq); 709 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 710 struct iwl_device_cmd *dev_cmd, int txq_id); 711 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 712 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 713 void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx); 714 void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans, 715 struct iwl_txq *txq); 716 void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 717 struct iwl_rx_cmd_buffer *rxb); 718 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 719 struct sk_buff_head *skbs); 720 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 721 void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans_pcie *trans_pcie, 722 struct iwl_txq *txq, u16 byte_cnt, 723 int num_tbs); 724 725 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd, 726 u8 idx) 727 { 728 if (trans->cfg->use_tfh) { 729 struct iwl_tfh_tfd *tfd = _tfd; 730 struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 731 732 return le16_to_cpu(tb->tb_len); 733 } else { 734 struct iwl_tfd *tfd = _tfd; 735 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 736 737 return le16_to_cpu(tb->hi_n_len) >> 4; 738 } 739 } 740 741 /***************************************************** 742 * Error handling 743 ******************************************************/ 744 void iwl_pcie_dump_csr(struct iwl_trans *trans); 745 746 /***************************************************** 747 * Helpers 748 ******************************************************/ 749 static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 750 { 751 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 752 753 clear_bit(STATUS_INT_ENABLED, &trans->status); 754 if (!trans_pcie->msix_enabled) { 755 /* disable interrupts from uCode/NIC to host */ 756 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 757 758 /* acknowledge/clear/reset any interrupts still pending 759 * from uCode or flow handler (Rx/Tx DMA) */ 760 iwl_write32(trans, CSR_INT, 0xffffffff); 761 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 762 } else { 763 /* disable all the interrupt we might use */ 764 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 765 trans_pcie->fh_init_mask); 766 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 767 trans_pcie->hw_init_mask); 768 } 769 IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 770 } 771 772 #define IWL_NUM_OF_COMPLETION_RINGS 31 773 #define IWL_NUM_OF_TRANSFER_RINGS 527 774 775 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw, 776 int start) 777 { 778 int i = 0; 779 780 while (start < fw->num_sec && 781 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && 782 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { 783 start++; 784 i++; 785 } 786 787 return i; 788 } 789 790 static inline int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans, 791 const struct fw_desc *sec, 792 struct iwl_dram_data *dram) 793 { 794 dram->block = dma_alloc_coherent(trans->dev, sec->len, 795 &dram->physical, 796 GFP_KERNEL); 797 if (!dram->block) 798 return -ENOMEM; 799 800 dram->size = sec->len; 801 memcpy(dram->block, sec->data, sec->len); 802 803 return 0; 804 } 805 806 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans) 807 { 808 struct iwl_self_init_dram *dram = &trans->init_dram; 809 int i; 810 811 if (!dram->fw) { 812 WARN_ON(dram->fw_cnt); 813 return; 814 } 815 816 for (i = 0; i < dram->fw_cnt; i++) 817 dma_free_coherent(trans->dev, dram->fw[i].size, 818 dram->fw[i].block, dram->fw[i].physical); 819 820 kfree(dram->fw); 821 dram->fw_cnt = 0; 822 dram->fw = NULL; 823 } 824 825 static inline void iwl_disable_interrupts(struct iwl_trans *trans) 826 { 827 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 828 829 spin_lock(&trans_pcie->irq_lock); 830 _iwl_disable_interrupts(trans); 831 spin_unlock(&trans_pcie->irq_lock); 832 } 833 834 static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 835 { 836 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 837 838 IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 839 set_bit(STATUS_INT_ENABLED, &trans->status); 840 if (!trans_pcie->msix_enabled) { 841 trans_pcie->inta_mask = CSR_INI_SET_MASK; 842 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 843 } else { 844 /* 845 * fh/hw_mask keeps all the unmasked causes. 846 * Unlike msi, in msix cause is enabled when it is unset. 847 */ 848 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 849 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 850 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 851 ~trans_pcie->fh_mask); 852 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 853 ~trans_pcie->hw_mask); 854 } 855 } 856 857 static inline void iwl_enable_interrupts(struct iwl_trans *trans) 858 { 859 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 860 861 spin_lock(&trans_pcie->irq_lock); 862 _iwl_enable_interrupts(trans); 863 spin_unlock(&trans_pcie->irq_lock); 864 } 865 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 866 { 867 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 868 869 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 870 trans_pcie->hw_mask = msk; 871 } 872 873 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 874 { 875 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 876 877 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 878 trans_pcie->fh_mask = msk; 879 } 880 881 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 882 { 883 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 884 885 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 886 if (!trans_pcie->msix_enabled) { 887 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 888 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 889 } else { 890 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 891 trans_pcie->hw_init_mask); 892 iwl_enable_fh_int_msk_msix(trans, 893 MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 894 } 895 } 896 897 static inline u16 iwl_pcie_get_cmd_index(const struct iwl_txq *q, u32 index) 898 { 899 return index & (q->n_window - 1); 900 } 901 902 static inline void *iwl_pcie_get_tfd(struct iwl_trans *trans, 903 struct iwl_txq *txq, int idx) 904 { 905 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 906 907 if (trans->cfg->use_tfh) 908 idx = iwl_pcie_get_cmd_index(txq, idx); 909 910 return txq->tfds + trans_pcie->tfd_size * idx; 911 } 912 913 static inline const char *queue_name(struct device *dev, 914 struct iwl_trans_pcie *trans_p, int i) 915 { 916 if (trans_p->shared_vec_mask) { 917 int vec = trans_p->shared_vec_mask & 918 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 919 920 if (i == 0) 921 return DRV_NAME ": shared IRQ"; 922 923 return devm_kasprintf(dev, GFP_KERNEL, 924 DRV_NAME ": queue %d", i + vec); 925 } 926 if (i == 0) 927 return DRV_NAME ": default queue"; 928 929 if (i == trans_p->alloc_vecs - 1) 930 return DRV_NAME ": exception"; 931 932 return devm_kasprintf(dev, GFP_KERNEL, 933 DRV_NAME ": queue %d", i); 934 } 935 936 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 937 { 938 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 939 940 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 941 if (!trans_pcie->msix_enabled) { 942 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 943 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 944 } else { 945 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 946 trans_pcie->fh_init_mask); 947 iwl_enable_hw_int_msk_msix(trans, 948 MSIX_HW_INT_CAUSES_REG_RF_KILL); 949 } 950 951 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_9000) { 952 /* 953 * On 9000-series devices this bit isn't enabled by default, so 954 * when we power down the device we need set the bit to allow it 955 * to wake up the PCI-E bus for RF-kill interrupts. 956 */ 957 iwl_set_bit(trans, CSR_GP_CNTRL, 958 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 959 } 960 } 961 962 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans); 963 964 static inline void iwl_wake_queue(struct iwl_trans *trans, 965 struct iwl_txq *txq) 966 { 967 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 968 969 if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) { 970 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id); 971 iwl_op_mode_queue_not_full(trans->op_mode, txq->id); 972 } 973 } 974 975 static inline void iwl_stop_queue(struct iwl_trans *trans, 976 struct iwl_txq *txq) 977 { 978 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 979 980 if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) { 981 iwl_op_mode_queue_full(trans->op_mode, txq->id); 982 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id); 983 } else 984 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 985 txq->id); 986 } 987 988 static inline bool iwl_queue_used(const struct iwl_txq *q, int i) 989 { 990 int index = iwl_pcie_get_cmd_index(q, i); 991 int r = iwl_pcie_get_cmd_index(q, q->read_ptr); 992 int w = iwl_pcie_get_cmd_index(q, q->write_ptr); 993 994 return w >= r ? 995 (index >= r && index < w) : 996 !(index < r && index >= w); 997 } 998 999 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 1000 { 1001 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1002 1003 lockdep_assert_held(&trans_pcie->mutex); 1004 1005 if (trans_pcie->debug_rfkill) 1006 return true; 1007 1008 return !(iwl_read32(trans, CSR_GP_CNTRL) & 1009 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 1010 } 1011 1012 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 1013 u32 reg, u32 mask, u32 value) 1014 { 1015 u32 v; 1016 1017 #ifdef CONFIG_IWLWIFI_DEBUG 1018 WARN_ON_ONCE(value & ~mask); 1019 #endif 1020 1021 v = iwl_read32(trans, reg); 1022 v &= ~mask; 1023 v |= value; 1024 iwl_write32(trans, reg, v); 1025 } 1026 1027 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 1028 u32 reg, u32 mask) 1029 { 1030 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 1031 } 1032 1033 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 1034 u32 reg, u32 mask) 1035 { 1036 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 1037 } 1038 1039 static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans) 1040 { 1041 return (trans->dbg_dest_tlv || trans->ini_valid); 1042 } 1043 1044 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 1045 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans); 1046 void iwl_trans_sync_nmi(struct iwl_trans *trans); 1047 1048 #ifdef CONFIG_IWLWIFI_DEBUGFS 1049 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 1050 #else 1051 static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 1052 { 1053 return 0; 1054 } 1055 #endif 1056 1057 int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans); 1058 int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans); 1059 1060 void iwl_pcie_rx_allocator_work(struct work_struct *data); 1061 1062 /* common functions that are used by gen2 transport */ 1063 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans); 1064 void iwl_pcie_apm_config(struct iwl_trans *trans); 1065 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 1066 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 1067 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans); 1068 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1069 bool was_in_rfkill); 1070 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq); 1071 int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q); 1072 void iwl_pcie_apm_stop_master(struct iwl_trans *trans); 1073 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 1074 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 1075 int slots_num, bool cmd_queue); 1076 int iwl_pcie_txq_alloc(struct iwl_trans *trans, 1077 struct iwl_txq *txq, int slots_num, bool cmd_queue); 1078 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 1079 struct iwl_dma_ptr *ptr, size_t size); 1080 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr); 1081 void iwl_pcie_apply_destination(struct iwl_trans *trans); 1082 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 1083 struct sk_buff *skb); 1084 #ifdef CONFIG_INET 1085 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len); 1086 #endif 1087 1088 /* common functions that are used by gen3 transport */ 1089 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power); 1090 1091 /* transport gen 2 exported functions */ 1092 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 1093 const struct fw_img *fw, bool run_in_rfkill); 1094 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr); 1095 void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans, 1096 struct iwl_txq *txq); 1097 int iwl_trans_pcie_dyn_txq_alloc_dma(struct iwl_trans *trans, 1098 struct iwl_txq **intxq, int size, 1099 unsigned int timeout); 1100 int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans, 1101 struct iwl_txq *txq, 1102 struct iwl_host_cmd *hcmd); 1103 int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans, 1104 __le16 flags, u8 sta_id, u8 tid, 1105 int cmd_id, int size, 1106 unsigned int timeout); 1107 void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue); 1108 int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb, 1109 struct iwl_device_cmd *dev_cmd, int txq_id); 1110 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 1111 struct iwl_host_cmd *cmd); 1112 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, 1113 bool low_power); 1114 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power); 1115 void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id); 1116 void iwl_pcie_gen2_tx_free(struct iwl_trans *trans); 1117 void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans); 1118 #endif /* __iwl_trans_int_pcie_h__ */ 1119