1 /****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6 * Copyright(c) 2018 Intel Corporation 7 * 8 * Portions of this file are derived from the ipw3945 project, as well 9 * as portions of the ieee80211 subsystem header files. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * The full GNU General Public License is included in this distribution in the 21 * file called LICENSE. 22 * 23 * Contact Information: 24 * Intel Linux Wireless <linuxwifi@intel.com> 25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 * 27 *****************************************************************************/ 28 #ifndef __iwl_trans_int_pcie_h__ 29 #define __iwl_trans_int_pcie_h__ 30 31 #include <linux/spinlock.h> 32 #include <linux/interrupt.h> 33 #include <linux/skbuff.h> 34 #include <linux/wait.h> 35 #include <linux/pci.h> 36 #include <linux/timer.h> 37 #include <linux/cpu.h> 38 39 #include "iwl-fh.h" 40 #include "iwl-csr.h" 41 #include "iwl-trans.h" 42 #include "iwl-debug.h" 43 #include "iwl-io.h" 44 #include "iwl-op-mode.h" 45 #include "iwl-drv.h" 46 47 /* We need 2 entries for the TX command and header, and another one might 48 * be needed for potential data in the SKB's head. The remaining ones can 49 * be used for frags. 50 */ 51 #define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3) 52 53 /* 54 * RX related structures and functions 55 */ 56 #define RX_NUM_QUEUES 1 57 #define RX_POST_REQ_ALLOC 2 58 #define RX_CLAIM_REQ_ALLOC 8 59 #define RX_PENDING_WATERMARK 16 60 #define FIRST_RX_QUEUE 512 61 62 struct iwl_host_cmd; 63 64 /*This file includes the declaration that are internal to the 65 * trans_pcie layer */ 66 67 /** 68 * struct iwl_rx_mem_buffer 69 * @page_dma: bus address of rxb page 70 * @page: driver's pointer to the rxb page 71 * @invalid: rxb is in driver ownership - not owned by HW 72 * @vid: index of this rxb in the global table 73 * @size: size used from the buffer 74 */ 75 struct iwl_rx_mem_buffer { 76 dma_addr_t page_dma; 77 struct page *page; 78 u16 vid; 79 bool invalid; 80 struct list_head list; 81 u32 size; 82 }; 83 84 /** 85 * struct isr_statistics - interrupt statistics 86 * 87 */ 88 struct isr_statistics { 89 u32 hw; 90 u32 sw; 91 u32 err_code; 92 u32 sch; 93 u32 alive; 94 u32 rfkill; 95 u32 ctkill; 96 u32 wakeup; 97 u32 rx; 98 u32 tx; 99 u32 unhandled; 100 }; 101 102 #define IWL_RX_TD_TYPE_MSK 0xff000000 103 #define IWL_RX_TD_SIZE_MSK 0x00ffffff 104 #define IWL_RX_TD_SIZE_2K BIT(11) 105 #define IWL_RX_TD_TYPE 0 106 107 /** 108 * struct iwl_rx_transfer_desc - transfer descriptor 109 * @type_n_size: buffer type (bit 0: external buff valid, 110 * bit 1: optional footer valid, bit 2-7: reserved) 111 * and buffer size 112 * @addr: ptr to free buffer start address 113 * @rbid: unique tag of the buffer 114 * @reserved: reserved 115 */ 116 struct iwl_rx_transfer_desc { 117 __le32 type_n_size; 118 __le64 addr; 119 __le16 rbid; 120 __le16 reserved; 121 } __packed; 122 123 #define IWL_RX_CD_SIZE 0xffffff00 124 125 /** 126 * struct iwl_rx_completion_desc - completion descriptor 127 * @type: buffer type (bit 0: external buff valid, 128 * bit 1: optional footer valid, bit 2-7: reserved) 129 * @status: status of the completion 130 * @reserved1: reserved 131 * @rbid: unique tag of the received buffer 132 * @size: buffer size, masked by IWL_RX_CD_SIZE 133 * @reserved2: reserved 134 */ 135 struct iwl_rx_completion_desc { 136 u8 type; 137 u8 status; 138 __le16 reserved1; 139 __le16 rbid; 140 __le32 size; 141 u8 reserved2[22]; 142 } __packed; 143 144 /** 145 * struct iwl_rxq - Rx queue 146 * @id: queue index 147 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 148 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 149 * In 22560 devices it is a pointer to a list of iwl_rx_transfer_desc's 150 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 151 * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd) 152 * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd) 153 * @tr_tail: driver's pointer to the transmission ring tail buffer 154 * @tr_tail_dma: physical address of the buffer for the transmission ring tail 155 * @cr_tail: driver's pointer to the completion ring tail buffer 156 * @cr_tail_dma: physical address of the buffer for the completion ring tail 157 * @read: Shared index to newest available Rx buffer 158 * @write: Shared index to oldest written Rx packet 159 * @free_count: Number of pre-allocated buffers in rx_free 160 * @used_count: Number of RBDs handled to allocator to use for allocation 161 * @write_actual: 162 * @rx_free: list of RBDs with allocated RB ready for use 163 * @rx_used: list of RBDs with no RB attached 164 * @need_update: flag to indicate we need to update read/write index 165 * @rb_stts: driver's pointer to receive buffer status 166 * @rb_stts_dma: bus address of receive buffer status 167 * @lock: 168 * @queue: actual rx queue. Not used for multi-rx queue. 169 * 170 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 171 */ 172 struct iwl_rxq { 173 int id; 174 void *bd; 175 dma_addr_t bd_dma; 176 union { 177 void *used_bd; 178 __le32 *bd_32; 179 struct iwl_rx_completion_desc *cd; 180 }; 181 dma_addr_t used_bd_dma; 182 __le16 *tr_tail; 183 dma_addr_t tr_tail_dma; 184 __le16 *cr_tail; 185 dma_addr_t cr_tail_dma; 186 u32 read; 187 u32 write; 188 u32 free_count; 189 u32 used_count; 190 u32 write_actual; 191 u32 queue_size; 192 struct list_head rx_free; 193 struct list_head rx_used; 194 bool need_update; 195 void *rb_stts; 196 dma_addr_t rb_stts_dma; 197 spinlock_t lock; 198 struct napi_struct napi; 199 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 200 }; 201 202 /** 203 * struct iwl_rb_allocator - Rx allocator 204 * @req_pending: number of requests the allcator had not processed yet 205 * @req_ready: number of requests honored and ready for claiming 206 * @rbd_allocated: RBDs with pages allocated and ready to be handled to 207 * the queue. This is a list of &struct iwl_rx_mem_buffer 208 * @rbd_empty: RBDs with no page attached for allocator use. This is a list 209 * of &struct iwl_rx_mem_buffer 210 * @lock: protects the rbd_allocated and rbd_empty lists 211 * @alloc_wq: work queue for background calls 212 * @rx_alloc: work struct for background calls 213 */ 214 struct iwl_rb_allocator { 215 atomic_t req_pending; 216 atomic_t req_ready; 217 struct list_head rbd_allocated; 218 struct list_head rbd_empty; 219 spinlock_t lock; 220 struct workqueue_struct *alloc_wq; 221 struct work_struct rx_alloc; 222 }; 223 224 struct iwl_dma_ptr { 225 dma_addr_t dma; 226 void *addr; 227 size_t size; 228 }; 229 230 /** 231 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 232 * @index -- current index 233 */ 234 static inline int iwl_queue_inc_wrap(struct iwl_trans *trans, int index) 235 { 236 return ++index & (trans->cfg->base_params->max_tfd_queue_size - 1); 237 } 238 239 /** 240 * iwl_get_closed_rb_stts - get closed rb stts from different structs 241 * @rxq - the rxq to get the rb stts from 242 */ 243 static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans, 244 struct iwl_rxq *rxq) 245 { 246 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 247 __le16 *rb_stts = rxq->rb_stts; 248 249 return READ_ONCE(*rb_stts); 250 } else { 251 struct iwl_rb_status *rb_stts = rxq->rb_stts; 252 253 return READ_ONCE(rb_stts->closed_rb_num); 254 } 255 } 256 257 /** 258 * iwl_queue_dec_wrap - decrement queue index, wrap back to end 259 * @index -- current index 260 */ 261 static inline int iwl_queue_dec_wrap(struct iwl_trans *trans, int index) 262 { 263 return --index & (trans->cfg->base_params->max_tfd_queue_size - 1); 264 } 265 266 struct iwl_cmd_meta { 267 /* only for SYNC commands, iff the reply skb is wanted */ 268 struct iwl_host_cmd *source; 269 u32 flags; 270 u32 tbs; 271 }; 272 273 274 #define TFD_TX_CMD_SLOTS 256 275 #define TFD_CMD_SLOTS 32 276 277 /* 278 * The FH will write back to the first TB only, so we need to copy some data 279 * into the buffer regardless of whether it should be mapped or not. 280 * This indicates how big the first TB must be to include the scratch buffer 281 * and the assigned PN. 282 * Since PN location is 8 bytes at offset 12, it's 20 now. 283 * If we make it bigger then allocations will be bigger and copy slower, so 284 * that's probably not useful. 285 */ 286 #define IWL_FIRST_TB_SIZE 20 287 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 288 289 struct iwl_pcie_txq_entry { 290 struct iwl_device_cmd *cmd; 291 struct sk_buff *skb; 292 /* buffer to free after command completes */ 293 const void *free_buf; 294 struct iwl_cmd_meta meta; 295 }; 296 297 struct iwl_pcie_first_tb_buf { 298 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 299 }; 300 301 /** 302 * struct iwl_txq - Tx Queue for DMA 303 * @q: generic Rx/Tx queue descriptor 304 * @tfds: transmit frame descriptors (DMA memory) 305 * @first_tb_bufs: start of command headers, including scratch buffers, for 306 * the writeback -- this is DMA memory and an array holding one buffer 307 * for each command on the queue 308 * @first_tb_dma: DMA address for the first_tb_bufs start 309 * @entries: transmit entries (driver state) 310 * @lock: queue lock 311 * @stuck_timer: timer that fires if queue gets stuck 312 * @trans_pcie: pointer back to transport (for timer) 313 * @need_update: indicates need to update read/write index 314 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 315 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 316 * @frozen: tx stuck queue timer is frozen 317 * @frozen_expiry_remainder: remember how long until the timer fires 318 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 319 * @write_ptr: 1-st empty entry (index) host_w 320 * @read_ptr: last used entry (index) host_r 321 * @dma_addr: physical addr for BD's 322 * @n_window: safe queue window 323 * @id: queue id 324 * @low_mark: low watermark, resume queue if free space more than this 325 * @high_mark: high watermark, stop queue if free space less than this 326 * 327 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 328 * descriptors) and required locking structures. 329 * 330 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 331 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 332 * there might be HW changes in the future). For the normal TX 333 * queues, n_window, which is the size of the software queue data 334 * is also 256; however, for the command queue, n_window is only 335 * 32 since we don't need so many commands pending. Since the HW 336 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 337 * This means that we end up with the following: 338 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 339 * SW entries: | 0 | ... | 31 | 340 * where N is a number between 0 and 7. This means that the SW 341 * data is a window overlayed over the HW queue. 342 */ 343 struct iwl_txq { 344 void *tfds; 345 struct iwl_pcie_first_tb_buf *first_tb_bufs; 346 dma_addr_t first_tb_dma; 347 struct iwl_pcie_txq_entry *entries; 348 spinlock_t lock; 349 unsigned long frozen_expiry_remainder; 350 struct timer_list stuck_timer; 351 struct iwl_trans_pcie *trans_pcie; 352 bool need_update; 353 bool frozen; 354 bool ampdu; 355 int block; 356 unsigned long wd_timeout; 357 struct sk_buff_head overflow_q; 358 struct iwl_dma_ptr bc_tbl; 359 360 int write_ptr; 361 int read_ptr; 362 dma_addr_t dma_addr; 363 int n_window; 364 u32 id; 365 int low_mark; 366 int high_mark; 367 }; 368 369 static inline dma_addr_t 370 iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx) 371 { 372 return txq->first_tb_dma + 373 sizeof(struct iwl_pcie_first_tb_buf) * idx; 374 } 375 376 struct iwl_tso_hdr_page { 377 struct page *page; 378 u8 *pos; 379 }; 380 381 /** 382 * enum iwl_shared_irq_flags - level of sharing for irq 383 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 384 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 385 */ 386 enum iwl_shared_irq_flags { 387 IWL_SHARED_IRQ_NON_RX = BIT(0), 388 IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 389 }; 390 391 /** 392 * enum iwl_image_response_code - image response values 393 * @IWL_IMAGE_RESP_DEF: the default value of the register 394 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully 395 * @IWL_IMAGE_RESP_FAIL: iml reading failed 396 */ 397 enum iwl_image_response_code { 398 IWL_IMAGE_RESP_DEF = 0, 399 IWL_IMAGE_RESP_SUCCESS = 1, 400 IWL_IMAGE_RESP_FAIL = 2, 401 }; 402 403 /** 404 * struct iwl_self_init_dram - dram data used by self init process 405 * @fw: lmac and umac dram data 406 * @fw_cnt: total number of items in array 407 * @paging: paging dram data 408 * @paging_cnt: total number of items in array 409 */ 410 struct iwl_self_init_dram { 411 struct iwl_dram_data *fw; 412 int fw_cnt; 413 struct iwl_dram_data *paging; 414 int paging_cnt; 415 }; 416 417 /** 418 * struct iwl_trans_pcie - PCIe transport specific data 419 * @rxq: all the RX queue data 420 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 421 * @global_table: table mapping received VID from hw to rxb 422 * @rba: allocator for RX replenishing 423 * @ctxt_info: context information for FW self init 424 * @ctxt_info_gen3: context information for gen3 devices 425 * @prph_info: prph info for self init 426 * @prph_scratch: prph scratch for self init 427 * @ctxt_info_dma_addr: dma addr of context information 428 * @prph_info_dma_addr: dma addr of prph info 429 * @prph_scratch_dma_addr: dma addr of prph scratch 430 * @ctxt_info_dma_addr: dma addr of context information 431 * @init_dram: DRAM data of firmware image (including paging). 432 * Context information addresses will be taken from here. 433 * This is driver's local copy for keeping track of size and 434 * count for allocating and freeing the memory. 435 * @trans: pointer to the generic transport area 436 * @scd_base_addr: scheduler sram base address in SRAM 437 * @scd_bc_tbls: pointer to the byte count table of the scheduler 438 * @kw: keep warm address 439 * @pci_dev: basic pci-network driver stuff 440 * @hw_base: pci hardware address support 441 * @ucode_write_complete: indicates that the ucode has been copied. 442 * @ucode_write_waitq: wait queue for uCode load 443 * @cmd_queue - command queue number 444 * @def_rx_queue - default rx queue number 445 * @rx_buf_size: Rx buffer size 446 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 447 * @scd_set_active: should the transport configure the SCD for HCMD queue 448 * @sw_csum_tx: if true, then the transport will compute the csum of the TXed 449 * frame. 450 * @rx_page_order: page order for receive buffer size 451 * @reg_lock: protect hw register access 452 * @mutex: to protect stop_device / start_fw / start_hw 453 * @cmd_in_flight: true when we have a host command in flight 454 * @msix_entries: array of MSI-X entries 455 * @msix_enabled: true if managed to enable MSI-X 456 * @shared_vec_mask: the type of causes the shared vector handles 457 * (see iwl_shared_irq_flags). 458 * @alloc_vecs: the number of interrupt vectors allocated by the OS 459 * @def_irq: default irq for non rx causes 460 * @fh_init_mask: initial unmasked fh causes 461 * @hw_init_mask: initial unmasked hw causes 462 * @fh_mask: current unmasked fh causes 463 * @hw_mask: current unmasked hw causes 464 * @in_rescan: true if we have triggered a device rescan 465 */ 466 struct iwl_trans_pcie { 467 struct iwl_rxq *rxq; 468 struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE]; 469 struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE]; 470 struct iwl_rb_allocator rba; 471 union { 472 struct iwl_context_info *ctxt_info; 473 struct iwl_context_info_gen3 *ctxt_info_gen3; 474 }; 475 struct iwl_prph_info *prph_info; 476 struct iwl_prph_scratch *prph_scratch; 477 dma_addr_t ctxt_info_dma_addr; 478 dma_addr_t prph_info_dma_addr; 479 dma_addr_t prph_scratch_dma_addr; 480 dma_addr_t iml_dma_addr; 481 struct iwl_self_init_dram init_dram; 482 struct iwl_trans *trans; 483 484 struct net_device napi_dev; 485 486 struct __percpu iwl_tso_hdr_page *tso_hdr_page; 487 488 /* INT ICT Table */ 489 __le32 *ict_tbl; 490 dma_addr_t ict_tbl_dma; 491 int ict_index; 492 bool use_ict; 493 bool is_down, opmode_down; 494 bool debug_rfkill; 495 struct isr_statistics isr_stats; 496 497 spinlock_t irq_lock; 498 struct mutex mutex; 499 u32 inta_mask; 500 u32 scd_base_addr; 501 struct iwl_dma_ptr scd_bc_tbls; 502 struct iwl_dma_ptr kw; 503 504 struct iwl_txq *txq_memory; 505 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 506 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 507 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 508 509 /* PCI bus related data */ 510 struct pci_dev *pci_dev; 511 void __iomem *hw_base; 512 513 bool ucode_write_complete; 514 wait_queue_head_t ucode_write_waitq; 515 wait_queue_head_t wait_command_queue; 516 wait_queue_head_t d0i3_waitq; 517 518 u8 page_offs, dev_cmd_offs; 519 520 u8 cmd_queue; 521 u8 def_rx_queue; 522 u8 cmd_fifo; 523 unsigned int cmd_q_wdg_timeout; 524 u8 n_no_reclaim_cmds; 525 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 526 u8 max_tbs; 527 u16 tfd_size; 528 529 enum iwl_amsdu_size rx_buf_size; 530 bool bc_table_dword; 531 bool scd_set_active; 532 bool sw_csum_tx; 533 bool pcie_dbg_dumped_once; 534 u32 rx_page_order; 535 536 /*protect hw register */ 537 spinlock_t reg_lock; 538 bool cmd_hold_nic_awake; 539 bool ref_cmd_in_flight; 540 541 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 542 bool msix_enabled; 543 u8 shared_vec_mask; 544 u32 alloc_vecs; 545 u32 def_irq; 546 u32 fh_init_mask; 547 u32 hw_init_mask; 548 u32 fh_mask; 549 u32 hw_mask; 550 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 551 u16 tx_cmd_queue_size; 552 bool in_rescan; 553 }; 554 555 static inline struct iwl_trans_pcie * 556 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 557 { 558 return (void *)trans->trans_specific; 559 } 560 561 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 562 struct msix_entry *entry) 563 { 564 /* 565 * Before sending the interrupt the HW disables it to prevent 566 * a nested interrupt. This is done by writing 1 to the corresponding 567 * bit in the mask register. After handling the interrupt, it should be 568 * re-enabled by clearing this bit. This register is defined as 569 * write 1 clear (W1C) register, meaning that it's being clear 570 * by writing 1 to the bit. 571 */ 572 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 573 } 574 575 static inline struct iwl_trans * 576 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 577 { 578 return container_of((void *)trans_pcie, struct iwl_trans, 579 trans_specific); 580 } 581 582 /* 583 * Convention: trans API functions: iwl_trans_pcie_XXX 584 * Other functions: iwl_pcie_XXX 585 */ 586 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 587 const struct pci_device_id *ent, 588 const struct iwl_cfg *cfg); 589 void iwl_trans_pcie_free(struct iwl_trans *trans); 590 591 /***************************************************** 592 * RX 593 ******************************************************/ 594 int _iwl_pcie_rx_init(struct iwl_trans *trans); 595 int iwl_pcie_rx_init(struct iwl_trans *trans); 596 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 597 irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 598 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 599 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 600 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 601 int iwl_pcie_rx_stop(struct iwl_trans *trans); 602 void iwl_pcie_rx_free(struct iwl_trans *trans); 603 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans); 604 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq); 605 int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget); 606 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 607 struct iwl_rxq *rxq); 608 int iwl_pcie_rx_alloc(struct iwl_trans *trans); 609 610 /***************************************************** 611 * ICT - interrupt handling 612 ******************************************************/ 613 irqreturn_t iwl_pcie_isr(int irq, void *data); 614 int iwl_pcie_alloc_ict(struct iwl_trans *trans); 615 void iwl_pcie_free_ict(struct iwl_trans *trans); 616 void iwl_pcie_reset_ict(struct iwl_trans *trans); 617 void iwl_pcie_disable_ict(struct iwl_trans *trans); 618 619 /***************************************************** 620 * TX / HCMD 621 ******************************************************/ 622 int iwl_pcie_tx_init(struct iwl_trans *trans); 623 int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id, 624 int queue_size); 625 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 626 int iwl_pcie_tx_stop(struct iwl_trans *trans); 627 void iwl_pcie_tx_free(struct iwl_trans *trans); 628 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 629 const struct iwl_trans_txq_scd_cfg *cfg, 630 unsigned int wdg_timeout); 631 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 632 bool configure_scd); 633 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 634 bool shared_mode); 635 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, 636 struct iwl_txq *txq); 637 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 638 struct iwl_device_cmd *dev_cmd, int txq_id); 639 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 640 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 641 void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx); 642 void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans, 643 struct iwl_txq *txq); 644 void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 645 struct iwl_rx_cmd_buffer *rxb); 646 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 647 struct sk_buff_head *skbs); 648 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 649 void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans_pcie *trans_pcie, 650 struct iwl_txq *txq, u16 byte_cnt, 651 int num_tbs); 652 653 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd, 654 u8 idx) 655 { 656 if (trans->cfg->use_tfh) { 657 struct iwl_tfh_tfd *tfd = _tfd; 658 struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 659 660 return le16_to_cpu(tb->tb_len); 661 } else { 662 struct iwl_tfd *tfd = _tfd; 663 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 664 665 return le16_to_cpu(tb->hi_n_len) >> 4; 666 } 667 } 668 669 /***************************************************** 670 * Error handling 671 ******************************************************/ 672 void iwl_pcie_dump_csr(struct iwl_trans *trans); 673 674 /***************************************************** 675 * Helpers 676 ******************************************************/ 677 static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 678 { 679 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 680 681 clear_bit(STATUS_INT_ENABLED, &trans->status); 682 if (!trans_pcie->msix_enabled) { 683 /* disable interrupts from uCode/NIC to host */ 684 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 685 686 /* acknowledge/clear/reset any interrupts still pending 687 * from uCode or flow handler (Rx/Tx DMA) */ 688 iwl_write32(trans, CSR_INT, 0xffffffff); 689 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 690 } else { 691 /* disable all the interrupt we might use */ 692 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 693 trans_pcie->fh_init_mask); 694 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 695 trans_pcie->hw_init_mask); 696 } 697 IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 698 } 699 700 #define IWL_NUM_OF_COMPLETION_RINGS 31 701 #define IWL_NUM_OF_TRANSFER_RINGS 527 702 703 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw, 704 int start) 705 { 706 int i = 0; 707 708 while (start < fw->num_sec && 709 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && 710 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { 711 start++; 712 i++; 713 } 714 715 return i; 716 } 717 718 static inline int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans, 719 const struct fw_desc *sec, 720 struct iwl_dram_data *dram) 721 { 722 dram->block = dma_alloc_coherent(trans->dev, sec->len, 723 &dram->physical, 724 GFP_KERNEL); 725 if (!dram->block) 726 return -ENOMEM; 727 728 dram->size = sec->len; 729 memcpy(dram->block, sec->data, sec->len); 730 731 return 0; 732 } 733 734 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans) 735 { 736 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 737 struct iwl_self_init_dram *dram = &trans_pcie->init_dram; 738 int i; 739 740 if (!dram->fw) { 741 WARN_ON(dram->fw_cnt); 742 return; 743 } 744 745 for (i = 0; i < dram->fw_cnt; i++) 746 dma_free_coherent(trans->dev, dram->fw[i].size, 747 dram->fw[i].block, dram->fw[i].physical); 748 749 kfree(dram->fw); 750 dram->fw_cnt = 0; 751 dram->fw = NULL; 752 } 753 754 static inline void iwl_disable_interrupts(struct iwl_trans *trans) 755 { 756 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 757 758 spin_lock(&trans_pcie->irq_lock); 759 _iwl_disable_interrupts(trans); 760 spin_unlock(&trans_pcie->irq_lock); 761 } 762 763 static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 764 { 765 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 766 767 IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 768 set_bit(STATUS_INT_ENABLED, &trans->status); 769 if (!trans_pcie->msix_enabled) { 770 trans_pcie->inta_mask = CSR_INI_SET_MASK; 771 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 772 } else { 773 /* 774 * fh/hw_mask keeps all the unmasked causes. 775 * Unlike msi, in msix cause is enabled when it is unset. 776 */ 777 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 778 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 779 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 780 ~trans_pcie->fh_mask); 781 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 782 ~trans_pcie->hw_mask); 783 } 784 } 785 786 static inline void iwl_enable_interrupts(struct iwl_trans *trans) 787 { 788 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 789 790 spin_lock(&trans_pcie->irq_lock); 791 _iwl_enable_interrupts(trans); 792 spin_unlock(&trans_pcie->irq_lock); 793 } 794 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 795 { 796 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 797 798 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 799 trans_pcie->hw_mask = msk; 800 } 801 802 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 803 { 804 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 805 806 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 807 trans_pcie->fh_mask = msk; 808 } 809 810 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 811 { 812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 813 814 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 815 if (!trans_pcie->msix_enabled) { 816 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 817 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 818 } else { 819 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 820 trans_pcie->hw_init_mask); 821 iwl_enable_fh_int_msk_msix(trans, 822 MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 823 } 824 } 825 826 static inline u16 iwl_pcie_get_cmd_index(const struct iwl_txq *q, u32 index) 827 { 828 return index & (q->n_window - 1); 829 } 830 831 static inline void *iwl_pcie_get_tfd(struct iwl_trans *trans, 832 struct iwl_txq *txq, int idx) 833 { 834 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 835 836 if (trans->cfg->use_tfh) 837 idx = iwl_pcie_get_cmd_index(txq, idx); 838 839 return txq->tfds + trans_pcie->tfd_size * idx; 840 } 841 842 static inline const char *queue_name(struct device *dev, 843 struct iwl_trans_pcie *trans_p, int i) 844 { 845 if (trans_p->shared_vec_mask) { 846 int vec = trans_p->shared_vec_mask & 847 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 848 849 if (i == 0) 850 return DRV_NAME ": shared IRQ"; 851 852 return devm_kasprintf(dev, GFP_KERNEL, 853 DRV_NAME ": queue %d", i + vec); 854 } 855 if (i == 0) 856 return DRV_NAME ": default queue"; 857 858 if (i == trans_p->alloc_vecs - 1) 859 return DRV_NAME ": exception"; 860 861 return devm_kasprintf(dev, GFP_KERNEL, 862 DRV_NAME ": queue %d", i); 863 } 864 865 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 866 { 867 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 868 869 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 870 if (!trans_pcie->msix_enabled) { 871 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 872 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 873 } else { 874 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 875 trans_pcie->fh_init_mask); 876 iwl_enable_hw_int_msk_msix(trans, 877 MSIX_HW_INT_CAUSES_REG_RF_KILL); 878 } 879 880 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_9000) { 881 /* 882 * On 9000-series devices this bit isn't enabled by default, so 883 * when we power down the device we need set the bit to allow it 884 * to wake up the PCI-E bus for RF-kill interrupts. 885 */ 886 iwl_set_bit(trans, CSR_GP_CNTRL, 887 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 888 } 889 } 890 891 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans); 892 893 static inline void iwl_wake_queue(struct iwl_trans *trans, 894 struct iwl_txq *txq) 895 { 896 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 897 898 if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) { 899 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id); 900 iwl_op_mode_queue_not_full(trans->op_mode, txq->id); 901 } 902 } 903 904 static inline void iwl_stop_queue(struct iwl_trans *trans, 905 struct iwl_txq *txq) 906 { 907 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 908 909 if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) { 910 iwl_op_mode_queue_full(trans->op_mode, txq->id); 911 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id); 912 } else 913 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 914 txq->id); 915 } 916 917 static inline bool iwl_queue_used(const struct iwl_txq *q, int i) 918 { 919 int index = iwl_pcie_get_cmd_index(q, i); 920 int r = iwl_pcie_get_cmd_index(q, q->read_ptr); 921 int w = iwl_pcie_get_cmd_index(q, q->write_ptr); 922 923 return w >= r ? 924 (index >= r && index < w) : 925 !(index < r && index >= w); 926 } 927 928 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 929 { 930 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 931 932 lockdep_assert_held(&trans_pcie->mutex); 933 934 if (trans_pcie->debug_rfkill) 935 return true; 936 937 return !(iwl_read32(trans, CSR_GP_CNTRL) & 938 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 939 } 940 941 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 942 u32 reg, u32 mask, u32 value) 943 { 944 u32 v; 945 946 #ifdef CONFIG_IWLWIFI_DEBUG 947 WARN_ON_ONCE(value & ~mask); 948 #endif 949 950 v = iwl_read32(trans, reg); 951 v &= ~mask; 952 v |= value; 953 iwl_write32(trans, reg, v); 954 } 955 956 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 957 u32 reg, u32 mask) 958 { 959 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 960 } 961 962 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 963 u32 reg, u32 mask) 964 { 965 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 966 } 967 968 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 969 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans); 970 971 #ifdef CONFIG_IWLWIFI_DEBUGFS 972 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 973 #else 974 static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 975 { 976 return 0; 977 } 978 #endif 979 980 int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans); 981 int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans); 982 983 void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable); 984 985 void iwl_pcie_rx_allocator_work(struct work_struct *data); 986 987 /* common functions that are used by gen2 transport */ 988 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans); 989 void iwl_pcie_apm_config(struct iwl_trans *trans); 990 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 991 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 992 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans); 993 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 994 bool was_in_rfkill); 995 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq); 996 int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q); 997 void iwl_pcie_apm_stop_master(struct iwl_trans *trans); 998 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 999 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 1000 int slots_num, bool cmd_queue); 1001 int iwl_pcie_txq_alloc(struct iwl_trans *trans, 1002 struct iwl_txq *txq, int slots_num, bool cmd_queue); 1003 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 1004 struct iwl_dma_ptr *ptr, size_t size); 1005 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr); 1006 void iwl_pcie_apply_destination(struct iwl_trans *trans); 1007 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 1008 struct sk_buff *skb); 1009 #ifdef CONFIG_INET 1010 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len); 1011 #endif 1012 1013 /* common functions that are used by gen3 transport */ 1014 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power); 1015 1016 /* transport gen 2 exported functions */ 1017 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 1018 const struct fw_img *fw, bool run_in_rfkill); 1019 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr); 1020 void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans, 1021 struct iwl_txq *txq); 1022 int iwl_trans_pcie_dyn_txq_alloc_dma(struct iwl_trans *trans, 1023 struct iwl_txq **intxq, int size, 1024 unsigned int timeout); 1025 int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans, 1026 struct iwl_txq *txq, 1027 struct iwl_host_cmd *hcmd); 1028 int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans, 1029 __le16 flags, u8 sta_id, u8 tid, 1030 int cmd_id, int size, 1031 unsigned int timeout); 1032 void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue); 1033 int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb, 1034 struct iwl_device_cmd *dev_cmd, int txq_id); 1035 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 1036 struct iwl_host_cmd *cmd); 1037 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, 1038 bool low_power); 1039 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power); 1040 void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id); 1041 void iwl_pcie_gen2_tx_free(struct iwl_trans *trans); 1042 void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans); 1043 #endif /* __iwl_trans_int_pcie_h__ */ 1044