1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2003-2015, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_trans_int_pcie_h__ 8 #define __iwl_trans_int_pcie_h__ 9 10 #include <linux/spinlock.h> 11 #include <linux/interrupt.h> 12 #include <linux/skbuff.h> 13 #include <linux/wait.h> 14 #include <linux/pci.h> 15 #include <linux/timer.h> 16 #include <linux/cpu.h> 17 18 #include "iwl-fh.h" 19 #include "iwl-csr.h" 20 #include "iwl-trans.h" 21 #include "iwl-debug.h" 22 #include "iwl-io.h" 23 #include "iwl-op-mode.h" 24 #include "iwl-drv.h" 25 #include "queue/tx.h" 26 27 /* 28 * RX related structures and functions 29 */ 30 #define RX_NUM_QUEUES 1 31 #define RX_POST_REQ_ALLOC 2 32 #define RX_CLAIM_REQ_ALLOC 8 33 #define RX_PENDING_WATERMARK 16 34 #define FIRST_RX_QUEUE 512 35 36 struct iwl_host_cmd; 37 38 /*This file includes the declaration that are internal to the 39 * trans_pcie layer */ 40 41 /** 42 * struct iwl_rx_mem_buffer 43 * @page_dma: bus address of rxb page 44 * @page: driver's pointer to the rxb page 45 * @invalid: rxb is in driver ownership - not owned by HW 46 * @vid: index of this rxb in the global table 47 * @offset: indicates which offset of the page (in bytes) 48 * this buffer uses (if multiple RBs fit into one page) 49 */ 50 struct iwl_rx_mem_buffer { 51 dma_addr_t page_dma; 52 struct page *page; 53 u16 vid; 54 bool invalid; 55 struct list_head list; 56 u32 offset; 57 }; 58 59 /** 60 * struct isr_statistics - interrupt statistics 61 * 62 */ 63 struct isr_statistics { 64 u32 hw; 65 u32 sw; 66 u32 err_code; 67 u32 sch; 68 u32 alive; 69 u32 rfkill; 70 u32 ctkill; 71 u32 wakeup; 72 u32 rx; 73 u32 tx; 74 u32 unhandled; 75 }; 76 77 /** 78 * struct iwl_rx_transfer_desc - transfer descriptor 79 * @addr: ptr to free buffer start address 80 * @rbid: unique tag of the buffer 81 * @reserved: reserved 82 */ 83 struct iwl_rx_transfer_desc { 84 __le16 rbid; 85 __le16 reserved[3]; 86 __le64 addr; 87 } __packed; 88 89 #define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0) 90 91 /** 92 * struct iwl_rx_completion_desc - completion descriptor 93 * @reserved1: reserved 94 * @rbid: unique tag of the received buffer 95 * @flags: flags (0: fragmented, all others: reserved) 96 * @reserved2: reserved 97 */ 98 struct iwl_rx_completion_desc { 99 __le32 reserved1; 100 __le16 rbid; 101 u8 flags; 102 u8 reserved2[25]; 103 } __packed; 104 105 /** 106 * struct iwl_rxq - Rx queue 107 * @id: queue index 108 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 109 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 110 * In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's 111 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 112 * @used_bd: driver's pointer to buffer of used receive buffer descriptors (rbd) 113 * @used_bd_dma: physical address of buffer of used receive buffer descriptors (rbd) 114 * @read: Shared index to newest available Rx buffer 115 * @write: Shared index to oldest written Rx packet 116 * @free_count: Number of pre-allocated buffers in rx_free 117 * @used_count: Number of RBDs handled to allocator to use for allocation 118 * @write_actual: 119 * @rx_free: list of RBDs with allocated RB ready for use 120 * @rx_used: list of RBDs with no RB attached 121 * @need_update: flag to indicate we need to update read/write index 122 * @rb_stts: driver's pointer to receive buffer status 123 * @rb_stts_dma: bus address of receive buffer status 124 * @lock: 125 * @queue: actual rx queue. Not used for multi-rx queue. 126 * @next_rb_is_fragment: indicates that the previous RB that we handled set 127 * the fragmented flag, so the next one is still another fragment 128 * 129 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 130 */ 131 struct iwl_rxq { 132 int id; 133 void *bd; 134 dma_addr_t bd_dma; 135 union { 136 void *used_bd; 137 __le32 *bd_32; 138 struct iwl_rx_completion_desc *cd; 139 }; 140 dma_addr_t used_bd_dma; 141 u32 read; 142 u32 write; 143 u32 free_count; 144 u32 used_count; 145 u32 write_actual; 146 u32 queue_size; 147 struct list_head rx_free; 148 struct list_head rx_used; 149 bool need_update, next_rb_is_fragment; 150 void *rb_stts; 151 dma_addr_t rb_stts_dma; 152 spinlock_t lock; 153 struct napi_struct napi; 154 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 155 }; 156 157 /** 158 * struct iwl_rb_allocator - Rx allocator 159 * @req_pending: number of requests the allcator had not processed yet 160 * @req_ready: number of requests honored and ready for claiming 161 * @rbd_allocated: RBDs with pages allocated and ready to be handled to 162 * the queue. This is a list of &struct iwl_rx_mem_buffer 163 * @rbd_empty: RBDs with no page attached for allocator use. This is a list 164 * of &struct iwl_rx_mem_buffer 165 * @lock: protects the rbd_allocated and rbd_empty lists 166 * @alloc_wq: work queue for background calls 167 * @rx_alloc: work struct for background calls 168 */ 169 struct iwl_rb_allocator { 170 atomic_t req_pending; 171 atomic_t req_ready; 172 struct list_head rbd_allocated; 173 struct list_head rbd_empty; 174 spinlock_t lock; 175 struct workqueue_struct *alloc_wq; 176 struct work_struct rx_alloc; 177 }; 178 179 /** 180 * iwl_get_closed_rb_stts - get closed rb stts from different structs 181 * @rxq - the rxq to get the rb stts from 182 */ 183 static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans, 184 struct iwl_rxq *rxq) 185 { 186 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 187 __le16 *rb_stts = rxq->rb_stts; 188 189 return READ_ONCE(*rb_stts); 190 } else { 191 struct iwl_rb_status *rb_stts = rxq->rb_stts; 192 193 return READ_ONCE(rb_stts->closed_rb_num); 194 } 195 } 196 197 #ifdef CONFIG_IWLWIFI_DEBUGFS 198 /** 199 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data 200 * debugfs file 201 * 202 * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed. 203 * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open. 204 * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is 205 * set the file can no longer be used. 206 */ 207 enum iwl_fw_mon_dbgfs_state { 208 IWL_FW_MON_DBGFS_STATE_CLOSED, 209 IWL_FW_MON_DBGFS_STATE_OPEN, 210 IWL_FW_MON_DBGFS_STATE_DISABLED, 211 }; 212 #endif 213 214 /** 215 * enum iwl_shared_irq_flags - level of sharing for irq 216 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 217 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 218 */ 219 enum iwl_shared_irq_flags { 220 IWL_SHARED_IRQ_NON_RX = BIT(0), 221 IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 222 }; 223 224 /** 225 * enum iwl_image_response_code - image response values 226 * @IWL_IMAGE_RESP_DEF: the default value of the register 227 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully 228 * @IWL_IMAGE_RESP_FAIL: iml reading failed 229 */ 230 enum iwl_image_response_code { 231 IWL_IMAGE_RESP_DEF = 0, 232 IWL_IMAGE_RESP_SUCCESS = 1, 233 IWL_IMAGE_RESP_FAIL = 2, 234 }; 235 236 /** 237 * struct cont_rec: continuous recording data structure 238 * @prev_wr_ptr: the last address that was read in monitor_data 239 * debugfs file 240 * @prev_wrap_cnt: the wrap count that was used during the last read in 241 * monitor_data debugfs file 242 * @state: the state of monitor_data debugfs file as described 243 * in &iwl_fw_mon_dbgfs_state enum 244 * @mutex: locked while reading from monitor_data debugfs file 245 */ 246 #ifdef CONFIG_IWLWIFI_DEBUGFS 247 struct cont_rec { 248 u32 prev_wr_ptr; 249 u32 prev_wrap_cnt; 250 u8 state; 251 /* Used to sync monitor_data debugfs file with driver unload flow */ 252 struct mutex mutex; 253 }; 254 #endif 255 256 /** 257 * struct iwl_trans_pcie - PCIe transport specific data 258 * @rxq: all the RX queue data 259 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 260 * @global_table: table mapping received VID from hw to rxb 261 * @rba: allocator for RX replenishing 262 * @ctxt_info: context information for FW self init 263 * @ctxt_info_gen3: context information for gen3 devices 264 * @prph_info: prph info for self init 265 * @prph_scratch: prph scratch for self init 266 * @ctxt_info_dma_addr: dma addr of context information 267 * @prph_info_dma_addr: dma addr of prph info 268 * @prph_scratch_dma_addr: dma addr of prph scratch 269 * @ctxt_info_dma_addr: dma addr of context information 270 * @init_dram: DRAM data of firmware image (including paging). 271 * Context information addresses will be taken from here. 272 * This is driver's local copy for keeping track of size and 273 * count for allocating and freeing the memory. 274 * @iml: image loader image virtual address 275 * @iml_dma_addr: image loader image DMA address 276 * @trans: pointer to the generic transport area 277 * @scd_base_addr: scheduler sram base address in SRAM 278 * @kw: keep warm address 279 * @pnvm_dram: DRAM area that contains the PNVM data 280 * @pci_dev: basic pci-network driver stuff 281 * @hw_base: pci hardware address support 282 * @ucode_write_complete: indicates that the ucode has been copied. 283 * @ucode_write_waitq: wait queue for uCode load 284 * @cmd_queue - command queue number 285 * @def_rx_queue - default rx queue number 286 * @rx_buf_size: Rx buffer size 287 * @scd_set_active: should the transport configure the SCD for HCMD queue 288 * @rx_page_order: page order for receive buffer size 289 * @rx_buf_bytes: RX buffer (RB) size in bytes 290 * @reg_lock: protect hw register access 291 * @mutex: to protect stop_device / start_fw / start_hw 292 * @cmd_in_flight: true when we have a host command in flight 293 #ifdef CONFIG_IWLWIFI_DEBUGFS 294 * @fw_mon_data: fw continuous recording data 295 #endif 296 * @msix_entries: array of MSI-X entries 297 * @msix_enabled: true if managed to enable MSI-X 298 * @shared_vec_mask: the type of causes the shared vector handles 299 * (see iwl_shared_irq_flags). 300 * @alloc_vecs: the number of interrupt vectors allocated by the OS 301 * @def_irq: default irq for non rx causes 302 * @fh_init_mask: initial unmasked fh causes 303 * @hw_init_mask: initial unmasked hw causes 304 * @fh_mask: current unmasked fh causes 305 * @hw_mask: current unmasked hw causes 306 * @in_rescan: true if we have triggered a device rescan 307 * @base_rb_stts: base virtual address of receive buffer status for all queues 308 * @base_rb_stts_dma: base physical address of receive buffer status 309 * @supported_dma_mask: DMA mask to validate the actual address against, 310 * will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device 311 * @alloc_page_lock: spinlock for the page allocator 312 * @alloc_page: allocated page to still use parts of 313 * @alloc_page_used: how much of the allocated page was already used (bytes) 314 * @rf_name: name/version of the CRF, if any 315 */ 316 struct iwl_trans_pcie { 317 struct iwl_rxq *rxq; 318 struct iwl_rx_mem_buffer *rx_pool; 319 struct iwl_rx_mem_buffer **global_table; 320 struct iwl_rb_allocator rba; 321 union { 322 struct iwl_context_info *ctxt_info; 323 struct iwl_context_info_gen3 *ctxt_info_gen3; 324 }; 325 struct iwl_prph_info *prph_info; 326 struct iwl_prph_scratch *prph_scratch; 327 void *iml; 328 dma_addr_t ctxt_info_dma_addr; 329 dma_addr_t prph_info_dma_addr; 330 dma_addr_t prph_scratch_dma_addr; 331 dma_addr_t iml_dma_addr; 332 struct iwl_trans *trans; 333 334 struct net_device napi_dev; 335 336 /* INT ICT Table */ 337 __le32 *ict_tbl; 338 dma_addr_t ict_tbl_dma; 339 int ict_index; 340 bool use_ict; 341 bool is_down, opmode_down; 342 s8 debug_rfkill; 343 struct isr_statistics isr_stats; 344 345 spinlock_t irq_lock; 346 struct mutex mutex; 347 u32 inta_mask; 348 u32 scd_base_addr; 349 struct iwl_dma_ptr kw; 350 351 struct iwl_dram_data pnvm_dram; 352 struct iwl_dram_data reduce_power_dram; 353 354 struct iwl_txq *txq_memory; 355 356 /* PCI bus related data */ 357 struct pci_dev *pci_dev; 358 void __iomem *hw_base; 359 360 bool ucode_write_complete; 361 bool sx_complete; 362 wait_queue_head_t ucode_write_waitq; 363 wait_queue_head_t sx_waitq; 364 365 u8 def_rx_queue; 366 u8 n_no_reclaim_cmds; 367 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 368 u16 num_rx_bufs; 369 370 enum iwl_amsdu_size rx_buf_size; 371 bool scd_set_active; 372 bool pcie_dbg_dumped_once; 373 u32 rx_page_order; 374 u32 rx_buf_bytes; 375 u32 supported_dma_mask; 376 377 /* allocator lock for the two values below */ 378 spinlock_t alloc_page_lock; 379 struct page *alloc_page; 380 u32 alloc_page_used; 381 382 /*protect hw register */ 383 spinlock_t reg_lock; 384 bool cmd_hold_nic_awake; 385 386 #ifdef CONFIG_IWLWIFI_DEBUGFS 387 struct cont_rec fw_mon_data; 388 #endif 389 390 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 391 bool msix_enabled; 392 u8 shared_vec_mask; 393 u32 alloc_vecs; 394 u32 def_irq; 395 u32 fh_init_mask; 396 u32 hw_init_mask; 397 u32 fh_mask; 398 u32 hw_mask; 399 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 400 u16 tx_cmd_queue_size; 401 bool in_rescan; 402 403 void *base_rb_stts; 404 dma_addr_t base_rb_stts_dma; 405 406 bool fw_reset_handshake; 407 bool fw_reset_done; 408 wait_queue_head_t fw_reset_waitq; 409 410 char rf_name[32]; 411 }; 412 413 static inline struct iwl_trans_pcie * 414 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 415 { 416 return (void *)trans->trans_specific; 417 } 418 419 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue) 420 { 421 /* 422 * Before sending the interrupt the HW disables it to prevent 423 * a nested interrupt. This is done by writing 1 to the corresponding 424 * bit in the mask register. After handling the interrupt, it should be 425 * re-enabled by clearing this bit. This register is defined as 426 * write 1 clear (W1C) register, meaning that it's being clear 427 * by writing 1 to the bit. 428 */ 429 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue)); 430 } 431 432 static inline struct iwl_trans * 433 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 434 { 435 return container_of((void *)trans_pcie, struct iwl_trans, 436 trans_specific); 437 } 438 439 /* 440 * Convention: trans API functions: iwl_trans_pcie_XXX 441 * Other functions: iwl_pcie_XXX 442 */ 443 struct iwl_trans 444 *iwl_trans_pcie_alloc(struct pci_dev *pdev, 445 const struct pci_device_id *ent, 446 const struct iwl_cfg_trans_params *cfg_trans); 447 void iwl_trans_pcie_free(struct iwl_trans *trans); 448 449 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans); 450 #define _iwl_trans_pcie_grab_nic_access(trans) \ 451 __cond_lock(nic_access_nobh, \ 452 likely(__iwl_trans_pcie_grab_nic_access(trans))) 453 454 /***************************************************** 455 * RX 456 ******************************************************/ 457 int iwl_pcie_rx_init(struct iwl_trans *trans); 458 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 459 irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 460 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 461 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 462 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 463 int iwl_pcie_rx_stop(struct iwl_trans *trans); 464 void iwl_pcie_rx_free(struct iwl_trans *trans); 465 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans); 466 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq); 467 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 468 struct iwl_rxq *rxq); 469 470 /***************************************************** 471 * ICT - interrupt handling 472 ******************************************************/ 473 irqreturn_t iwl_pcie_isr(int irq, void *data); 474 int iwl_pcie_alloc_ict(struct iwl_trans *trans); 475 void iwl_pcie_free_ict(struct iwl_trans *trans); 476 void iwl_pcie_reset_ict(struct iwl_trans *trans); 477 void iwl_pcie_disable_ict(struct iwl_trans *trans); 478 479 /***************************************************** 480 * TX / HCMD 481 ******************************************************/ 482 int iwl_pcie_tx_init(struct iwl_trans *trans); 483 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 484 int iwl_pcie_tx_stop(struct iwl_trans *trans); 485 void iwl_pcie_tx_free(struct iwl_trans *trans); 486 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 487 const struct iwl_trans_txq_scd_cfg *cfg, 488 unsigned int wdg_timeout); 489 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 490 bool configure_scd); 491 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 492 bool shared_mode); 493 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 494 struct iwl_device_tx_cmd *dev_cmd, int txq_id); 495 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 496 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 497 void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 498 struct iwl_rx_cmd_buffer *rxb); 499 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 500 501 /***************************************************** 502 * Error handling 503 ******************************************************/ 504 void iwl_pcie_dump_csr(struct iwl_trans *trans); 505 506 /***************************************************** 507 * Helpers 508 ******************************************************/ 509 static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 510 { 511 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 512 513 clear_bit(STATUS_INT_ENABLED, &trans->status); 514 if (!trans_pcie->msix_enabled) { 515 /* disable interrupts from uCode/NIC to host */ 516 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 517 518 /* acknowledge/clear/reset any interrupts still pending 519 * from uCode or flow handler (Rx/Tx DMA) */ 520 iwl_write32(trans, CSR_INT, 0xffffffff); 521 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 522 } else { 523 /* disable all the interrupt we might use */ 524 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 525 trans_pcie->fh_init_mask); 526 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 527 trans_pcie->hw_init_mask); 528 } 529 IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 530 } 531 532 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw, 533 int start) 534 { 535 int i = 0; 536 537 while (start < fw->num_sec && 538 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && 539 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { 540 start++; 541 i++; 542 } 543 544 return i; 545 } 546 547 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans) 548 { 549 struct iwl_self_init_dram *dram = &trans->init_dram; 550 int i; 551 552 if (!dram->fw) { 553 WARN_ON(dram->fw_cnt); 554 return; 555 } 556 557 for (i = 0; i < dram->fw_cnt; i++) 558 dma_free_coherent(trans->dev, dram->fw[i].size, 559 dram->fw[i].block, dram->fw[i].physical); 560 561 kfree(dram->fw); 562 dram->fw_cnt = 0; 563 dram->fw = NULL; 564 } 565 566 static inline void iwl_disable_interrupts(struct iwl_trans *trans) 567 { 568 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 569 570 spin_lock_bh(&trans_pcie->irq_lock); 571 _iwl_disable_interrupts(trans); 572 spin_unlock_bh(&trans_pcie->irq_lock); 573 } 574 575 static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 576 { 577 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 578 579 IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 580 set_bit(STATUS_INT_ENABLED, &trans->status); 581 if (!trans_pcie->msix_enabled) { 582 trans_pcie->inta_mask = CSR_INI_SET_MASK; 583 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 584 } else { 585 /* 586 * fh/hw_mask keeps all the unmasked causes. 587 * Unlike msi, in msix cause is enabled when it is unset. 588 */ 589 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 590 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 591 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 592 ~trans_pcie->fh_mask); 593 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 594 ~trans_pcie->hw_mask); 595 } 596 } 597 598 static inline void iwl_enable_interrupts(struct iwl_trans *trans) 599 { 600 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 601 602 spin_lock_bh(&trans_pcie->irq_lock); 603 _iwl_enable_interrupts(trans); 604 spin_unlock_bh(&trans_pcie->irq_lock); 605 } 606 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 607 { 608 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 609 610 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 611 trans_pcie->hw_mask = msk; 612 } 613 614 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 615 { 616 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 617 618 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 619 trans_pcie->fh_mask = msk; 620 } 621 622 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 623 { 624 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 625 626 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 627 if (!trans_pcie->msix_enabled) { 628 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 629 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 630 } else { 631 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 632 trans_pcie->hw_init_mask); 633 iwl_enable_fh_int_msk_msix(trans, 634 MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 635 } 636 } 637 638 static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans) 639 { 640 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 641 642 IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n"); 643 644 if (!trans_pcie->msix_enabled) { 645 /* 646 * When we'll receive the ALIVE interrupt, the ISR will call 647 * iwl_enable_fw_load_int_ctx_info again to set the ALIVE 648 * interrupt (which is not really needed anymore) but also the 649 * RX interrupt which will allow us to receive the ALIVE 650 * notification (which is Rx) and continue the flow. 651 */ 652 trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX; 653 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 654 } else { 655 iwl_enable_hw_int_msk_msix(trans, 656 MSIX_HW_INT_CAUSES_REG_ALIVE); 657 /* 658 * Leave all the FH causes enabled to get the ALIVE 659 * notification. 660 */ 661 iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask); 662 } 663 } 664 665 static inline const char *queue_name(struct device *dev, 666 struct iwl_trans_pcie *trans_p, int i) 667 { 668 if (trans_p->shared_vec_mask) { 669 int vec = trans_p->shared_vec_mask & 670 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 671 672 if (i == 0) 673 return DRV_NAME ": shared IRQ"; 674 675 return devm_kasprintf(dev, GFP_KERNEL, 676 DRV_NAME ": queue %d", i + vec); 677 } 678 if (i == 0) 679 return DRV_NAME ": default queue"; 680 681 if (i == trans_p->alloc_vecs - 1) 682 return DRV_NAME ": exception"; 683 684 return devm_kasprintf(dev, GFP_KERNEL, 685 DRV_NAME ": queue %d", i); 686 } 687 688 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 689 { 690 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 691 692 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 693 if (!trans_pcie->msix_enabled) { 694 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 695 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 696 } else { 697 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 698 trans_pcie->fh_init_mask); 699 iwl_enable_hw_int_msk_msix(trans, 700 MSIX_HW_INT_CAUSES_REG_RF_KILL); 701 } 702 703 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) { 704 /* 705 * On 9000-series devices this bit isn't enabled by default, so 706 * when we power down the device we need set the bit to allow it 707 * to wake up the PCI-E bus for RF-kill interrupts. 708 */ 709 iwl_set_bit(trans, CSR_GP_CNTRL, 710 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 711 } 712 } 713 714 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans); 715 716 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 717 { 718 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 719 720 lockdep_assert_held(&trans_pcie->mutex); 721 722 if (trans_pcie->debug_rfkill == 1) 723 return true; 724 725 return !(iwl_read32(trans, CSR_GP_CNTRL) & 726 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 727 } 728 729 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 730 u32 reg, u32 mask, u32 value) 731 { 732 u32 v; 733 734 #ifdef CONFIG_IWLWIFI_DEBUG 735 WARN_ON_ONCE(value & ~mask); 736 #endif 737 738 v = iwl_read32(trans, reg); 739 v &= ~mask; 740 v |= value; 741 iwl_write32(trans, reg, v); 742 } 743 744 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 745 u32 reg, u32 mask) 746 { 747 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 748 } 749 750 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 751 u32 reg, u32 mask) 752 { 753 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 754 } 755 756 static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans) 757 { 758 return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans)); 759 } 760 761 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 762 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans); 763 764 #ifdef CONFIG_IWLWIFI_DEBUGFS 765 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 766 #else 767 static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { } 768 #endif 769 770 void iwl_pcie_rx_allocator_work(struct work_struct *data); 771 772 /* common functions that are used by gen2 transport */ 773 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans); 774 void iwl_pcie_apm_config(struct iwl_trans *trans); 775 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 776 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 777 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans); 778 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 779 bool was_in_rfkill); 780 void iwl_pcie_apm_stop_master(struct iwl_trans *trans); 781 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 782 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 783 struct iwl_dma_ptr *ptr, size_t size); 784 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr); 785 void iwl_pcie_apply_destination(struct iwl_trans *trans); 786 787 /* common functions that are used by gen3 transport */ 788 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power); 789 790 /* transport gen 2 exported functions */ 791 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 792 const struct fw_img *fw, bool run_in_rfkill); 793 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr); 794 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 795 struct iwl_host_cmd *cmd); 796 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans); 797 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans); 798 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 799 bool test, bool reset); 800 int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans, 801 struct iwl_host_cmd *cmd); 802 int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 803 struct iwl_host_cmd *cmd); 804 #endif /* __iwl_trans_int_pcie_h__ */ 805