1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3  * Copyright (C) 2003-2015, 2018-2022 Intel Corporation
4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5  * Copyright (C) 2016-2017 Intel Deutschland GmbH
6  */
7 #ifndef __iwl_trans_int_pcie_h__
8 #define __iwl_trans_int_pcie_h__
9 
10 #include <linux/spinlock.h>
11 #include <linux/interrupt.h>
12 #include <linux/skbuff.h>
13 #include <linux/wait.h>
14 #include <linux/pci.h>
15 #include <linux/timer.h>
16 #include <linux/cpu.h>
17 
18 #include "iwl-fh.h"
19 #include "iwl-csr.h"
20 #include "iwl-trans.h"
21 #include "iwl-debug.h"
22 #include "iwl-io.h"
23 #include "iwl-op-mode.h"
24 #include "iwl-drv.h"
25 #include "queue/tx.h"
26 #include "iwl-context-info.h"
27 
28 /*
29  * RX related structures and functions
30  */
31 #define RX_NUM_QUEUES 1
32 #define RX_POST_REQ_ALLOC 2
33 #define RX_CLAIM_REQ_ALLOC 8
34 #define RX_PENDING_WATERMARK 16
35 #define FIRST_RX_QUEUE 512
36 
37 struct iwl_host_cmd;
38 
39 /*This file includes the declaration that are internal to the
40  * trans_pcie layer */
41 
42 /**
43  * struct iwl_rx_mem_buffer
44  * @page_dma: bus address of rxb page
45  * @page: driver's pointer to the rxb page
46  * @list: list entry for the membuffer
47  * @invalid: rxb is in driver ownership - not owned by HW
48  * @vid: index of this rxb in the global table
49  * @offset: indicates which offset of the page (in bytes)
50  *	this buffer uses (if multiple RBs fit into one page)
51  */
52 struct iwl_rx_mem_buffer {
53 	dma_addr_t page_dma;
54 	struct page *page;
55 	struct list_head list;
56 	u32 offset;
57 	u16 vid;
58 	bool invalid;
59 };
60 
61 /**
62  * struct isr_statistics - interrupt statistics
63  *
64  */
65 struct isr_statistics {
66 	u32 hw;
67 	u32 sw;
68 	u32 err_code;
69 	u32 sch;
70 	u32 alive;
71 	u32 rfkill;
72 	u32 ctkill;
73 	u32 wakeup;
74 	u32 rx;
75 	u32 tx;
76 	u32 unhandled;
77 };
78 
79 /**
80  * struct iwl_rx_transfer_desc - transfer descriptor
81  * @addr: ptr to free buffer start address
82  * @rbid: unique tag of the buffer
83  * @reserved: reserved
84  */
85 struct iwl_rx_transfer_desc {
86 	__le16 rbid;
87 	__le16 reserved[3];
88 	__le64 addr;
89 } __packed;
90 
91 #define IWL_RX_CD_FLAGS_FRAGMENTED	BIT(0)
92 
93 /**
94  * struct iwl_rx_completion_desc - completion descriptor
95  * @reserved1: reserved
96  * @rbid: unique tag of the received buffer
97  * @flags: flags (0: fragmented, all others: reserved)
98  * @reserved2: reserved
99  */
100 struct iwl_rx_completion_desc {
101 	__le32 reserved1;
102 	__le16 rbid;
103 	u8 flags;
104 	u8 reserved2[25];
105 } __packed;
106 
107 /**
108  * struct iwl_rx_completion_desc_bz - Bz completion descriptor
109  * @rbid: unique tag of the received buffer
110  * @flags: flags (0: fragmented, all others: reserved)
111  * @reserved: reserved
112  */
113 struct iwl_rx_completion_desc_bz {
114 	__le16 rbid;
115 	u8 flags;
116 	u8 reserved[1];
117 } __packed;
118 
119 /**
120  * struct iwl_rxq - Rx queue
121  * @id: queue index
122  * @bd: driver's pointer to buffer of receive buffer descriptors (rbd).
123  *	Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
124  *	In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's
125  * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
126  * @used_bd: driver's pointer to buffer of used receive buffer descriptors (rbd)
127  * @used_bd_dma: physical address of buffer of used receive buffer descriptors (rbd)
128  * @read: Shared index to newest available Rx buffer
129  * @write: Shared index to oldest written Rx packet
130  * @free_count: Number of pre-allocated buffers in rx_free
131  * @used_count: Number of RBDs handled to allocator to use for allocation
132  * @write_actual:
133  * @rx_free: list of RBDs with allocated RB ready for use
134  * @rx_used: list of RBDs with no RB attached
135  * @need_update: flag to indicate we need to update read/write index
136  * @rb_stts: driver's pointer to receive buffer status
137  * @rb_stts_dma: bus address of receive buffer status
138  * @lock:
139  * @queue: actual rx queue. Not used for multi-rx queue.
140  * @next_rb_is_fragment: indicates that the previous RB that we handled set
141  *	the fragmented flag, so the next one is still another fragment
142  *
143  * NOTE:  rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
144  */
145 struct iwl_rxq {
146 	int id;
147 	void *bd;
148 	dma_addr_t bd_dma;
149 	void *used_bd;
150 	dma_addr_t used_bd_dma;
151 	u32 read;
152 	u32 write;
153 	u32 free_count;
154 	u32 used_count;
155 	u32 write_actual;
156 	u32 queue_size;
157 	struct list_head rx_free;
158 	struct list_head rx_used;
159 	bool need_update, next_rb_is_fragment;
160 	void *rb_stts;
161 	dma_addr_t rb_stts_dma;
162 	spinlock_t lock;
163 	struct napi_struct napi;
164 	struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
165 };
166 
167 /**
168  * struct iwl_rb_allocator - Rx allocator
169  * @req_pending: number of requests the allcator had not processed yet
170  * @req_ready: number of requests honored and ready for claiming
171  * @rbd_allocated: RBDs with pages allocated and ready to be handled to
172  *	the queue. This is a list of &struct iwl_rx_mem_buffer
173  * @rbd_empty: RBDs with no page attached for allocator use. This is a list
174  *	of &struct iwl_rx_mem_buffer
175  * @lock: protects the rbd_allocated and rbd_empty lists
176  * @alloc_wq: work queue for background calls
177  * @rx_alloc: work struct for background calls
178  */
179 struct iwl_rb_allocator {
180 	atomic_t req_pending;
181 	atomic_t req_ready;
182 	struct list_head rbd_allocated;
183 	struct list_head rbd_empty;
184 	spinlock_t lock;
185 	struct workqueue_struct *alloc_wq;
186 	struct work_struct rx_alloc;
187 };
188 
189 /**
190  * iwl_get_closed_rb_stts - get closed rb stts from different structs
191  * @rxq - the rxq to get the rb stts from
192  */
193 static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans,
194 					    struct iwl_rxq *rxq)
195 {
196 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
197 		__le16 *rb_stts = rxq->rb_stts;
198 
199 		return READ_ONCE(*rb_stts);
200 	} else {
201 		struct iwl_rb_status *rb_stts = rxq->rb_stts;
202 
203 		return READ_ONCE(rb_stts->closed_rb_num);
204 	}
205 }
206 
207 #ifdef CONFIG_IWLWIFI_DEBUGFS
208 /**
209  * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data
210  * debugfs file
211  *
212  * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed.
213  * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open.
214  * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is
215  *	set the file can no longer be used.
216  */
217 enum iwl_fw_mon_dbgfs_state {
218 	IWL_FW_MON_DBGFS_STATE_CLOSED,
219 	IWL_FW_MON_DBGFS_STATE_OPEN,
220 	IWL_FW_MON_DBGFS_STATE_DISABLED,
221 };
222 #endif
223 
224 /**
225  * enum iwl_shared_irq_flags - level of sharing for irq
226  * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes.
227  * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
228  */
229 enum iwl_shared_irq_flags {
230 	IWL_SHARED_IRQ_NON_RX		= BIT(0),
231 	IWL_SHARED_IRQ_FIRST_RSS	= BIT(1),
232 };
233 
234 /**
235  * enum iwl_image_response_code - image response values
236  * @IWL_IMAGE_RESP_DEF: the default value of the register
237  * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully
238  * @IWL_IMAGE_RESP_FAIL: iml reading failed
239  */
240 enum iwl_image_response_code {
241 	IWL_IMAGE_RESP_DEF		= 0,
242 	IWL_IMAGE_RESP_SUCCESS		= 1,
243 	IWL_IMAGE_RESP_FAIL		= 2,
244 };
245 
246 /**
247  * struct cont_rec: continuous recording data structure
248  * @prev_wr_ptr: the last address that was read in monitor_data
249  *	debugfs file
250  * @prev_wrap_cnt: the wrap count that was used during the last read in
251  *	monitor_data debugfs file
252  * @state: the state of monitor_data debugfs file as described
253  *	in &iwl_fw_mon_dbgfs_state enum
254  * @mutex: locked while reading from monitor_data debugfs file
255  */
256 #ifdef CONFIG_IWLWIFI_DEBUGFS
257 struct cont_rec {
258 	u32 prev_wr_ptr;
259 	u32 prev_wrap_cnt;
260 	u8  state;
261 	/* Used to sync monitor_data debugfs file with driver unload flow */
262 	struct mutex mutex;
263 };
264 #endif
265 
266 enum iwl_pcie_fw_reset_state {
267 	FW_RESET_IDLE,
268 	FW_RESET_REQUESTED,
269 	FW_RESET_OK,
270 	FW_RESET_ERROR,
271 };
272 
273 /**
274  * enum wl_pcie_imr_status - imr dma transfer state
275  * @IMR_D2S_IDLE: default value of the dma transfer
276  * @IMR_D2S_REQUESTED: dma transfer requested
277  * @IMR_D2S_COMPLETED: dma transfer completed
278  * @IMR_D2S_ERROR: dma transfer error
279  */
280 enum iwl_pcie_imr_status {
281 	IMR_D2S_IDLE,
282 	IMR_D2S_REQUESTED,
283 	IMR_D2S_COMPLETED,
284 	IMR_D2S_ERROR,
285 };
286 
287 /**
288  * struct iwl_trans_pcie - PCIe transport specific data
289  * @rxq: all the RX queue data
290  * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
291  * @global_table: table mapping received VID from hw to rxb
292  * @rba: allocator for RX replenishing
293  * @ctxt_info: context information for FW self init
294  * @ctxt_info_gen3: context information for gen3 devices
295  * @prph_info: prph info for self init
296  * @prph_scratch: prph scratch for self init
297  * @ctxt_info_dma_addr: dma addr of context information
298  * @prph_info_dma_addr: dma addr of prph info
299  * @prph_scratch_dma_addr: dma addr of prph scratch
300  * @ctxt_info_dma_addr: dma addr of context information
301  * @init_dram: DRAM data of firmware image (including paging).
302  *	Context information addresses will be taken from here.
303  *	This is driver's local copy for keeping track of size and
304  *	count for allocating and freeing the memory.
305  * @iml: image loader image virtual address
306  * @iml_dma_addr: image loader image DMA address
307  * @trans: pointer to the generic transport area
308  * @scd_base_addr: scheduler sram base address in SRAM
309  * @kw: keep warm address
310  * @pnvm_data: holds info about pnvm payloads allocated in DRAM
311  * @reduced_tables_data: holds info about power reduced tablse
312  *	payloads allocated in DRAM
313  * @pci_dev: basic pci-network driver stuff
314  * @hw_base: pci hardware address support
315  * @ucode_write_complete: indicates that the ucode has been copied.
316  * @ucode_write_waitq: wait queue for uCode load
317  * @cmd_queue - command queue number
318  * @def_rx_queue - default rx queue number
319  * @rx_buf_size: Rx buffer size
320  * @scd_set_active: should the transport configure the SCD for HCMD queue
321  * @rx_page_order: page order for receive buffer size
322  * @rx_buf_bytes: RX buffer (RB) size in bytes
323  * @reg_lock: protect hw register access
324  * @mutex: to protect stop_device / start_fw / start_hw
325  * @cmd_in_flight: true when we have a host command in flight
326 #ifdef CONFIG_IWLWIFI_DEBUGFS
327  * @fw_mon_data: fw continuous recording data
328 #endif
329  * @msix_entries: array of MSI-X entries
330  * @msix_enabled: true if managed to enable MSI-X
331  * @shared_vec_mask: the type of causes the shared vector handles
332  *	(see iwl_shared_irq_flags).
333  * @alloc_vecs: the number of interrupt vectors allocated by the OS
334  * @def_irq: default irq for non rx causes
335  * @fh_init_mask: initial unmasked fh causes
336  * @hw_init_mask: initial unmasked hw causes
337  * @fh_mask: current unmasked fh causes
338  * @hw_mask: current unmasked hw causes
339  * @in_rescan: true if we have triggered a device rescan
340  * @base_rb_stts: base virtual address of receive buffer status for all queues
341  * @base_rb_stts_dma: base physical address of receive buffer status
342  * @supported_dma_mask: DMA mask to validate the actual address against,
343  *	will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device
344  * @alloc_page_lock: spinlock for the page allocator
345  * @alloc_page: allocated page to still use parts of
346  * @alloc_page_used: how much of the allocated page was already used (bytes)
347  * @imr_status: imr dma state machine
348  * @wait_queue_head_t: imr wait queue for dma completion
349  * @rf_name: name/version of the CRF, if any
350  */
351 struct iwl_trans_pcie {
352 	struct iwl_rxq *rxq;
353 	struct iwl_rx_mem_buffer *rx_pool;
354 	struct iwl_rx_mem_buffer **global_table;
355 	struct iwl_rb_allocator rba;
356 	union {
357 		struct iwl_context_info *ctxt_info;
358 		struct iwl_context_info_gen3 *ctxt_info_gen3;
359 	};
360 	struct iwl_prph_info *prph_info;
361 	struct iwl_prph_scratch *prph_scratch;
362 	void *iml;
363 	dma_addr_t ctxt_info_dma_addr;
364 	dma_addr_t prph_info_dma_addr;
365 	dma_addr_t prph_scratch_dma_addr;
366 	dma_addr_t iml_dma_addr;
367 	struct iwl_trans *trans;
368 
369 	struct net_device napi_dev;
370 
371 	/* INT ICT Table */
372 	__le32 *ict_tbl;
373 	dma_addr_t ict_tbl_dma;
374 	int ict_index;
375 	bool use_ict;
376 	bool is_down, opmode_down;
377 	s8 debug_rfkill;
378 	struct isr_statistics isr_stats;
379 
380 	spinlock_t irq_lock;
381 	struct mutex mutex;
382 	u32 inta_mask;
383 	u32 scd_base_addr;
384 	struct iwl_dma_ptr kw;
385 
386 	/* pnvm data */
387 	struct iwl_dram_regions pnvm_data;
388 	struct iwl_dram_regions reduced_tables_data;
389 
390 	struct iwl_txq *txq_memory;
391 
392 	/* PCI bus related data */
393 	struct pci_dev *pci_dev;
394 	u8 __iomem *hw_base;
395 
396 	bool ucode_write_complete;
397 	bool sx_complete;
398 	wait_queue_head_t ucode_write_waitq;
399 	wait_queue_head_t sx_waitq;
400 
401 	u8 def_rx_queue;
402 	u8 n_no_reclaim_cmds;
403 	u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
404 	u16 num_rx_bufs;
405 
406 	enum iwl_amsdu_size rx_buf_size;
407 	bool scd_set_active;
408 	bool pcie_dbg_dumped_once;
409 	u32 rx_page_order;
410 	u32 rx_buf_bytes;
411 	u32 supported_dma_mask;
412 
413 	/* allocator lock for the two values below */
414 	spinlock_t alloc_page_lock;
415 	struct page *alloc_page;
416 	u32 alloc_page_used;
417 
418 	/*protect hw register */
419 	spinlock_t reg_lock;
420 	bool cmd_hold_nic_awake;
421 
422 #ifdef CONFIG_IWLWIFI_DEBUGFS
423 	struct cont_rec fw_mon_data;
424 #endif
425 
426 	struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
427 	bool msix_enabled;
428 	u8 shared_vec_mask;
429 	u32 alloc_vecs;
430 	u32 def_irq;
431 	u32 fh_init_mask;
432 	u32 hw_init_mask;
433 	u32 fh_mask;
434 	u32 hw_mask;
435 	cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
436 	u16 tx_cmd_queue_size;
437 	bool in_rescan;
438 
439 	void *base_rb_stts;
440 	dma_addr_t base_rb_stts_dma;
441 
442 	bool fw_reset_handshake;
443 	enum iwl_pcie_fw_reset_state fw_reset_state;
444 	wait_queue_head_t fw_reset_waitq;
445 	enum iwl_pcie_imr_status imr_status;
446 	wait_queue_head_t imr_waitq;
447 	char rf_name[32];
448 };
449 
450 static inline struct iwl_trans_pcie *
451 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
452 {
453 	return (void *)trans->trans_specific;
454 }
455 
456 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue)
457 {
458 	/*
459 	 * Before sending the interrupt the HW disables it to prevent
460 	 * a nested interrupt. This is done by writing 1 to the corresponding
461 	 * bit in the mask register. After handling the interrupt, it should be
462 	 * re-enabled by clearing this bit. This register is defined as
463 	 * write 1 clear (W1C) register, meaning that it's being clear
464 	 * by writing 1 to the bit.
465 	 */
466 	iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));
467 }
468 
469 static inline struct iwl_trans *
470 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
471 {
472 	return container_of((void *)trans_pcie, struct iwl_trans,
473 			    trans_specific);
474 }
475 
476 /*
477  * Convention: trans API functions: iwl_trans_pcie_XXX
478  *	Other functions: iwl_pcie_XXX
479  */
480 struct iwl_trans
481 *iwl_trans_pcie_alloc(struct pci_dev *pdev,
482 		      const struct pci_device_id *ent,
483 		      const struct iwl_cfg_trans_params *cfg_trans);
484 void iwl_trans_pcie_free(struct iwl_trans *trans);
485 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
486 					   struct device *dev);
487 
488 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
489 #define _iwl_trans_pcie_grab_nic_access(trans)			\
490 	__cond_lock(nic_access_nobh,				\
491 		    likely(__iwl_trans_pcie_grab_nic_access(trans)))
492 
493 /*****************************************************
494 * RX
495 ******************************************************/
496 int iwl_pcie_rx_init(struct iwl_trans *trans);
497 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
498 irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
499 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
500 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
501 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
502 int iwl_pcie_rx_stop(struct iwl_trans *trans);
503 void iwl_pcie_rx_free(struct iwl_trans *trans);
504 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
505 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq);
506 void iwl_pcie_rx_napi_sync(struct iwl_trans *trans);
507 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
508 			    struct iwl_rxq *rxq);
509 
510 /*****************************************************
511 * ICT - interrupt handling
512 ******************************************************/
513 irqreturn_t iwl_pcie_isr(int irq, void *data);
514 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
515 void iwl_pcie_free_ict(struct iwl_trans *trans);
516 void iwl_pcie_reset_ict(struct iwl_trans *trans);
517 void iwl_pcie_disable_ict(struct iwl_trans *trans);
518 
519 /*****************************************************
520 * TX / HCMD
521 ******************************************************/
522 int iwl_pcie_tx_init(struct iwl_trans *trans);
523 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
524 int iwl_pcie_tx_stop(struct iwl_trans *trans);
525 void iwl_pcie_tx_free(struct iwl_trans *trans);
526 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
527 			       const struct iwl_trans_txq_scd_cfg *cfg,
528 			       unsigned int wdg_timeout);
529 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
530 				bool configure_scd);
531 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
532 					bool shared_mode);
533 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
534 		      struct iwl_device_tx_cmd *dev_cmd, int txq_id);
535 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
536 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
537 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
538 			    struct iwl_rx_cmd_buffer *rxb);
539 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
540 
541 /*****************************************************
542 * Error handling
543 ******************************************************/
544 void iwl_pcie_dump_csr(struct iwl_trans *trans);
545 
546 /*****************************************************
547 * Helpers
548 ******************************************************/
549 static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
550 {
551 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
552 
553 	clear_bit(STATUS_INT_ENABLED, &trans->status);
554 	if (!trans_pcie->msix_enabled) {
555 		/* disable interrupts from uCode/NIC to host */
556 		iwl_write32(trans, CSR_INT_MASK, 0x00000000);
557 
558 		/* acknowledge/clear/reset any interrupts still pending
559 		 * from uCode or flow handler (Rx/Tx DMA) */
560 		iwl_write32(trans, CSR_INT, 0xffffffff);
561 		iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
562 	} else {
563 		/* disable all the interrupt we might use */
564 		iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
565 			    trans_pcie->fh_init_mask);
566 		iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
567 			    trans_pcie->hw_init_mask);
568 	}
569 	IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
570 }
571 
572 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw,
573 					    int start)
574 {
575 	int i = 0;
576 
577 	while (start < fw->num_sec &&
578 	       fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION &&
579 	       fw->sec[start].offset != PAGING_SEPARATOR_SECTION) {
580 		start++;
581 		i++;
582 	}
583 
584 	return i;
585 }
586 
587 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
588 {
589 	struct iwl_self_init_dram *dram = &trans->init_dram;
590 	int i;
591 
592 	if (!dram->fw) {
593 		WARN_ON(dram->fw_cnt);
594 		return;
595 	}
596 
597 	for (i = 0; i < dram->fw_cnt; i++)
598 		dma_free_coherent(trans->dev, dram->fw[i].size,
599 				  dram->fw[i].block, dram->fw[i].physical);
600 
601 	kfree(dram->fw);
602 	dram->fw_cnt = 0;
603 	dram->fw = NULL;
604 }
605 
606 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
607 {
608 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
609 
610 	spin_lock_bh(&trans_pcie->irq_lock);
611 	_iwl_disable_interrupts(trans);
612 	spin_unlock_bh(&trans_pcie->irq_lock);
613 }
614 
615 static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
616 {
617 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
618 
619 	IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
620 	set_bit(STATUS_INT_ENABLED, &trans->status);
621 	if (!trans_pcie->msix_enabled) {
622 		trans_pcie->inta_mask = CSR_INI_SET_MASK;
623 		iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
624 	} else {
625 		/*
626 		 * fh/hw_mask keeps all the unmasked causes.
627 		 * Unlike msi, in msix cause is enabled when it is unset.
628 		 */
629 		trans_pcie->hw_mask = trans_pcie->hw_init_mask;
630 		trans_pcie->fh_mask = trans_pcie->fh_init_mask;
631 		iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
632 			    ~trans_pcie->fh_mask);
633 		iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
634 			    ~trans_pcie->hw_mask);
635 	}
636 }
637 
638 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
639 {
640 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
641 
642 	spin_lock_bh(&trans_pcie->irq_lock);
643 	_iwl_enable_interrupts(trans);
644 	spin_unlock_bh(&trans_pcie->irq_lock);
645 }
646 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
647 {
648 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
649 
650 	iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
651 	trans_pcie->hw_mask = msk;
652 }
653 
654 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
655 {
656 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
657 
658 	iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
659 	trans_pcie->fh_mask = msk;
660 }
661 
662 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
663 {
664 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
665 
666 	IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
667 	if (!trans_pcie->msix_enabled) {
668 		trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
669 		iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
670 	} else {
671 		iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
672 			    trans_pcie->hw_init_mask);
673 		iwl_enable_fh_int_msk_msix(trans,
674 					   MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
675 	}
676 }
677 
678 static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans)
679 {
680 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
681 
682 	IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n");
683 
684 	if (!trans_pcie->msix_enabled) {
685 		/*
686 		 * When we'll receive the ALIVE interrupt, the ISR will call
687 		 * iwl_enable_fw_load_int_ctx_info again to set the ALIVE
688 		 * interrupt (which is not really needed anymore) but also the
689 		 * RX interrupt which will allow us to receive the ALIVE
690 		 * notification (which is Rx) and continue the flow.
691 		 */
692 		trans_pcie->inta_mask =  CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX;
693 		iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
694 	} else {
695 		iwl_enable_hw_int_msk_msix(trans,
696 					   MSIX_HW_INT_CAUSES_REG_ALIVE);
697 		/*
698 		 * Leave all the FH causes enabled to get the ALIVE
699 		 * notification.
700 		 */
701 		iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask);
702 	}
703 }
704 
705 static inline const char *queue_name(struct device *dev,
706 				     struct iwl_trans_pcie *trans_p, int i)
707 {
708 	if (trans_p->shared_vec_mask) {
709 		int vec = trans_p->shared_vec_mask &
710 			  IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
711 
712 		if (i == 0)
713 			return DRV_NAME ":shared_IRQ";
714 
715 		return devm_kasprintf(dev, GFP_KERNEL,
716 				      DRV_NAME ":queue_%d", i + vec);
717 	}
718 	if (i == 0)
719 		return DRV_NAME ":default_queue";
720 
721 	if (i == trans_p->alloc_vecs - 1)
722 		return DRV_NAME ":exception";
723 
724 	return devm_kasprintf(dev, GFP_KERNEL,
725 			      DRV_NAME  ":queue_%d", i);
726 }
727 
728 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
729 {
730 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
731 
732 	IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
733 	if (!trans_pcie->msix_enabled) {
734 		trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
735 		iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
736 	} else {
737 		iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
738 			    trans_pcie->fh_init_mask);
739 		iwl_enable_hw_int_msk_msix(trans,
740 					   MSIX_HW_INT_CAUSES_REG_RF_KILL);
741 	}
742 
743 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) {
744 		/*
745 		 * On 9000-series devices this bit isn't enabled by default, so
746 		 * when we power down the device we need set the bit to allow it
747 		 * to wake up the PCI-E bus for RF-kill interrupts.
748 		 */
749 		iwl_set_bit(trans, CSR_GP_CNTRL,
750 			    CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
751 	}
752 }
753 
754 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans);
755 
756 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
757 {
758 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
759 
760 	lockdep_assert_held(&trans_pcie->mutex);
761 
762 	if (trans_pcie->debug_rfkill == 1)
763 		return true;
764 
765 	return !(iwl_read32(trans, CSR_GP_CNTRL) &
766 		CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
767 }
768 
769 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
770 						  u32 reg, u32 mask, u32 value)
771 {
772 	u32 v;
773 
774 #ifdef CONFIG_IWLWIFI_DEBUG
775 	WARN_ON_ONCE(value & ~mask);
776 #endif
777 
778 	v = iwl_read32(trans, reg);
779 	v &= ~mask;
780 	v |= value;
781 	iwl_write32(trans, reg, v);
782 }
783 
784 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
785 					      u32 reg, u32 mask)
786 {
787 	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
788 }
789 
790 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
791 					    u32 reg, u32 mask)
792 {
793 	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
794 }
795 
796 static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
797 {
798 	return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans));
799 }
800 
801 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
802 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
803 
804 #ifdef CONFIG_IWLWIFI_DEBUGFS
805 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
806 #else
807 static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { }
808 #endif
809 
810 void iwl_pcie_rx_allocator_work(struct work_struct *data);
811 
812 /* common functions that are used by gen2 transport */
813 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans);
814 void iwl_pcie_apm_config(struct iwl_trans *trans);
815 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
816 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
817 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans);
818 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
819 				       bool was_in_rfkill);
820 void iwl_pcie_apm_stop_master(struct iwl_trans *trans);
821 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie);
822 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
823 			   struct iwl_dma_ptr *ptr, size_t size);
824 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr);
825 void iwl_pcie_apply_destination(struct iwl_trans *trans);
826 
827 /* common functions that are used by gen3 transport */
828 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power);
829 
830 /* transport gen 2 exported functions */
831 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
832 				 const struct fw_img *fw, bool run_in_rfkill);
833 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr);
834 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
835 				  struct iwl_host_cmd *cmd);
836 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
837 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
838 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
839 				  bool test, bool reset);
840 int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
841 			       struct iwl_host_cmd *cmd);
842 int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
843 			  struct iwl_host_cmd *cmd);
844 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
845 				u32 dst_addr, u64 src_addr, u32 byte_cnt);
846 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
847 			    u32 dst_addr, u64 src_addr, u32 byte_cnt);
848 
849 #endif /* __iwl_trans_int_pcie_h__ */
850