1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 4e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 61b493e30SGolan Ben Ami * Copyright(c) 2018 Intel Corporation 7e705c121SKalle Valo * 8e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 9e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 10e705c121SKalle Valo * 11e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 12e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 13e705c121SKalle Valo * published by the Free Software Foundation. 14e705c121SKalle Valo * 15e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 16e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18e705c121SKalle Valo * more details. 19e705c121SKalle Valo * 20e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 211b493e30SGolan Ben Ami * this program. 22e705c121SKalle Valo * 23e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 24e705c121SKalle Valo * file called LICENSE. 25e705c121SKalle Valo * 26e705c121SKalle Valo * Contact Information: 27cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 28e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29e705c121SKalle Valo * 30e705c121SKalle Valo *****************************************************************************/ 31e705c121SKalle Valo #ifndef __iwl_trans_int_pcie_h__ 32e705c121SKalle Valo #define __iwl_trans_int_pcie_h__ 33e705c121SKalle Valo 34e705c121SKalle Valo #include <linux/spinlock.h> 35e705c121SKalle Valo #include <linux/interrupt.h> 36e705c121SKalle Valo #include <linux/skbuff.h> 37e705c121SKalle Valo #include <linux/wait.h> 38e705c121SKalle Valo #include <linux/pci.h> 39e705c121SKalle Valo #include <linux/timer.h> 407c8d91ebSHaim Dreyfuss #include <linux/cpu.h> 41e705c121SKalle Valo 42e705c121SKalle Valo #include "iwl-fh.h" 43e705c121SKalle Valo #include "iwl-csr.h" 44e705c121SKalle Valo #include "iwl-trans.h" 45e705c121SKalle Valo #include "iwl-debug.h" 46e705c121SKalle Valo #include "iwl-io.h" 47e705c121SKalle Valo #include "iwl-op-mode.h" 48e705c121SKalle Valo 49e705c121SKalle Valo /* We need 2 entries for the TX command and header, and another one might 50e705c121SKalle Valo * be needed for potential data in the SKB's head. The remaining ones can 51e705c121SKalle Valo * be used for frags. 52e705c121SKalle Valo */ 533cd1980bSSara Sharon #define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3) 54e705c121SKalle Valo 55e705c121SKalle Valo /* 56e705c121SKalle Valo * RX related structures and functions 57e705c121SKalle Valo */ 58e705c121SKalle Valo #define RX_NUM_QUEUES 1 59e705c121SKalle Valo #define RX_POST_REQ_ALLOC 2 60e705c121SKalle Valo #define RX_CLAIM_REQ_ALLOC 8 6178485054SSara Sharon #define RX_PENDING_WATERMARK 16 621b493e30SGolan Ben Ami #define FIRST_RX_QUEUE 512 63e705c121SKalle Valo 64e705c121SKalle Valo struct iwl_host_cmd; 65e705c121SKalle Valo 66e705c121SKalle Valo /*This file includes the declaration that are internal to the 67e705c121SKalle Valo * trans_pcie layer */ 68e705c121SKalle Valo 6996a6497bSSara Sharon /** 7096a6497bSSara Sharon * struct iwl_rx_mem_buffer 7196a6497bSSara Sharon * @page_dma: bus address of rxb page 7296a6497bSSara Sharon * @page: driver's pointer to the rxb page 73b1753c62SSara Sharon * @invalid: rxb is in driver ownership - not owned by HW 7496a6497bSSara Sharon * @vid: index of this rxb in the global table 7596a6497bSSara Sharon */ 76e705c121SKalle Valo struct iwl_rx_mem_buffer { 77e705c121SKalle Valo dma_addr_t page_dma; 78e705c121SKalle Valo struct page *page; 7996a6497bSSara Sharon u16 vid; 80b1753c62SSara Sharon bool invalid; 81e705c121SKalle Valo struct list_head list; 82e705c121SKalle Valo }; 83e705c121SKalle Valo 84e705c121SKalle Valo /** 85e705c121SKalle Valo * struct isr_statistics - interrupt statistics 86e705c121SKalle Valo * 87e705c121SKalle Valo */ 88e705c121SKalle Valo struct isr_statistics { 89e705c121SKalle Valo u32 hw; 90e705c121SKalle Valo u32 sw; 91e705c121SKalle Valo u32 err_code; 92e705c121SKalle Valo u32 sch; 93e705c121SKalle Valo u32 alive; 94e705c121SKalle Valo u32 rfkill; 95e705c121SKalle Valo u32 ctkill; 96e705c121SKalle Valo u32 wakeup; 97e705c121SKalle Valo u32 rx; 98e705c121SKalle Valo u32 tx; 99e705c121SKalle Valo u32 unhandled; 100e705c121SKalle Valo }; 101e705c121SKalle Valo 102e705c121SKalle Valo /** 103e705c121SKalle Valo * struct iwl_rxq - Rx queue 10496a6497bSSara Sharon * @id: queue index 10596a6497bSSara Sharon * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 10696a6497bSSara Sharon * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 107e705c121SKalle Valo * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 10896a6497bSSara Sharon * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd) 10996a6497bSSara Sharon * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd) 1101b493e30SGolan Ben Ami * @tr_tail: driver's pointer to the transmission ring tail buffer 1111b493e30SGolan Ben Ami * @tr_tail_dma: physical address of the buffer for the transmission ring tail 1121b493e30SGolan Ben Ami * @cr_tail: driver's pointer to the completion ring tail buffer 1131b493e30SGolan Ben Ami * @cr_tail_dma: physical address of the buffer for the completion ring tail 114e705c121SKalle Valo * @read: Shared index to newest available Rx buffer 115e705c121SKalle Valo * @write: Shared index to oldest written Rx packet 116e705c121SKalle Valo * @free_count: Number of pre-allocated buffers in rx_free 117e705c121SKalle Valo * @used_count: Number of RBDs handled to allocator to use for allocation 118e705c121SKalle Valo * @write_actual: 119e705c121SKalle Valo * @rx_free: list of RBDs with allocated RB ready for use 120e705c121SKalle Valo * @rx_used: list of RBDs with no RB attached 121e705c121SKalle Valo * @need_update: flag to indicate we need to update read/write index 122e705c121SKalle Valo * @rb_stts: driver's pointer to receive buffer status 123e705c121SKalle Valo * @rb_stts_dma: bus address of receive buffer status 124e705c121SKalle Valo * @lock: 12596a6497bSSara Sharon * @queue: actual rx queue. Not used for multi-rx queue. 126e705c121SKalle Valo * 127e705c121SKalle Valo * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 128e705c121SKalle Valo */ 129e705c121SKalle Valo struct iwl_rxq { 13096a6497bSSara Sharon int id; 13196a6497bSSara Sharon void *bd; 132e705c121SKalle Valo dma_addr_t bd_dma; 13396a6497bSSara Sharon __le32 *used_bd; 13496a6497bSSara Sharon dma_addr_t used_bd_dma; 1351b493e30SGolan Ben Ami __le16 *tr_tail; 1361b493e30SGolan Ben Ami dma_addr_t tr_tail_dma; 1371b493e30SGolan Ben Ami __le16 *cr_tail; 1381b493e30SGolan Ben Ami dma_addr_t cr_tail_dma; 139e705c121SKalle Valo u32 read; 140e705c121SKalle Valo u32 write; 141e705c121SKalle Valo u32 free_count; 142e705c121SKalle Valo u32 used_count; 143e705c121SKalle Valo u32 write_actual; 14496a6497bSSara Sharon u32 queue_size; 145e705c121SKalle Valo struct list_head rx_free; 146e705c121SKalle Valo struct list_head rx_used; 147e705c121SKalle Valo bool need_update; 148e705c121SKalle Valo struct iwl_rb_status *rb_stts; 149e705c121SKalle Valo dma_addr_t rb_stts_dma; 150e705c121SKalle Valo spinlock_t lock; 151bce97731SSara Sharon struct napi_struct napi; 152e705c121SKalle Valo struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 153e705c121SKalle Valo }; 154e705c121SKalle Valo 155e705c121SKalle Valo /** 156e705c121SKalle Valo * struct iwl_rb_allocator - Rx allocator 157e705c121SKalle Valo * @req_pending: number of requests the allcator had not processed yet 158e705c121SKalle Valo * @req_ready: number of requests honored and ready for claiming 159e705c121SKalle Valo * @rbd_allocated: RBDs with pages allocated and ready to be handled to 160e705c121SKalle Valo * the queue. This is a list of &struct iwl_rx_mem_buffer 161e705c121SKalle Valo * @rbd_empty: RBDs with no page attached for allocator use. This is a list 162e705c121SKalle Valo * of &struct iwl_rx_mem_buffer 163e705c121SKalle Valo * @lock: protects the rbd_allocated and rbd_empty lists 164e705c121SKalle Valo * @alloc_wq: work queue for background calls 165e705c121SKalle Valo * @rx_alloc: work struct for background calls 166e705c121SKalle Valo */ 167e705c121SKalle Valo struct iwl_rb_allocator { 168e705c121SKalle Valo atomic_t req_pending; 169e705c121SKalle Valo atomic_t req_ready; 170e705c121SKalle Valo struct list_head rbd_allocated; 171e705c121SKalle Valo struct list_head rbd_empty; 172e705c121SKalle Valo spinlock_t lock; 173e705c121SKalle Valo struct workqueue_struct *alloc_wq; 174e705c121SKalle Valo struct work_struct rx_alloc; 175e705c121SKalle Valo }; 176e705c121SKalle Valo 177e705c121SKalle Valo struct iwl_dma_ptr { 178e705c121SKalle Valo dma_addr_t dma; 179e705c121SKalle Valo void *addr; 180e705c121SKalle Valo size_t size; 181e705c121SKalle Valo }; 182e705c121SKalle Valo 183e705c121SKalle Valo /** 184e705c121SKalle Valo * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 185e705c121SKalle Valo * @index -- current index 186e705c121SKalle Valo */ 187e705c121SKalle Valo static inline int iwl_queue_inc_wrap(int index) 188e705c121SKalle Valo { 189e705c121SKalle Valo return ++index & (TFD_QUEUE_SIZE_MAX - 1); 190e705c121SKalle Valo } 191e705c121SKalle Valo 192e705c121SKalle Valo /** 193e705c121SKalle Valo * iwl_queue_dec_wrap - decrement queue index, wrap back to end 194e705c121SKalle Valo * @index -- current index 195e705c121SKalle Valo */ 196e705c121SKalle Valo static inline int iwl_queue_dec_wrap(int index) 197e705c121SKalle Valo { 198e705c121SKalle Valo return --index & (TFD_QUEUE_SIZE_MAX - 1); 199e705c121SKalle Valo } 200e705c121SKalle Valo 201e705c121SKalle Valo struct iwl_cmd_meta { 202e705c121SKalle Valo /* only for SYNC commands, iff the reply skb is wanted */ 203e705c121SKalle Valo struct iwl_host_cmd *source; 204e705c121SKalle Valo u32 flags; 2053cd1980bSSara Sharon u32 tbs; 206e705c121SKalle Valo }; 207e705c121SKalle Valo 208e705c121SKalle Valo 209e705c121SKalle Valo #define TFD_TX_CMD_SLOTS 256 210e705c121SKalle Valo #define TFD_CMD_SLOTS 32 211e705c121SKalle Valo 212e705c121SKalle Valo /* 2138de437c7SSara Sharon * The FH will write back to the first TB only, so we need to copy some data 2148de437c7SSara Sharon * into the buffer regardless of whether it should be mapped or not. 2158de437c7SSara Sharon * This indicates how big the first TB must be to include the scratch buffer 2168de437c7SSara Sharon * and the assigned PN. 217b97277ccSSara Sharon * Since PN location is 8 bytes at offset 12, it's 20 now. 2188de437c7SSara Sharon * If we make it bigger then allocations will be bigger and copy slower, so 2198de437c7SSara Sharon * that's probably not useful. 220e705c121SKalle Valo */ 221b97277ccSSara Sharon #define IWL_FIRST_TB_SIZE 20 2228de437c7SSara Sharon #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 223e705c121SKalle Valo 224e705c121SKalle Valo struct iwl_pcie_txq_entry { 225e705c121SKalle Valo struct iwl_device_cmd *cmd; 226e705c121SKalle Valo struct sk_buff *skb; 227e705c121SKalle Valo /* buffer to free after command completes */ 228e705c121SKalle Valo const void *free_buf; 229e705c121SKalle Valo struct iwl_cmd_meta meta; 230e705c121SKalle Valo }; 231e705c121SKalle Valo 2328de437c7SSara Sharon struct iwl_pcie_first_tb_buf { 2338de437c7SSara Sharon u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 234e705c121SKalle Valo }; 235e705c121SKalle Valo 236e705c121SKalle Valo /** 237e705c121SKalle Valo * struct iwl_txq - Tx Queue for DMA 238e705c121SKalle Valo * @q: generic Rx/Tx queue descriptor 239e705c121SKalle Valo * @tfds: transmit frame descriptors (DMA memory) 2408de437c7SSara Sharon * @first_tb_bufs: start of command headers, including scratch buffers, for 241e705c121SKalle Valo * the writeback -- this is DMA memory and an array holding one buffer 242e705c121SKalle Valo * for each command on the queue 2438de437c7SSara Sharon * @first_tb_dma: DMA address for the first_tb_bufs start 244e705c121SKalle Valo * @entries: transmit entries (driver state) 245e705c121SKalle Valo * @lock: queue lock 246e705c121SKalle Valo * @stuck_timer: timer that fires if queue gets stuck 247e705c121SKalle Valo * @trans_pcie: pointer back to transport (for timer) 248e705c121SKalle Valo * @need_update: indicates need to update read/write index 249e705c121SKalle Valo * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 250e705c121SKalle Valo * @wd_timeout: queue watchdog timeout (jiffies) - per queue 251e705c121SKalle Valo * @frozen: tx stuck queue timer is frozen 252e705c121SKalle Valo * @frozen_expiry_remainder: remember how long until the timer fires 25313a3a390SSara Sharon * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 254bb98ecd4SSara Sharon * @write_ptr: 1-st empty entry (index) host_w 255bb98ecd4SSara Sharon * @read_ptr: last used entry (index) host_r 256bb98ecd4SSara Sharon * @dma_addr: physical addr for BD's 257bb98ecd4SSara Sharon * @n_window: safe queue window 258bb98ecd4SSara Sharon * @id: queue id 259bb98ecd4SSara Sharon * @low_mark: low watermark, resume queue if free space more than this 260bb98ecd4SSara Sharon * @high_mark: high watermark, stop queue if free space less than this 261e705c121SKalle Valo * 262e705c121SKalle Valo * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 263e705c121SKalle Valo * descriptors) and required locking structures. 264bb98ecd4SSara Sharon * 265bb98ecd4SSara Sharon * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 266bb98ecd4SSara Sharon * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 267bb98ecd4SSara Sharon * there might be HW changes in the future). For the normal TX 268bb98ecd4SSara Sharon * queues, n_window, which is the size of the software queue data 269bb98ecd4SSara Sharon * is also 256; however, for the command queue, n_window is only 270bb98ecd4SSara Sharon * 32 since we don't need so many commands pending. Since the HW 271bb98ecd4SSara Sharon * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 272bb98ecd4SSara Sharon * This means that we end up with the following: 273bb98ecd4SSara Sharon * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 274bb98ecd4SSara Sharon * SW entries: | 0 | ... | 31 | 275bb98ecd4SSara Sharon * where N is a number between 0 and 7. This means that the SW 276bb98ecd4SSara Sharon * data is a window overlayed over the HW queue. 277e705c121SKalle Valo */ 278e705c121SKalle Valo struct iwl_txq { 2796983ba69SSara Sharon void *tfds; 2808de437c7SSara Sharon struct iwl_pcie_first_tb_buf *first_tb_bufs; 2818de437c7SSara Sharon dma_addr_t first_tb_dma; 282e705c121SKalle Valo struct iwl_pcie_txq_entry *entries; 283e705c121SKalle Valo spinlock_t lock; 284e705c121SKalle Valo unsigned long frozen_expiry_remainder; 285e705c121SKalle Valo struct timer_list stuck_timer; 286e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 287e705c121SKalle Valo bool need_update; 288e705c121SKalle Valo bool frozen; 289e705c121SKalle Valo bool ampdu; 29004fa3e68SEmmanuel Grumbach int block; 291e705c121SKalle Valo unsigned long wd_timeout; 2923955525dSEmmanuel Grumbach struct sk_buff_head overflow_q; 29313a3a390SSara Sharon struct iwl_dma_ptr bc_tbl; 294bb98ecd4SSara Sharon 295bb98ecd4SSara Sharon int write_ptr; 296bb98ecd4SSara Sharon int read_ptr; 297bb98ecd4SSara Sharon dma_addr_t dma_addr; 298bb98ecd4SSara Sharon int n_window; 299bb98ecd4SSara Sharon u32 id; 300bb98ecd4SSara Sharon int low_mark; 301bb98ecd4SSara Sharon int high_mark; 302e705c121SKalle Valo }; 303e705c121SKalle Valo 304e705c121SKalle Valo static inline dma_addr_t 3058de437c7SSara Sharon iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx) 306e705c121SKalle Valo { 3078de437c7SSara Sharon return txq->first_tb_dma + 3088de437c7SSara Sharon sizeof(struct iwl_pcie_first_tb_buf) * idx; 309e705c121SKalle Valo } 310e705c121SKalle Valo 3116eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page { 3126eb5e529SEmmanuel Grumbach struct page *page; 3136eb5e529SEmmanuel Grumbach u8 *pos; 3146eb5e529SEmmanuel Grumbach }; 3156eb5e529SEmmanuel Grumbach 316e705c121SKalle Valo /** 317496d83caSHaim Dreyfuss * enum iwl_shared_irq_flags - level of sharing for irq 318496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 319496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 320496d83caSHaim Dreyfuss */ 321496d83caSHaim Dreyfuss enum iwl_shared_irq_flags { 322496d83caSHaim Dreyfuss IWL_SHARED_IRQ_NON_RX = BIT(0), 323496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 324496d83caSHaim Dreyfuss }; 325496d83caSHaim Dreyfuss 326496d83caSHaim Dreyfuss /** 3279b58419eSGolan Ben Ami * enum iwl_image_response_code - image response values 3289b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_DEF: the default value of the register 3299b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully 3309b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_FAIL: iml reading failed 3319b58419eSGolan Ben Ami */ 3329b58419eSGolan Ben Ami enum iwl_image_response_code { 3339b58419eSGolan Ben Ami IWL_IMAGE_RESP_DEF = 0, 3349b58419eSGolan Ben Ami IWL_IMAGE_RESP_SUCCESS = 1, 3359b58419eSGolan Ben Ami IWL_IMAGE_RESP_FAIL = 2, 3369b58419eSGolan Ben Ami }; 3379b58419eSGolan Ben Ami 3389b58419eSGolan Ben Ami /** 339eda50cdeSSara Sharon * struct iwl_dram_data 340eda50cdeSSara Sharon * @physical: page phy pointer 341eda50cdeSSara Sharon * @block: pointer to the allocated block/page 342eda50cdeSSara Sharon * @size: size of the block/page 343eda50cdeSSara Sharon */ 344eda50cdeSSara Sharon struct iwl_dram_data { 345eda50cdeSSara Sharon dma_addr_t physical; 346eda50cdeSSara Sharon void *block; 347eda50cdeSSara Sharon int size; 348eda50cdeSSara Sharon }; 349eda50cdeSSara Sharon 350eda50cdeSSara Sharon /** 351eda50cdeSSara Sharon * struct iwl_self_init_dram - dram data used by self init process 352eda50cdeSSara Sharon * @fw: lmac and umac dram data 353eda50cdeSSara Sharon * @fw_cnt: total number of items in array 354eda50cdeSSara Sharon * @paging: paging dram data 355eda50cdeSSara Sharon * @paging_cnt: total number of items in array 356eda50cdeSSara Sharon */ 357eda50cdeSSara Sharon struct iwl_self_init_dram { 358eda50cdeSSara Sharon struct iwl_dram_data *fw; 359eda50cdeSSara Sharon int fw_cnt; 360eda50cdeSSara Sharon struct iwl_dram_data *paging; 361eda50cdeSSara Sharon int paging_cnt; 362eda50cdeSSara Sharon }; 363eda50cdeSSara Sharon 364eda50cdeSSara Sharon /** 365e705c121SKalle Valo * struct iwl_trans_pcie - PCIe transport specific data 366e705c121SKalle Valo * @rxq: all the RX queue data 36778485054SSara Sharon * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 36896a6497bSSara Sharon * @global_table: table mapping received VID from hw to rxb 369e705c121SKalle Valo * @rba: allocator for RX replenishing 370eda50cdeSSara Sharon * @ctxt_info: context information for FW self init 3712ee82402SGolan Ben Ami * @ctxt_info_gen3: context information for gen3 devices 3722ee82402SGolan Ben Ami * @prph_info: prph info for self init 3732ee82402SGolan Ben Ami * @prph_scratch: prph scratch for self init 3742ee82402SGolan Ben Ami * @ctxt_info_dma_addr: dma addr of context information 3752ee82402SGolan Ben Ami * @prph_info_dma_addr: dma addr of prph info 3762ee82402SGolan Ben Ami * @prph_scratch_dma_addr: dma addr of prph scratch 377eda50cdeSSara Sharon * @ctxt_info_dma_addr: dma addr of context information 378eda50cdeSSara Sharon * @init_dram: DRAM data of firmware image (including paging). 379eda50cdeSSara Sharon * Context information addresses will be taken from here. 380eda50cdeSSara Sharon * This is driver's local copy for keeping track of size and 381eda50cdeSSara Sharon * count for allocating and freeing the memory. 382e705c121SKalle Valo * @trans: pointer to the generic transport area 383e705c121SKalle Valo * @scd_base_addr: scheduler sram base address in SRAM 384e705c121SKalle Valo * @scd_bc_tbls: pointer to the byte count table of the scheduler 385e705c121SKalle Valo * @kw: keep warm address 386e705c121SKalle Valo * @pci_dev: basic pci-network driver stuff 387e705c121SKalle Valo * @hw_base: pci hardware address support 388e705c121SKalle Valo * @ucode_write_complete: indicates that the ucode has been copied. 389e705c121SKalle Valo * @ucode_write_waitq: wait queue for uCode load 390e705c121SKalle Valo * @cmd_queue - command queue number 3916c4fbcbcSEmmanuel Grumbach * @rx_buf_size: Rx buffer size 392e705c121SKalle Valo * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 393e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 39441837ca9SEmmanuel Grumbach * @sw_csum_tx: if true, then the transport will compute the csum of the TXed 39541837ca9SEmmanuel Grumbach * frame. 396e705c121SKalle Valo * @rx_page_order: page order for receive buffer size 397e705c121SKalle Valo * @reg_lock: protect hw register access 398e705c121SKalle Valo * @mutex: to protect stop_device / start_fw / start_hw 399e705c121SKalle Valo * @cmd_in_flight: true when we have a host command in flight 400e705c121SKalle Valo * @fw_mon_phys: physical address of the buffer for the firmware monitor 401e705c121SKalle Valo * @fw_mon_page: points to the first page of the buffer for the firmware monitor 402e705c121SKalle Valo * @fw_mon_size: size of the buffer for the firmware monitor 4032e5d4a8fSHaim Dreyfuss * @msix_entries: array of MSI-X entries 4042e5d4a8fSHaim Dreyfuss * @msix_enabled: true if managed to enable MSI-X 405496d83caSHaim Dreyfuss * @shared_vec_mask: the type of causes the shared vector handles 406496d83caSHaim Dreyfuss * (see iwl_shared_irq_flags). 407496d83caSHaim Dreyfuss * @alloc_vecs: the number of interrupt vectors allocated by the OS 408496d83caSHaim Dreyfuss * @def_irq: default irq for non rx causes 4092e5d4a8fSHaim Dreyfuss * @fh_init_mask: initial unmasked fh causes 4102e5d4a8fSHaim Dreyfuss * @hw_init_mask: initial unmasked hw causes 4112e5d4a8fSHaim Dreyfuss * @fh_mask: current unmasked fh causes 4122e5d4a8fSHaim Dreyfuss * @hw_mask: current unmasked hw causes 41349564a80SLuca Coelho * @in_rescan: true if we have triggered a device rescan 41449564a80SLuca Coelho * @scheduled_for_removal: true if we have scheduled a device removal 415e705c121SKalle Valo */ 416e705c121SKalle Valo struct iwl_trans_pcie { 41778485054SSara Sharon struct iwl_rxq *rxq; 4187b542436SSara Sharon struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE]; 41943146925SSara Sharon struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE]; 420e705c121SKalle Valo struct iwl_rb_allocator rba; 4212ee82402SGolan Ben Ami union { 422eda50cdeSSara Sharon struct iwl_context_info *ctxt_info; 4232ee82402SGolan Ben Ami struct iwl_context_info_gen3 *ctxt_info_gen3; 4242ee82402SGolan Ben Ami }; 4252ee82402SGolan Ben Ami struct iwl_prph_info *prph_info; 4262ee82402SGolan Ben Ami struct iwl_prph_scratch *prph_scratch; 427eda50cdeSSara Sharon dma_addr_t ctxt_info_dma_addr; 4282ee82402SGolan Ben Ami dma_addr_t prph_info_dma_addr; 4292ee82402SGolan Ben Ami dma_addr_t prph_scratch_dma_addr; 4302ee82402SGolan Ben Ami dma_addr_t iml_dma_addr; 431eda50cdeSSara Sharon struct iwl_self_init_dram init_dram; 432e705c121SKalle Valo struct iwl_trans *trans; 433e705c121SKalle Valo 434e705c121SKalle Valo struct net_device napi_dev; 435e705c121SKalle Valo 4366eb5e529SEmmanuel Grumbach struct __percpu iwl_tso_hdr_page *tso_hdr_page; 4376eb5e529SEmmanuel Grumbach 438e705c121SKalle Valo /* INT ICT Table */ 439e705c121SKalle Valo __le32 *ict_tbl; 440e705c121SKalle Valo dma_addr_t ict_tbl_dma; 441e705c121SKalle Valo int ict_index; 442e705c121SKalle Valo bool use_ict; 443326477e4SJohannes Berg bool is_down, opmode_down; 444fa4de7f7SJohannes Berg bool debug_rfkill; 445e705c121SKalle Valo struct isr_statistics isr_stats; 446e705c121SKalle Valo 447e705c121SKalle Valo spinlock_t irq_lock; 448e705c121SKalle Valo struct mutex mutex; 449e705c121SKalle Valo u32 inta_mask; 450e705c121SKalle Valo u32 scd_base_addr; 451e705c121SKalle Valo struct iwl_dma_ptr scd_bc_tbls; 452e705c121SKalle Valo struct iwl_dma_ptr kw; 453e705c121SKalle Valo 454b2a3b1c1SSara Sharon struct iwl_txq *txq_memory; 455e982bc2cSSara Sharon struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 456e982bc2cSSara Sharon unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 457e982bc2cSSara Sharon unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 458e705c121SKalle Valo 459e705c121SKalle Valo /* PCI bus related data */ 460e705c121SKalle Valo struct pci_dev *pci_dev; 461e705c121SKalle Valo void __iomem *hw_base; 462e705c121SKalle Valo 463e705c121SKalle Valo bool ucode_write_complete; 464e705c121SKalle Valo wait_queue_head_t ucode_write_waitq; 465e705c121SKalle Valo wait_queue_head_t wait_command_queue; 4664cbb8e50SLuciano Coelho wait_queue_head_t d0i3_waitq; 467e705c121SKalle Valo 46821cb3222SJohannes Berg u8 page_offs, dev_cmd_offs; 46921cb3222SJohannes Berg 470e705c121SKalle Valo u8 cmd_queue; 471e705c121SKalle Valo u8 cmd_fifo; 472e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 473e705c121SKalle Valo u8 n_no_reclaim_cmds; 474e705c121SKalle Valo u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 4753cd1980bSSara Sharon u8 max_tbs; 4766983ba69SSara Sharon u16 tfd_size; 477e705c121SKalle Valo 4786c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 479e705c121SKalle Valo bool bc_table_dword; 480e705c121SKalle Valo bool scd_set_active; 48141837ca9SEmmanuel Grumbach bool sw_csum_tx; 482a6d24fadSRajat Jain bool pcie_dbg_dumped_once; 483e705c121SKalle Valo u32 rx_page_order; 484e705c121SKalle Valo 485e705c121SKalle Valo /*protect hw register */ 486e705c121SKalle Valo spinlock_t reg_lock; 487e705c121SKalle Valo bool cmd_hold_nic_awake; 488e705c121SKalle Valo bool ref_cmd_in_flight; 489e705c121SKalle Valo 490e705c121SKalle Valo dma_addr_t fw_mon_phys; 491e705c121SKalle Valo struct page *fw_mon_page; 492e705c121SKalle Valo u32 fw_mon_size; 4932e5d4a8fSHaim Dreyfuss 4942e5d4a8fSHaim Dreyfuss struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 4952e5d4a8fSHaim Dreyfuss bool msix_enabled; 496496d83caSHaim Dreyfuss u8 shared_vec_mask; 497496d83caSHaim Dreyfuss u32 alloc_vecs; 498496d83caSHaim Dreyfuss u32 def_irq; 4992e5d4a8fSHaim Dreyfuss u32 fh_init_mask; 5002e5d4a8fSHaim Dreyfuss u32 hw_init_mask; 5012e5d4a8fSHaim Dreyfuss u32 fh_mask; 5022e5d4a8fSHaim Dreyfuss u32 hw_mask; 5037c8d91ebSHaim Dreyfuss cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 50449564a80SLuca Coelho u16 tx_cmd_queue_size; 50549564a80SLuca Coelho bool in_rescan; 50649564a80SLuca Coelho bool scheduled_for_removal; 507e705c121SKalle Valo }; 508e705c121SKalle Valo 50985e5a387SJohannes Berg static inline struct iwl_trans_pcie * 51085e5a387SJohannes Berg IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 51185e5a387SJohannes Berg { 51285e5a387SJohannes Berg return (void *)trans->trans_specific; 51385e5a387SJohannes Berg } 514e705c121SKalle Valo 515e705c121SKalle Valo static inline struct iwl_trans * 516e705c121SKalle Valo iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 517e705c121SKalle Valo { 518e705c121SKalle Valo return container_of((void *)trans_pcie, struct iwl_trans, 519e705c121SKalle Valo trans_specific); 520e705c121SKalle Valo } 521e705c121SKalle Valo 522e705c121SKalle Valo /* 523e705c121SKalle Valo * Convention: trans API functions: iwl_trans_pcie_XXX 524e705c121SKalle Valo * Other functions: iwl_pcie_XXX 525e705c121SKalle Valo */ 526e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 527e705c121SKalle Valo const struct pci_device_id *ent, 528e705c121SKalle Valo const struct iwl_cfg *cfg); 529e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans); 530e705c121SKalle Valo 531e705c121SKalle Valo /***************************************************** 532e705c121SKalle Valo * RX 533e705c121SKalle Valo ******************************************************/ 534e705c121SKalle Valo int iwl_pcie_rx_init(struct iwl_trans *trans); 535eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 5362e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 537e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 5382e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 5392e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 540e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans); 541e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans); 542e705c121SKalle Valo 543e705c121SKalle Valo /***************************************************** 544e705c121SKalle Valo * ICT - interrupt handling 545e705c121SKalle Valo ******************************************************/ 546e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data); 547e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans); 548e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans); 549e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans); 550e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans); 551e705c121SKalle Valo 552e705c121SKalle Valo /***************************************************** 553e705c121SKalle Valo * TX / HCMD 554e705c121SKalle Valo ******************************************************/ 555e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans); 556eda50cdeSSara Sharon int iwl_pcie_gen2_tx_init(struct iwl_trans *trans); 557e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 558e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans); 559e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans); 560dcfbd67bSEmmanuel Grumbach bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 561e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 562e705c121SKalle Valo unsigned int wdg_timeout); 563e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 564e705c121SKalle Valo bool configure_scd); 56542db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 56642db09c1SLiad Kaufman bool shared_mode); 56738398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, 56838398efbSSara Sharon struct iwl_txq *txq); 569e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 570e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id); 571e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 572e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 573e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 574e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb); 575e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 576e705c121SKalle Valo struct sk_buff_head *skbs); 577e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 578e705c121SKalle Valo 579cc2f41f8SJohannes Berg static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd, 5806983ba69SSara Sharon u8 idx) 581e705c121SKalle Valo { 5826983ba69SSara Sharon if (trans->cfg->use_tfh) { 583cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 584cc2f41f8SJohannes Berg struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 5856983ba69SSara Sharon 5866983ba69SSara Sharon return le16_to_cpu(tb->tb_len); 587cc2f41f8SJohannes Berg } else { 588cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 589cc2f41f8SJohannes Berg struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 590e705c121SKalle Valo 591e705c121SKalle Valo return le16_to_cpu(tb->hi_n_len) >> 4; 592e705c121SKalle Valo } 593cc2f41f8SJohannes Berg } 594e705c121SKalle Valo 595e705c121SKalle Valo /***************************************************** 596e705c121SKalle Valo * Error handling 597e705c121SKalle Valo ******************************************************/ 598e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans); 599e705c121SKalle Valo 600e705c121SKalle Valo /***************************************************** 601e705c121SKalle Valo * Helpers 602e705c121SKalle Valo ******************************************************/ 603f16c3ebfSEmmanuel Grumbach static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 604e705c121SKalle Valo { 6052e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 606e705c121SKalle Valo 6072e5d4a8fSHaim Dreyfuss clear_bit(STATUS_INT_ENABLED, &trans->status); 6082e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 609e705c121SKalle Valo /* disable interrupts from uCode/NIC to host */ 610e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 611e705c121SKalle Valo 612e705c121SKalle Valo /* acknowledge/clear/reset any interrupts still pending 613e705c121SKalle Valo * from uCode or flow handler (Rx/Tx DMA) */ 614e705c121SKalle Valo iwl_write32(trans, CSR_INT, 0xffffffff); 615e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 6162e5d4a8fSHaim Dreyfuss } else { 6172e5d4a8fSHaim Dreyfuss /* disable all the interrupt we might use */ 6182e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 6192e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 6202e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 6212e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 6222e5d4a8fSHaim Dreyfuss } 623e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 624e705c121SKalle Valo } 625e705c121SKalle Valo 6262ee82402SGolan Ben Ami #define IWL_NUM_OF_COMPLETION_RINGS 31 6272ee82402SGolan Ben Ami #define IWL_NUM_OF_TRANSFER_RINGS 527 6282ee82402SGolan Ben Ami 6292ee82402SGolan Ben Ami static inline int iwl_pcie_get_num_sections(const struct fw_img *fw, 6302ee82402SGolan Ben Ami int start) 6312ee82402SGolan Ben Ami { 6322ee82402SGolan Ben Ami int i = 0; 6332ee82402SGolan Ben Ami 6342ee82402SGolan Ben Ami while (start < fw->num_sec && 6352ee82402SGolan Ben Ami fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && 6362ee82402SGolan Ben Ami fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { 6372ee82402SGolan Ben Ami start++; 6382ee82402SGolan Ben Ami i++; 6392ee82402SGolan Ben Ami } 6402ee82402SGolan Ben Ami 6412ee82402SGolan Ben Ami return i; 6422ee82402SGolan Ben Ami } 6432ee82402SGolan Ben Ami 6442ee82402SGolan Ben Ami static inline int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans, 6452ee82402SGolan Ben Ami const struct fw_desc *sec, 6462ee82402SGolan Ben Ami struct iwl_dram_data *dram) 6472ee82402SGolan Ben Ami { 6482ee82402SGolan Ben Ami dram->block = dma_alloc_coherent(trans->dev, sec->len, 6492ee82402SGolan Ben Ami &dram->physical, 6502ee82402SGolan Ben Ami GFP_KERNEL); 6512ee82402SGolan Ben Ami if (!dram->block) 6522ee82402SGolan Ben Ami return -ENOMEM; 6532ee82402SGolan Ben Ami 6542ee82402SGolan Ben Ami dram->size = sec->len; 6552ee82402SGolan Ben Ami memcpy(dram->block, sec->data, sec->len); 6562ee82402SGolan Ben Ami 6572ee82402SGolan Ben Ami return 0; 6582ee82402SGolan Ben Ami } 6592ee82402SGolan Ben Ami 6602ee82402SGolan Ben Ami static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans) 6612ee82402SGolan Ben Ami { 6622ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 6632ee82402SGolan Ben Ami struct iwl_self_init_dram *dram = &trans_pcie->init_dram; 6642ee82402SGolan Ben Ami int i; 6652ee82402SGolan Ben Ami 6662ee82402SGolan Ben Ami if (!dram->fw) { 6672ee82402SGolan Ben Ami WARN_ON(dram->fw_cnt); 6682ee82402SGolan Ben Ami return; 6692ee82402SGolan Ben Ami } 6702ee82402SGolan Ben Ami 6712ee82402SGolan Ben Ami for (i = 0; i < dram->fw_cnt; i++) 6722ee82402SGolan Ben Ami dma_free_coherent(trans->dev, dram->fw[i].size, 6732ee82402SGolan Ben Ami dram->fw[i].block, dram->fw[i].physical); 6742ee82402SGolan Ben Ami 6752ee82402SGolan Ben Ami kfree(dram->fw); 6762ee82402SGolan Ben Ami dram->fw_cnt = 0; 6772ee82402SGolan Ben Ami dram->fw = NULL; 6782ee82402SGolan Ben Ami } 6792ee82402SGolan Ben Ami 680f16c3ebfSEmmanuel Grumbach static inline void iwl_disable_interrupts(struct iwl_trans *trans) 681f16c3ebfSEmmanuel Grumbach { 682f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 683f16c3ebfSEmmanuel Grumbach 684f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 685f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 686f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 687f16c3ebfSEmmanuel Grumbach } 688f16c3ebfSEmmanuel Grumbach 689f16c3ebfSEmmanuel Grumbach static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 690e705c121SKalle Valo { 691e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 692e705c121SKalle Valo 693e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 694e705c121SKalle Valo set_bit(STATUS_INT_ENABLED, &trans->status); 6952e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 696e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 697e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 6982e5d4a8fSHaim Dreyfuss } else { 6992e5d4a8fSHaim Dreyfuss /* 7002e5d4a8fSHaim Dreyfuss * fh/hw_mask keeps all the unmasked causes. 7012e5d4a8fSHaim Dreyfuss * Unlike msi, in msix cause is enabled when it is unset. 7022e5d4a8fSHaim Dreyfuss */ 7032e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 7042e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 7052e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 7062e5d4a8fSHaim Dreyfuss ~trans_pcie->fh_mask); 7072e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 7082e5d4a8fSHaim Dreyfuss ~trans_pcie->hw_mask); 7092e5d4a8fSHaim Dreyfuss } 7102e5d4a8fSHaim Dreyfuss } 7112e5d4a8fSHaim Dreyfuss 712f16c3ebfSEmmanuel Grumbach static inline void iwl_enable_interrupts(struct iwl_trans *trans) 713f16c3ebfSEmmanuel Grumbach { 714f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 715f16c3ebfSEmmanuel Grumbach 716f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 717f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 718f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 719f16c3ebfSEmmanuel Grumbach } 7202e5d4a8fSHaim Dreyfuss static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 7212e5d4a8fSHaim Dreyfuss { 7222e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 7232e5d4a8fSHaim Dreyfuss 7242e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 7252e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = msk; 7262e5d4a8fSHaim Dreyfuss } 7272e5d4a8fSHaim Dreyfuss 7282e5d4a8fSHaim Dreyfuss static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 7292e5d4a8fSHaim Dreyfuss { 7302e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 7312e5d4a8fSHaim Dreyfuss 7322e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 7332e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = msk; 734e705c121SKalle Valo } 735e705c121SKalle Valo 736a6bd005fSEmmanuel Grumbach static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 737a6bd005fSEmmanuel Grumbach { 738a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 739a6bd005fSEmmanuel Grumbach 740a6bd005fSEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 7412e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 742a6bd005fSEmmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 743a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 7442e5d4a8fSHaim Dreyfuss } else { 7452e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 7462e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 7472e5d4a8fSHaim Dreyfuss iwl_enable_fh_int_msk_msix(trans, 7482e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 7492e5d4a8fSHaim Dreyfuss } 750a6bd005fSEmmanuel Grumbach } 751a6bd005fSEmmanuel Grumbach 752f5955a6cSGolan Ben Ami static inline u8 iwl_pcie_get_cmd_index(const struct iwl_txq *q, u32 index) 7534ecab561SEmmanuel Grumbach { 7544ecab561SEmmanuel Grumbach return index & (q->n_window - 1); 7554ecab561SEmmanuel Grumbach } 7564ecab561SEmmanuel Grumbach 757943309d4SEmmanuel Grumbach static inline void *iwl_pcie_get_tfd(struct iwl_trans *trans, 758ab6c6445SSara Sharon struct iwl_txq *txq, int idx) 759ab6c6445SSara Sharon { 760943309d4SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 761943309d4SEmmanuel Grumbach 762943309d4SEmmanuel Grumbach if (trans->cfg->use_tfh) 763943309d4SEmmanuel Grumbach idx = iwl_pcie_get_cmd_index(txq, idx); 764943309d4SEmmanuel Grumbach 765943309d4SEmmanuel Grumbach return txq->tfds + trans_pcie->tfd_size * idx; 766ab6c6445SSara Sharon } 767ab6c6445SSara Sharon 768e705c121SKalle Valo static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 769e705c121SKalle Valo { 770e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 771e705c121SKalle Valo 772e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 7732e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 774e705c121SKalle Valo trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 775e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 7762e5d4a8fSHaim Dreyfuss } else { 7772e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 7782e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 7792e5d4a8fSHaim Dreyfuss iwl_enable_hw_int_msk_msix(trans, 7802e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_RF_KILL); 7812e5d4a8fSHaim Dreyfuss } 782ae5bb2a6SJohannes Berg 783ae5bb2a6SJohannes Berg if (trans->cfg->device_family == IWL_DEVICE_FAMILY_9000) { 784ae5bb2a6SJohannes Berg /* 785ae5bb2a6SJohannes Berg * On 9000-series devices this bit isn't enabled by default, so 786ae5bb2a6SJohannes Berg * when we power down the device we need set the bit to allow it 787ae5bb2a6SJohannes Berg * to wake up the PCI-E bus for RF-kill interrupts. 788ae5bb2a6SJohannes Berg */ 789ae5bb2a6SJohannes Berg iwl_set_bit(trans, CSR_GP_CNTRL, 790ae5bb2a6SJohannes Berg CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 791ae5bb2a6SJohannes Berg } 792e705c121SKalle Valo } 793e705c121SKalle Valo 794fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans); 795fa4de7f7SJohannes Berg 796e705c121SKalle Valo static inline void iwl_wake_queue(struct iwl_trans *trans, 797e705c121SKalle Valo struct iwl_txq *txq) 798e705c121SKalle Valo { 799e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 800e705c121SKalle Valo 801bb98ecd4SSara Sharon if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) { 802bb98ecd4SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id); 803bb98ecd4SSara Sharon iwl_op_mode_queue_not_full(trans->op_mode, txq->id); 804e705c121SKalle Valo } 805e705c121SKalle Valo } 806e705c121SKalle Valo 807e705c121SKalle Valo static inline void iwl_stop_queue(struct iwl_trans *trans, 808e705c121SKalle Valo struct iwl_txq *txq) 809e705c121SKalle Valo { 810e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 811e705c121SKalle Valo 812bb98ecd4SSara Sharon if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) { 813bb98ecd4SSara Sharon iwl_op_mode_queue_full(trans->op_mode, txq->id); 814bb98ecd4SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id); 815e705c121SKalle Valo } else 816e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 817bb98ecd4SSara Sharon txq->id); 818e705c121SKalle Valo } 819e705c121SKalle Valo 820bb98ecd4SSara Sharon static inline bool iwl_queue_used(const struct iwl_txq *q, int i) 821e705c121SKalle Valo { 822f5955a6cSGolan Ben Ami int index = iwl_pcie_get_cmd_index(q, i); 823f5955a6cSGolan Ben Ami int r = iwl_pcie_get_cmd_index(q, q->read_ptr); 824f5955a6cSGolan Ben Ami int w = iwl_pcie_get_cmd_index(q, q->write_ptr); 825f5955a6cSGolan Ben Ami 826f5955a6cSGolan Ben Ami return w >= r ? 827f5955a6cSGolan Ben Ami (index >= r && index < w) : 828f5955a6cSGolan Ben Ami !(index < r && index >= w); 829e705c121SKalle Valo } 830e705c121SKalle Valo 831e705c121SKalle Valo static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 832e705c121SKalle Valo { 833fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 834fa4de7f7SJohannes Berg 835fa4de7f7SJohannes Berg lockdep_assert_held(&trans_pcie->mutex); 836fa4de7f7SJohannes Berg 837fa4de7f7SJohannes Berg if (trans_pcie->debug_rfkill) 838fa4de7f7SJohannes Berg return true; 83923aeea94SJohannes Berg 840e705c121SKalle Valo return !(iwl_read32(trans, CSR_GP_CNTRL) & 841e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 842e705c121SKalle Valo } 843e705c121SKalle Valo 844e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 845e705c121SKalle Valo u32 reg, u32 mask, u32 value) 846e705c121SKalle Valo { 847e705c121SKalle Valo u32 v; 848e705c121SKalle Valo 849e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 850e705c121SKalle Valo WARN_ON_ONCE(value & ~mask); 851e705c121SKalle Valo #endif 852e705c121SKalle Valo 853e705c121SKalle Valo v = iwl_read32(trans, reg); 854e705c121SKalle Valo v &= ~mask; 855e705c121SKalle Valo v |= value; 856e705c121SKalle Valo iwl_write32(trans, reg, v); 857e705c121SKalle Valo } 858e705c121SKalle Valo 859e705c121SKalle Valo static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 860e705c121SKalle Valo u32 reg, u32 mask) 861e705c121SKalle Valo { 862e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 863e705c121SKalle Valo } 864e705c121SKalle Valo 865e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 866e705c121SKalle Valo u32 reg, u32 mask) 867e705c121SKalle Valo { 868e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 869e705c121SKalle Valo } 870e705c121SKalle Valo 871e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 872e705c121SKalle Valo 873f8a1edb7SJohannes Berg #ifdef CONFIG_IWLWIFI_DEBUGFS 874f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 875f8a1edb7SJohannes Berg #else 876f8a1edb7SJohannes Berg static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 877f8a1edb7SJohannes Berg { 878f8a1edb7SJohannes Berg return 0; 879f8a1edb7SJohannes Berg } 880f8a1edb7SJohannes Berg #endif 881f8a1edb7SJohannes Berg 8824cbb8e50SLuciano Coelho int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans); 8834cbb8e50SLuciano Coelho int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans); 8844cbb8e50SLuciano Coelho 8851316d595SSara Sharon void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable); 8861316d595SSara Sharon 88710a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data); 88810a54d81SLuca Coelho 889eda50cdeSSara Sharon /* common functions that are used by gen2 transport */ 890eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans); 891eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 892eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 8939ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans); 894326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 895326477e4SJohannes Berg bool was_in_rfkill); 8966b35ff91SSara Sharon void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq); 897ab6c6445SSara Sharon int iwl_queue_space(const struct iwl_txq *q); 898e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans); 89977c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 90013a3a390SSara Sharon int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 901b8e8d7ceSSara Sharon int slots_num, bool cmd_queue); 90213a3a390SSara Sharon int iwl_pcie_txq_alloc(struct iwl_trans *trans, 903b8e8d7ceSSara Sharon struct iwl_txq *txq, int slots_num, bool cmd_queue); 90413a3a390SSara Sharon int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 90513a3a390SSara Sharon struct iwl_dma_ptr *ptr, size_t size); 90613a3a390SSara Sharon void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr); 907c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans); 9089bb3d5a0SEmmanuel Grumbach void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 9099bb3d5a0SEmmanuel Grumbach struct sk_buff *skb); 9106ffe5de3SSara Sharon #ifdef CONFIG_INET 9116ffe5de3SSara Sharon struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len); 9126ffe5de3SSara Sharon #endif 913eda50cdeSSara Sharon 9149f358c17SGolan Ben Ami /* common functions that are used by gen3 transport */ 9159f358c17SGolan Ben Ami void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power); 9169f358c17SGolan Ben Ami 917eda50cdeSSara Sharon /* transport gen 2 exported functions */ 918eda50cdeSSara Sharon int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 919eda50cdeSSara Sharon const struct fw_img *fw, bool run_in_rfkill); 920eda50cdeSSara Sharon void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr); 9216b35ff91SSara Sharon int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans, 9226b35ff91SSara Sharon struct iwl_tx_queue_cfg_cmd *cmd, 9235369774cSSara Sharon int cmd_id, int size, 9246b35ff91SSara Sharon unsigned int timeout); 9256b35ff91SSara Sharon void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue); 926ab6c6445SSara Sharon int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb, 927ab6c6445SSara Sharon struct iwl_device_cmd *dev_cmd, int txq_id); 928ca60da2eSSara Sharon int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 929ca60da2eSSara Sharon struct iwl_host_cmd *cmd); 93077c09bc8SSara Sharon void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, 93177c09bc8SSara Sharon bool low_power); 93277c09bc8SSara Sharon void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power); 93313a3a390SSara Sharon void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id); 93413a3a390SSara Sharon void iwl_pcie_gen2_tx_free(struct iwl_trans *trans); 93513a3a390SSara Sharon void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans); 936e705c121SKalle Valo #endif /* __iwl_trans_int_pcie_h__ */ 937