1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 4e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 54cbb8e50SLuciano Coelho * Copyright(c) 2016 Intel Deutschland GmbH 6e705c121SKalle Valo * 7e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 8e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 9e705c121SKalle Valo * 10e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 11e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 12e705c121SKalle Valo * published by the Free Software Foundation. 13e705c121SKalle Valo * 14e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 15e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17e705c121SKalle Valo * more details. 18e705c121SKalle Valo * 19e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 20e705c121SKalle Valo * this program; if not, write to the Free Software Foundation, Inc., 21e705c121SKalle Valo * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 22e705c121SKalle Valo * 23e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 24e705c121SKalle Valo * file called LICENSE. 25e705c121SKalle Valo * 26e705c121SKalle Valo * Contact Information: 27cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 28e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29e705c121SKalle Valo * 30e705c121SKalle Valo *****************************************************************************/ 31e705c121SKalle Valo #ifndef __iwl_trans_int_pcie_h__ 32e705c121SKalle Valo #define __iwl_trans_int_pcie_h__ 33e705c121SKalle Valo 34e705c121SKalle Valo #include <linux/spinlock.h> 35e705c121SKalle Valo #include <linux/interrupt.h> 36e705c121SKalle Valo #include <linux/skbuff.h> 37e705c121SKalle Valo #include <linux/wait.h> 38e705c121SKalle Valo #include <linux/pci.h> 39e705c121SKalle Valo #include <linux/timer.h> 40e705c121SKalle Valo 41e705c121SKalle Valo #include "iwl-fh.h" 42e705c121SKalle Valo #include "iwl-csr.h" 43e705c121SKalle Valo #include "iwl-trans.h" 44e705c121SKalle Valo #include "iwl-debug.h" 45e705c121SKalle Valo #include "iwl-io.h" 46e705c121SKalle Valo #include "iwl-op-mode.h" 47e705c121SKalle Valo 48e705c121SKalle Valo /* We need 2 entries for the TX command and header, and another one might 49e705c121SKalle Valo * be needed for potential data in the SKB's head. The remaining ones can 50e705c121SKalle Valo * be used for frags. 51e705c121SKalle Valo */ 523cd1980bSSara Sharon #define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3) 53e705c121SKalle Valo 54e705c121SKalle Valo /* 55e705c121SKalle Valo * RX related structures and functions 56e705c121SKalle Valo */ 57e705c121SKalle Valo #define RX_NUM_QUEUES 1 58e705c121SKalle Valo #define RX_POST_REQ_ALLOC 2 59e705c121SKalle Valo #define RX_CLAIM_REQ_ALLOC 8 6078485054SSara Sharon #define RX_PENDING_WATERMARK 16 61e705c121SKalle Valo 62e705c121SKalle Valo struct iwl_host_cmd; 63e705c121SKalle Valo 64e705c121SKalle Valo /*This file includes the declaration that are internal to the 65e705c121SKalle Valo * trans_pcie layer */ 66e705c121SKalle Valo 6796a6497bSSara Sharon /** 6896a6497bSSara Sharon * struct iwl_rx_mem_buffer 6996a6497bSSara Sharon * @page_dma: bus address of rxb page 7096a6497bSSara Sharon * @page: driver's pointer to the rxb page 71b1753c62SSara Sharon * @invalid: rxb is in driver ownership - not owned by HW 7296a6497bSSara Sharon * @vid: index of this rxb in the global table 7396a6497bSSara Sharon */ 74e705c121SKalle Valo struct iwl_rx_mem_buffer { 75e705c121SKalle Valo dma_addr_t page_dma; 76e705c121SKalle Valo struct page *page; 7796a6497bSSara Sharon u16 vid; 78b1753c62SSara Sharon bool invalid; 79e705c121SKalle Valo struct list_head list; 80e705c121SKalle Valo }; 81e705c121SKalle Valo 82e705c121SKalle Valo /** 83e705c121SKalle Valo * struct isr_statistics - interrupt statistics 84e705c121SKalle Valo * 85e705c121SKalle Valo */ 86e705c121SKalle Valo struct isr_statistics { 87e705c121SKalle Valo u32 hw; 88e705c121SKalle Valo u32 sw; 89e705c121SKalle Valo u32 err_code; 90e705c121SKalle Valo u32 sch; 91e705c121SKalle Valo u32 alive; 92e705c121SKalle Valo u32 rfkill; 93e705c121SKalle Valo u32 ctkill; 94e705c121SKalle Valo u32 wakeup; 95e705c121SKalle Valo u32 rx; 96e705c121SKalle Valo u32 tx; 97e705c121SKalle Valo u32 unhandled; 98e705c121SKalle Valo }; 99e705c121SKalle Valo 100e705c121SKalle Valo /** 101e705c121SKalle Valo * struct iwl_rxq - Rx queue 10296a6497bSSara Sharon * @id: queue index 10396a6497bSSara Sharon * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 10496a6497bSSara Sharon * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 105e705c121SKalle Valo * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 10696a6497bSSara Sharon * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd) 10796a6497bSSara Sharon * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd) 108e705c121SKalle Valo * @read: Shared index to newest available Rx buffer 109e705c121SKalle Valo * @write: Shared index to oldest written Rx packet 110e705c121SKalle Valo * @free_count: Number of pre-allocated buffers in rx_free 111e705c121SKalle Valo * @used_count: Number of RBDs handled to allocator to use for allocation 112e705c121SKalle Valo * @write_actual: 113e705c121SKalle Valo * @rx_free: list of RBDs with allocated RB ready for use 114e705c121SKalle Valo * @rx_used: list of RBDs with no RB attached 115e705c121SKalle Valo * @need_update: flag to indicate we need to update read/write index 116e705c121SKalle Valo * @rb_stts: driver's pointer to receive buffer status 117e705c121SKalle Valo * @rb_stts_dma: bus address of receive buffer status 118e705c121SKalle Valo * @lock: 11996a6497bSSara Sharon * @queue: actual rx queue. Not used for multi-rx queue. 120e705c121SKalle Valo * 121e705c121SKalle Valo * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 122e705c121SKalle Valo */ 123e705c121SKalle Valo struct iwl_rxq { 12496a6497bSSara Sharon int id; 12596a6497bSSara Sharon void *bd; 126e705c121SKalle Valo dma_addr_t bd_dma; 12796a6497bSSara Sharon __le32 *used_bd; 12896a6497bSSara Sharon dma_addr_t used_bd_dma; 129e705c121SKalle Valo u32 read; 130e705c121SKalle Valo u32 write; 131e705c121SKalle Valo u32 free_count; 132e705c121SKalle Valo u32 used_count; 133e705c121SKalle Valo u32 write_actual; 13496a6497bSSara Sharon u32 queue_size; 135e705c121SKalle Valo struct list_head rx_free; 136e705c121SKalle Valo struct list_head rx_used; 137e705c121SKalle Valo bool need_update; 138e705c121SKalle Valo struct iwl_rb_status *rb_stts; 139e705c121SKalle Valo dma_addr_t rb_stts_dma; 140e705c121SKalle Valo spinlock_t lock; 141bce97731SSara Sharon struct napi_struct napi; 142e705c121SKalle Valo struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 143e705c121SKalle Valo }; 144e705c121SKalle Valo 145e705c121SKalle Valo /** 146e705c121SKalle Valo * struct iwl_rb_allocator - Rx allocator 147e705c121SKalle Valo * @req_pending: number of requests the allcator had not processed yet 148e705c121SKalle Valo * @req_ready: number of requests honored and ready for claiming 149e705c121SKalle Valo * @rbd_allocated: RBDs with pages allocated and ready to be handled to 150e705c121SKalle Valo * the queue. This is a list of &struct iwl_rx_mem_buffer 151e705c121SKalle Valo * @rbd_empty: RBDs with no page attached for allocator use. This is a list 152e705c121SKalle Valo * of &struct iwl_rx_mem_buffer 153e705c121SKalle Valo * @lock: protects the rbd_allocated and rbd_empty lists 154e705c121SKalle Valo * @alloc_wq: work queue for background calls 155e705c121SKalle Valo * @rx_alloc: work struct for background calls 156e705c121SKalle Valo */ 157e705c121SKalle Valo struct iwl_rb_allocator { 158e705c121SKalle Valo atomic_t req_pending; 159e705c121SKalle Valo atomic_t req_ready; 160e705c121SKalle Valo struct list_head rbd_allocated; 161e705c121SKalle Valo struct list_head rbd_empty; 162e705c121SKalle Valo spinlock_t lock; 163e705c121SKalle Valo struct workqueue_struct *alloc_wq; 164e705c121SKalle Valo struct work_struct rx_alloc; 165e705c121SKalle Valo }; 166e705c121SKalle Valo 167e705c121SKalle Valo struct iwl_dma_ptr { 168e705c121SKalle Valo dma_addr_t dma; 169e705c121SKalle Valo void *addr; 170e705c121SKalle Valo size_t size; 171e705c121SKalle Valo }; 172e705c121SKalle Valo 173e705c121SKalle Valo /** 174e705c121SKalle Valo * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 175e705c121SKalle Valo * @index -- current index 176e705c121SKalle Valo */ 177e705c121SKalle Valo static inline int iwl_queue_inc_wrap(int index) 178e705c121SKalle Valo { 179e705c121SKalle Valo return ++index & (TFD_QUEUE_SIZE_MAX - 1); 180e705c121SKalle Valo } 181e705c121SKalle Valo 182e705c121SKalle Valo /** 183e705c121SKalle Valo * iwl_queue_dec_wrap - decrement queue index, wrap back to end 184e705c121SKalle Valo * @index -- current index 185e705c121SKalle Valo */ 186e705c121SKalle Valo static inline int iwl_queue_dec_wrap(int index) 187e705c121SKalle Valo { 188e705c121SKalle Valo return --index & (TFD_QUEUE_SIZE_MAX - 1); 189e705c121SKalle Valo } 190e705c121SKalle Valo 191e705c121SKalle Valo struct iwl_cmd_meta { 192e705c121SKalle Valo /* only for SYNC commands, iff the reply skb is wanted */ 193e705c121SKalle Valo struct iwl_host_cmd *source; 194e705c121SKalle Valo u32 flags; 1953cd1980bSSara Sharon u32 tbs; 196e705c121SKalle Valo }; 197e705c121SKalle Valo 198e705c121SKalle Valo 199e705c121SKalle Valo #define TFD_TX_CMD_SLOTS 256 200e705c121SKalle Valo #define TFD_CMD_SLOTS 32 201e705c121SKalle Valo 202e705c121SKalle Valo /* 2038de437c7SSara Sharon * The FH will write back to the first TB only, so we need to copy some data 2048de437c7SSara Sharon * into the buffer regardless of whether it should be mapped or not. 2058de437c7SSara Sharon * This indicates how big the first TB must be to include the scratch buffer 2068de437c7SSara Sharon * and the assigned PN. 2078de437c7SSara Sharon * Since PN location is 16 bytes at offset 24, it's 40 now. 2088de437c7SSara Sharon * If we make it bigger then allocations will be bigger and copy slower, so 2098de437c7SSara Sharon * that's probably not useful. 210e705c121SKalle Valo */ 2118de437c7SSara Sharon #define IWL_FIRST_TB_SIZE 40 2128de437c7SSara Sharon #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 213e705c121SKalle Valo 214e705c121SKalle Valo struct iwl_pcie_txq_entry { 215e705c121SKalle Valo struct iwl_device_cmd *cmd; 216e705c121SKalle Valo struct sk_buff *skb; 217e705c121SKalle Valo /* buffer to free after command completes */ 218e705c121SKalle Valo const void *free_buf; 219e705c121SKalle Valo struct iwl_cmd_meta meta; 220e705c121SKalle Valo }; 221e705c121SKalle Valo 2228de437c7SSara Sharon struct iwl_pcie_first_tb_buf { 2238de437c7SSara Sharon u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 224e705c121SKalle Valo }; 225e705c121SKalle Valo 226e705c121SKalle Valo /** 227e705c121SKalle Valo * struct iwl_txq - Tx Queue for DMA 228e705c121SKalle Valo * @q: generic Rx/Tx queue descriptor 229e705c121SKalle Valo * @tfds: transmit frame descriptors (DMA memory) 2308de437c7SSara Sharon * @first_tb_bufs: start of command headers, including scratch buffers, for 231e705c121SKalle Valo * the writeback -- this is DMA memory and an array holding one buffer 232e705c121SKalle Valo * for each command on the queue 2338de437c7SSara Sharon * @first_tb_dma: DMA address for the first_tb_bufs start 234e705c121SKalle Valo * @entries: transmit entries (driver state) 235e705c121SKalle Valo * @lock: queue lock 236e705c121SKalle Valo * @stuck_timer: timer that fires if queue gets stuck 237e705c121SKalle Valo * @trans_pcie: pointer back to transport (for timer) 238e705c121SKalle Valo * @need_update: indicates need to update read/write index 239e705c121SKalle Valo * @active: stores if queue is active 240e705c121SKalle Valo * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 241e705c121SKalle Valo * @wd_timeout: queue watchdog timeout (jiffies) - per queue 242e705c121SKalle Valo * @frozen: tx stuck queue timer is frozen 243e705c121SKalle Valo * @frozen_expiry_remainder: remember how long until the timer fires 244bb98ecd4SSara Sharon * @write_ptr: 1-st empty entry (index) host_w 245bb98ecd4SSara Sharon * @read_ptr: last used entry (index) host_r 246bb98ecd4SSara Sharon * @dma_addr: physical addr for BD's 247bb98ecd4SSara Sharon * @n_window: safe queue window 248bb98ecd4SSara Sharon * @id: queue id 249bb98ecd4SSara Sharon * @low_mark: low watermark, resume queue if free space more than this 250bb98ecd4SSara Sharon * @high_mark: high watermark, stop queue if free space less than this 251e705c121SKalle Valo * 252e705c121SKalle Valo * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 253e705c121SKalle Valo * descriptors) and required locking structures. 254bb98ecd4SSara Sharon * 255bb98ecd4SSara Sharon * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 256bb98ecd4SSara Sharon * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 257bb98ecd4SSara Sharon * there might be HW changes in the future). For the normal TX 258bb98ecd4SSara Sharon * queues, n_window, which is the size of the software queue data 259bb98ecd4SSara Sharon * is also 256; however, for the command queue, n_window is only 260bb98ecd4SSara Sharon * 32 since we don't need so many commands pending. Since the HW 261bb98ecd4SSara Sharon * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 262bb98ecd4SSara Sharon * This means that we end up with the following: 263bb98ecd4SSara Sharon * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 264bb98ecd4SSara Sharon * SW entries: | 0 | ... | 31 | 265bb98ecd4SSara Sharon * where N is a number between 0 and 7. This means that the SW 266bb98ecd4SSara Sharon * data is a window overlayed over the HW queue. 267e705c121SKalle Valo */ 268e705c121SKalle Valo struct iwl_txq { 2696983ba69SSara Sharon void *tfds; 2708de437c7SSara Sharon struct iwl_pcie_first_tb_buf *first_tb_bufs; 2718de437c7SSara Sharon dma_addr_t first_tb_dma; 272e705c121SKalle Valo struct iwl_pcie_txq_entry *entries; 273e705c121SKalle Valo spinlock_t lock; 274e705c121SKalle Valo unsigned long frozen_expiry_remainder; 275e705c121SKalle Valo struct timer_list stuck_timer; 276e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 277e705c121SKalle Valo bool need_update; 278e705c121SKalle Valo bool frozen; 279e705c121SKalle Valo u8 active; 280e705c121SKalle Valo bool ampdu; 2810cd58eaaSEmmanuel Grumbach bool block; 282e705c121SKalle Valo unsigned long wd_timeout; 2833955525dSEmmanuel Grumbach struct sk_buff_head overflow_q; 284bb98ecd4SSara Sharon 285bb98ecd4SSara Sharon int write_ptr; 286bb98ecd4SSara Sharon int read_ptr; 287bb98ecd4SSara Sharon dma_addr_t dma_addr; 288bb98ecd4SSara Sharon int n_window; 289bb98ecd4SSara Sharon u32 id; 290bb98ecd4SSara Sharon int low_mark; 291bb98ecd4SSara Sharon int high_mark; 292e705c121SKalle Valo }; 293e705c121SKalle Valo 294e705c121SKalle Valo static inline dma_addr_t 2958de437c7SSara Sharon iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx) 296e705c121SKalle Valo { 2978de437c7SSara Sharon return txq->first_tb_dma + 2988de437c7SSara Sharon sizeof(struct iwl_pcie_first_tb_buf) * idx; 299e705c121SKalle Valo } 300e705c121SKalle Valo 3016eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page { 3026eb5e529SEmmanuel Grumbach struct page *page; 3036eb5e529SEmmanuel Grumbach u8 *pos; 3046eb5e529SEmmanuel Grumbach }; 3056eb5e529SEmmanuel Grumbach 306e705c121SKalle Valo /** 307e705c121SKalle Valo * struct iwl_trans_pcie - PCIe transport specific data 308e705c121SKalle Valo * @rxq: all the RX queue data 30978485054SSara Sharon * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 31096a6497bSSara Sharon * @global_table: table mapping received VID from hw to rxb 311e705c121SKalle Valo * @rba: allocator for RX replenishing 312e705c121SKalle Valo * @trans: pointer to the generic transport area 313e705c121SKalle Valo * @scd_base_addr: scheduler sram base address in SRAM 314e705c121SKalle Valo * @scd_bc_tbls: pointer to the byte count table of the scheduler 315e705c121SKalle Valo * @kw: keep warm address 316e705c121SKalle Valo * @pci_dev: basic pci-network driver stuff 317e705c121SKalle Valo * @hw_base: pci hardware address support 318e705c121SKalle Valo * @ucode_write_complete: indicates that the ucode has been copied. 319e705c121SKalle Valo * @ucode_write_waitq: wait queue for uCode load 320e705c121SKalle Valo * @cmd_queue - command queue number 3216c4fbcbcSEmmanuel Grumbach * @rx_buf_size: Rx buffer size 322e705c121SKalle Valo * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 323e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 324e705c121SKalle Valo * @wide_cmd_header: true when ucode supports wide command header format 32541837ca9SEmmanuel Grumbach * @sw_csum_tx: if true, then the transport will compute the csum of the TXed 32641837ca9SEmmanuel Grumbach * frame. 327e705c121SKalle Valo * @rx_page_order: page order for receive buffer size 328e705c121SKalle Valo * @reg_lock: protect hw register access 329e705c121SKalle Valo * @mutex: to protect stop_device / start_fw / start_hw 330e705c121SKalle Valo * @cmd_in_flight: true when we have a host command in flight 331e705c121SKalle Valo * @fw_mon_phys: physical address of the buffer for the firmware monitor 332e705c121SKalle Valo * @fw_mon_page: points to the first page of the buffer for the firmware monitor 333e705c121SKalle Valo * @fw_mon_size: size of the buffer for the firmware monitor 3342e5d4a8fSHaim Dreyfuss * @msix_entries: array of MSI-X entries 3352e5d4a8fSHaim Dreyfuss * @msix_enabled: true if managed to enable MSI-X 3362e5d4a8fSHaim Dreyfuss * @allocated_vector: the number of interrupt vector allocated by the OS 3372e5d4a8fSHaim Dreyfuss * @default_irq_num: default irq for non rx interrupt 3382e5d4a8fSHaim Dreyfuss * @fh_init_mask: initial unmasked fh causes 3392e5d4a8fSHaim Dreyfuss * @hw_init_mask: initial unmasked hw causes 3402e5d4a8fSHaim Dreyfuss * @fh_mask: current unmasked fh causes 3412e5d4a8fSHaim Dreyfuss * @hw_mask: current unmasked hw causes 342e705c121SKalle Valo */ 343e705c121SKalle Valo struct iwl_trans_pcie { 34478485054SSara Sharon struct iwl_rxq *rxq; 3457b542436SSara Sharon struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE]; 34643146925SSara Sharon struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE]; 347e705c121SKalle Valo struct iwl_rb_allocator rba; 348e705c121SKalle Valo struct iwl_trans *trans; 349e705c121SKalle Valo 350e705c121SKalle Valo struct net_device napi_dev; 351e705c121SKalle Valo 3526eb5e529SEmmanuel Grumbach struct __percpu iwl_tso_hdr_page *tso_hdr_page; 3536eb5e529SEmmanuel Grumbach 354e705c121SKalle Valo /* INT ICT Table */ 355e705c121SKalle Valo __le32 *ict_tbl; 356e705c121SKalle Valo dma_addr_t ict_tbl_dma; 357e705c121SKalle Valo int ict_index; 358e705c121SKalle Valo bool use_ict; 359e705c121SKalle Valo bool is_down; 360e705c121SKalle Valo struct isr_statistics isr_stats; 361e705c121SKalle Valo 362e705c121SKalle Valo spinlock_t irq_lock; 363e705c121SKalle Valo struct mutex mutex; 364e705c121SKalle Valo u32 inta_mask; 365e705c121SKalle Valo u32 scd_base_addr; 366e705c121SKalle Valo struct iwl_dma_ptr scd_bc_tbls; 367e705c121SKalle Valo struct iwl_dma_ptr kw; 368e705c121SKalle Valo 369e705c121SKalle Valo struct iwl_txq *txq; 370e705c121SKalle Valo unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 371e705c121SKalle Valo unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 372e705c121SKalle Valo 373e705c121SKalle Valo /* PCI bus related data */ 374e705c121SKalle Valo struct pci_dev *pci_dev; 375e705c121SKalle Valo void __iomem *hw_base; 376e705c121SKalle Valo 377e705c121SKalle Valo bool ucode_write_complete; 378e705c121SKalle Valo wait_queue_head_t ucode_write_waitq; 379e705c121SKalle Valo wait_queue_head_t wait_command_queue; 3804cbb8e50SLuciano Coelho wait_queue_head_t d0i3_waitq; 381e705c121SKalle Valo 38221cb3222SJohannes Berg u8 page_offs, dev_cmd_offs; 38321cb3222SJohannes Berg 384e705c121SKalle Valo u8 cmd_queue; 385e705c121SKalle Valo u8 cmd_fifo; 386e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 387e705c121SKalle Valo u8 n_no_reclaim_cmds; 388e705c121SKalle Valo u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 3893cd1980bSSara Sharon u8 max_tbs; 3906983ba69SSara Sharon u16 tfd_size; 391e705c121SKalle Valo 3926c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 393e705c121SKalle Valo bool bc_table_dword; 394e705c121SKalle Valo bool scd_set_active; 395e705c121SKalle Valo bool wide_cmd_header; 39641837ca9SEmmanuel Grumbach bool sw_csum_tx; 397e705c121SKalle Valo u32 rx_page_order; 398e705c121SKalle Valo 399e705c121SKalle Valo /*protect hw register */ 400e705c121SKalle Valo spinlock_t reg_lock; 401e705c121SKalle Valo bool cmd_hold_nic_awake; 402e705c121SKalle Valo bool ref_cmd_in_flight; 403e705c121SKalle Valo 404e705c121SKalle Valo dma_addr_t fw_mon_phys; 405e705c121SKalle Valo struct page *fw_mon_page; 406e705c121SKalle Valo u32 fw_mon_size; 4072e5d4a8fSHaim Dreyfuss 4082e5d4a8fSHaim Dreyfuss struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 4092e5d4a8fSHaim Dreyfuss bool msix_enabled; 4102e5d4a8fSHaim Dreyfuss u32 allocated_vector; 4112e5d4a8fSHaim Dreyfuss u32 default_irq_num; 4122e5d4a8fSHaim Dreyfuss u32 fh_init_mask; 4132e5d4a8fSHaim Dreyfuss u32 hw_init_mask; 4142e5d4a8fSHaim Dreyfuss u32 fh_mask; 4152e5d4a8fSHaim Dreyfuss u32 hw_mask; 416e705c121SKalle Valo }; 417e705c121SKalle Valo 41885e5a387SJohannes Berg static inline struct iwl_trans_pcie * 41985e5a387SJohannes Berg IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 42085e5a387SJohannes Berg { 42185e5a387SJohannes Berg return (void *)trans->trans_specific; 42285e5a387SJohannes Berg } 423e705c121SKalle Valo 424e705c121SKalle Valo static inline struct iwl_trans * 425e705c121SKalle Valo iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 426e705c121SKalle Valo { 427e705c121SKalle Valo return container_of((void *)trans_pcie, struct iwl_trans, 428e705c121SKalle Valo trans_specific); 429e705c121SKalle Valo } 430e705c121SKalle Valo 431e705c121SKalle Valo /* 432e705c121SKalle Valo * Convention: trans API functions: iwl_trans_pcie_XXX 433e705c121SKalle Valo * Other functions: iwl_pcie_XXX 434e705c121SKalle Valo */ 435e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 436e705c121SKalle Valo const struct pci_device_id *ent, 437e705c121SKalle Valo const struct iwl_cfg *cfg); 438e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans); 439e705c121SKalle Valo 440e705c121SKalle Valo /***************************************************** 441e705c121SKalle Valo * RX 442e705c121SKalle Valo ******************************************************/ 443e705c121SKalle Valo int iwl_pcie_rx_init(struct iwl_trans *trans); 4442e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 445e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 4462e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 4472e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 448e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans); 449e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans); 450e705c121SKalle Valo 451e705c121SKalle Valo /***************************************************** 452e705c121SKalle Valo * ICT - interrupt handling 453e705c121SKalle Valo ******************************************************/ 454e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data); 455e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans); 456e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans); 457e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans); 458e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans); 459e705c121SKalle Valo 460e705c121SKalle Valo /***************************************************** 461e705c121SKalle Valo * TX / HCMD 462e705c121SKalle Valo ******************************************************/ 463e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans); 464e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 465e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans); 466e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans); 467e705c121SKalle Valo void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 468e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 469e705c121SKalle Valo unsigned int wdg_timeout); 470e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 471e705c121SKalle Valo bool configure_scd); 47242db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 47342db09c1SLiad Kaufman bool shared_mode); 4748aacf4b7SSara Sharon dma_addr_t iwl_trans_pcie_get_txq_byte_table(struct iwl_trans *trans, int txq); 47538398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, 47638398efbSSara Sharon struct iwl_txq *txq); 477e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 478e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id); 479e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 480e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 481e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 482e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb); 483e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 484e705c121SKalle Valo struct sk_buff_head *skbs); 485e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 486e705c121SKalle Valo 4876983ba69SSara Sharon static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *tfd, 4886983ba69SSara Sharon u8 idx) 489e705c121SKalle Valo { 4906983ba69SSara Sharon struct iwl_tfd *tfd_fh; 4916983ba69SSara Sharon struct iwl_tfd_tb *tb; 4926983ba69SSara Sharon 4936983ba69SSara Sharon if (trans->cfg->use_tfh) { 4946983ba69SSara Sharon struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 4956983ba69SSara Sharon struct iwl_tfh_tb *tb = &tfd_fh->tbs[idx]; 4966983ba69SSara Sharon 4976983ba69SSara Sharon return le16_to_cpu(tb->tb_len); 4986983ba69SSara Sharon } 4996983ba69SSara Sharon 5006983ba69SSara Sharon tfd_fh = (void *)tfd; 5016983ba69SSara Sharon tb = &tfd_fh->tbs[idx]; 502e705c121SKalle Valo 503e705c121SKalle Valo return le16_to_cpu(tb->hi_n_len) >> 4; 504e705c121SKalle Valo } 505e705c121SKalle Valo 506e705c121SKalle Valo /***************************************************** 507e705c121SKalle Valo * Error handling 508e705c121SKalle Valo ******************************************************/ 509e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans); 510e705c121SKalle Valo 511e705c121SKalle Valo /***************************************************** 512e705c121SKalle Valo * Helpers 513e705c121SKalle Valo ******************************************************/ 514f16c3ebfSEmmanuel Grumbach static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 515e705c121SKalle Valo { 5162e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 517e705c121SKalle Valo 5182e5d4a8fSHaim Dreyfuss clear_bit(STATUS_INT_ENABLED, &trans->status); 5192e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 520e705c121SKalle Valo /* disable interrupts from uCode/NIC to host */ 521e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 522e705c121SKalle Valo 523e705c121SKalle Valo /* acknowledge/clear/reset any interrupts still pending 524e705c121SKalle Valo * from uCode or flow handler (Rx/Tx DMA) */ 525e705c121SKalle Valo iwl_write32(trans, CSR_INT, 0xffffffff); 526e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 5272e5d4a8fSHaim Dreyfuss } else { 5282e5d4a8fSHaim Dreyfuss /* disable all the interrupt we might use */ 5292e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 5302e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 5312e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 5322e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 5332e5d4a8fSHaim Dreyfuss } 534e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 535e705c121SKalle Valo } 536e705c121SKalle Valo 537f16c3ebfSEmmanuel Grumbach static inline void iwl_disable_interrupts(struct iwl_trans *trans) 538f16c3ebfSEmmanuel Grumbach { 539f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 540f16c3ebfSEmmanuel Grumbach 541f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 542f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 543f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 544f16c3ebfSEmmanuel Grumbach } 545f16c3ebfSEmmanuel Grumbach 546f16c3ebfSEmmanuel Grumbach static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 547e705c121SKalle Valo { 548e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 549e705c121SKalle Valo 550e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 551e705c121SKalle Valo set_bit(STATUS_INT_ENABLED, &trans->status); 5522e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 553e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 554e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 5552e5d4a8fSHaim Dreyfuss } else { 5562e5d4a8fSHaim Dreyfuss /* 5572e5d4a8fSHaim Dreyfuss * fh/hw_mask keeps all the unmasked causes. 5582e5d4a8fSHaim Dreyfuss * Unlike msi, in msix cause is enabled when it is unset. 5592e5d4a8fSHaim Dreyfuss */ 5602e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 5612e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 5622e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 5632e5d4a8fSHaim Dreyfuss ~trans_pcie->fh_mask); 5642e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 5652e5d4a8fSHaim Dreyfuss ~trans_pcie->hw_mask); 5662e5d4a8fSHaim Dreyfuss } 5672e5d4a8fSHaim Dreyfuss } 5682e5d4a8fSHaim Dreyfuss 569f16c3ebfSEmmanuel Grumbach static inline void iwl_enable_interrupts(struct iwl_trans *trans) 570f16c3ebfSEmmanuel Grumbach { 571f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 572f16c3ebfSEmmanuel Grumbach 573f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 574f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 575f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 576f16c3ebfSEmmanuel Grumbach } 5772e5d4a8fSHaim Dreyfuss static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 5782e5d4a8fSHaim Dreyfuss { 5792e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 5802e5d4a8fSHaim Dreyfuss 5812e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 5822e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = msk; 5832e5d4a8fSHaim Dreyfuss } 5842e5d4a8fSHaim Dreyfuss 5852e5d4a8fSHaim Dreyfuss static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 5862e5d4a8fSHaim Dreyfuss { 5872e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 5882e5d4a8fSHaim Dreyfuss 5892e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 5902e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = msk; 591e705c121SKalle Valo } 592e705c121SKalle Valo 593a6bd005fSEmmanuel Grumbach static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 594a6bd005fSEmmanuel Grumbach { 595a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 596a6bd005fSEmmanuel Grumbach 597a6bd005fSEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 5982e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 599a6bd005fSEmmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 600a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 6012e5d4a8fSHaim Dreyfuss } else { 6022e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 6032e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 6042e5d4a8fSHaim Dreyfuss iwl_enable_fh_int_msk_msix(trans, 6052e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 6062e5d4a8fSHaim Dreyfuss } 607a6bd005fSEmmanuel Grumbach } 608a6bd005fSEmmanuel Grumbach 609e705c121SKalle Valo static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 610e705c121SKalle Valo { 611e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 612e705c121SKalle Valo 613e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 6142e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 615e705c121SKalle Valo trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 616e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 6172e5d4a8fSHaim Dreyfuss } else { 6182e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 6192e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 6202e5d4a8fSHaim Dreyfuss iwl_enable_hw_int_msk_msix(trans, 6212e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_RF_KILL); 6222e5d4a8fSHaim Dreyfuss } 623e705c121SKalle Valo } 624e705c121SKalle Valo 625e705c121SKalle Valo static inline void iwl_wake_queue(struct iwl_trans *trans, 626e705c121SKalle Valo struct iwl_txq *txq) 627e705c121SKalle Valo { 628e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 629e705c121SKalle Valo 630bb98ecd4SSara Sharon if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) { 631bb98ecd4SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id); 632bb98ecd4SSara Sharon iwl_op_mode_queue_not_full(trans->op_mode, txq->id); 633e705c121SKalle Valo } 634e705c121SKalle Valo } 635e705c121SKalle Valo 636e705c121SKalle Valo static inline void iwl_stop_queue(struct iwl_trans *trans, 637e705c121SKalle Valo struct iwl_txq *txq) 638e705c121SKalle Valo { 639e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 640e705c121SKalle Valo 641bb98ecd4SSara Sharon if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) { 642bb98ecd4SSara Sharon iwl_op_mode_queue_full(trans->op_mode, txq->id); 643bb98ecd4SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id); 644e705c121SKalle Valo } else 645e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 646bb98ecd4SSara Sharon txq->id); 647e705c121SKalle Valo } 648e705c121SKalle Valo 649bb98ecd4SSara Sharon static inline bool iwl_queue_used(const struct iwl_txq *q, int i) 650e705c121SKalle Valo { 651e705c121SKalle Valo return q->write_ptr >= q->read_ptr ? 652e705c121SKalle Valo (i >= q->read_ptr && i < q->write_ptr) : 653e705c121SKalle Valo !(i < q->read_ptr && i >= q->write_ptr); 654e705c121SKalle Valo } 655e705c121SKalle Valo 656bb98ecd4SSara Sharon static inline u8 get_cmd_index(struct iwl_txq *q, u32 index) 657e705c121SKalle Valo { 658e705c121SKalle Valo return index & (q->n_window - 1); 659e705c121SKalle Valo } 660e705c121SKalle Valo 661e705c121SKalle Valo static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 662e705c121SKalle Valo { 663e705c121SKalle Valo return !(iwl_read32(trans, CSR_GP_CNTRL) & 664e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 665e705c121SKalle Valo } 666e705c121SKalle Valo 667e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 668e705c121SKalle Valo u32 reg, u32 mask, u32 value) 669e705c121SKalle Valo { 670e705c121SKalle Valo u32 v; 671e705c121SKalle Valo 672e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 673e705c121SKalle Valo WARN_ON_ONCE(value & ~mask); 674e705c121SKalle Valo #endif 675e705c121SKalle Valo 676e705c121SKalle Valo v = iwl_read32(trans, reg); 677e705c121SKalle Valo v &= ~mask; 678e705c121SKalle Valo v |= value; 679e705c121SKalle Valo iwl_write32(trans, reg, v); 680e705c121SKalle Valo } 681e705c121SKalle Valo 682e705c121SKalle Valo static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 683e705c121SKalle Valo u32 reg, u32 mask) 684e705c121SKalle Valo { 685e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 686e705c121SKalle Valo } 687e705c121SKalle Valo 688e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 689e705c121SKalle Valo u32 reg, u32 mask) 690e705c121SKalle Valo { 691e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 692e705c121SKalle Valo } 693e705c121SKalle Valo 694e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 695e705c121SKalle Valo 696f8a1edb7SJohannes Berg #ifdef CONFIG_IWLWIFI_DEBUGFS 697f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 698f8a1edb7SJohannes Berg #else 699f8a1edb7SJohannes Berg static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 700f8a1edb7SJohannes Berg { 701f8a1edb7SJohannes Berg return 0; 702f8a1edb7SJohannes Berg } 703f8a1edb7SJohannes Berg #endif 704f8a1edb7SJohannes Berg 7054cbb8e50SLuciano Coelho int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans); 7064cbb8e50SLuciano Coelho int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans); 7074cbb8e50SLuciano Coelho 7081316d595SSara Sharon void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable); 7091316d595SSara Sharon 710e705c121SKalle Valo #endif /* __iwl_trans_int_pcie_h__ */ 711