1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 4e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 61b493e30SGolan Ben Ami * Copyright(c) 2018 Intel Corporation 7e705c121SKalle Valo * 8e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 9e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 10e705c121SKalle Valo * 11e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 12e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 13e705c121SKalle Valo * published by the Free Software Foundation. 14e705c121SKalle Valo * 15e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 16e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18e705c121SKalle Valo * more details. 19e705c121SKalle Valo * 20e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 211b493e30SGolan Ben Ami * this program. 22e705c121SKalle Valo * 23e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 24e705c121SKalle Valo * file called LICENSE. 25e705c121SKalle Valo * 26e705c121SKalle Valo * Contact Information: 27cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 28e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29e705c121SKalle Valo * 30e705c121SKalle Valo *****************************************************************************/ 31e705c121SKalle Valo #ifndef __iwl_trans_int_pcie_h__ 32e705c121SKalle Valo #define __iwl_trans_int_pcie_h__ 33e705c121SKalle Valo 34e705c121SKalle Valo #include <linux/spinlock.h> 35e705c121SKalle Valo #include <linux/interrupt.h> 36e705c121SKalle Valo #include <linux/skbuff.h> 37e705c121SKalle Valo #include <linux/wait.h> 38e705c121SKalle Valo #include <linux/pci.h> 39e705c121SKalle Valo #include <linux/timer.h> 407c8d91ebSHaim Dreyfuss #include <linux/cpu.h> 41e705c121SKalle Valo 42e705c121SKalle Valo #include "iwl-fh.h" 43e705c121SKalle Valo #include "iwl-csr.h" 44e705c121SKalle Valo #include "iwl-trans.h" 45e705c121SKalle Valo #include "iwl-debug.h" 46e705c121SKalle Valo #include "iwl-io.h" 47e705c121SKalle Valo #include "iwl-op-mode.h" 48ff932f61SGolan Ben Ami #include "iwl-drv.h" 49e705c121SKalle Valo 50e705c121SKalle Valo /* We need 2 entries for the TX command and header, and another one might 51e705c121SKalle Valo * be needed for potential data in the SKB's head. The remaining ones can 52e705c121SKalle Valo * be used for frags. 53e705c121SKalle Valo */ 543cd1980bSSara Sharon #define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3) 55e705c121SKalle Valo 56e705c121SKalle Valo /* 57e705c121SKalle Valo * RX related structures and functions 58e705c121SKalle Valo */ 59e705c121SKalle Valo #define RX_NUM_QUEUES 1 60e705c121SKalle Valo #define RX_POST_REQ_ALLOC 2 61e705c121SKalle Valo #define RX_CLAIM_REQ_ALLOC 8 6278485054SSara Sharon #define RX_PENDING_WATERMARK 16 631b493e30SGolan Ben Ami #define FIRST_RX_QUEUE 512 64e705c121SKalle Valo 65e705c121SKalle Valo struct iwl_host_cmd; 66e705c121SKalle Valo 67e705c121SKalle Valo /*This file includes the declaration that are internal to the 68e705c121SKalle Valo * trans_pcie layer */ 69e705c121SKalle Valo 7096a6497bSSara Sharon /** 7196a6497bSSara Sharon * struct iwl_rx_mem_buffer 7296a6497bSSara Sharon * @page_dma: bus address of rxb page 7396a6497bSSara Sharon * @page: driver's pointer to the rxb page 74b1753c62SSara Sharon * @invalid: rxb is in driver ownership - not owned by HW 7596a6497bSSara Sharon * @vid: index of this rxb in the global table 760307c839SGolan Ben Ami * @size: size used from the buffer 7796a6497bSSara Sharon */ 78e705c121SKalle Valo struct iwl_rx_mem_buffer { 79e705c121SKalle Valo dma_addr_t page_dma; 80e705c121SKalle Valo struct page *page; 8196a6497bSSara Sharon u16 vid; 82b1753c62SSara Sharon bool invalid; 83e705c121SKalle Valo struct list_head list; 840307c839SGolan Ben Ami u32 size; 85e705c121SKalle Valo }; 86e705c121SKalle Valo 87e705c121SKalle Valo /** 88e705c121SKalle Valo * struct isr_statistics - interrupt statistics 89e705c121SKalle Valo * 90e705c121SKalle Valo */ 91e705c121SKalle Valo struct isr_statistics { 92e705c121SKalle Valo u32 hw; 93e705c121SKalle Valo u32 sw; 94e705c121SKalle Valo u32 err_code; 95e705c121SKalle Valo u32 sch; 96e705c121SKalle Valo u32 alive; 97e705c121SKalle Valo u32 rfkill; 98e705c121SKalle Valo u32 ctkill; 99e705c121SKalle Valo u32 wakeup; 100e705c121SKalle Valo u32 rx; 101e705c121SKalle Valo u32 tx; 102e705c121SKalle Valo u32 unhandled; 103e705c121SKalle Valo }; 104e705c121SKalle Valo 1050307c839SGolan Ben Ami #define IWL_RX_TD_TYPE_MSK 0xff000000 1060307c839SGolan Ben Ami #define IWL_RX_TD_SIZE_MSK 0x00ffffff 1070307c839SGolan Ben Ami #define IWL_RX_TD_SIZE_2K BIT(11) 1080307c839SGolan Ben Ami #define IWL_RX_TD_TYPE 0 109cf495496SGolan Ben Ami 110cf495496SGolan Ben Ami /** 111cf495496SGolan Ben Ami * struct iwl_rx_transfer_desc - transfer descriptor 112cf495496SGolan Ben Ami * @type_n_size: buffer type (bit 0: external buff valid, 113cf495496SGolan Ben Ami * bit 1: optional footer valid, bit 2-7: reserved) 114cf495496SGolan Ben Ami * and buffer size 115cf495496SGolan Ben Ami * @addr: ptr to free buffer start address 116cf495496SGolan Ben Ami * @rbid: unique tag of the buffer 117cf495496SGolan Ben Ami * @reserved: reserved 118cf495496SGolan Ben Ami */ 119cf495496SGolan Ben Ami struct iwl_rx_transfer_desc { 120cf495496SGolan Ben Ami __le32 type_n_size; 121cf495496SGolan Ben Ami __le64 addr; 122cf495496SGolan Ben Ami __le16 rbid; 123cf495496SGolan Ben Ami __le16 reserved; 124cf495496SGolan Ben Ami } __packed; 125cf495496SGolan Ben Ami 126cf495496SGolan Ben Ami #define IWL_RX_CD_SIZE 0xffffff00 127cf495496SGolan Ben Ami 128cf495496SGolan Ben Ami /** 129cf495496SGolan Ben Ami * struct iwl_rx_completion_desc - completion descriptor 130cf495496SGolan Ben Ami * @type: buffer type (bit 0: external buff valid, 131cf495496SGolan Ben Ami * bit 1: optional footer valid, bit 2-7: reserved) 132cf495496SGolan Ben Ami * @status: status of the completion 133cf495496SGolan Ben Ami * @reserved1: reserved 134cf495496SGolan Ben Ami * @rbid: unique tag of the received buffer 135cf495496SGolan Ben Ami * @size: buffer size, masked by IWL_RX_CD_SIZE 136cf495496SGolan Ben Ami * @reserved2: reserved 137cf495496SGolan Ben Ami */ 138cf495496SGolan Ben Ami struct iwl_rx_completion_desc { 139cf495496SGolan Ben Ami u8 type; 140cf495496SGolan Ben Ami u8 status; 141cf495496SGolan Ben Ami __le16 reserved1; 142cf495496SGolan Ben Ami __le16 rbid; 143cf495496SGolan Ben Ami __le32 size; 144cf495496SGolan Ben Ami u8 reserved2[22]; 145cf495496SGolan Ben Ami } __packed; 146cf495496SGolan Ben Ami 147e705c121SKalle Valo /** 148e705c121SKalle Valo * struct iwl_rxq - Rx queue 14996a6497bSSara Sharon * @id: queue index 15096a6497bSSara Sharon * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 15196a6497bSSara Sharon * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 1520307c839SGolan Ben Ami * In 22560 devices it is a pointer to a list of iwl_rx_transfer_desc's 153e705c121SKalle Valo * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 15496a6497bSSara Sharon * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd) 15596a6497bSSara Sharon * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd) 1561b493e30SGolan Ben Ami * @tr_tail: driver's pointer to the transmission ring tail buffer 1571b493e30SGolan Ben Ami * @tr_tail_dma: physical address of the buffer for the transmission ring tail 1581b493e30SGolan Ben Ami * @cr_tail: driver's pointer to the completion ring tail buffer 1591b493e30SGolan Ben Ami * @cr_tail_dma: physical address of the buffer for the completion ring tail 160e705c121SKalle Valo * @read: Shared index to newest available Rx buffer 161e705c121SKalle Valo * @write: Shared index to oldest written Rx packet 162e705c121SKalle Valo * @free_count: Number of pre-allocated buffers in rx_free 163e705c121SKalle Valo * @used_count: Number of RBDs handled to allocator to use for allocation 164e705c121SKalle Valo * @write_actual: 165e705c121SKalle Valo * @rx_free: list of RBDs with allocated RB ready for use 166e705c121SKalle Valo * @rx_used: list of RBDs with no RB attached 167e705c121SKalle Valo * @need_update: flag to indicate we need to update read/write index 168e705c121SKalle Valo * @rb_stts: driver's pointer to receive buffer status 169e705c121SKalle Valo * @rb_stts_dma: bus address of receive buffer status 170e705c121SKalle Valo * @lock: 17196a6497bSSara Sharon * @queue: actual rx queue. Not used for multi-rx queue. 172e705c121SKalle Valo * 173e705c121SKalle Valo * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 174e705c121SKalle Valo */ 175e705c121SKalle Valo struct iwl_rxq { 17696a6497bSSara Sharon int id; 17796a6497bSSara Sharon void *bd; 178e705c121SKalle Valo dma_addr_t bd_dma; 179b2a58c97SSara Sharon union { 1800307c839SGolan Ben Ami void *used_bd; 181b2a58c97SSara Sharon __le32 *bd_32; 182b2a58c97SSara Sharon struct iwl_rx_completion_desc *cd; 183b2a58c97SSara Sharon }; 18496a6497bSSara Sharon dma_addr_t used_bd_dma; 1851b493e30SGolan Ben Ami __le16 *tr_tail; 1861b493e30SGolan Ben Ami dma_addr_t tr_tail_dma; 1871b493e30SGolan Ben Ami __le16 *cr_tail; 1881b493e30SGolan Ben Ami dma_addr_t cr_tail_dma; 189e705c121SKalle Valo u32 read; 190e705c121SKalle Valo u32 write; 191e705c121SKalle Valo u32 free_count; 192e705c121SKalle Valo u32 used_count; 193e705c121SKalle Valo u32 write_actual; 19496a6497bSSara Sharon u32 queue_size; 195e705c121SKalle Valo struct list_head rx_free; 196e705c121SKalle Valo struct list_head rx_used; 197e705c121SKalle Valo bool need_update; 1980307c839SGolan Ben Ami void *rb_stts; 199e705c121SKalle Valo dma_addr_t rb_stts_dma; 200e705c121SKalle Valo spinlock_t lock; 201bce97731SSara Sharon struct napi_struct napi; 202e705c121SKalle Valo struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 203e705c121SKalle Valo }; 204e705c121SKalle Valo 205e705c121SKalle Valo /** 206e705c121SKalle Valo * struct iwl_rb_allocator - Rx allocator 207e705c121SKalle Valo * @req_pending: number of requests the allcator had not processed yet 208e705c121SKalle Valo * @req_ready: number of requests honored and ready for claiming 209e705c121SKalle Valo * @rbd_allocated: RBDs with pages allocated and ready to be handled to 210e705c121SKalle Valo * the queue. This is a list of &struct iwl_rx_mem_buffer 211e705c121SKalle Valo * @rbd_empty: RBDs with no page attached for allocator use. This is a list 212e705c121SKalle Valo * of &struct iwl_rx_mem_buffer 213e705c121SKalle Valo * @lock: protects the rbd_allocated and rbd_empty lists 214e705c121SKalle Valo * @alloc_wq: work queue for background calls 215e705c121SKalle Valo * @rx_alloc: work struct for background calls 216e705c121SKalle Valo */ 217e705c121SKalle Valo struct iwl_rb_allocator { 218e705c121SKalle Valo atomic_t req_pending; 219e705c121SKalle Valo atomic_t req_ready; 220e705c121SKalle Valo struct list_head rbd_allocated; 221e705c121SKalle Valo struct list_head rbd_empty; 222e705c121SKalle Valo spinlock_t lock; 223e705c121SKalle Valo struct workqueue_struct *alloc_wq; 224e705c121SKalle Valo struct work_struct rx_alloc; 225e705c121SKalle Valo }; 226e705c121SKalle Valo 227e705c121SKalle Valo struct iwl_dma_ptr { 228e705c121SKalle Valo dma_addr_t dma; 229e705c121SKalle Valo void *addr; 230e705c121SKalle Valo size_t size; 231e705c121SKalle Valo }; 232e705c121SKalle Valo 233e705c121SKalle Valo /** 234e705c121SKalle Valo * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 235e705c121SKalle Valo * @index -- current index 236e705c121SKalle Valo */ 2377b3e42eaSGolan Ben Ami static inline int iwl_queue_inc_wrap(struct iwl_trans *trans, int index) 238e705c121SKalle Valo { 2397b3e42eaSGolan Ben Ami return ++index & (trans->cfg->base_params->max_tfd_queue_size - 1); 240e705c121SKalle Valo } 241e705c121SKalle Valo 242e705c121SKalle Valo /** 2430307c839SGolan Ben Ami * iwl_get_closed_rb_stts - get closed rb stts from different structs 2440307c839SGolan Ben Ami * @rxq - the rxq to get the rb stts from 2450307c839SGolan Ben Ami */ 2460307c839SGolan Ben Ami static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans, 2470307c839SGolan Ben Ami struct iwl_rxq *rxq) 2480307c839SGolan Ben Ami { 2490307c839SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 2500307c839SGolan Ben Ami __le16 *rb_stts = rxq->rb_stts; 2510307c839SGolan Ben Ami 2520307c839SGolan Ben Ami return READ_ONCE(*rb_stts); 2530307c839SGolan Ben Ami } else { 2540307c839SGolan Ben Ami struct iwl_rb_status *rb_stts = rxq->rb_stts; 2550307c839SGolan Ben Ami 2560307c839SGolan Ben Ami return READ_ONCE(rb_stts->closed_rb_num); 2570307c839SGolan Ben Ami } 2580307c839SGolan Ben Ami } 2590307c839SGolan Ben Ami 2600307c839SGolan Ben Ami /** 261e705c121SKalle Valo * iwl_queue_dec_wrap - decrement queue index, wrap back to end 262e705c121SKalle Valo * @index -- current index 263e705c121SKalle Valo */ 2647b3e42eaSGolan Ben Ami static inline int iwl_queue_dec_wrap(struct iwl_trans *trans, int index) 265e705c121SKalle Valo { 2667b3e42eaSGolan Ben Ami return --index & (trans->cfg->base_params->max_tfd_queue_size - 1); 267e705c121SKalle Valo } 268e705c121SKalle Valo 269e705c121SKalle Valo struct iwl_cmd_meta { 270e705c121SKalle Valo /* only for SYNC commands, iff the reply skb is wanted */ 271e705c121SKalle Valo struct iwl_host_cmd *source; 272e705c121SKalle Valo u32 flags; 2733cd1980bSSara Sharon u32 tbs; 274e705c121SKalle Valo }; 275e705c121SKalle Valo 276e705c121SKalle Valo 277e705c121SKalle Valo #define TFD_TX_CMD_SLOTS 256 278e705c121SKalle Valo #define TFD_CMD_SLOTS 32 279e705c121SKalle Valo 280e705c121SKalle Valo /* 2818de437c7SSara Sharon * The FH will write back to the first TB only, so we need to copy some data 2828de437c7SSara Sharon * into the buffer regardless of whether it should be mapped or not. 2838de437c7SSara Sharon * This indicates how big the first TB must be to include the scratch buffer 2848de437c7SSara Sharon * and the assigned PN. 285b97277ccSSara Sharon * Since PN location is 8 bytes at offset 12, it's 20 now. 2868de437c7SSara Sharon * If we make it bigger then allocations will be bigger and copy slower, so 2878de437c7SSara Sharon * that's probably not useful. 288e705c121SKalle Valo */ 289b97277ccSSara Sharon #define IWL_FIRST_TB_SIZE 20 2908de437c7SSara Sharon #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 291e705c121SKalle Valo 292e705c121SKalle Valo struct iwl_pcie_txq_entry { 293e705c121SKalle Valo struct iwl_device_cmd *cmd; 294e705c121SKalle Valo struct sk_buff *skb; 295e705c121SKalle Valo /* buffer to free after command completes */ 296e705c121SKalle Valo const void *free_buf; 297e705c121SKalle Valo struct iwl_cmd_meta meta; 298e705c121SKalle Valo }; 299e705c121SKalle Valo 3008de437c7SSara Sharon struct iwl_pcie_first_tb_buf { 3018de437c7SSara Sharon u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 302e705c121SKalle Valo }; 303e705c121SKalle Valo 304e705c121SKalle Valo /** 305e705c121SKalle Valo * struct iwl_txq - Tx Queue for DMA 306e705c121SKalle Valo * @q: generic Rx/Tx queue descriptor 307e705c121SKalle Valo * @tfds: transmit frame descriptors (DMA memory) 3088de437c7SSara Sharon * @first_tb_bufs: start of command headers, including scratch buffers, for 309e705c121SKalle Valo * the writeback -- this is DMA memory and an array holding one buffer 310e705c121SKalle Valo * for each command on the queue 3118de437c7SSara Sharon * @first_tb_dma: DMA address for the first_tb_bufs start 312e705c121SKalle Valo * @entries: transmit entries (driver state) 313e705c121SKalle Valo * @lock: queue lock 314e705c121SKalle Valo * @stuck_timer: timer that fires if queue gets stuck 315e705c121SKalle Valo * @trans_pcie: pointer back to transport (for timer) 316e705c121SKalle Valo * @need_update: indicates need to update read/write index 317e705c121SKalle Valo * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 318e705c121SKalle Valo * @wd_timeout: queue watchdog timeout (jiffies) - per queue 319e705c121SKalle Valo * @frozen: tx stuck queue timer is frozen 320e705c121SKalle Valo * @frozen_expiry_remainder: remember how long until the timer fires 32113a3a390SSara Sharon * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 322bb98ecd4SSara Sharon * @write_ptr: 1-st empty entry (index) host_w 323bb98ecd4SSara Sharon * @read_ptr: last used entry (index) host_r 324bb98ecd4SSara Sharon * @dma_addr: physical addr for BD's 325bb98ecd4SSara Sharon * @n_window: safe queue window 326bb98ecd4SSara Sharon * @id: queue id 327bb98ecd4SSara Sharon * @low_mark: low watermark, resume queue if free space more than this 328bb98ecd4SSara Sharon * @high_mark: high watermark, stop queue if free space less than this 329e705c121SKalle Valo * 330e705c121SKalle Valo * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 331e705c121SKalle Valo * descriptors) and required locking structures. 332bb98ecd4SSara Sharon * 333bb98ecd4SSara Sharon * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 334bb98ecd4SSara Sharon * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 335bb98ecd4SSara Sharon * there might be HW changes in the future). For the normal TX 336bb98ecd4SSara Sharon * queues, n_window, which is the size of the software queue data 337bb98ecd4SSara Sharon * is also 256; however, for the command queue, n_window is only 338bb98ecd4SSara Sharon * 32 since we don't need so many commands pending. Since the HW 339bb98ecd4SSara Sharon * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 340bb98ecd4SSara Sharon * This means that we end up with the following: 341bb98ecd4SSara Sharon * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 342bb98ecd4SSara Sharon * SW entries: | 0 | ... | 31 | 343bb98ecd4SSara Sharon * where N is a number between 0 and 7. This means that the SW 344bb98ecd4SSara Sharon * data is a window overlayed over the HW queue. 345e705c121SKalle Valo */ 346e705c121SKalle Valo struct iwl_txq { 3476983ba69SSara Sharon void *tfds; 3488de437c7SSara Sharon struct iwl_pcie_first_tb_buf *first_tb_bufs; 3498de437c7SSara Sharon dma_addr_t first_tb_dma; 350e705c121SKalle Valo struct iwl_pcie_txq_entry *entries; 351e705c121SKalle Valo spinlock_t lock; 352e705c121SKalle Valo unsigned long frozen_expiry_remainder; 353e705c121SKalle Valo struct timer_list stuck_timer; 354e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 355e705c121SKalle Valo bool need_update; 356e705c121SKalle Valo bool frozen; 357e705c121SKalle Valo bool ampdu; 35804fa3e68SEmmanuel Grumbach int block; 359e705c121SKalle Valo unsigned long wd_timeout; 3603955525dSEmmanuel Grumbach struct sk_buff_head overflow_q; 36113a3a390SSara Sharon struct iwl_dma_ptr bc_tbl; 362bb98ecd4SSara Sharon 363bb98ecd4SSara Sharon int write_ptr; 364bb98ecd4SSara Sharon int read_ptr; 365bb98ecd4SSara Sharon dma_addr_t dma_addr; 366bb98ecd4SSara Sharon int n_window; 367bb98ecd4SSara Sharon u32 id; 368bb98ecd4SSara Sharon int low_mark; 369bb98ecd4SSara Sharon int high_mark; 370e705c121SKalle Valo }; 371e705c121SKalle Valo 372e705c121SKalle Valo static inline dma_addr_t 3738de437c7SSara Sharon iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx) 374e705c121SKalle Valo { 3758de437c7SSara Sharon return txq->first_tb_dma + 3768de437c7SSara Sharon sizeof(struct iwl_pcie_first_tb_buf) * idx; 377e705c121SKalle Valo } 378e705c121SKalle Valo 3796eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page { 3806eb5e529SEmmanuel Grumbach struct page *page; 3816eb5e529SEmmanuel Grumbach u8 *pos; 3826eb5e529SEmmanuel Grumbach }; 3836eb5e529SEmmanuel Grumbach 384e705c121SKalle Valo /** 385496d83caSHaim Dreyfuss * enum iwl_shared_irq_flags - level of sharing for irq 386496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 387496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 388496d83caSHaim Dreyfuss */ 389496d83caSHaim Dreyfuss enum iwl_shared_irq_flags { 390496d83caSHaim Dreyfuss IWL_SHARED_IRQ_NON_RX = BIT(0), 391496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 392496d83caSHaim Dreyfuss }; 393496d83caSHaim Dreyfuss 394496d83caSHaim Dreyfuss /** 3959b58419eSGolan Ben Ami * enum iwl_image_response_code - image response values 3969b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_DEF: the default value of the register 3979b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully 3989b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_FAIL: iml reading failed 3999b58419eSGolan Ben Ami */ 4009b58419eSGolan Ben Ami enum iwl_image_response_code { 4019b58419eSGolan Ben Ami IWL_IMAGE_RESP_DEF = 0, 4029b58419eSGolan Ben Ami IWL_IMAGE_RESP_SUCCESS = 1, 4039b58419eSGolan Ben Ami IWL_IMAGE_RESP_FAIL = 2, 4049b58419eSGolan Ben Ami }; 4059b58419eSGolan Ben Ami 4069b58419eSGolan Ben Ami /** 407eda50cdeSSara Sharon * struct iwl_dram_data 408eda50cdeSSara Sharon * @physical: page phy pointer 409eda50cdeSSara Sharon * @block: pointer to the allocated block/page 410eda50cdeSSara Sharon * @size: size of the block/page 411eda50cdeSSara Sharon */ 412eda50cdeSSara Sharon struct iwl_dram_data { 413eda50cdeSSara Sharon dma_addr_t physical; 414eda50cdeSSara Sharon void *block; 415eda50cdeSSara Sharon int size; 416eda50cdeSSara Sharon }; 417eda50cdeSSara Sharon 418eda50cdeSSara Sharon /** 419eda50cdeSSara Sharon * struct iwl_self_init_dram - dram data used by self init process 420eda50cdeSSara Sharon * @fw: lmac and umac dram data 421eda50cdeSSara Sharon * @fw_cnt: total number of items in array 422eda50cdeSSara Sharon * @paging: paging dram data 423eda50cdeSSara Sharon * @paging_cnt: total number of items in array 424eda50cdeSSara Sharon */ 425eda50cdeSSara Sharon struct iwl_self_init_dram { 426eda50cdeSSara Sharon struct iwl_dram_data *fw; 427eda50cdeSSara Sharon int fw_cnt; 428eda50cdeSSara Sharon struct iwl_dram_data *paging; 429eda50cdeSSara Sharon int paging_cnt; 430eda50cdeSSara Sharon }; 431eda50cdeSSara Sharon 432eda50cdeSSara Sharon /** 433e705c121SKalle Valo * struct iwl_trans_pcie - PCIe transport specific data 434e705c121SKalle Valo * @rxq: all the RX queue data 43578485054SSara Sharon * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 43696a6497bSSara Sharon * @global_table: table mapping received VID from hw to rxb 437e705c121SKalle Valo * @rba: allocator for RX replenishing 438eda50cdeSSara Sharon * @ctxt_info: context information for FW self init 4392ee82402SGolan Ben Ami * @ctxt_info_gen3: context information for gen3 devices 4402ee82402SGolan Ben Ami * @prph_info: prph info for self init 4412ee82402SGolan Ben Ami * @prph_scratch: prph scratch for self init 4422ee82402SGolan Ben Ami * @ctxt_info_dma_addr: dma addr of context information 4432ee82402SGolan Ben Ami * @prph_info_dma_addr: dma addr of prph info 4442ee82402SGolan Ben Ami * @prph_scratch_dma_addr: dma addr of prph scratch 445eda50cdeSSara Sharon * @ctxt_info_dma_addr: dma addr of context information 446eda50cdeSSara Sharon * @init_dram: DRAM data of firmware image (including paging). 447eda50cdeSSara Sharon * Context information addresses will be taken from here. 448eda50cdeSSara Sharon * This is driver's local copy for keeping track of size and 449eda50cdeSSara Sharon * count for allocating and freeing the memory. 450e705c121SKalle Valo * @trans: pointer to the generic transport area 451e705c121SKalle Valo * @scd_base_addr: scheduler sram base address in SRAM 452e705c121SKalle Valo * @scd_bc_tbls: pointer to the byte count table of the scheduler 453e705c121SKalle Valo * @kw: keep warm address 454e705c121SKalle Valo * @pci_dev: basic pci-network driver stuff 455e705c121SKalle Valo * @hw_base: pci hardware address support 456e705c121SKalle Valo * @ucode_write_complete: indicates that the ucode has been copied. 457e705c121SKalle Valo * @ucode_write_waitq: wait queue for uCode load 458e705c121SKalle Valo * @cmd_queue - command queue number 4599416560eSGolan Ben Ami * @def_rx_queue - default rx queue number 4606c4fbcbcSEmmanuel Grumbach * @rx_buf_size: Rx buffer size 461e705c121SKalle Valo * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 462e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 46341837ca9SEmmanuel Grumbach * @sw_csum_tx: if true, then the transport will compute the csum of the TXed 46441837ca9SEmmanuel Grumbach * frame. 465e705c121SKalle Valo * @rx_page_order: page order for receive buffer size 466e705c121SKalle Valo * @reg_lock: protect hw register access 467e705c121SKalle Valo * @mutex: to protect stop_device / start_fw / start_hw 468e705c121SKalle Valo * @cmd_in_flight: true when we have a host command in flight 469e705c121SKalle Valo * @fw_mon_phys: physical address of the buffer for the firmware monitor 470e705c121SKalle Valo * @fw_mon_page: points to the first page of the buffer for the firmware monitor 471e705c121SKalle Valo * @fw_mon_size: size of the buffer for the firmware monitor 4722e5d4a8fSHaim Dreyfuss * @msix_entries: array of MSI-X entries 4732e5d4a8fSHaim Dreyfuss * @msix_enabled: true if managed to enable MSI-X 474496d83caSHaim Dreyfuss * @shared_vec_mask: the type of causes the shared vector handles 475496d83caSHaim Dreyfuss * (see iwl_shared_irq_flags). 476496d83caSHaim Dreyfuss * @alloc_vecs: the number of interrupt vectors allocated by the OS 477496d83caSHaim Dreyfuss * @def_irq: default irq for non rx causes 4782e5d4a8fSHaim Dreyfuss * @fh_init_mask: initial unmasked fh causes 4792e5d4a8fSHaim Dreyfuss * @hw_init_mask: initial unmasked hw causes 4802e5d4a8fSHaim Dreyfuss * @fh_mask: current unmasked fh causes 4812e5d4a8fSHaim Dreyfuss * @hw_mask: current unmasked hw causes 48249564a80SLuca Coelho * @in_rescan: true if we have triggered a device rescan 48349564a80SLuca Coelho * @scheduled_for_removal: true if we have scheduled a device removal 484e705c121SKalle Valo */ 485e705c121SKalle Valo struct iwl_trans_pcie { 48678485054SSara Sharon struct iwl_rxq *rxq; 4877b542436SSara Sharon struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE]; 48843146925SSara Sharon struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE]; 489e705c121SKalle Valo struct iwl_rb_allocator rba; 4902ee82402SGolan Ben Ami union { 491eda50cdeSSara Sharon struct iwl_context_info *ctxt_info; 4922ee82402SGolan Ben Ami struct iwl_context_info_gen3 *ctxt_info_gen3; 4932ee82402SGolan Ben Ami }; 4942ee82402SGolan Ben Ami struct iwl_prph_info *prph_info; 4952ee82402SGolan Ben Ami struct iwl_prph_scratch *prph_scratch; 496eda50cdeSSara Sharon dma_addr_t ctxt_info_dma_addr; 4972ee82402SGolan Ben Ami dma_addr_t prph_info_dma_addr; 4982ee82402SGolan Ben Ami dma_addr_t prph_scratch_dma_addr; 4992ee82402SGolan Ben Ami dma_addr_t iml_dma_addr; 500eda50cdeSSara Sharon struct iwl_self_init_dram init_dram; 501e705c121SKalle Valo struct iwl_trans *trans; 502e705c121SKalle Valo 503e705c121SKalle Valo struct net_device napi_dev; 504e705c121SKalle Valo 5056eb5e529SEmmanuel Grumbach struct __percpu iwl_tso_hdr_page *tso_hdr_page; 5066eb5e529SEmmanuel Grumbach 507e705c121SKalle Valo /* INT ICT Table */ 508e705c121SKalle Valo __le32 *ict_tbl; 509e705c121SKalle Valo dma_addr_t ict_tbl_dma; 510e705c121SKalle Valo int ict_index; 511e705c121SKalle Valo bool use_ict; 512326477e4SJohannes Berg bool is_down, opmode_down; 513fa4de7f7SJohannes Berg bool debug_rfkill; 514e705c121SKalle Valo struct isr_statistics isr_stats; 515e705c121SKalle Valo 516e705c121SKalle Valo spinlock_t irq_lock; 517e705c121SKalle Valo struct mutex mutex; 518e705c121SKalle Valo u32 inta_mask; 519e705c121SKalle Valo u32 scd_base_addr; 520e705c121SKalle Valo struct iwl_dma_ptr scd_bc_tbls; 521e705c121SKalle Valo struct iwl_dma_ptr kw; 522e705c121SKalle Valo 523b2a3b1c1SSara Sharon struct iwl_txq *txq_memory; 524e982bc2cSSara Sharon struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 525e982bc2cSSara Sharon unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 526e982bc2cSSara Sharon unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 527e705c121SKalle Valo 528e705c121SKalle Valo /* PCI bus related data */ 529e705c121SKalle Valo struct pci_dev *pci_dev; 530e705c121SKalle Valo void __iomem *hw_base; 531e705c121SKalle Valo 532e705c121SKalle Valo bool ucode_write_complete; 533e705c121SKalle Valo wait_queue_head_t ucode_write_waitq; 534e705c121SKalle Valo wait_queue_head_t wait_command_queue; 5354cbb8e50SLuciano Coelho wait_queue_head_t d0i3_waitq; 536e705c121SKalle Valo 53721cb3222SJohannes Berg u8 page_offs, dev_cmd_offs; 53821cb3222SJohannes Berg 539e705c121SKalle Valo u8 cmd_queue; 5409416560eSGolan Ben Ami u8 def_rx_queue; 541e705c121SKalle Valo u8 cmd_fifo; 542e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 543e705c121SKalle Valo u8 n_no_reclaim_cmds; 544e705c121SKalle Valo u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 5453cd1980bSSara Sharon u8 max_tbs; 5466983ba69SSara Sharon u16 tfd_size; 547e705c121SKalle Valo 5486c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 549e705c121SKalle Valo bool bc_table_dword; 550e705c121SKalle Valo bool scd_set_active; 55141837ca9SEmmanuel Grumbach bool sw_csum_tx; 552a6d24fadSRajat Jain bool pcie_dbg_dumped_once; 553e705c121SKalle Valo u32 rx_page_order; 554e705c121SKalle Valo 555e705c121SKalle Valo /*protect hw register */ 556e705c121SKalle Valo spinlock_t reg_lock; 557e705c121SKalle Valo bool cmd_hold_nic_awake; 558e705c121SKalle Valo bool ref_cmd_in_flight; 559e705c121SKalle Valo 560e705c121SKalle Valo dma_addr_t fw_mon_phys; 561e705c121SKalle Valo struct page *fw_mon_page; 562e705c121SKalle Valo u32 fw_mon_size; 5632e5d4a8fSHaim Dreyfuss 5642e5d4a8fSHaim Dreyfuss struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 5652e5d4a8fSHaim Dreyfuss bool msix_enabled; 566496d83caSHaim Dreyfuss u8 shared_vec_mask; 567496d83caSHaim Dreyfuss u32 alloc_vecs; 568496d83caSHaim Dreyfuss u32 def_irq; 5692e5d4a8fSHaim Dreyfuss u32 fh_init_mask; 5702e5d4a8fSHaim Dreyfuss u32 hw_init_mask; 5712e5d4a8fSHaim Dreyfuss u32 fh_mask; 5722e5d4a8fSHaim Dreyfuss u32 hw_mask; 5737c8d91ebSHaim Dreyfuss cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 57449564a80SLuca Coelho u16 tx_cmd_queue_size; 57549564a80SLuca Coelho bool in_rescan; 57649564a80SLuca Coelho bool scheduled_for_removal; 577e705c121SKalle Valo }; 578e705c121SKalle Valo 57985e5a387SJohannes Berg static inline struct iwl_trans_pcie * 58085e5a387SJohannes Berg IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 58185e5a387SJohannes Berg { 58285e5a387SJohannes Berg return (void *)trans->trans_specific; 58385e5a387SJohannes Berg } 584e705c121SKalle Valo 585ff932f61SGolan Ben Ami static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 586ff932f61SGolan Ben Ami struct msix_entry *entry) 587ff932f61SGolan Ben Ami { 588ff932f61SGolan Ben Ami /* 589ff932f61SGolan Ben Ami * Before sending the interrupt the HW disables it to prevent 590ff932f61SGolan Ben Ami * a nested interrupt. This is done by writing 1 to the corresponding 591ff932f61SGolan Ben Ami * bit in the mask register. After handling the interrupt, it should be 592ff932f61SGolan Ben Ami * re-enabled by clearing this bit. This register is defined as 593ff932f61SGolan Ben Ami * write 1 clear (W1C) register, meaning that it's being clear 594ff932f61SGolan Ben Ami * by writing 1 to the bit. 595ff932f61SGolan Ben Ami */ 596ff932f61SGolan Ben Ami iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 597ff932f61SGolan Ben Ami } 598ff932f61SGolan Ben Ami 599e705c121SKalle Valo static inline struct iwl_trans * 600e705c121SKalle Valo iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 601e705c121SKalle Valo { 602e705c121SKalle Valo return container_of((void *)trans_pcie, struct iwl_trans, 603e705c121SKalle Valo trans_specific); 604e705c121SKalle Valo } 605e705c121SKalle Valo 606e705c121SKalle Valo /* 607e705c121SKalle Valo * Convention: trans API functions: iwl_trans_pcie_XXX 608e705c121SKalle Valo * Other functions: iwl_pcie_XXX 609e705c121SKalle Valo */ 610e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 611e705c121SKalle Valo const struct pci_device_id *ent, 612e705c121SKalle Valo const struct iwl_cfg *cfg); 613e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans); 614e705c121SKalle Valo 615e705c121SKalle Valo /***************************************************** 616e705c121SKalle Valo * RX 617e705c121SKalle Valo ******************************************************/ 61889d5e833SGolan Ben Ami int _iwl_pcie_rx_init(struct iwl_trans *trans); 619e705c121SKalle Valo int iwl_pcie_rx_init(struct iwl_trans *trans); 620eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 6212e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 622e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 6232e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 6242e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 625e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans); 626e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans); 627ff932f61SGolan Ben Ami void iwl_pcie_free_rbs_pool(struct iwl_trans *trans); 628ff932f61SGolan Ben Ami void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq); 629ff932f61SGolan Ben Ami int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget); 630ff932f61SGolan Ben Ami void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 631ff932f61SGolan Ben Ami struct iwl_rxq *rxq); 63289d5e833SGolan Ben Ami int iwl_pcie_rx_alloc(struct iwl_trans *trans); 633e705c121SKalle Valo 634e705c121SKalle Valo /***************************************************** 635e705c121SKalle Valo * ICT - interrupt handling 636e705c121SKalle Valo ******************************************************/ 637e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data); 638e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans); 639e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans); 640e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans); 641e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans); 642e705c121SKalle Valo 643e705c121SKalle Valo /***************************************************** 644e705c121SKalle Valo * TX / HCMD 645e705c121SKalle Valo ******************************************************/ 646e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans); 6479b3089bdSGolan Ben Ami int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id, 6489b3089bdSGolan Ben Ami int queue_size); 649e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 650e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans); 651e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans); 652dcfbd67bSEmmanuel Grumbach bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 653e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 654e705c121SKalle Valo unsigned int wdg_timeout); 655e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 656e705c121SKalle Valo bool configure_scd); 65742db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 65842db09c1SLiad Kaufman bool shared_mode); 65938398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, 66038398efbSSara Sharon struct iwl_txq *txq); 661e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 662e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id); 663e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 664e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 66589d5e833SGolan Ben Ami void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx); 66689d5e833SGolan Ben Ami void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans, 66789d5e833SGolan Ben Ami struct iwl_txq *txq); 668e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 669e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb); 670e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 671e705c121SKalle Valo struct sk_buff_head *skbs); 672e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 67389d5e833SGolan Ben Ami void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans_pcie *trans_pcie, 67489d5e833SGolan Ben Ami struct iwl_txq *txq, u16 byte_cnt, 67589d5e833SGolan Ben Ami int num_tbs); 676e705c121SKalle Valo 677cc2f41f8SJohannes Berg static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd, 6786983ba69SSara Sharon u8 idx) 679e705c121SKalle Valo { 6806983ba69SSara Sharon if (trans->cfg->use_tfh) { 681cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 682cc2f41f8SJohannes Berg struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 6836983ba69SSara Sharon 6846983ba69SSara Sharon return le16_to_cpu(tb->tb_len); 685cc2f41f8SJohannes Berg } else { 686cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 687cc2f41f8SJohannes Berg struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 688e705c121SKalle Valo 689e705c121SKalle Valo return le16_to_cpu(tb->hi_n_len) >> 4; 690e705c121SKalle Valo } 691cc2f41f8SJohannes Berg } 692e705c121SKalle Valo 693e705c121SKalle Valo /***************************************************** 694e705c121SKalle Valo * Error handling 695e705c121SKalle Valo ******************************************************/ 696e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans); 697e705c121SKalle Valo 698e705c121SKalle Valo /***************************************************** 699e705c121SKalle Valo * Helpers 700e705c121SKalle Valo ******************************************************/ 701f16c3ebfSEmmanuel Grumbach static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 702e705c121SKalle Valo { 7032e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 704e705c121SKalle Valo 7052e5d4a8fSHaim Dreyfuss clear_bit(STATUS_INT_ENABLED, &trans->status); 7062e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 707e705c121SKalle Valo /* disable interrupts from uCode/NIC to host */ 708e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 709e705c121SKalle Valo 710e705c121SKalle Valo /* acknowledge/clear/reset any interrupts still pending 711e705c121SKalle Valo * from uCode or flow handler (Rx/Tx DMA) */ 712e705c121SKalle Valo iwl_write32(trans, CSR_INT, 0xffffffff); 713e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 7142e5d4a8fSHaim Dreyfuss } else { 7152e5d4a8fSHaim Dreyfuss /* disable all the interrupt we might use */ 7162e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 7172e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 7182e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 7192e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 7202e5d4a8fSHaim Dreyfuss } 721e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 722e705c121SKalle Valo } 723e705c121SKalle Valo 7242ee82402SGolan Ben Ami #define IWL_NUM_OF_COMPLETION_RINGS 31 7252ee82402SGolan Ben Ami #define IWL_NUM_OF_TRANSFER_RINGS 527 7262ee82402SGolan Ben Ami 7272ee82402SGolan Ben Ami static inline int iwl_pcie_get_num_sections(const struct fw_img *fw, 7282ee82402SGolan Ben Ami int start) 7292ee82402SGolan Ben Ami { 7302ee82402SGolan Ben Ami int i = 0; 7312ee82402SGolan Ben Ami 7322ee82402SGolan Ben Ami while (start < fw->num_sec && 7332ee82402SGolan Ben Ami fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && 7342ee82402SGolan Ben Ami fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { 7352ee82402SGolan Ben Ami start++; 7362ee82402SGolan Ben Ami i++; 7372ee82402SGolan Ben Ami } 7382ee82402SGolan Ben Ami 7392ee82402SGolan Ben Ami return i; 7402ee82402SGolan Ben Ami } 7412ee82402SGolan Ben Ami 7422ee82402SGolan Ben Ami static inline int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans, 7432ee82402SGolan Ben Ami const struct fw_desc *sec, 7442ee82402SGolan Ben Ami struct iwl_dram_data *dram) 7452ee82402SGolan Ben Ami { 7462ee82402SGolan Ben Ami dram->block = dma_alloc_coherent(trans->dev, sec->len, 7472ee82402SGolan Ben Ami &dram->physical, 7482ee82402SGolan Ben Ami GFP_KERNEL); 7492ee82402SGolan Ben Ami if (!dram->block) 7502ee82402SGolan Ben Ami return -ENOMEM; 7512ee82402SGolan Ben Ami 7522ee82402SGolan Ben Ami dram->size = sec->len; 7532ee82402SGolan Ben Ami memcpy(dram->block, sec->data, sec->len); 7542ee82402SGolan Ben Ami 7552ee82402SGolan Ben Ami return 0; 7562ee82402SGolan Ben Ami } 7572ee82402SGolan Ben Ami 7582ee82402SGolan Ben Ami static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans) 7592ee82402SGolan Ben Ami { 7602ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 7612ee82402SGolan Ben Ami struct iwl_self_init_dram *dram = &trans_pcie->init_dram; 7622ee82402SGolan Ben Ami int i; 7632ee82402SGolan Ben Ami 7642ee82402SGolan Ben Ami if (!dram->fw) { 7652ee82402SGolan Ben Ami WARN_ON(dram->fw_cnt); 7662ee82402SGolan Ben Ami return; 7672ee82402SGolan Ben Ami } 7682ee82402SGolan Ben Ami 7692ee82402SGolan Ben Ami for (i = 0; i < dram->fw_cnt; i++) 7702ee82402SGolan Ben Ami dma_free_coherent(trans->dev, dram->fw[i].size, 7712ee82402SGolan Ben Ami dram->fw[i].block, dram->fw[i].physical); 7722ee82402SGolan Ben Ami 7732ee82402SGolan Ben Ami kfree(dram->fw); 7742ee82402SGolan Ben Ami dram->fw_cnt = 0; 7752ee82402SGolan Ben Ami dram->fw = NULL; 7762ee82402SGolan Ben Ami } 7772ee82402SGolan Ben Ami 778f16c3ebfSEmmanuel Grumbach static inline void iwl_disable_interrupts(struct iwl_trans *trans) 779f16c3ebfSEmmanuel Grumbach { 780f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 781f16c3ebfSEmmanuel Grumbach 782f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 783f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 784f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 785f16c3ebfSEmmanuel Grumbach } 786f16c3ebfSEmmanuel Grumbach 787f16c3ebfSEmmanuel Grumbach static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 788e705c121SKalle Valo { 789e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 790e705c121SKalle Valo 791e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 792e705c121SKalle Valo set_bit(STATUS_INT_ENABLED, &trans->status); 7932e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 794e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 795e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 7962e5d4a8fSHaim Dreyfuss } else { 7972e5d4a8fSHaim Dreyfuss /* 7982e5d4a8fSHaim Dreyfuss * fh/hw_mask keeps all the unmasked causes. 7992e5d4a8fSHaim Dreyfuss * Unlike msi, in msix cause is enabled when it is unset. 8002e5d4a8fSHaim Dreyfuss */ 8012e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 8022e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 8032e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 8042e5d4a8fSHaim Dreyfuss ~trans_pcie->fh_mask); 8052e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 8062e5d4a8fSHaim Dreyfuss ~trans_pcie->hw_mask); 8072e5d4a8fSHaim Dreyfuss } 8082e5d4a8fSHaim Dreyfuss } 8092e5d4a8fSHaim Dreyfuss 810f16c3ebfSEmmanuel Grumbach static inline void iwl_enable_interrupts(struct iwl_trans *trans) 811f16c3ebfSEmmanuel Grumbach { 812f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 813f16c3ebfSEmmanuel Grumbach 814f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 815f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 816f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 817f16c3ebfSEmmanuel Grumbach } 8182e5d4a8fSHaim Dreyfuss static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 8192e5d4a8fSHaim Dreyfuss { 8202e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 8212e5d4a8fSHaim Dreyfuss 8222e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 8232e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = msk; 8242e5d4a8fSHaim Dreyfuss } 8252e5d4a8fSHaim Dreyfuss 8262e5d4a8fSHaim Dreyfuss static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 8272e5d4a8fSHaim Dreyfuss { 8282e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 8292e5d4a8fSHaim Dreyfuss 8302e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 8312e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = msk; 832e705c121SKalle Valo } 833e705c121SKalle Valo 834a6bd005fSEmmanuel Grumbach static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 835a6bd005fSEmmanuel Grumbach { 836a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 837a6bd005fSEmmanuel Grumbach 838a6bd005fSEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 8392e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 840a6bd005fSEmmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 841a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 8422e5d4a8fSHaim Dreyfuss } else { 8432e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 8442e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 8452e5d4a8fSHaim Dreyfuss iwl_enable_fh_int_msk_msix(trans, 8462e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 8472e5d4a8fSHaim Dreyfuss } 848a6bd005fSEmmanuel Grumbach } 849a6bd005fSEmmanuel Grumbach 8507b3e42eaSGolan Ben Ami static inline u16 iwl_pcie_get_cmd_index(const struct iwl_txq *q, u32 index) 8514ecab561SEmmanuel Grumbach { 8524ecab561SEmmanuel Grumbach return index & (q->n_window - 1); 8534ecab561SEmmanuel Grumbach } 8544ecab561SEmmanuel Grumbach 855943309d4SEmmanuel Grumbach static inline void *iwl_pcie_get_tfd(struct iwl_trans *trans, 856ab6c6445SSara Sharon struct iwl_txq *txq, int idx) 857ab6c6445SSara Sharon { 858943309d4SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 859943309d4SEmmanuel Grumbach 860943309d4SEmmanuel Grumbach if (trans->cfg->use_tfh) 861943309d4SEmmanuel Grumbach idx = iwl_pcie_get_cmd_index(txq, idx); 862943309d4SEmmanuel Grumbach 863943309d4SEmmanuel Grumbach return txq->tfds + trans_pcie->tfd_size * idx; 864ab6c6445SSara Sharon } 865ab6c6445SSara Sharon 866ff932f61SGolan Ben Ami static inline const char *queue_name(struct device *dev, 867ff932f61SGolan Ben Ami struct iwl_trans_pcie *trans_p, int i) 868ff932f61SGolan Ben Ami { 869ff932f61SGolan Ben Ami if (trans_p->shared_vec_mask) { 870ff932f61SGolan Ben Ami int vec = trans_p->shared_vec_mask & 871ff932f61SGolan Ben Ami IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 872ff932f61SGolan Ben Ami 873ff932f61SGolan Ben Ami if (i == 0) 874ff932f61SGolan Ben Ami return DRV_NAME ": shared IRQ"; 875ff932f61SGolan Ben Ami 876ff932f61SGolan Ben Ami return devm_kasprintf(dev, GFP_KERNEL, 877ff932f61SGolan Ben Ami DRV_NAME ": queue %d", i + vec); 878ff932f61SGolan Ben Ami } 879ff932f61SGolan Ben Ami if (i == 0) 880ff932f61SGolan Ben Ami return DRV_NAME ": default queue"; 881ff932f61SGolan Ben Ami 882ff932f61SGolan Ben Ami if (i == trans_p->alloc_vecs - 1) 883ff932f61SGolan Ben Ami return DRV_NAME ": exception"; 884ff932f61SGolan Ben Ami 885ff932f61SGolan Ben Ami return devm_kasprintf(dev, GFP_KERNEL, 886ff932f61SGolan Ben Ami DRV_NAME ": queue %d", i); 887ff932f61SGolan Ben Ami } 888ff932f61SGolan Ben Ami 889e705c121SKalle Valo static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 890e705c121SKalle Valo { 891e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 892e705c121SKalle Valo 893e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 8942e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 895e705c121SKalle Valo trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 896e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 8972e5d4a8fSHaim Dreyfuss } else { 8982e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 8992e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 9002e5d4a8fSHaim Dreyfuss iwl_enable_hw_int_msk_msix(trans, 9012e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_RF_KILL); 9022e5d4a8fSHaim Dreyfuss } 903ae5bb2a6SJohannes Berg 904ae5bb2a6SJohannes Berg if (trans->cfg->device_family == IWL_DEVICE_FAMILY_9000) { 905ae5bb2a6SJohannes Berg /* 906ae5bb2a6SJohannes Berg * On 9000-series devices this bit isn't enabled by default, so 907ae5bb2a6SJohannes Berg * when we power down the device we need set the bit to allow it 908ae5bb2a6SJohannes Berg * to wake up the PCI-E bus for RF-kill interrupts. 909ae5bb2a6SJohannes Berg */ 910ae5bb2a6SJohannes Berg iwl_set_bit(trans, CSR_GP_CNTRL, 911ae5bb2a6SJohannes Berg CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 912ae5bb2a6SJohannes Berg } 913e705c121SKalle Valo } 914e705c121SKalle Valo 915fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans); 916fa4de7f7SJohannes Berg 917e705c121SKalle Valo static inline void iwl_wake_queue(struct iwl_trans *trans, 918e705c121SKalle Valo struct iwl_txq *txq) 919e705c121SKalle Valo { 920e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 921e705c121SKalle Valo 922bb98ecd4SSara Sharon if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) { 923bb98ecd4SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id); 924bb98ecd4SSara Sharon iwl_op_mode_queue_not_full(trans->op_mode, txq->id); 925e705c121SKalle Valo } 926e705c121SKalle Valo } 927e705c121SKalle Valo 928e705c121SKalle Valo static inline void iwl_stop_queue(struct iwl_trans *trans, 929e705c121SKalle Valo struct iwl_txq *txq) 930e705c121SKalle Valo { 931e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 932e705c121SKalle Valo 933bb98ecd4SSara Sharon if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) { 934bb98ecd4SSara Sharon iwl_op_mode_queue_full(trans->op_mode, txq->id); 935bb98ecd4SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id); 936e705c121SKalle Valo } else 937e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 938bb98ecd4SSara Sharon txq->id); 939e705c121SKalle Valo } 940e705c121SKalle Valo 941bb98ecd4SSara Sharon static inline bool iwl_queue_used(const struct iwl_txq *q, int i) 942e705c121SKalle Valo { 943f5955a6cSGolan Ben Ami int index = iwl_pcie_get_cmd_index(q, i); 944f5955a6cSGolan Ben Ami int r = iwl_pcie_get_cmd_index(q, q->read_ptr); 945f5955a6cSGolan Ben Ami int w = iwl_pcie_get_cmd_index(q, q->write_ptr); 946f5955a6cSGolan Ben Ami 947f5955a6cSGolan Ben Ami return w >= r ? 948f5955a6cSGolan Ben Ami (index >= r && index < w) : 949f5955a6cSGolan Ben Ami !(index < r && index >= w); 950e705c121SKalle Valo } 951e705c121SKalle Valo 952e705c121SKalle Valo static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 953e705c121SKalle Valo { 954fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 955fa4de7f7SJohannes Berg 956fa4de7f7SJohannes Berg lockdep_assert_held(&trans_pcie->mutex); 957fa4de7f7SJohannes Berg 958fa4de7f7SJohannes Berg if (trans_pcie->debug_rfkill) 959fa4de7f7SJohannes Berg return true; 96023aeea94SJohannes Berg 961e705c121SKalle Valo return !(iwl_read32(trans, CSR_GP_CNTRL) & 962e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 963e705c121SKalle Valo } 964e705c121SKalle Valo 965e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 966e705c121SKalle Valo u32 reg, u32 mask, u32 value) 967e705c121SKalle Valo { 968e705c121SKalle Valo u32 v; 969e705c121SKalle Valo 970e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 971e705c121SKalle Valo WARN_ON_ONCE(value & ~mask); 972e705c121SKalle Valo #endif 973e705c121SKalle Valo 974e705c121SKalle Valo v = iwl_read32(trans, reg); 975e705c121SKalle Valo v &= ~mask; 976e705c121SKalle Valo v |= value; 977e705c121SKalle Valo iwl_write32(trans, reg, v); 978e705c121SKalle Valo } 979e705c121SKalle Valo 980e705c121SKalle Valo static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 981e705c121SKalle Valo u32 reg, u32 mask) 982e705c121SKalle Valo { 983e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 984e705c121SKalle Valo } 985e705c121SKalle Valo 986e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 987e705c121SKalle Valo u32 reg, u32 mask) 988e705c121SKalle Valo { 989e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 990e705c121SKalle Valo } 991e705c121SKalle Valo 992e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 9934290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans); 994e705c121SKalle Valo 995f8a1edb7SJohannes Berg #ifdef CONFIG_IWLWIFI_DEBUGFS 996f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 997f8a1edb7SJohannes Berg #else 998f8a1edb7SJohannes Berg static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 999f8a1edb7SJohannes Berg { 1000f8a1edb7SJohannes Berg return 0; 1001f8a1edb7SJohannes Berg } 1002f8a1edb7SJohannes Berg #endif 1003f8a1edb7SJohannes Berg 10044cbb8e50SLuciano Coelho int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans); 10054cbb8e50SLuciano Coelho int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans); 10064cbb8e50SLuciano Coelho 10071316d595SSara Sharon void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable); 10081316d595SSara Sharon 100910a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data); 101010a54d81SLuca Coelho 1011eda50cdeSSara Sharon /* common functions that are used by gen2 transport */ 1012eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans); 1013eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 1014eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 10159ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans); 1016326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1017326477e4SJohannes Berg bool was_in_rfkill); 10186b35ff91SSara Sharon void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq); 10197b3e42eaSGolan Ben Ami int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q); 1020e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans); 102177c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 102213a3a390SSara Sharon int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 1023b8e8d7ceSSara Sharon int slots_num, bool cmd_queue); 102413a3a390SSara Sharon int iwl_pcie_txq_alloc(struct iwl_trans *trans, 1025b8e8d7ceSSara Sharon struct iwl_txq *txq, int slots_num, bool cmd_queue); 102613a3a390SSara Sharon int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 102713a3a390SSara Sharon struct iwl_dma_ptr *ptr, size_t size); 102813a3a390SSara Sharon void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr); 1029c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans); 10309bb3d5a0SEmmanuel Grumbach void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 10319bb3d5a0SEmmanuel Grumbach struct sk_buff *skb); 10326ffe5de3SSara Sharon #ifdef CONFIG_INET 10336ffe5de3SSara Sharon struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len); 10346ffe5de3SSara Sharon #endif 1035eda50cdeSSara Sharon 10369f358c17SGolan Ben Ami /* common functions that are used by gen3 transport */ 10379f358c17SGolan Ben Ami void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power); 10389f358c17SGolan Ben Ami 1039eda50cdeSSara Sharon /* transport gen 2 exported functions */ 1040eda50cdeSSara Sharon int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 1041eda50cdeSSara Sharon const struct fw_img *fw, bool run_in_rfkill); 1042eda50cdeSSara Sharon void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr); 10436b35ff91SSara Sharon int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans, 10446b35ff91SSara Sharon struct iwl_tx_queue_cfg_cmd *cmd, 10455369774cSSara Sharon int cmd_id, int size, 10466b35ff91SSara Sharon unsigned int timeout); 10476b35ff91SSara Sharon void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue); 1048ab6c6445SSara Sharon int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb, 1049ab6c6445SSara Sharon struct iwl_device_cmd *dev_cmd, int txq_id); 1050ca60da2eSSara Sharon int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 1051ca60da2eSSara Sharon struct iwl_host_cmd *cmd); 105277c09bc8SSara Sharon void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, 105377c09bc8SSara Sharon bool low_power); 105477c09bc8SSara Sharon void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power); 105513a3a390SSara Sharon void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id); 105613a3a390SSara Sharon void iwl_pcie_gen2_tx_free(struct iwl_trans *trans); 105713a3a390SSara Sharon void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans); 1058e705c121SKalle Valo #endif /* __iwl_trans_int_pcie_h__ */ 1059