1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 4e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 61b493e30SGolan Ben Ami * Copyright(c) 2018 Intel Corporation 7e705c121SKalle Valo * 8e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 9e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 10e705c121SKalle Valo * 11e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 12e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 13e705c121SKalle Valo * published by the Free Software Foundation. 14e705c121SKalle Valo * 15e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 16e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18e705c121SKalle Valo * more details. 19e705c121SKalle Valo * 20e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 21e705c121SKalle Valo * file called LICENSE. 22e705c121SKalle Valo * 23e705c121SKalle Valo * Contact Information: 24cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 25e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26e705c121SKalle Valo * 27e705c121SKalle Valo *****************************************************************************/ 28e705c121SKalle Valo #ifndef __iwl_trans_int_pcie_h__ 29e705c121SKalle Valo #define __iwl_trans_int_pcie_h__ 30e705c121SKalle Valo 31e705c121SKalle Valo #include <linux/spinlock.h> 32e705c121SKalle Valo #include <linux/interrupt.h> 33e705c121SKalle Valo #include <linux/skbuff.h> 34e705c121SKalle Valo #include <linux/wait.h> 35e705c121SKalle Valo #include <linux/pci.h> 36e705c121SKalle Valo #include <linux/timer.h> 377c8d91ebSHaim Dreyfuss #include <linux/cpu.h> 38e705c121SKalle Valo 39e705c121SKalle Valo #include "iwl-fh.h" 40e705c121SKalle Valo #include "iwl-csr.h" 41e705c121SKalle Valo #include "iwl-trans.h" 42e705c121SKalle Valo #include "iwl-debug.h" 43e705c121SKalle Valo #include "iwl-io.h" 44e705c121SKalle Valo #include "iwl-op-mode.h" 45ff932f61SGolan Ben Ami #include "iwl-drv.h" 46e705c121SKalle Valo 47e705c121SKalle Valo /* We need 2 entries for the TX command and header, and another one might 48e705c121SKalle Valo * be needed for potential data in the SKB's head. The remaining ones can 49e705c121SKalle Valo * be used for frags. 50e705c121SKalle Valo */ 513cd1980bSSara Sharon #define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3) 52e705c121SKalle Valo 53e705c121SKalle Valo /* 54e705c121SKalle Valo * RX related structures and functions 55e705c121SKalle Valo */ 56e705c121SKalle Valo #define RX_NUM_QUEUES 1 57e705c121SKalle Valo #define RX_POST_REQ_ALLOC 2 58e705c121SKalle Valo #define RX_CLAIM_REQ_ALLOC 8 5978485054SSara Sharon #define RX_PENDING_WATERMARK 16 601b493e30SGolan Ben Ami #define FIRST_RX_QUEUE 512 61e705c121SKalle Valo 62e705c121SKalle Valo struct iwl_host_cmd; 63e705c121SKalle Valo 64e705c121SKalle Valo /*This file includes the declaration that are internal to the 65e705c121SKalle Valo * trans_pcie layer */ 66e705c121SKalle Valo 6796a6497bSSara Sharon /** 6896a6497bSSara Sharon * struct iwl_rx_mem_buffer 6996a6497bSSara Sharon * @page_dma: bus address of rxb page 7096a6497bSSara Sharon * @page: driver's pointer to the rxb page 71b1753c62SSara Sharon * @invalid: rxb is in driver ownership - not owned by HW 7296a6497bSSara Sharon * @vid: index of this rxb in the global table 730307c839SGolan Ben Ami * @size: size used from the buffer 7496a6497bSSara Sharon */ 75e705c121SKalle Valo struct iwl_rx_mem_buffer { 76e705c121SKalle Valo dma_addr_t page_dma; 77e705c121SKalle Valo struct page *page; 7896a6497bSSara Sharon u16 vid; 79b1753c62SSara Sharon bool invalid; 80e705c121SKalle Valo struct list_head list; 810307c839SGolan Ben Ami u32 size; 82e705c121SKalle Valo }; 83e705c121SKalle Valo 84e705c121SKalle Valo /** 85e705c121SKalle Valo * struct isr_statistics - interrupt statistics 86e705c121SKalle Valo * 87e705c121SKalle Valo */ 88e705c121SKalle Valo struct isr_statistics { 89e705c121SKalle Valo u32 hw; 90e705c121SKalle Valo u32 sw; 91e705c121SKalle Valo u32 err_code; 92e705c121SKalle Valo u32 sch; 93e705c121SKalle Valo u32 alive; 94e705c121SKalle Valo u32 rfkill; 95e705c121SKalle Valo u32 ctkill; 96e705c121SKalle Valo u32 wakeup; 97e705c121SKalle Valo u32 rx; 98e705c121SKalle Valo u32 tx; 99e705c121SKalle Valo u32 unhandled; 100e705c121SKalle Valo }; 101e705c121SKalle Valo 1020307c839SGolan Ben Ami #define IWL_RX_TD_TYPE_MSK 0xff000000 1030307c839SGolan Ben Ami #define IWL_RX_TD_SIZE_MSK 0x00ffffff 1040307c839SGolan Ben Ami #define IWL_RX_TD_SIZE_2K BIT(11) 1050307c839SGolan Ben Ami #define IWL_RX_TD_TYPE 0 106cf495496SGolan Ben Ami 107cf495496SGolan Ben Ami /** 108cf495496SGolan Ben Ami * struct iwl_rx_transfer_desc - transfer descriptor 109cf495496SGolan Ben Ami * @type_n_size: buffer type (bit 0: external buff valid, 110cf495496SGolan Ben Ami * bit 1: optional footer valid, bit 2-7: reserved) 111cf495496SGolan Ben Ami * and buffer size 112cf495496SGolan Ben Ami * @addr: ptr to free buffer start address 113cf495496SGolan Ben Ami * @rbid: unique tag of the buffer 114cf495496SGolan Ben Ami * @reserved: reserved 115cf495496SGolan Ben Ami */ 116cf495496SGolan Ben Ami struct iwl_rx_transfer_desc { 117cf495496SGolan Ben Ami __le32 type_n_size; 118cf495496SGolan Ben Ami __le64 addr; 119cf495496SGolan Ben Ami __le16 rbid; 120cf495496SGolan Ben Ami __le16 reserved; 121cf495496SGolan Ben Ami } __packed; 122cf495496SGolan Ben Ami 123cf495496SGolan Ben Ami #define IWL_RX_CD_SIZE 0xffffff00 124cf495496SGolan Ben Ami 125cf495496SGolan Ben Ami /** 126cf495496SGolan Ben Ami * struct iwl_rx_completion_desc - completion descriptor 127cf495496SGolan Ben Ami * @type: buffer type (bit 0: external buff valid, 128cf495496SGolan Ben Ami * bit 1: optional footer valid, bit 2-7: reserved) 129cf495496SGolan Ben Ami * @status: status of the completion 130cf495496SGolan Ben Ami * @reserved1: reserved 131cf495496SGolan Ben Ami * @rbid: unique tag of the received buffer 132cf495496SGolan Ben Ami * @size: buffer size, masked by IWL_RX_CD_SIZE 133cf495496SGolan Ben Ami * @reserved2: reserved 134cf495496SGolan Ben Ami */ 135cf495496SGolan Ben Ami struct iwl_rx_completion_desc { 136cf495496SGolan Ben Ami u8 type; 137cf495496SGolan Ben Ami u8 status; 138cf495496SGolan Ben Ami __le16 reserved1; 139cf495496SGolan Ben Ami __le16 rbid; 140cf495496SGolan Ben Ami __le32 size; 141cf495496SGolan Ben Ami u8 reserved2[22]; 142cf495496SGolan Ben Ami } __packed; 143cf495496SGolan Ben Ami 144e705c121SKalle Valo /** 145e705c121SKalle Valo * struct iwl_rxq - Rx queue 14696a6497bSSara Sharon * @id: queue index 14796a6497bSSara Sharon * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 14896a6497bSSara Sharon * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 1490307c839SGolan Ben Ami * In 22560 devices it is a pointer to a list of iwl_rx_transfer_desc's 150e705c121SKalle Valo * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 15196a6497bSSara Sharon * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd) 15296a6497bSSara Sharon * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd) 1531b493e30SGolan Ben Ami * @tr_tail: driver's pointer to the transmission ring tail buffer 1541b493e30SGolan Ben Ami * @tr_tail_dma: physical address of the buffer for the transmission ring tail 1551b493e30SGolan Ben Ami * @cr_tail: driver's pointer to the completion ring tail buffer 1561b493e30SGolan Ben Ami * @cr_tail_dma: physical address of the buffer for the completion ring tail 157e705c121SKalle Valo * @read: Shared index to newest available Rx buffer 158e705c121SKalle Valo * @write: Shared index to oldest written Rx packet 159e705c121SKalle Valo * @free_count: Number of pre-allocated buffers in rx_free 160e705c121SKalle Valo * @used_count: Number of RBDs handled to allocator to use for allocation 161e705c121SKalle Valo * @write_actual: 162e705c121SKalle Valo * @rx_free: list of RBDs with allocated RB ready for use 163e705c121SKalle Valo * @rx_used: list of RBDs with no RB attached 164e705c121SKalle Valo * @need_update: flag to indicate we need to update read/write index 165e705c121SKalle Valo * @rb_stts: driver's pointer to receive buffer status 166e705c121SKalle Valo * @rb_stts_dma: bus address of receive buffer status 167e705c121SKalle Valo * @lock: 16896a6497bSSara Sharon * @queue: actual rx queue. Not used for multi-rx queue. 169e705c121SKalle Valo * 170e705c121SKalle Valo * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 171e705c121SKalle Valo */ 172e705c121SKalle Valo struct iwl_rxq { 17396a6497bSSara Sharon int id; 17496a6497bSSara Sharon void *bd; 175e705c121SKalle Valo dma_addr_t bd_dma; 176b2a58c97SSara Sharon union { 1770307c839SGolan Ben Ami void *used_bd; 178b2a58c97SSara Sharon __le32 *bd_32; 179b2a58c97SSara Sharon struct iwl_rx_completion_desc *cd; 180b2a58c97SSara Sharon }; 18196a6497bSSara Sharon dma_addr_t used_bd_dma; 1821b493e30SGolan Ben Ami __le16 *tr_tail; 1831b493e30SGolan Ben Ami dma_addr_t tr_tail_dma; 1841b493e30SGolan Ben Ami __le16 *cr_tail; 1851b493e30SGolan Ben Ami dma_addr_t cr_tail_dma; 186e705c121SKalle Valo u32 read; 187e705c121SKalle Valo u32 write; 188e705c121SKalle Valo u32 free_count; 189e705c121SKalle Valo u32 used_count; 190e705c121SKalle Valo u32 write_actual; 19196a6497bSSara Sharon u32 queue_size; 192e705c121SKalle Valo struct list_head rx_free; 193e705c121SKalle Valo struct list_head rx_used; 194e705c121SKalle Valo bool need_update; 1950307c839SGolan Ben Ami void *rb_stts; 196e705c121SKalle Valo dma_addr_t rb_stts_dma; 197e705c121SKalle Valo spinlock_t lock; 198bce97731SSara Sharon struct napi_struct napi; 199e705c121SKalle Valo struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 200e705c121SKalle Valo }; 201e705c121SKalle Valo 202e705c121SKalle Valo /** 203e705c121SKalle Valo * struct iwl_rb_allocator - Rx allocator 204e705c121SKalle Valo * @req_pending: number of requests the allcator had not processed yet 205e705c121SKalle Valo * @req_ready: number of requests honored and ready for claiming 206e705c121SKalle Valo * @rbd_allocated: RBDs with pages allocated and ready to be handled to 207e705c121SKalle Valo * the queue. This is a list of &struct iwl_rx_mem_buffer 208e705c121SKalle Valo * @rbd_empty: RBDs with no page attached for allocator use. This is a list 209e705c121SKalle Valo * of &struct iwl_rx_mem_buffer 210e705c121SKalle Valo * @lock: protects the rbd_allocated and rbd_empty lists 211e705c121SKalle Valo * @alloc_wq: work queue for background calls 212e705c121SKalle Valo * @rx_alloc: work struct for background calls 213e705c121SKalle Valo */ 214e705c121SKalle Valo struct iwl_rb_allocator { 215e705c121SKalle Valo atomic_t req_pending; 216e705c121SKalle Valo atomic_t req_ready; 217e705c121SKalle Valo struct list_head rbd_allocated; 218e705c121SKalle Valo struct list_head rbd_empty; 219e705c121SKalle Valo spinlock_t lock; 220e705c121SKalle Valo struct workqueue_struct *alloc_wq; 221e705c121SKalle Valo struct work_struct rx_alloc; 222e705c121SKalle Valo }; 223e705c121SKalle Valo 224e705c121SKalle Valo struct iwl_dma_ptr { 225e705c121SKalle Valo dma_addr_t dma; 226e705c121SKalle Valo void *addr; 227e705c121SKalle Valo size_t size; 228e705c121SKalle Valo }; 229e705c121SKalle Valo 230e705c121SKalle Valo /** 231e705c121SKalle Valo * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 232e705c121SKalle Valo * @index -- current index 233e705c121SKalle Valo */ 2347b3e42eaSGolan Ben Ami static inline int iwl_queue_inc_wrap(struct iwl_trans *trans, int index) 235e705c121SKalle Valo { 2367b3e42eaSGolan Ben Ami return ++index & (trans->cfg->base_params->max_tfd_queue_size - 1); 237e705c121SKalle Valo } 238e705c121SKalle Valo 239e705c121SKalle Valo /** 2400307c839SGolan Ben Ami * iwl_get_closed_rb_stts - get closed rb stts from different structs 2410307c839SGolan Ben Ami * @rxq - the rxq to get the rb stts from 2420307c839SGolan Ben Ami */ 2430307c839SGolan Ben Ami static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans, 2440307c839SGolan Ben Ami struct iwl_rxq *rxq) 2450307c839SGolan Ben Ami { 2460307c839SGolan Ben Ami if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 2470307c839SGolan Ben Ami __le16 *rb_stts = rxq->rb_stts; 2480307c839SGolan Ben Ami 2490307c839SGolan Ben Ami return READ_ONCE(*rb_stts); 2500307c839SGolan Ben Ami } else { 2510307c839SGolan Ben Ami struct iwl_rb_status *rb_stts = rxq->rb_stts; 2520307c839SGolan Ben Ami 2530307c839SGolan Ben Ami return READ_ONCE(rb_stts->closed_rb_num); 2540307c839SGolan Ben Ami } 2550307c839SGolan Ben Ami } 2560307c839SGolan Ben Ami 2570307c839SGolan Ben Ami /** 258e705c121SKalle Valo * iwl_queue_dec_wrap - decrement queue index, wrap back to end 259e705c121SKalle Valo * @index -- current index 260e705c121SKalle Valo */ 2617b3e42eaSGolan Ben Ami static inline int iwl_queue_dec_wrap(struct iwl_trans *trans, int index) 262e705c121SKalle Valo { 2637b3e42eaSGolan Ben Ami return --index & (trans->cfg->base_params->max_tfd_queue_size - 1); 264e705c121SKalle Valo } 265e705c121SKalle Valo 266e705c121SKalle Valo struct iwl_cmd_meta { 267e705c121SKalle Valo /* only for SYNC commands, iff the reply skb is wanted */ 268e705c121SKalle Valo struct iwl_host_cmd *source; 269e705c121SKalle Valo u32 flags; 2703cd1980bSSara Sharon u32 tbs; 271e705c121SKalle Valo }; 272e705c121SKalle Valo 273e705c121SKalle Valo 274e705c121SKalle Valo #define TFD_TX_CMD_SLOTS 256 275e705c121SKalle Valo #define TFD_CMD_SLOTS 32 276e705c121SKalle Valo 277e705c121SKalle Valo /* 2788de437c7SSara Sharon * The FH will write back to the first TB only, so we need to copy some data 2798de437c7SSara Sharon * into the buffer regardless of whether it should be mapped or not. 2808de437c7SSara Sharon * This indicates how big the first TB must be to include the scratch buffer 2818de437c7SSara Sharon * and the assigned PN. 282b97277ccSSara Sharon * Since PN location is 8 bytes at offset 12, it's 20 now. 2838de437c7SSara Sharon * If we make it bigger then allocations will be bigger and copy slower, so 2848de437c7SSara Sharon * that's probably not useful. 285e705c121SKalle Valo */ 286b97277ccSSara Sharon #define IWL_FIRST_TB_SIZE 20 2878de437c7SSara Sharon #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 288e705c121SKalle Valo 289e705c121SKalle Valo struct iwl_pcie_txq_entry { 290e705c121SKalle Valo struct iwl_device_cmd *cmd; 291e705c121SKalle Valo struct sk_buff *skb; 292e705c121SKalle Valo /* buffer to free after command completes */ 293e705c121SKalle Valo const void *free_buf; 294e705c121SKalle Valo struct iwl_cmd_meta meta; 295e705c121SKalle Valo }; 296e705c121SKalle Valo 2978de437c7SSara Sharon struct iwl_pcie_first_tb_buf { 2988de437c7SSara Sharon u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 299e705c121SKalle Valo }; 300e705c121SKalle Valo 301e705c121SKalle Valo /** 302e705c121SKalle Valo * struct iwl_txq - Tx Queue for DMA 303e705c121SKalle Valo * @q: generic Rx/Tx queue descriptor 304e705c121SKalle Valo * @tfds: transmit frame descriptors (DMA memory) 3058de437c7SSara Sharon * @first_tb_bufs: start of command headers, including scratch buffers, for 306e705c121SKalle Valo * the writeback -- this is DMA memory and an array holding one buffer 307e705c121SKalle Valo * for each command on the queue 3088de437c7SSara Sharon * @first_tb_dma: DMA address for the first_tb_bufs start 309e705c121SKalle Valo * @entries: transmit entries (driver state) 310e705c121SKalle Valo * @lock: queue lock 311e705c121SKalle Valo * @stuck_timer: timer that fires if queue gets stuck 312e705c121SKalle Valo * @trans_pcie: pointer back to transport (for timer) 313e705c121SKalle Valo * @need_update: indicates need to update read/write index 314e705c121SKalle Valo * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 315e705c121SKalle Valo * @wd_timeout: queue watchdog timeout (jiffies) - per queue 316e705c121SKalle Valo * @frozen: tx stuck queue timer is frozen 317e705c121SKalle Valo * @frozen_expiry_remainder: remember how long until the timer fires 31813a3a390SSara Sharon * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 319bb98ecd4SSara Sharon * @write_ptr: 1-st empty entry (index) host_w 320bb98ecd4SSara Sharon * @read_ptr: last used entry (index) host_r 321bb98ecd4SSara Sharon * @dma_addr: physical addr for BD's 322bb98ecd4SSara Sharon * @n_window: safe queue window 323bb98ecd4SSara Sharon * @id: queue id 324bb98ecd4SSara Sharon * @low_mark: low watermark, resume queue if free space more than this 325bb98ecd4SSara Sharon * @high_mark: high watermark, stop queue if free space less than this 326e705c121SKalle Valo * 327e705c121SKalle Valo * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 328e705c121SKalle Valo * descriptors) and required locking structures. 329bb98ecd4SSara Sharon * 330bb98ecd4SSara Sharon * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 331bb98ecd4SSara Sharon * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 332bb98ecd4SSara Sharon * there might be HW changes in the future). For the normal TX 333bb98ecd4SSara Sharon * queues, n_window, which is the size of the software queue data 334bb98ecd4SSara Sharon * is also 256; however, for the command queue, n_window is only 335bb98ecd4SSara Sharon * 32 since we don't need so many commands pending. Since the HW 336bb98ecd4SSara Sharon * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 337bb98ecd4SSara Sharon * This means that we end up with the following: 338bb98ecd4SSara Sharon * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 339bb98ecd4SSara Sharon * SW entries: | 0 | ... | 31 | 340bb98ecd4SSara Sharon * where N is a number between 0 and 7. This means that the SW 341bb98ecd4SSara Sharon * data is a window overlayed over the HW queue. 342e705c121SKalle Valo */ 343e705c121SKalle Valo struct iwl_txq { 3446983ba69SSara Sharon void *tfds; 3458de437c7SSara Sharon struct iwl_pcie_first_tb_buf *first_tb_bufs; 3468de437c7SSara Sharon dma_addr_t first_tb_dma; 347e705c121SKalle Valo struct iwl_pcie_txq_entry *entries; 348e705c121SKalle Valo spinlock_t lock; 349e705c121SKalle Valo unsigned long frozen_expiry_remainder; 350e705c121SKalle Valo struct timer_list stuck_timer; 351e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 352e705c121SKalle Valo bool need_update; 353e705c121SKalle Valo bool frozen; 354e705c121SKalle Valo bool ampdu; 35504fa3e68SEmmanuel Grumbach int block; 356e705c121SKalle Valo unsigned long wd_timeout; 3573955525dSEmmanuel Grumbach struct sk_buff_head overflow_q; 35813a3a390SSara Sharon struct iwl_dma_ptr bc_tbl; 359bb98ecd4SSara Sharon 360bb98ecd4SSara Sharon int write_ptr; 361bb98ecd4SSara Sharon int read_ptr; 362bb98ecd4SSara Sharon dma_addr_t dma_addr; 363bb98ecd4SSara Sharon int n_window; 364bb98ecd4SSara Sharon u32 id; 365bb98ecd4SSara Sharon int low_mark; 366bb98ecd4SSara Sharon int high_mark; 367e705c121SKalle Valo }; 368e705c121SKalle Valo 369e705c121SKalle Valo static inline dma_addr_t 3708de437c7SSara Sharon iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx) 371e705c121SKalle Valo { 3728de437c7SSara Sharon return txq->first_tb_dma + 3738de437c7SSara Sharon sizeof(struct iwl_pcie_first_tb_buf) * idx; 374e705c121SKalle Valo } 375e705c121SKalle Valo 3766eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page { 3776eb5e529SEmmanuel Grumbach struct page *page; 3786eb5e529SEmmanuel Grumbach u8 *pos; 3796eb5e529SEmmanuel Grumbach }; 3806eb5e529SEmmanuel Grumbach 381f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 382f7805b33SLior Cohen /** 383f7805b33SLior Cohen * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data 384f7805b33SLior Cohen * debugfs file 385f7805b33SLior Cohen * 386f7805b33SLior Cohen * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed. 387f7805b33SLior Cohen * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open. 388f7805b33SLior Cohen * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is 389f7805b33SLior Cohen * set the file can no longer be used. 390f7805b33SLior Cohen */ 391f7805b33SLior Cohen enum iwl_fw_mon_dbgfs_state { 392f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_CLOSED, 393f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_OPEN, 394f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED, 395f7805b33SLior Cohen }; 396f7805b33SLior Cohen #endif 397f7805b33SLior Cohen 398e705c121SKalle Valo /** 399496d83caSHaim Dreyfuss * enum iwl_shared_irq_flags - level of sharing for irq 400496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 401496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 402496d83caSHaim Dreyfuss */ 403496d83caSHaim Dreyfuss enum iwl_shared_irq_flags { 404496d83caSHaim Dreyfuss IWL_SHARED_IRQ_NON_RX = BIT(0), 405496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 406496d83caSHaim Dreyfuss }; 407496d83caSHaim Dreyfuss 408496d83caSHaim Dreyfuss /** 4099b58419eSGolan Ben Ami * enum iwl_image_response_code - image response values 4109b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_DEF: the default value of the register 4119b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully 4129b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_FAIL: iml reading failed 4139b58419eSGolan Ben Ami */ 4149b58419eSGolan Ben Ami enum iwl_image_response_code { 4159b58419eSGolan Ben Ami IWL_IMAGE_RESP_DEF = 0, 4169b58419eSGolan Ben Ami IWL_IMAGE_RESP_SUCCESS = 1, 4179b58419eSGolan Ben Ami IWL_IMAGE_RESP_FAIL = 2, 4189b58419eSGolan Ben Ami }; 4199b58419eSGolan Ben Ami 4209b58419eSGolan Ben Ami /** 421eda50cdeSSara Sharon * struct iwl_self_init_dram - dram data used by self init process 422eda50cdeSSara Sharon * @fw: lmac and umac dram data 423eda50cdeSSara Sharon * @fw_cnt: total number of items in array 424eda50cdeSSara Sharon * @paging: paging dram data 425eda50cdeSSara Sharon * @paging_cnt: total number of items in array 426eda50cdeSSara Sharon */ 427eda50cdeSSara Sharon struct iwl_self_init_dram { 428eda50cdeSSara Sharon struct iwl_dram_data *fw; 429eda50cdeSSara Sharon int fw_cnt; 430eda50cdeSSara Sharon struct iwl_dram_data *paging; 431eda50cdeSSara Sharon int paging_cnt; 432eda50cdeSSara Sharon }; 433eda50cdeSSara Sharon 434eda50cdeSSara Sharon /** 435f7805b33SLior Cohen * struct cont_rec: continuous recording data structure 436f7805b33SLior Cohen * @prev_wr_ptr: the last address that was read in monitor_data 437f7805b33SLior Cohen * debugfs file 438f7805b33SLior Cohen * @prev_wrap_cnt: the wrap count that was used during the last read in 439f7805b33SLior Cohen * monitor_data debugfs file 440f7805b33SLior Cohen * @state: the state of monitor_data debugfs file as described 441f7805b33SLior Cohen * in &iwl_fw_mon_dbgfs_state enum 442f7805b33SLior Cohen * @mutex: locked while reading from monitor_data debugfs file 443f7805b33SLior Cohen */ 444f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 445f7805b33SLior Cohen struct cont_rec { 446f7805b33SLior Cohen u32 prev_wr_ptr; 447f7805b33SLior Cohen u32 prev_wrap_cnt; 448f7805b33SLior Cohen u8 state; 449f7805b33SLior Cohen /* Used to sync monitor_data debugfs file with driver unload flow */ 450f7805b33SLior Cohen struct mutex mutex; 451f7805b33SLior Cohen }; 452f7805b33SLior Cohen #endif 453f7805b33SLior Cohen 454f7805b33SLior Cohen /** 455e705c121SKalle Valo * struct iwl_trans_pcie - PCIe transport specific data 456e705c121SKalle Valo * @rxq: all the RX queue data 45778485054SSara Sharon * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 45896a6497bSSara Sharon * @global_table: table mapping received VID from hw to rxb 459e705c121SKalle Valo * @rba: allocator for RX replenishing 460eda50cdeSSara Sharon * @ctxt_info: context information for FW self init 4612ee82402SGolan Ben Ami * @ctxt_info_gen3: context information for gen3 devices 4622ee82402SGolan Ben Ami * @prph_info: prph info for self init 4632ee82402SGolan Ben Ami * @prph_scratch: prph scratch for self init 4642ee82402SGolan Ben Ami * @ctxt_info_dma_addr: dma addr of context information 4652ee82402SGolan Ben Ami * @prph_info_dma_addr: dma addr of prph info 4662ee82402SGolan Ben Ami * @prph_scratch_dma_addr: dma addr of prph scratch 467eda50cdeSSara Sharon * @ctxt_info_dma_addr: dma addr of context information 468eda50cdeSSara Sharon * @init_dram: DRAM data of firmware image (including paging). 469eda50cdeSSara Sharon * Context information addresses will be taken from here. 470eda50cdeSSara Sharon * This is driver's local copy for keeping track of size and 471eda50cdeSSara Sharon * count for allocating and freeing the memory. 472e705c121SKalle Valo * @trans: pointer to the generic transport area 473e705c121SKalle Valo * @scd_base_addr: scheduler sram base address in SRAM 474e705c121SKalle Valo * @scd_bc_tbls: pointer to the byte count table of the scheduler 475e705c121SKalle Valo * @kw: keep warm address 476e705c121SKalle Valo * @pci_dev: basic pci-network driver stuff 477e705c121SKalle Valo * @hw_base: pci hardware address support 478e705c121SKalle Valo * @ucode_write_complete: indicates that the ucode has been copied. 479e705c121SKalle Valo * @ucode_write_waitq: wait queue for uCode load 480e705c121SKalle Valo * @cmd_queue - command queue number 4819416560eSGolan Ben Ami * @def_rx_queue - default rx queue number 4826c4fbcbcSEmmanuel Grumbach * @rx_buf_size: Rx buffer size 483e705c121SKalle Valo * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 484e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 48541837ca9SEmmanuel Grumbach * @sw_csum_tx: if true, then the transport will compute the csum of the TXed 48641837ca9SEmmanuel Grumbach * frame. 487e705c121SKalle Valo * @rx_page_order: page order for receive buffer size 488e705c121SKalle Valo * @reg_lock: protect hw register access 489e705c121SKalle Valo * @mutex: to protect stop_device / start_fw / start_hw 490e705c121SKalle Valo * @cmd_in_flight: true when we have a host command in flight 491f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 492f7805b33SLior Cohen * @fw_mon_data: fw continuous recording data 493f7805b33SLior Cohen #endif 4942e5d4a8fSHaim Dreyfuss * @msix_entries: array of MSI-X entries 4952e5d4a8fSHaim Dreyfuss * @msix_enabled: true if managed to enable MSI-X 496496d83caSHaim Dreyfuss * @shared_vec_mask: the type of causes the shared vector handles 497496d83caSHaim Dreyfuss * (see iwl_shared_irq_flags). 498496d83caSHaim Dreyfuss * @alloc_vecs: the number of interrupt vectors allocated by the OS 499496d83caSHaim Dreyfuss * @def_irq: default irq for non rx causes 5002e5d4a8fSHaim Dreyfuss * @fh_init_mask: initial unmasked fh causes 5012e5d4a8fSHaim Dreyfuss * @hw_init_mask: initial unmasked hw causes 5022e5d4a8fSHaim Dreyfuss * @fh_mask: current unmasked fh causes 5032e5d4a8fSHaim Dreyfuss * @hw_mask: current unmasked hw causes 50449564a80SLuca Coelho * @in_rescan: true if we have triggered a device rescan 505e705c121SKalle Valo */ 506e705c121SKalle Valo struct iwl_trans_pcie { 50778485054SSara Sharon struct iwl_rxq *rxq; 5087b542436SSara Sharon struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE]; 50943146925SSara Sharon struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE]; 510e705c121SKalle Valo struct iwl_rb_allocator rba; 5112ee82402SGolan Ben Ami union { 512eda50cdeSSara Sharon struct iwl_context_info *ctxt_info; 5132ee82402SGolan Ben Ami struct iwl_context_info_gen3 *ctxt_info_gen3; 5142ee82402SGolan Ben Ami }; 5152ee82402SGolan Ben Ami struct iwl_prph_info *prph_info; 5162ee82402SGolan Ben Ami struct iwl_prph_scratch *prph_scratch; 517eda50cdeSSara Sharon dma_addr_t ctxt_info_dma_addr; 5182ee82402SGolan Ben Ami dma_addr_t prph_info_dma_addr; 5192ee82402SGolan Ben Ami dma_addr_t prph_scratch_dma_addr; 5202ee82402SGolan Ben Ami dma_addr_t iml_dma_addr; 521eda50cdeSSara Sharon struct iwl_self_init_dram init_dram; 522e705c121SKalle Valo struct iwl_trans *trans; 523e705c121SKalle Valo 524e705c121SKalle Valo struct net_device napi_dev; 525e705c121SKalle Valo 5266eb5e529SEmmanuel Grumbach struct __percpu iwl_tso_hdr_page *tso_hdr_page; 5276eb5e529SEmmanuel Grumbach 528e705c121SKalle Valo /* INT ICT Table */ 529e705c121SKalle Valo __le32 *ict_tbl; 530e705c121SKalle Valo dma_addr_t ict_tbl_dma; 531e705c121SKalle Valo int ict_index; 532e705c121SKalle Valo bool use_ict; 533326477e4SJohannes Berg bool is_down, opmode_down; 534fa4de7f7SJohannes Berg bool debug_rfkill; 535e705c121SKalle Valo struct isr_statistics isr_stats; 536e705c121SKalle Valo 537e705c121SKalle Valo spinlock_t irq_lock; 538e705c121SKalle Valo struct mutex mutex; 539e705c121SKalle Valo u32 inta_mask; 540e705c121SKalle Valo u32 scd_base_addr; 541e705c121SKalle Valo struct iwl_dma_ptr scd_bc_tbls; 542e705c121SKalle Valo struct iwl_dma_ptr kw; 543e705c121SKalle Valo 544b2a3b1c1SSara Sharon struct iwl_txq *txq_memory; 545e982bc2cSSara Sharon struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 546e982bc2cSSara Sharon unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 547e982bc2cSSara Sharon unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 548e705c121SKalle Valo 549e705c121SKalle Valo /* PCI bus related data */ 550e705c121SKalle Valo struct pci_dev *pci_dev; 551e705c121SKalle Valo void __iomem *hw_base; 552e705c121SKalle Valo 553e705c121SKalle Valo bool ucode_write_complete; 554e705c121SKalle Valo wait_queue_head_t ucode_write_waitq; 555e705c121SKalle Valo wait_queue_head_t wait_command_queue; 5564cbb8e50SLuciano Coelho wait_queue_head_t d0i3_waitq; 557e705c121SKalle Valo 55821cb3222SJohannes Berg u8 page_offs, dev_cmd_offs; 55921cb3222SJohannes Berg 560e705c121SKalle Valo u8 cmd_queue; 5619416560eSGolan Ben Ami u8 def_rx_queue; 562e705c121SKalle Valo u8 cmd_fifo; 563e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 564e705c121SKalle Valo u8 n_no_reclaim_cmds; 565e705c121SKalle Valo u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 5663cd1980bSSara Sharon u8 max_tbs; 5676983ba69SSara Sharon u16 tfd_size; 568e705c121SKalle Valo 5696c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 570e705c121SKalle Valo bool bc_table_dword; 571e705c121SKalle Valo bool scd_set_active; 57241837ca9SEmmanuel Grumbach bool sw_csum_tx; 573a6d24fadSRajat Jain bool pcie_dbg_dumped_once; 574e705c121SKalle Valo u32 rx_page_order; 575e705c121SKalle Valo 576e705c121SKalle Valo /*protect hw register */ 577e705c121SKalle Valo spinlock_t reg_lock; 578e705c121SKalle Valo bool cmd_hold_nic_awake; 579e705c121SKalle Valo bool ref_cmd_in_flight; 580e705c121SKalle Valo 581f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 582f7805b33SLior Cohen struct cont_rec fw_mon_data; 583f7805b33SLior Cohen #endif 584f7805b33SLior Cohen 5852e5d4a8fSHaim Dreyfuss struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 5862e5d4a8fSHaim Dreyfuss bool msix_enabled; 587496d83caSHaim Dreyfuss u8 shared_vec_mask; 588496d83caSHaim Dreyfuss u32 alloc_vecs; 589496d83caSHaim Dreyfuss u32 def_irq; 5902e5d4a8fSHaim Dreyfuss u32 fh_init_mask; 5912e5d4a8fSHaim Dreyfuss u32 hw_init_mask; 5922e5d4a8fSHaim Dreyfuss u32 fh_mask; 5932e5d4a8fSHaim Dreyfuss u32 hw_mask; 5947c8d91ebSHaim Dreyfuss cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 59549564a80SLuca Coelho u16 tx_cmd_queue_size; 59649564a80SLuca Coelho bool in_rescan; 597e705c121SKalle Valo }; 598e705c121SKalle Valo 59985e5a387SJohannes Berg static inline struct iwl_trans_pcie * 60085e5a387SJohannes Berg IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 60185e5a387SJohannes Berg { 60285e5a387SJohannes Berg return (void *)trans->trans_specific; 60385e5a387SJohannes Berg } 604e705c121SKalle Valo 605ff932f61SGolan Ben Ami static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 606ff932f61SGolan Ben Ami struct msix_entry *entry) 607ff932f61SGolan Ben Ami { 608ff932f61SGolan Ben Ami /* 609ff932f61SGolan Ben Ami * Before sending the interrupt the HW disables it to prevent 610ff932f61SGolan Ben Ami * a nested interrupt. This is done by writing 1 to the corresponding 611ff932f61SGolan Ben Ami * bit in the mask register. After handling the interrupt, it should be 612ff932f61SGolan Ben Ami * re-enabled by clearing this bit. This register is defined as 613ff932f61SGolan Ben Ami * write 1 clear (W1C) register, meaning that it's being clear 614ff932f61SGolan Ben Ami * by writing 1 to the bit. 615ff932f61SGolan Ben Ami */ 616ff932f61SGolan Ben Ami iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 617ff932f61SGolan Ben Ami } 618ff932f61SGolan Ben Ami 619e705c121SKalle Valo static inline struct iwl_trans * 620e705c121SKalle Valo iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 621e705c121SKalle Valo { 622e705c121SKalle Valo return container_of((void *)trans_pcie, struct iwl_trans, 623e705c121SKalle Valo trans_specific); 624e705c121SKalle Valo } 625e705c121SKalle Valo 626e705c121SKalle Valo /* 627e705c121SKalle Valo * Convention: trans API functions: iwl_trans_pcie_XXX 628e705c121SKalle Valo * Other functions: iwl_pcie_XXX 629e705c121SKalle Valo */ 630e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 631e705c121SKalle Valo const struct pci_device_id *ent, 632e705c121SKalle Valo const struct iwl_cfg *cfg); 633e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans); 634e705c121SKalle Valo 635e705c121SKalle Valo /***************************************************** 636e705c121SKalle Valo * RX 637e705c121SKalle Valo ******************************************************/ 63889d5e833SGolan Ben Ami int _iwl_pcie_rx_init(struct iwl_trans *trans); 639e705c121SKalle Valo int iwl_pcie_rx_init(struct iwl_trans *trans); 640eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 6412e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 642e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 6432e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 6442e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 645e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans); 646e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans); 647ff932f61SGolan Ben Ami void iwl_pcie_free_rbs_pool(struct iwl_trans *trans); 648ff932f61SGolan Ben Ami void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq); 649ff932f61SGolan Ben Ami int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget); 650ff932f61SGolan Ben Ami void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 651ff932f61SGolan Ben Ami struct iwl_rxq *rxq); 65289d5e833SGolan Ben Ami int iwl_pcie_rx_alloc(struct iwl_trans *trans); 653e705c121SKalle Valo 654e705c121SKalle Valo /***************************************************** 655e705c121SKalle Valo * ICT - interrupt handling 656e705c121SKalle Valo ******************************************************/ 657e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data); 658e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans); 659e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans); 660e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans); 661e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans); 662e705c121SKalle Valo 663e705c121SKalle Valo /***************************************************** 664e705c121SKalle Valo * TX / HCMD 665e705c121SKalle Valo ******************************************************/ 666e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans); 6679b3089bdSGolan Ben Ami int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id, 6689b3089bdSGolan Ben Ami int queue_size); 669e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 670e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans); 671e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans); 672dcfbd67bSEmmanuel Grumbach bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 673e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 674e705c121SKalle Valo unsigned int wdg_timeout); 675e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 676e705c121SKalle Valo bool configure_scd); 67742db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 67842db09c1SLiad Kaufman bool shared_mode); 67938398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, 68038398efbSSara Sharon struct iwl_txq *txq); 681e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 682e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id); 683e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 684e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 68589d5e833SGolan Ben Ami void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx); 68689d5e833SGolan Ben Ami void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans, 68789d5e833SGolan Ben Ami struct iwl_txq *txq); 688e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 689e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb); 690e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 691e705c121SKalle Valo struct sk_buff_head *skbs); 692e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 69389d5e833SGolan Ben Ami void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans_pcie *trans_pcie, 69489d5e833SGolan Ben Ami struct iwl_txq *txq, u16 byte_cnt, 69589d5e833SGolan Ben Ami int num_tbs); 696e705c121SKalle Valo 697cc2f41f8SJohannes Berg static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd, 6986983ba69SSara Sharon u8 idx) 699e705c121SKalle Valo { 7006983ba69SSara Sharon if (trans->cfg->use_tfh) { 701cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 702cc2f41f8SJohannes Berg struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 7036983ba69SSara Sharon 7046983ba69SSara Sharon return le16_to_cpu(tb->tb_len); 705cc2f41f8SJohannes Berg } else { 706cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 707cc2f41f8SJohannes Berg struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 708e705c121SKalle Valo 709e705c121SKalle Valo return le16_to_cpu(tb->hi_n_len) >> 4; 710e705c121SKalle Valo } 711cc2f41f8SJohannes Berg } 712e705c121SKalle Valo 713e705c121SKalle Valo /***************************************************** 714e705c121SKalle Valo * Error handling 715e705c121SKalle Valo ******************************************************/ 716e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans); 717e705c121SKalle Valo 718e705c121SKalle Valo /***************************************************** 719e705c121SKalle Valo * Helpers 720e705c121SKalle Valo ******************************************************/ 721f16c3ebfSEmmanuel Grumbach static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 722e705c121SKalle Valo { 7232e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 724e705c121SKalle Valo 7252e5d4a8fSHaim Dreyfuss clear_bit(STATUS_INT_ENABLED, &trans->status); 7262e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 727e705c121SKalle Valo /* disable interrupts from uCode/NIC to host */ 728e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 729e705c121SKalle Valo 730e705c121SKalle Valo /* acknowledge/clear/reset any interrupts still pending 731e705c121SKalle Valo * from uCode or flow handler (Rx/Tx DMA) */ 732e705c121SKalle Valo iwl_write32(trans, CSR_INT, 0xffffffff); 733e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 7342e5d4a8fSHaim Dreyfuss } else { 7352e5d4a8fSHaim Dreyfuss /* disable all the interrupt we might use */ 7362e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 7372e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 7382e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 7392e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 7402e5d4a8fSHaim Dreyfuss } 741e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 742e705c121SKalle Valo } 743e705c121SKalle Valo 7442ee82402SGolan Ben Ami #define IWL_NUM_OF_COMPLETION_RINGS 31 7452ee82402SGolan Ben Ami #define IWL_NUM_OF_TRANSFER_RINGS 527 7462ee82402SGolan Ben Ami 7472ee82402SGolan Ben Ami static inline int iwl_pcie_get_num_sections(const struct fw_img *fw, 7482ee82402SGolan Ben Ami int start) 7492ee82402SGolan Ben Ami { 7502ee82402SGolan Ben Ami int i = 0; 7512ee82402SGolan Ben Ami 7522ee82402SGolan Ben Ami while (start < fw->num_sec && 7532ee82402SGolan Ben Ami fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && 7542ee82402SGolan Ben Ami fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { 7552ee82402SGolan Ben Ami start++; 7562ee82402SGolan Ben Ami i++; 7572ee82402SGolan Ben Ami } 7582ee82402SGolan Ben Ami 7592ee82402SGolan Ben Ami return i; 7602ee82402SGolan Ben Ami } 7612ee82402SGolan Ben Ami 7622ee82402SGolan Ben Ami static inline int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans, 7632ee82402SGolan Ben Ami const struct fw_desc *sec, 7642ee82402SGolan Ben Ami struct iwl_dram_data *dram) 7652ee82402SGolan Ben Ami { 7662ee82402SGolan Ben Ami dram->block = dma_alloc_coherent(trans->dev, sec->len, 7672ee82402SGolan Ben Ami &dram->physical, 7682ee82402SGolan Ben Ami GFP_KERNEL); 7692ee82402SGolan Ben Ami if (!dram->block) 7702ee82402SGolan Ben Ami return -ENOMEM; 7712ee82402SGolan Ben Ami 7722ee82402SGolan Ben Ami dram->size = sec->len; 7732ee82402SGolan Ben Ami memcpy(dram->block, sec->data, sec->len); 7742ee82402SGolan Ben Ami 7752ee82402SGolan Ben Ami return 0; 7762ee82402SGolan Ben Ami } 7772ee82402SGolan Ben Ami 7782ee82402SGolan Ben Ami static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans) 7792ee82402SGolan Ben Ami { 7802ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 7812ee82402SGolan Ben Ami struct iwl_self_init_dram *dram = &trans_pcie->init_dram; 7822ee82402SGolan Ben Ami int i; 7832ee82402SGolan Ben Ami 7842ee82402SGolan Ben Ami if (!dram->fw) { 7852ee82402SGolan Ben Ami WARN_ON(dram->fw_cnt); 7862ee82402SGolan Ben Ami return; 7872ee82402SGolan Ben Ami } 7882ee82402SGolan Ben Ami 7892ee82402SGolan Ben Ami for (i = 0; i < dram->fw_cnt; i++) 7902ee82402SGolan Ben Ami dma_free_coherent(trans->dev, dram->fw[i].size, 7912ee82402SGolan Ben Ami dram->fw[i].block, dram->fw[i].physical); 7922ee82402SGolan Ben Ami 7932ee82402SGolan Ben Ami kfree(dram->fw); 7942ee82402SGolan Ben Ami dram->fw_cnt = 0; 7952ee82402SGolan Ben Ami dram->fw = NULL; 7962ee82402SGolan Ben Ami } 7972ee82402SGolan Ben Ami 798f16c3ebfSEmmanuel Grumbach static inline void iwl_disable_interrupts(struct iwl_trans *trans) 799f16c3ebfSEmmanuel Grumbach { 800f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 801f16c3ebfSEmmanuel Grumbach 802f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 803f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 804f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 805f16c3ebfSEmmanuel Grumbach } 806f16c3ebfSEmmanuel Grumbach 807f16c3ebfSEmmanuel Grumbach static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 808e705c121SKalle Valo { 809e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 810e705c121SKalle Valo 811e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 812e705c121SKalle Valo set_bit(STATUS_INT_ENABLED, &trans->status); 8132e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 814e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 815e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 8162e5d4a8fSHaim Dreyfuss } else { 8172e5d4a8fSHaim Dreyfuss /* 8182e5d4a8fSHaim Dreyfuss * fh/hw_mask keeps all the unmasked causes. 8192e5d4a8fSHaim Dreyfuss * Unlike msi, in msix cause is enabled when it is unset. 8202e5d4a8fSHaim Dreyfuss */ 8212e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 8222e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 8232e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 8242e5d4a8fSHaim Dreyfuss ~trans_pcie->fh_mask); 8252e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 8262e5d4a8fSHaim Dreyfuss ~trans_pcie->hw_mask); 8272e5d4a8fSHaim Dreyfuss } 8282e5d4a8fSHaim Dreyfuss } 8292e5d4a8fSHaim Dreyfuss 830f16c3ebfSEmmanuel Grumbach static inline void iwl_enable_interrupts(struct iwl_trans *trans) 831f16c3ebfSEmmanuel Grumbach { 832f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 833f16c3ebfSEmmanuel Grumbach 834f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 835f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 836f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 837f16c3ebfSEmmanuel Grumbach } 8382e5d4a8fSHaim Dreyfuss static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 8392e5d4a8fSHaim Dreyfuss { 8402e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 8412e5d4a8fSHaim Dreyfuss 8422e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 8432e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = msk; 8442e5d4a8fSHaim Dreyfuss } 8452e5d4a8fSHaim Dreyfuss 8462e5d4a8fSHaim Dreyfuss static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 8472e5d4a8fSHaim Dreyfuss { 8482e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 8492e5d4a8fSHaim Dreyfuss 8502e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 8512e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = msk; 852e705c121SKalle Valo } 853e705c121SKalle Valo 854a6bd005fSEmmanuel Grumbach static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 855a6bd005fSEmmanuel Grumbach { 856a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 857a6bd005fSEmmanuel Grumbach 858a6bd005fSEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 8592e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 860a6bd005fSEmmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 861a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 8622e5d4a8fSHaim Dreyfuss } else { 8632e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 8642e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 8652e5d4a8fSHaim Dreyfuss iwl_enable_fh_int_msk_msix(trans, 8662e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 8672e5d4a8fSHaim Dreyfuss } 868a6bd005fSEmmanuel Grumbach } 869a6bd005fSEmmanuel Grumbach 8707b3e42eaSGolan Ben Ami static inline u16 iwl_pcie_get_cmd_index(const struct iwl_txq *q, u32 index) 8714ecab561SEmmanuel Grumbach { 8724ecab561SEmmanuel Grumbach return index & (q->n_window - 1); 8734ecab561SEmmanuel Grumbach } 8744ecab561SEmmanuel Grumbach 875943309d4SEmmanuel Grumbach static inline void *iwl_pcie_get_tfd(struct iwl_trans *trans, 876ab6c6445SSara Sharon struct iwl_txq *txq, int idx) 877ab6c6445SSara Sharon { 878943309d4SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 879943309d4SEmmanuel Grumbach 880943309d4SEmmanuel Grumbach if (trans->cfg->use_tfh) 881943309d4SEmmanuel Grumbach idx = iwl_pcie_get_cmd_index(txq, idx); 882943309d4SEmmanuel Grumbach 883943309d4SEmmanuel Grumbach return txq->tfds + trans_pcie->tfd_size * idx; 884ab6c6445SSara Sharon } 885ab6c6445SSara Sharon 886ff932f61SGolan Ben Ami static inline const char *queue_name(struct device *dev, 887ff932f61SGolan Ben Ami struct iwl_trans_pcie *trans_p, int i) 888ff932f61SGolan Ben Ami { 889ff932f61SGolan Ben Ami if (trans_p->shared_vec_mask) { 890ff932f61SGolan Ben Ami int vec = trans_p->shared_vec_mask & 891ff932f61SGolan Ben Ami IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 892ff932f61SGolan Ben Ami 893ff932f61SGolan Ben Ami if (i == 0) 894ff932f61SGolan Ben Ami return DRV_NAME ": shared IRQ"; 895ff932f61SGolan Ben Ami 896ff932f61SGolan Ben Ami return devm_kasprintf(dev, GFP_KERNEL, 897ff932f61SGolan Ben Ami DRV_NAME ": queue %d", i + vec); 898ff932f61SGolan Ben Ami } 899ff932f61SGolan Ben Ami if (i == 0) 900ff932f61SGolan Ben Ami return DRV_NAME ": default queue"; 901ff932f61SGolan Ben Ami 902ff932f61SGolan Ben Ami if (i == trans_p->alloc_vecs - 1) 903ff932f61SGolan Ben Ami return DRV_NAME ": exception"; 904ff932f61SGolan Ben Ami 905ff932f61SGolan Ben Ami return devm_kasprintf(dev, GFP_KERNEL, 906ff932f61SGolan Ben Ami DRV_NAME ": queue %d", i); 907ff932f61SGolan Ben Ami } 908ff932f61SGolan Ben Ami 909e705c121SKalle Valo static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 910e705c121SKalle Valo { 911e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 912e705c121SKalle Valo 913e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 9142e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 915e705c121SKalle Valo trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 916e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 9172e5d4a8fSHaim Dreyfuss } else { 9182e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 9192e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 9202e5d4a8fSHaim Dreyfuss iwl_enable_hw_int_msk_msix(trans, 9212e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_RF_KILL); 9222e5d4a8fSHaim Dreyfuss } 923ae5bb2a6SJohannes Berg 924ae5bb2a6SJohannes Berg if (trans->cfg->device_family == IWL_DEVICE_FAMILY_9000) { 925ae5bb2a6SJohannes Berg /* 926ae5bb2a6SJohannes Berg * On 9000-series devices this bit isn't enabled by default, so 927ae5bb2a6SJohannes Berg * when we power down the device we need set the bit to allow it 928ae5bb2a6SJohannes Berg * to wake up the PCI-E bus for RF-kill interrupts. 929ae5bb2a6SJohannes Berg */ 930ae5bb2a6SJohannes Berg iwl_set_bit(trans, CSR_GP_CNTRL, 931ae5bb2a6SJohannes Berg CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 932ae5bb2a6SJohannes Berg } 933e705c121SKalle Valo } 934e705c121SKalle Valo 935fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans); 936fa4de7f7SJohannes Berg 937e705c121SKalle Valo static inline void iwl_wake_queue(struct iwl_trans *trans, 938e705c121SKalle Valo struct iwl_txq *txq) 939e705c121SKalle Valo { 940e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 941e705c121SKalle Valo 942bb98ecd4SSara Sharon if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) { 943bb98ecd4SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id); 944bb98ecd4SSara Sharon iwl_op_mode_queue_not_full(trans->op_mode, txq->id); 945e705c121SKalle Valo } 946e705c121SKalle Valo } 947e705c121SKalle Valo 948e705c121SKalle Valo static inline void iwl_stop_queue(struct iwl_trans *trans, 949e705c121SKalle Valo struct iwl_txq *txq) 950e705c121SKalle Valo { 951e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 952e705c121SKalle Valo 953bb98ecd4SSara Sharon if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) { 954bb98ecd4SSara Sharon iwl_op_mode_queue_full(trans->op_mode, txq->id); 955bb98ecd4SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id); 956e705c121SKalle Valo } else 957e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 958bb98ecd4SSara Sharon txq->id); 959e705c121SKalle Valo } 960e705c121SKalle Valo 961bb98ecd4SSara Sharon static inline bool iwl_queue_used(const struct iwl_txq *q, int i) 962e705c121SKalle Valo { 963f5955a6cSGolan Ben Ami int index = iwl_pcie_get_cmd_index(q, i); 964f5955a6cSGolan Ben Ami int r = iwl_pcie_get_cmd_index(q, q->read_ptr); 965f5955a6cSGolan Ben Ami int w = iwl_pcie_get_cmd_index(q, q->write_ptr); 966f5955a6cSGolan Ben Ami 967f5955a6cSGolan Ben Ami return w >= r ? 968f5955a6cSGolan Ben Ami (index >= r && index < w) : 969f5955a6cSGolan Ben Ami !(index < r && index >= w); 970e705c121SKalle Valo } 971e705c121SKalle Valo 972e705c121SKalle Valo static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 973e705c121SKalle Valo { 974fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 975fa4de7f7SJohannes Berg 976fa4de7f7SJohannes Berg lockdep_assert_held(&trans_pcie->mutex); 977fa4de7f7SJohannes Berg 978fa4de7f7SJohannes Berg if (trans_pcie->debug_rfkill) 979fa4de7f7SJohannes Berg return true; 98023aeea94SJohannes Berg 981e705c121SKalle Valo return !(iwl_read32(trans, CSR_GP_CNTRL) & 982e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 983e705c121SKalle Valo } 984e705c121SKalle Valo 985e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 986e705c121SKalle Valo u32 reg, u32 mask, u32 value) 987e705c121SKalle Valo { 988e705c121SKalle Valo u32 v; 989e705c121SKalle Valo 990e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 991e705c121SKalle Valo WARN_ON_ONCE(value & ~mask); 992e705c121SKalle Valo #endif 993e705c121SKalle Valo 994e705c121SKalle Valo v = iwl_read32(trans, reg); 995e705c121SKalle Valo v &= ~mask; 996e705c121SKalle Valo v |= value; 997e705c121SKalle Valo iwl_write32(trans, reg, v); 998e705c121SKalle Valo } 999e705c121SKalle Valo 1000e705c121SKalle Valo static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 1001e705c121SKalle Valo u32 reg, u32 mask) 1002e705c121SKalle Valo { 1003e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 1004e705c121SKalle Valo } 1005e705c121SKalle Valo 1006e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 1007e705c121SKalle Valo u32 reg, u32 mask) 1008e705c121SKalle Valo { 1009e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 1010e705c121SKalle Valo } 1011e705c121SKalle Valo 10127a14c23dSSara Sharon static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans) 10137a14c23dSSara Sharon { 10147a14c23dSSara Sharon return (trans->dbg_dest_tlv || trans->ini_valid); 10157a14c23dSSara Sharon } 10167a14c23dSSara Sharon 1017e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 10184290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans); 1019e705c121SKalle Valo 1020f8a1edb7SJohannes Berg #ifdef CONFIG_IWLWIFI_DEBUGFS 1021f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 1022f8a1edb7SJohannes Berg #else 1023f8a1edb7SJohannes Berg static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 1024f8a1edb7SJohannes Berg { 1025f8a1edb7SJohannes Berg return 0; 1026f8a1edb7SJohannes Berg } 1027f8a1edb7SJohannes Berg #endif 1028f8a1edb7SJohannes Berg 10294cbb8e50SLuciano Coelho int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans); 10304cbb8e50SLuciano Coelho int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans); 10314cbb8e50SLuciano Coelho 10321316d595SSara Sharon void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable); 10331316d595SSara Sharon 103410a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data); 103510a54d81SLuca Coelho 1036eda50cdeSSara Sharon /* common functions that are used by gen2 transport */ 1037b6fe2757SGolan Ben Ami int iwl_pcie_gen2_apm_init(struct iwl_trans *trans); 1038eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans); 1039eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 1040eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 10419ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans); 1042326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1043326477e4SJohannes Berg bool was_in_rfkill); 10446b35ff91SSara Sharon void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq); 10457b3e42eaSGolan Ben Ami int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q); 1046e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans); 104777c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 104813a3a390SSara Sharon int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 1049b8e8d7ceSSara Sharon int slots_num, bool cmd_queue); 105013a3a390SSara Sharon int iwl_pcie_txq_alloc(struct iwl_trans *trans, 1051b8e8d7ceSSara Sharon struct iwl_txq *txq, int slots_num, bool cmd_queue); 105213a3a390SSara Sharon int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 105313a3a390SSara Sharon struct iwl_dma_ptr *ptr, size_t size); 105413a3a390SSara Sharon void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr); 1055c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans); 10569bb3d5a0SEmmanuel Grumbach void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 10579bb3d5a0SEmmanuel Grumbach struct sk_buff *skb); 10586ffe5de3SSara Sharon #ifdef CONFIG_INET 10596ffe5de3SSara Sharon struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len); 10606ffe5de3SSara Sharon #endif 1061eda50cdeSSara Sharon 10629f358c17SGolan Ben Ami /* common functions that are used by gen3 transport */ 10639f358c17SGolan Ben Ami void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power); 10649f358c17SGolan Ben Ami 1065eda50cdeSSara Sharon /* transport gen 2 exported functions */ 1066eda50cdeSSara Sharon int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 1067eda50cdeSSara Sharon const struct fw_img *fw, bool run_in_rfkill); 1068eda50cdeSSara Sharon void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr); 10691169310fSGolan Ben Ami void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans, 10701169310fSGolan Ben Ami struct iwl_txq *txq); 10711169310fSGolan Ben Ami int iwl_trans_pcie_dyn_txq_alloc_dma(struct iwl_trans *trans, 10721169310fSGolan Ben Ami struct iwl_txq **intxq, int size, 10731169310fSGolan Ben Ami unsigned int timeout); 10741169310fSGolan Ben Ami int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans, 10751169310fSGolan Ben Ami struct iwl_txq *txq, 10761169310fSGolan Ben Ami struct iwl_host_cmd *hcmd); 10776b35ff91SSara Sharon int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans, 10781169310fSGolan Ben Ami __le16 flags, u8 sta_id, u8 tid, 10795369774cSSara Sharon int cmd_id, int size, 10806b35ff91SSara Sharon unsigned int timeout); 10816b35ff91SSara Sharon void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue); 1082ab6c6445SSara Sharon int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb, 1083ab6c6445SSara Sharon struct iwl_device_cmd *dev_cmd, int txq_id); 1084ca60da2eSSara Sharon int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 1085ca60da2eSSara Sharon struct iwl_host_cmd *cmd); 108677c09bc8SSara Sharon void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, 108777c09bc8SSara Sharon bool low_power); 108877c09bc8SSara Sharon void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power); 108913a3a390SSara Sharon void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id); 109013a3a390SSara Sharon void iwl_pcie_gen2_tx_free(struct iwl_trans *trans); 109113a3a390SSara Sharon void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans); 1092e705c121SKalle Valo #endif /* __iwl_trans_int_pcie_h__ */ 1093