1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 4e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6e705c121SKalle Valo * 7e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 8e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 9e705c121SKalle Valo * 10e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 11e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 12e705c121SKalle Valo * published by the Free Software Foundation. 13e705c121SKalle Valo * 14e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 15e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17e705c121SKalle Valo * more details. 18e705c121SKalle Valo * 19e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 20e705c121SKalle Valo * this program; if not, write to the Free Software Foundation, Inc., 21e705c121SKalle Valo * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 22e705c121SKalle Valo * 23e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 24e705c121SKalle Valo * file called LICENSE. 25e705c121SKalle Valo * 26e705c121SKalle Valo * Contact Information: 27cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 28e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29e705c121SKalle Valo * 30e705c121SKalle Valo *****************************************************************************/ 31e705c121SKalle Valo #ifndef __iwl_trans_int_pcie_h__ 32e705c121SKalle Valo #define __iwl_trans_int_pcie_h__ 33e705c121SKalle Valo 34e705c121SKalle Valo #include <linux/spinlock.h> 35e705c121SKalle Valo #include <linux/interrupt.h> 36e705c121SKalle Valo #include <linux/skbuff.h> 37e705c121SKalle Valo #include <linux/wait.h> 38e705c121SKalle Valo #include <linux/pci.h> 39e705c121SKalle Valo #include <linux/timer.h> 407c8d91ebSHaim Dreyfuss #include <linux/cpu.h> 41e705c121SKalle Valo 42e705c121SKalle Valo #include "iwl-fh.h" 43e705c121SKalle Valo #include "iwl-csr.h" 44e705c121SKalle Valo #include "iwl-trans.h" 45e705c121SKalle Valo #include "iwl-debug.h" 46e705c121SKalle Valo #include "iwl-io.h" 47e705c121SKalle Valo #include "iwl-op-mode.h" 48e705c121SKalle Valo 49e705c121SKalle Valo /* We need 2 entries for the TX command and header, and another one might 50e705c121SKalle Valo * be needed for potential data in the SKB's head. The remaining ones can 51e705c121SKalle Valo * be used for frags. 52e705c121SKalle Valo */ 533cd1980bSSara Sharon #define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3) 54e705c121SKalle Valo 55e705c121SKalle Valo /* 56e705c121SKalle Valo * RX related structures and functions 57e705c121SKalle Valo */ 58e705c121SKalle Valo #define RX_NUM_QUEUES 1 59e705c121SKalle Valo #define RX_POST_REQ_ALLOC 2 60e705c121SKalle Valo #define RX_CLAIM_REQ_ALLOC 8 6178485054SSara Sharon #define RX_PENDING_WATERMARK 16 62e705c121SKalle Valo 63e705c121SKalle Valo struct iwl_host_cmd; 64e705c121SKalle Valo 65e705c121SKalle Valo /*This file includes the declaration that are internal to the 66e705c121SKalle Valo * trans_pcie layer */ 67e705c121SKalle Valo 6896a6497bSSara Sharon /** 6996a6497bSSara Sharon * struct iwl_rx_mem_buffer 7096a6497bSSara Sharon * @page_dma: bus address of rxb page 7196a6497bSSara Sharon * @page: driver's pointer to the rxb page 72b1753c62SSara Sharon * @invalid: rxb is in driver ownership - not owned by HW 7396a6497bSSara Sharon * @vid: index of this rxb in the global table 7496a6497bSSara Sharon */ 75e705c121SKalle Valo struct iwl_rx_mem_buffer { 76e705c121SKalle Valo dma_addr_t page_dma; 77e705c121SKalle Valo struct page *page; 7896a6497bSSara Sharon u16 vid; 79b1753c62SSara Sharon bool invalid; 80e705c121SKalle Valo struct list_head list; 81e705c121SKalle Valo }; 82e705c121SKalle Valo 83e705c121SKalle Valo /** 84e705c121SKalle Valo * struct isr_statistics - interrupt statistics 85e705c121SKalle Valo * 86e705c121SKalle Valo */ 87e705c121SKalle Valo struct isr_statistics { 88e705c121SKalle Valo u32 hw; 89e705c121SKalle Valo u32 sw; 90e705c121SKalle Valo u32 err_code; 91e705c121SKalle Valo u32 sch; 92e705c121SKalle Valo u32 alive; 93e705c121SKalle Valo u32 rfkill; 94e705c121SKalle Valo u32 ctkill; 95e705c121SKalle Valo u32 wakeup; 96e705c121SKalle Valo u32 rx; 97e705c121SKalle Valo u32 tx; 98e705c121SKalle Valo u32 unhandled; 99e705c121SKalle Valo }; 100e705c121SKalle Valo 101e705c121SKalle Valo /** 102e705c121SKalle Valo * struct iwl_rxq - Rx queue 10396a6497bSSara Sharon * @id: queue index 10496a6497bSSara Sharon * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 10596a6497bSSara Sharon * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 106e705c121SKalle Valo * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 10796a6497bSSara Sharon * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd) 10896a6497bSSara Sharon * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd) 109e705c121SKalle Valo * @read: Shared index to newest available Rx buffer 110e705c121SKalle Valo * @write: Shared index to oldest written Rx packet 111e705c121SKalle Valo * @free_count: Number of pre-allocated buffers in rx_free 112e705c121SKalle Valo * @used_count: Number of RBDs handled to allocator to use for allocation 113e705c121SKalle Valo * @write_actual: 114e705c121SKalle Valo * @rx_free: list of RBDs with allocated RB ready for use 115e705c121SKalle Valo * @rx_used: list of RBDs with no RB attached 116e705c121SKalle Valo * @need_update: flag to indicate we need to update read/write index 117e705c121SKalle Valo * @rb_stts: driver's pointer to receive buffer status 118e705c121SKalle Valo * @rb_stts_dma: bus address of receive buffer status 119e705c121SKalle Valo * @lock: 12096a6497bSSara Sharon * @queue: actual rx queue. Not used for multi-rx queue. 121e705c121SKalle Valo * 122e705c121SKalle Valo * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 123e705c121SKalle Valo */ 124e705c121SKalle Valo struct iwl_rxq { 12596a6497bSSara Sharon int id; 12696a6497bSSara Sharon void *bd; 127e705c121SKalle Valo dma_addr_t bd_dma; 12896a6497bSSara Sharon __le32 *used_bd; 12996a6497bSSara Sharon dma_addr_t used_bd_dma; 130e705c121SKalle Valo u32 read; 131e705c121SKalle Valo u32 write; 132e705c121SKalle Valo u32 free_count; 133e705c121SKalle Valo u32 used_count; 134e705c121SKalle Valo u32 write_actual; 13596a6497bSSara Sharon u32 queue_size; 136e705c121SKalle Valo struct list_head rx_free; 137e705c121SKalle Valo struct list_head rx_used; 138e705c121SKalle Valo bool need_update; 139e705c121SKalle Valo struct iwl_rb_status *rb_stts; 140e705c121SKalle Valo dma_addr_t rb_stts_dma; 141e705c121SKalle Valo spinlock_t lock; 142bce97731SSara Sharon struct napi_struct napi; 143e705c121SKalle Valo struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 144e705c121SKalle Valo }; 145e705c121SKalle Valo 146e705c121SKalle Valo /** 147e705c121SKalle Valo * struct iwl_rb_allocator - Rx allocator 148e705c121SKalle Valo * @req_pending: number of requests the allcator had not processed yet 149e705c121SKalle Valo * @req_ready: number of requests honored and ready for claiming 150e705c121SKalle Valo * @rbd_allocated: RBDs with pages allocated and ready to be handled to 151e705c121SKalle Valo * the queue. This is a list of &struct iwl_rx_mem_buffer 152e705c121SKalle Valo * @rbd_empty: RBDs with no page attached for allocator use. This is a list 153e705c121SKalle Valo * of &struct iwl_rx_mem_buffer 154e705c121SKalle Valo * @lock: protects the rbd_allocated and rbd_empty lists 155e705c121SKalle Valo * @alloc_wq: work queue for background calls 156e705c121SKalle Valo * @rx_alloc: work struct for background calls 157e705c121SKalle Valo */ 158e705c121SKalle Valo struct iwl_rb_allocator { 159e705c121SKalle Valo atomic_t req_pending; 160e705c121SKalle Valo atomic_t req_ready; 161e705c121SKalle Valo struct list_head rbd_allocated; 162e705c121SKalle Valo struct list_head rbd_empty; 163e705c121SKalle Valo spinlock_t lock; 164e705c121SKalle Valo struct workqueue_struct *alloc_wq; 165e705c121SKalle Valo struct work_struct rx_alloc; 166e705c121SKalle Valo }; 167e705c121SKalle Valo 168e705c121SKalle Valo struct iwl_dma_ptr { 169e705c121SKalle Valo dma_addr_t dma; 170e705c121SKalle Valo void *addr; 171e705c121SKalle Valo size_t size; 172e705c121SKalle Valo }; 173e705c121SKalle Valo 174e705c121SKalle Valo /** 175e705c121SKalle Valo * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 176e705c121SKalle Valo * @index -- current index 177e705c121SKalle Valo */ 178e705c121SKalle Valo static inline int iwl_queue_inc_wrap(int index) 179e705c121SKalle Valo { 180e705c121SKalle Valo return ++index & (TFD_QUEUE_SIZE_MAX - 1); 181e705c121SKalle Valo } 182e705c121SKalle Valo 183e705c121SKalle Valo /** 184e705c121SKalle Valo * iwl_queue_dec_wrap - decrement queue index, wrap back to end 185e705c121SKalle Valo * @index -- current index 186e705c121SKalle Valo */ 187e705c121SKalle Valo static inline int iwl_queue_dec_wrap(int index) 188e705c121SKalle Valo { 189e705c121SKalle Valo return --index & (TFD_QUEUE_SIZE_MAX - 1); 190e705c121SKalle Valo } 191e705c121SKalle Valo 192e705c121SKalle Valo struct iwl_cmd_meta { 193e705c121SKalle Valo /* only for SYNC commands, iff the reply skb is wanted */ 194e705c121SKalle Valo struct iwl_host_cmd *source; 195e705c121SKalle Valo u32 flags; 1963cd1980bSSara Sharon u32 tbs; 197e705c121SKalle Valo }; 198e705c121SKalle Valo 199e705c121SKalle Valo 200e705c121SKalle Valo #define TFD_TX_CMD_SLOTS 256 201e705c121SKalle Valo #define TFD_CMD_SLOTS 32 202e705c121SKalle Valo 203e705c121SKalle Valo /* 2048de437c7SSara Sharon * The FH will write back to the first TB only, so we need to copy some data 2058de437c7SSara Sharon * into the buffer regardless of whether it should be mapped or not. 2068de437c7SSara Sharon * This indicates how big the first TB must be to include the scratch buffer 2078de437c7SSara Sharon * and the assigned PN. 208b97277ccSSara Sharon * Since PN location is 8 bytes at offset 12, it's 20 now. 2098de437c7SSara Sharon * If we make it bigger then allocations will be bigger and copy slower, so 2108de437c7SSara Sharon * that's probably not useful. 211e705c121SKalle Valo */ 212b97277ccSSara Sharon #define IWL_FIRST_TB_SIZE 20 2138de437c7SSara Sharon #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 214e705c121SKalle Valo 215e705c121SKalle Valo struct iwl_pcie_txq_entry { 216e705c121SKalle Valo struct iwl_device_cmd *cmd; 217e705c121SKalle Valo struct sk_buff *skb; 218e705c121SKalle Valo /* buffer to free after command completes */ 219e705c121SKalle Valo const void *free_buf; 220e705c121SKalle Valo struct iwl_cmd_meta meta; 221e705c121SKalle Valo }; 222e705c121SKalle Valo 2238de437c7SSara Sharon struct iwl_pcie_first_tb_buf { 2248de437c7SSara Sharon u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 225e705c121SKalle Valo }; 226e705c121SKalle Valo 227e705c121SKalle Valo /** 228e705c121SKalle Valo * struct iwl_txq - Tx Queue for DMA 229e705c121SKalle Valo * @q: generic Rx/Tx queue descriptor 230e705c121SKalle Valo * @tfds: transmit frame descriptors (DMA memory) 2318de437c7SSara Sharon * @first_tb_bufs: start of command headers, including scratch buffers, for 232e705c121SKalle Valo * the writeback -- this is DMA memory and an array holding one buffer 233e705c121SKalle Valo * for each command on the queue 2348de437c7SSara Sharon * @first_tb_dma: DMA address for the first_tb_bufs start 235e705c121SKalle Valo * @entries: transmit entries (driver state) 236e705c121SKalle Valo * @lock: queue lock 237e705c121SKalle Valo * @stuck_timer: timer that fires if queue gets stuck 238e705c121SKalle Valo * @trans_pcie: pointer back to transport (for timer) 239e705c121SKalle Valo * @need_update: indicates need to update read/write index 240e705c121SKalle Valo * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 241e705c121SKalle Valo * @wd_timeout: queue watchdog timeout (jiffies) - per queue 242e705c121SKalle Valo * @frozen: tx stuck queue timer is frozen 243e705c121SKalle Valo * @frozen_expiry_remainder: remember how long until the timer fires 244bb98ecd4SSara Sharon * @write_ptr: 1-st empty entry (index) host_w 245bb98ecd4SSara Sharon * @read_ptr: last used entry (index) host_r 246bb98ecd4SSara Sharon * @dma_addr: physical addr for BD's 247bb98ecd4SSara Sharon * @n_window: safe queue window 248bb98ecd4SSara Sharon * @id: queue id 249bb98ecd4SSara Sharon * @low_mark: low watermark, resume queue if free space more than this 250bb98ecd4SSara Sharon * @high_mark: high watermark, stop queue if free space less than this 251e705c121SKalle Valo * 252e705c121SKalle Valo * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 253e705c121SKalle Valo * descriptors) and required locking structures. 254bb98ecd4SSara Sharon * 255bb98ecd4SSara Sharon * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 256bb98ecd4SSara Sharon * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 257bb98ecd4SSara Sharon * there might be HW changes in the future). For the normal TX 258bb98ecd4SSara Sharon * queues, n_window, which is the size of the software queue data 259bb98ecd4SSara Sharon * is also 256; however, for the command queue, n_window is only 260bb98ecd4SSara Sharon * 32 since we don't need so many commands pending. Since the HW 261bb98ecd4SSara Sharon * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 262bb98ecd4SSara Sharon * This means that we end up with the following: 263bb98ecd4SSara Sharon * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 264bb98ecd4SSara Sharon * SW entries: | 0 | ... | 31 | 265bb98ecd4SSara Sharon * where N is a number between 0 and 7. This means that the SW 266bb98ecd4SSara Sharon * data is a window overlayed over the HW queue. 267e705c121SKalle Valo */ 268e705c121SKalle Valo struct iwl_txq { 2696983ba69SSara Sharon void *tfds; 2708de437c7SSara Sharon struct iwl_pcie_first_tb_buf *first_tb_bufs; 2718de437c7SSara Sharon dma_addr_t first_tb_dma; 272e705c121SKalle Valo struct iwl_pcie_txq_entry *entries; 273e705c121SKalle Valo spinlock_t lock; 274e705c121SKalle Valo unsigned long frozen_expiry_remainder; 275e705c121SKalle Valo struct timer_list stuck_timer; 276e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 277e705c121SKalle Valo bool need_update; 278e705c121SKalle Valo bool frozen; 279e705c121SKalle Valo bool ampdu; 28004fa3e68SEmmanuel Grumbach int block; 281e705c121SKalle Valo unsigned long wd_timeout; 2823955525dSEmmanuel Grumbach struct sk_buff_head overflow_q; 283bb98ecd4SSara Sharon 284bb98ecd4SSara Sharon int write_ptr; 285bb98ecd4SSara Sharon int read_ptr; 286bb98ecd4SSara Sharon dma_addr_t dma_addr; 287bb98ecd4SSara Sharon int n_window; 288bb98ecd4SSara Sharon u32 id; 289bb98ecd4SSara Sharon int low_mark; 290bb98ecd4SSara Sharon int high_mark; 291e705c121SKalle Valo }; 292e705c121SKalle Valo 293e705c121SKalle Valo static inline dma_addr_t 2948de437c7SSara Sharon iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx) 295e705c121SKalle Valo { 2968de437c7SSara Sharon return txq->first_tb_dma + 2978de437c7SSara Sharon sizeof(struct iwl_pcie_first_tb_buf) * idx; 298e705c121SKalle Valo } 299e705c121SKalle Valo 3006eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page { 3016eb5e529SEmmanuel Grumbach struct page *page; 3026eb5e529SEmmanuel Grumbach u8 *pos; 3036eb5e529SEmmanuel Grumbach }; 3046eb5e529SEmmanuel Grumbach 305e705c121SKalle Valo /** 306496d83caSHaim Dreyfuss * enum iwl_shared_irq_flags - level of sharing for irq 307496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 308496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 309496d83caSHaim Dreyfuss */ 310496d83caSHaim Dreyfuss enum iwl_shared_irq_flags { 311496d83caSHaim Dreyfuss IWL_SHARED_IRQ_NON_RX = BIT(0), 312496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 313496d83caSHaim Dreyfuss }; 314496d83caSHaim Dreyfuss 315496d83caSHaim Dreyfuss /** 316eda50cdeSSara Sharon * struct iwl_dram_data 317eda50cdeSSara Sharon * @physical: page phy pointer 318eda50cdeSSara Sharon * @block: pointer to the allocated block/page 319eda50cdeSSara Sharon * @size: size of the block/page 320eda50cdeSSara Sharon */ 321eda50cdeSSara Sharon struct iwl_dram_data { 322eda50cdeSSara Sharon dma_addr_t physical; 323eda50cdeSSara Sharon void *block; 324eda50cdeSSara Sharon int size; 325eda50cdeSSara Sharon }; 326eda50cdeSSara Sharon 327eda50cdeSSara Sharon /** 328eda50cdeSSara Sharon * struct iwl_self_init_dram - dram data used by self init process 329eda50cdeSSara Sharon * @fw: lmac and umac dram data 330eda50cdeSSara Sharon * @fw_cnt: total number of items in array 331eda50cdeSSara Sharon * @paging: paging dram data 332eda50cdeSSara Sharon * @paging_cnt: total number of items in array 333eda50cdeSSara Sharon */ 334eda50cdeSSara Sharon struct iwl_self_init_dram { 335eda50cdeSSara Sharon struct iwl_dram_data *fw; 336eda50cdeSSara Sharon int fw_cnt; 337eda50cdeSSara Sharon struct iwl_dram_data *paging; 338eda50cdeSSara Sharon int paging_cnt; 339eda50cdeSSara Sharon }; 340eda50cdeSSara Sharon 341eda50cdeSSara Sharon /** 342e705c121SKalle Valo * struct iwl_trans_pcie - PCIe transport specific data 343e705c121SKalle Valo * @rxq: all the RX queue data 34478485054SSara Sharon * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 34596a6497bSSara Sharon * @global_table: table mapping received VID from hw to rxb 346e705c121SKalle Valo * @rba: allocator for RX replenishing 347eda50cdeSSara Sharon * @ctxt_info: context information for FW self init 348eda50cdeSSara Sharon * @ctxt_info_dma_addr: dma addr of context information 349eda50cdeSSara Sharon * @init_dram: DRAM data of firmware image (including paging). 350eda50cdeSSara Sharon * Context information addresses will be taken from here. 351eda50cdeSSara Sharon * This is driver's local copy for keeping track of size and 352eda50cdeSSara Sharon * count for allocating and freeing the memory. 353e705c121SKalle Valo * @trans: pointer to the generic transport area 354e705c121SKalle Valo * @scd_base_addr: scheduler sram base address in SRAM 355e705c121SKalle Valo * @scd_bc_tbls: pointer to the byte count table of the scheduler 356e705c121SKalle Valo * @kw: keep warm address 357e705c121SKalle Valo * @pci_dev: basic pci-network driver stuff 358e705c121SKalle Valo * @hw_base: pci hardware address support 359e705c121SKalle Valo * @ucode_write_complete: indicates that the ucode has been copied. 360e705c121SKalle Valo * @ucode_write_waitq: wait queue for uCode load 361e705c121SKalle Valo * @cmd_queue - command queue number 3626c4fbcbcSEmmanuel Grumbach * @rx_buf_size: Rx buffer size 363e705c121SKalle Valo * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 364e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 36541837ca9SEmmanuel Grumbach * @sw_csum_tx: if true, then the transport will compute the csum of the TXed 36641837ca9SEmmanuel Grumbach * frame. 367e705c121SKalle Valo * @rx_page_order: page order for receive buffer size 368e705c121SKalle Valo * @reg_lock: protect hw register access 369e705c121SKalle Valo * @mutex: to protect stop_device / start_fw / start_hw 370e705c121SKalle Valo * @cmd_in_flight: true when we have a host command in flight 371e705c121SKalle Valo * @fw_mon_phys: physical address of the buffer for the firmware monitor 372e705c121SKalle Valo * @fw_mon_page: points to the first page of the buffer for the firmware monitor 373e705c121SKalle Valo * @fw_mon_size: size of the buffer for the firmware monitor 3742e5d4a8fSHaim Dreyfuss * @msix_entries: array of MSI-X entries 3752e5d4a8fSHaim Dreyfuss * @msix_enabled: true if managed to enable MSI-X 376496d83caSHaim Dreyfuss * @shared_vec_mask: the type of causes the shared vector handles 377496d83caSHaim Dreyfuss * (see iwl_shared_irq_flags). 378496d83caSHaim Dreyfuss * @alloc_vecs: the number of interrupt vectors allocated by the OS 379496d83caSHaim Dreyfuss * @def_irq: default irq for non rx causes 3802e5d4a8fSHaim Dreyfuss * @fh_init_mask: initial unmasked fh causes 3812e5d4a8fSHaim Dreyfuss * @hw_init_mask: initial unmasked hw causes 3822e5d4a8fSHaim Dreyfuss * @fh_mask: current unmasked fh causes 3832e5d4a8fSHaim Dreyfuss * @hw_mask: current unmasked hw causes 384e705c121SKalle Valo */ 385e705c121SKalle Valo struct iwl_trans_pcie { 38678485054SSara Sharon struct iwl_rxq *rxq; 3877b542436SSara Sharon struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE]; 38843146925SSara Sharon struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE]; 389e705c121SKalle Valo struct iwl_rb_allocator rba; 390eda50cdeSSara Sharon struct iwl_context_info *ctxt_info; 391eda50cdeSSara Sharon dma_addr_t ctxt_info_dma_addr; 392eda50cdeSSara Sharon struct iwl_self_init_dram init_dram; 393e705c121SKalle Valo struct iwl_trans *trans; 394e705c121SKalle Valo 395e705c121SKalle Valo struct net_device napi_dev; 396e705c121SKalle Valo 3976eb5e529SEmmanuel Grumbach struct __percpu iwl_tso_hdr_page *tso_hdr_page; 3986eb5e529SEmmanuel Grumbach 399e705c121SKalle Valo /* INT ICT Table */ 400e705c121SKalle Valo __le32 *ict_tbl; 401e705c121SKalle Valo dma_addr_t ict_tbl_dma; 402e705c121SKalle Valo int ict_index; 403e705c121SKalle Valo bool use_ict; 404e705c121SKalle Valo bool is_down; 405e705c121SKalle Valo struct isr_statistics isr_stats; 406e705c121SKalle Valo 407e705c121SKalle Valo spinlock_t irq_lock; 408e705c121SKalle Valo struct mutex mutex; 409e705c121SKalle Valo u32 inta_mask; 410e705c121SKalle Valo u32 scd_base_addr; 411e705c121SKalle Valo struct iwl_dma_ptr scd_bc_tbls; 412e705c121SKalle Valo struct iwl_dma_ptr kw; 413e705c121SKalle Valo 414b2a3b1c1SSara Sharon struct iwl_txq *txq_memory; 415b2a3b1c1SSara Sharon struct iwl_txq *txq[IWL_MAX_HW_QUEUES]; 416e705c121SKalle Valo unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 417e705c121SKalle Valo unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 418e705c121SKalle Valo 419e705c121SKalle Valo /* PCI bus related data */ 420e705c121SKalle Valo struct pci_dev *pci_dev; 421e705c121SKalle Valo void __iomem *hw_base; 422e705c121SKalle Valo 423e705c121SKalle Valo bool ucode_write_complete; 424e705c121SKalle Valo wait_queue_head_t ucode_write_waitq; 425e705c121SKalle Valo wait_queue_head_t wait_command_queue; 4264cbb8e50SLuciano Coelho wait_queue_head_t d0i3_waitq; 427e705c121SKalle Valo 42821cb3222SJohannes Berg u8 page_offs, dev_cmd_offs; 42921cb3222SJohannes Berg 430e705c121SKalle Valo u8 cmd_queue; 431e705c121SKalle Valo u8 cmd_fifo; 432e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 433e705c121SKalle Valo u8 n_no_reclaim_cmds; 434e705c121SKalle Valo u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 4353cd1980bSSara Sharon u8 max_tbs; 4366983ba69SSara Sharon u16 tfd_size; 437e705c121SKalle Valo 4386c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 439e705c121SKalle Valo bool bc_table_dword; 440e705c121SKalle Valo bool scd_set_active; 44141837ca9SEmmanuel Grumbach bool sw_csum_tx; 442e705c121SKalle Valo u32 rx_page_order; 443e705c121SKalle Valo 444e705c121SKalle Valo /*protect hw register */ 445e705c121SKalle Valo spinlock_t reg_lock; 446e705c121SKalle Valo bool cmd_hold_nic_awake; 447e705c121SKalle Valo bool ref_cmd_in_flight; 448e705c121SKalle Valo 449e705c121SKalle Valo dma_addr_t fw_mon_phys; 450e705c121SKalle Valo struct page *fw_mon_page; 451e705c121SKalle Valo u32 fw_mon_size; 4522e5d4a8fSHaim Dreyfuss 4532e5d4a8fSHaim Dreyfuss struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 4542e5d4a8fSHaim Dreyfuss bool msix_enabled; 455496d83caSHaim Dreyfuss u8 shared_vec_mask; 456496d83caSHaim Dreyfuss u32 alloc_vecs; 457496d83caSHaim Dreyfuss u32 def_irq; 4582e5d4a8fSHaim Dreyfuss u32 fh_init_mask; 4592e5d4a8fSHaim Dreyfuss u32 hw_init_mask; 4602e5d4a8fSHaim Dreyfuss u32 fh_mask; 4612e5d4a8fSHaim Dreyfuss u32 hw_mask; 4627c8d91ebSHaim Dreyfuss cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 463e705c121SKalle Valo }; 464e705c121SKalle Valo 46585e5a387SJohannes Berg static inline struct iwl_trans_pcie * 46685e5a387SJohannes Berg IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 46785e5a387SJohannes Berg { 46885e5a387SJohannes Berg return (void *)trans->trans_specific; 46985e5a387SJohannes Berg } 470e705c121SKalle Valo 471e705c121SKalle Valo static inline struct iwl_trans * 472e705c121SKalle Valo iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 473e705c121SKalle Valo { 474e705c121SKalle Valo return container_of((void *)trans_pcie, struct iwl_trans, 475e705c121SKalle Valo trans_specific); 476e705c121SKalle Valo } 477e705c121SKalle Valo 478e705c121SKalle Valo /* 479e705c121SKalle Valo * Convention: trans API functions: iwl_trans_pcie_XXX 480e705c121SKalle Valo * Other functions: iwl_pcie_XXX 481e705c121SKalle Valo */ 482e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 483e705c121SKalle Valo const struct pci_device_id *ent, 484e705c121SKalle Valo const struct iwl_cfg *cfg); 485e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans); 486e705c121SKalle Valo 487e705c121SKalle Valo /***************************************************** 488e705c121SKalle Valo * RX 489e705c121SKalle Valo ******************************************************/ 490e705c121SKalle Valo int iwl_pcie_rx_init(struct iwl_trans *trans); 491eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 4922e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 493e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 4942e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 4952e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 496e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans); 497e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans); 498e705c121SKalle Valo 499e705c121SKalle Valo /***************************************************** 500e705c121SKalle Valo * ICT - interrupt handling 501e705c121SKalle Valo ******************************************************/ 502e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data); 503e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans); 504e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans); 505e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans); 506e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans); 507e705c121SKalle Valo 508e705c121SKalle Valo /***************************************************** 509e705c121SKalle Valo * TX / HCMD 510e705c121SKalle Valo ******************************************************/ 511e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans); 512eda50cdeSSara Sharon int iwl_pcie_gen2_tx_init(struct iwl_trans *trans); 513e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 514e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans); 515e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans); 516e705c121SKalle Valo void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 517e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 518e705c121SKalle Valo unsigned int wdg_timeout); 519e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 520e705c121SKalle Valo bool configure_scd); 52142db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 52242db09c1SLiad Kaufman bool shared_mode); 52338398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, 52438398efbSSara Sharon struct iwl_txq *txq); 525e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 526e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id); 527e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 528e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 529e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 530e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb); 531e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 532e705c121SKalle Valo struct sk_buff_head *skbs); 533e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 534e705c121SKalle Valo 535cc2f41f8SJohannes Berg static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd, 5366983ba69SSara Sharon u8 idx) 537e705c121SKalle Valo { 5386983ba69SSara Sharon if (trans->cfg->use_tfh) { 539cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 540cc2f41f8SJohannes Berg struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 5416983ba69SSara Sharon 5426983ba69SSara Sharon return le16_to_cpu(tb->tb_len); 543cc2f41f8SJohannes Berg } else { 544cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 545cc2f41f8SJohannes Berg struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 546e705c121SKalle Valo 547e705c121SKalle Valo return le16_to_cpu(tb->hi_n_len) >> 4; 548e705c121SKalle Valo } 549cc2f41f8SJohannes Berg } 550e705c121SKalle Valo 551e705c121SKalle Valo /***************************************************** 552e705c121SKalle Valo * Error handling 553e705c121SKalle Valo ******************************************************/ 554e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans); 555e705c121SKalle Valo 556e705c121SKalle Valo /***************************************************** 557e705c121SKalle Valo * Helpers 558e705c121SKalle Valo ******************************************************/ 559f16c3ebfSEmmanuel Grumbach static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 560e705c121SKalle Valo { 5612e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 562e705c121SKalle Valo 5632e5d4a8fSHaim Dreyfuss clear_bit(STATUS_INT_ENABLED, &trans->status); 5642e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 565e705c121SKalle Valo /* disable interrupts from uCode/NIC to host */ 566e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 567e705c121SKalle Valo 568e705c121SKalle Valo /* acknowledge/clear/reset any interrupts still pending 569e705c121SKalle Valo * from uCode or flow handler (Rx/Tx DMA) */ 570e705c121SKalle Valo iwl_write32(trans, CSR_INT, 0xffffffff); 571e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 5722e5d4a8fSHaim Dreyfuss } else { 5732e5d4a8fSHaim Dreyfuss /* disable all the interrupt we might use */ 5742e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 5752e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 5762e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 5772e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 5782e5d4a8fSHaim Dreyfuss } 579e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 580e705c121SKalle Valo } 581e705c121SKalle Valo 582f16c3ebfSEmmanuel Grumbach static inline void iwl_disable_interrupts(struct iwl_trans *trans) 583f16c3ebfSEmmanuel Grumbach { 584f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 585f16c3ebfSEmmanuel Grumbach 586f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 587f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 588f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 589f16c3ebfSEmmanuel Grumbach } 590f16c3ebfSEmmanuel Grumbach 591f16c3ebfSEmmanuel Grumbach static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 592e705c121SKalle Valo { 593e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 594e705c121SKalle Valo 595e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 596e705c121SKalle Valo set_bit(STATUS_INT_ENABLED, &trans->status); 5972e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 598e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 599e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 6002e5d4a8fSHaim Dreyfuss } else { 6012e5d4a8fSHaim Dreyfuss /* 6022e5d4a8fSHaim Dreyfuss * fh/hw_mask keeps all the unmasked causes. 6032e5d4a8fSHaim Dreyfuss * Unlike msi, in msix cause is enabled when it is unset. 6042e5d4a8fSHaim Dreyfuss */ 6052e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 6062e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 6072e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 6082e5d4a8fSHaim Dreyfuss ~trans_pcie->fh_mask); 6092e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 6102e5d4a8fSHaim Dreyfuss ~trans_pcie->hw_mask); 6112e5d4a8fSHaim Dreyfuss } 6122e5d4a8fSHaim Dreyfuss } 6132e5d4a8fSHaim Dreyfuss 614f16c3ebfSEmmanuel Grumbach static inline void iwl_enable_interrupts(struct iwl_trans *trans) 615f16c3ebfSEmmanuel Grumbach { 616f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 617f16c3ebfSEmmanuel Grumbach 618f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 619f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 620f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 621f16c3ebfSEmmanuel Grumbach } 6222e5d4a8fSHaim Dreyfuss static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 6232e5d4a8fSHaim Dreyfuss { 6242e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 6252e5d4a8fSHaim Dreyfuss 6262e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 6272e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = msk; 6282e5d4a8fSHaim Dreyfuss } 6292e5d4a8fSHaim Dreyfuss 6302e5d4a8fSHaim Dreyfuss static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 6312e5d4a8fSHaim Dreyfuss { 6322e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 6332e5d4a8fSHaim Dreyfuss 6342e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 6352e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = msk; 636e705c121SKalle Valo } 637e705c121SKalle Valo 638a6bd005fSEmmanuel Grumbach static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 639a6bd005fSEmmanuel Grumbach { 640a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 641a6bd005fSEmmanuel Grumbach 642a6bd005fSEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 6432e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 644a6bd005fSEmmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 645a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 6462e5d4a8fSHaim Dreyfuss } else { 6472e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 6482e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 6492e5d4a8fSHaim Dreyfuss iwl_enable_fh_int_msk_msix(trans, 6502e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 6512e5d4a8fSHaim Dreyfuss } 652a6bd005fSEmmanuel Grumbach } 653a6bd005fSEmmanuel Grumbach 654ab6c6445SSara Sharon static inline void *iwl_pcie_get_tfd(struct iwl_trans_pcie *trans_pcie, 655ab6c6445SSara Sharon struct iwl_txq *txq, int idx) 656ab6c6445SSara Sharon { 657ab6c6445SSara Sharon return txq->tfds + trans_pcie->tfd_size * idx; 658ab6c6445SSara Sharon } 659ab6c6445SSara Sharon 660e705c121SKalle Valo static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 661e705c121SKalle Valo { 662e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 663e705c121SKalle Valo 664e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 6652e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 666e705c121SKalle Valo trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 667e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 6682e5d4a8fSHaim Dreyfuss } else { 6692e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 6702e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 6712e5d4a8fSHaim Dreyfuss iwl_enable_hw_int_msk_msix(trans, 6722e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_RF_KILL); 6732e5d4a8fSHaim Dreyfuss } 674e705c121SKalle Valo } 675e705c121SKalle Valo 676e705c121SKalle Valo static inline void iwl_wake_queue(struct iwl_trans *trans, 677e705c121SKalle Valo struct iwl_txq *txq) 678e705c121SKalle Valo { 679e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 680e705c121SKalle Valo 681bb98ecd4SSara Sharon if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) { 682bb98ecd4SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id); 683bb98ecd4SSara Sharon iwl_op_mode_queue_not_full(trans->op_mode, txq->id); 684e705c121SKalle Valo } 685e705c121SKalle Valo } 686e705c121SKalle Valo 687e705c121SKalle Valo static inline void iwl_stop_queue(struct iwl_trans *trans, 688e705c121SKalle Valo struct iwl_txq *txq) 689e705c121SKalle Valo { 690e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 691e705c121SKalle Valo 692bb98ecd4SSara Sharon if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) { 693bb98ecd4SSara Sharon iwl_op_mode_queue_full(trans->op_mode, txq->id); 694bb98ecd4SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id); 695e705c121SKalle Valo } else 696e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 697bb98ecd4SSara Sharon txq->id); 698e705c121SKalle Valo } 699e705c121SKalle Valo 700bb98ecd4SSara Sharon static inline bool iwl_queue_used(const struct iwl_txq *q, int i) 701e705c121SKalle Valo { 702e705c121SKalle Valo return q->write_ptr >= q->read_ptr ? 703e705c121SKalle Valo (i >= q->read_ptr && i < q->write_ptr) : 704e705c121SKalle Valo !(i < q->read_ptr && i >= q->write_ptr); 705e705c121SKalle Valo } 706e705c121SKalle Valo 707bb98ecd4SSara Sharon static inline u8 get_cmd_index(struct iwl_txq *q, u32 index) 708e705c121SKalle Valo { 709e705c121SKalle Valo return index & (q->n_window - 1); 710e705c121SKalle Valo } 711e705c121SKalle Valo 712e705c121SKalle Valo static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 713e705c121SKalle Valo { 71423aeea94SJohannes Berg lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->mutex); 71523aeea94SJohannes Berg 716e705c121SKalle Valo return !(iwl_read32(trans, CSR_GP_CNTRL) & 717e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 718e705c121SKalle Valo } 719e705c121SKalle Valo 720e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 721e705c121SKalle Valo u32 reg, u32 mask, u32 value) 722e705c121SKalle Valo { 723e705c121SKalle Valo u32 v; 724e705c121SKalle Valo 725e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 726e705c121SKalle Valo WARN_ON_ONCE(value & ~mask); 727e705c121SKalle Valo #endif 728e705c121SKalle Valo 729e705c121SKalle Valo v = iwl_read32(trans, reg); 730e705c121SKalle Valo v &= ~mask; 731e705c121SKalle Valo v |= value; 732e705c121SKalle Valo iwl_write32(trans, reg, v); 733e705c121SKalle Valo } 734e705c121SKalle Valo 735e705c121SKalle Valo static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 736e705c121SKalle Valo u32 reg, u32 mask) 737e705c121SKalle Valo { 738e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 739e705c121SKalle Valo } 740e705c121SKalle Valo 741e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 742e705c121SKalle Valo u32 reg, u32 mask) 743e705c121SKalle Valo { 744e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 745e705c121SKalle Valo } 746e705c121SKalle Valo 747e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 748e705c121SKalle Valo 749f8a1edb7SJohannes Berg #ifdef CONFIG_IWLWIFI_DEBUGFS 750f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 751f8a1edb7SJohannes Berg #else 752f8a1edb7SJohannes Berg static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 753f8a1edb7SJohannes Berg { 754f8a1edb7SJohannes Berg return 0; 755f8a1edb7SJohannes Berg } 756f8a1edb7SJohannes Berg #endif 757f8a1edb7SJohannes Berg 7584cbb8e50SLuciano Coelho int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans); 7594cbb8e50SLuciano Coelho int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans); 7604cbb8e50SLuciano Coelho 7611316d595SSara Sharon void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable); 7621316d595SSara Sharon 763eda50cdeSSara Sharon /* common functions that are used by gen2 transport */ 764eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans); 765eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 766eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 767eda50cdeSSara Sharon bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans); 7686b35ff91SSara Sharon void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq); 769ab6c6445SSara Sharon int iwl_queue_space(const struct iwl_txq *q); 77077c09bc8SSara Sharon int iwl_pcie_apm_stop_master(struct iwl_trans *trans); 77177c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 772eda50cdeSSara Sharon 773eda50cdeSSara Sharon /* transport gen 2 exported functions */ 774eda50cdeSSara Sharon int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 775eda50cdeSSara Sharon const struct fw_img *fw, bool run_in_rfkill); 776eda50cdeSSara Sharon void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr); 7776b35ff91SSara Sharon int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans, 7786b35ff91SSara Sharon struct iwl_tx_queue_cfg_cmd *cmd, 7796b35ff91SSara Sharon int cmd_id, 7806b35ff91SSara Sharon unsigned int timeout); 7816b35ff91SSara Sharon void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue); 782ab6c6445SSara Sharon int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb, 783ab6c6445SSara Sharon struct iwl_device_cmd *dev_cmd, int txq_id); 784ca60da2eSSara Sharon int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 785ca60da2eSSara Sharon struct iwl_host_cmd *cmd); 78677c09bc8SSara Sharon void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, 78777c09bc8SSara Sharon bool low_power); 78877c09bc8SSara Sharon void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power); 789eda50cdeSSara Sharon 790e705c121SKalle Valo #endif /* __iwl_trans_int_pcie_h__ */ 791