1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 4e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 54cbb8e50SLuciano Coelho * Copyright(c) 2016 Intel Deutschland GmbH 6e705c121SKalle Valo * 7e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 8e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 9e705c121SKalle Valo * 10e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 11e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 12e705c121SKalle Valo * published by the Free Software Foundation. 13e705c121SKalle Valo * 14e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 15e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17e705c121SKalle Valo * more details. 18e705c121SKalle Valo * 19e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 20e705c121SKalle Valo * this program; if not, write to the Free Software Foundation, Inc., 21e705c121SKalle Valo * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 22e705c121SKalle Valo * 23e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 24e705c121SKalle Valo * file called LICENSE. 25e705c121SKalle Valo * 26e705c121SKalle Valo * Contact Information: 27cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 28e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29e705c121SKalle Valo * 30e705c121SKalle Valo *****************************************************************************/ 31e705c121SKalle Valo #ifndef __iwl_trans_int_pcie_h__ 32e705c121SKalle Valo #define __iwl_trans_int_pcie_h__ 33e705c121SKalle Valo 34e705c121SKalle Valo #include <linux/spinlock.h> 35e705c121SKalle Valo #include <linux/interrupt.h> 36e705c121SKalle Valo #include <linux/skbuff.h> 37e705c121SKalle Valo #include <linux/wait.h> 38e705c121SKalle Valo #include <linux/pci.h> 39e705c121SKalle Valo #include <linux/timer.h> 40e705c121SKalle Valo 41e705c121SKalle Valo #include "iwl-fh.h" 42e705c121SKalle Valo #include "iwl-csr.h" 43e705c121SKalle Valo #include "iwl-trans.h" 44e705c121SKalle Valo #include "iwl-debug.h" 45e705c121SKalle Valo #include "iwl-io.h" 46e705c121SKalle Valo #include "iwl-op-mode.h" 47e705c121SKalle Valo 48e705c121SKalle Valo /* We need 2 entries for the TX command and header, and another one might 49e705c121SKalle Valo * be needed for potential data in the SKB's head. The remaining ones can 50e705c121SKalle Valo * be used for frags. 51e705c121SKalle Valo */ 52e705c121SKalle Valo #define IWL_PCIE_MAX_FRAGS (IWL_NUM_OF_TBS - 3) 53e705c121SKalle Valo 54e705c121SKalle Valo /* 55e705c121SKalle Valo * RX related structures and functions 56e705c121SKalle Valo */ 57e705c121SKalle Valo #define RX_NUM_QUEUES 1 58e705c121SKalle Valo #define RX_POST_REQ_ALLOC 2 59e705c121SKalle Valo #define RX_CLAIM_REQ_ALLOC 8 6078485054SSara Sharon #define RX_PENDING_WATERMARK 16 61e705c121SKalle Valo 62e705c121SKalle Valo struct iwl_host_cmd; 63e705c121SKalle Valo 64e705c121SKalle Valo /*This file includes the declaration that are internal to the 65e705c121SKalle Valo * trans_pcie layer */ 66e705c121SKalle Valo 6796a6497bSSara Sharon /** 6896a6497bSSara Sharon * struct iwl_rx_mem_buffer 6996a6497bSSara Sharon * @page_dma: bus address of rxb page 7096a6497bSSara Sharon * @page: driver's pointer to the rxb page 71b1753c62SSara Sharon * @invalid: rxb is in driver ownership - not owned by HW 7296a6497bSSara Sharon * @vid: index of this rxb in the global table 7396a6497bSSara Sharon */ 74e705c121SKalle Valo struct iwl_rx_mem_buffer { 75e705c121SKalle Valo dma_addr_t page_dma; 76e705c121SKalle Valo struct page *page; 7796a6497bSSara Sharon u16 vid; 78b1753c62SSara Sharon bool invalid; 79e705c121SKalle Valo struct list_head list; 80e705c121SKalle Valo }; 81e705c121SKalle Valo 82e705c121SKalle Valo /** 83e705c121SKalle Valo * struct isr_statistics - interrupt statistics 84e705c121SKalle Valo * 85e705c121SKalle Valo */ 86e705c121SKalle Valo struct isr_statistics { 87e705c121SKalle Valo u32 hw; 88e705c121SKalle Valo u32 sw; 89e705c121SKalle Valo u32 err_code; 90e705c121SKalle Valo u32 sch; 91e705c121SKalle Valo u32 alive; 92e705c121SKalle Valo u32 rfkill; 93e705c121SKalle Valo u32 ctkill; 94e705c121SKalle Valo u32 wakeup; 95e705c121SKalle Valo u32 rx; 96e705c121SKalle Valo u32 tx; 97e705c121SKalle Valo u32 unhandled; 98e705c121SKalle Valo }; 99e705c121SKalle Valo 100e705c121SKalle Valo /** 101e705c121SKalle Valo * struct iwl_rxq - Rx queue 10296a6497bSSara Sharon * @id: queue index 10396a6497bSSara Sharon * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 10496a6497bSSara Sharon * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 105e705c121SKalle Valo * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 10696a6497bSSara Sharon * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd) 10796a6497bSSara Sharon * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd) 108e705c121SKalle Valo * @read: Shared index to newest available Rx buffer 109e705c121SKalle Valo * @write: Shared index to oldest written Rx packet 110e705c121SKalle Valo * @free_count: Number of pre-allocated buffers in rx_free 111e705c121SKalle Valo * @used_count: Number of RBDs handled to allocator to use for allocation 112e705c121SKalle Valo * @write_actual: 113e705c121SKalle Valo * @rx_free: list of RBDs with allocated RB ready for use 114e705c121SKalle Valo * @rx_used: list of RBDs with no RB attached 115e705c121SKalle Valo * @need_update: flag to indicate we need to update read/write index 116e705c121SKalle Valo * @rb_stts: driver's pointer to receive buffer status 117e705c121SKalle Valo * @rb_stts_dma: bus address of receive buffer status 118e705c121SKalle Valo * @lock: 11996a6497bSSara Sharon * @queue: actual rx queue. Not used for multi-rx queue. 120e705c121SKalle Valo * 121e705c121SKalle Valo * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 122e705c121SKalle Valo */ 123e705c121SKalle Valo struct iwl_rxq { 12496a6497bSSara Sharon int id; 12596a6497bSSara Sharon void *bd; 126e705c121SKalle Valo dma_addr_t bd_dma; 12796a6497bSSara Sharon __le32 *used_bd; 12896a6497bSSara Sharon dma_addr_t used_bd_dma; 129e705c121SKalle Valo u32 read; 130e705c121SKalle Valo u32 write; 131e705c121SKalle Valo u32 free_count; 132e705c121SKalle Valo u32 used_count; 133e705c121SKalle Valo u32 write_actual; 13496a6497bSSara Sharon u32 queue_size; 135e705c121SKalle Valo struct list_head rx_free; 136e705c121SKalle Valo struct list_head rx_used; 137e705c121SKalle Valo bool need_update; 138e705c121SKalle Valo struct iwl_rb_status *rb_stts; 139e705c121SKalle Valo dma_addr_t rb_stts_dma; 140e705c121SKalle Valo spinlock_t lock; 141bce97731SSara Sharon struct napi_struct napi; 142e705c121SKalle Valo struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 143e705c121SKalle Valo }; 144e705c121SKalle Valo 145e705c121SKalle Valo /** 146e705c121SKalle Valo * struct iwl_rb_allocator - Rx allocator 147e705c121SKalle Valo * @req_pending: number of requests the allcator had not processed yet 148e705c121SKalle Valo * @req_ready: number of requests honored and ready for claiming 149e705c121SKalle Valo * @rbd_allocated: RBDs with pages allocated and ready to be handled to 150e705c121SKalle Valo * the queue. This is a list of &struct iwl_rx_mem_buffer 151e705c121SKalle Valo * @rbd_empty: RBDs with no page attached for allocator use. This is a list 152e705c121SKalle Valo * of &struct iwl_rx_mem_buffer 153e705c121SKalle Valo * @lock: protects the rbd_allocated and rbd_empty lists 154e705c121SKalle Valo * @alloc_wq: work queue for background calls 155e705c121SKalle Valo * @rx_alloc: work struct for background calls 156e705c121SKalle Valo */ 157e705c121SKalle Valo struct iwl_rb_allocator { 158e705c121SKalle Valo atomic_t req_pending; 159e705c121SKalle Valo atomic_t req_ready; 160e705c121SKalle Valo struct list_head rbd_allocated; 161e705c121SKalle Valo struct list_head rbd_empty; 162e705c121SKalle Valo spinlock_t lock; 163e705c121SKalle Valo struct workqueue_struct *alloc_wq; 164e705c121SKalle Valo struct work_struct rx_alloc; 165e705c121SKalle Valo }; 166e705c121SKalle Valo 167e705c121SKalle Valo struct iwl_dma_ptr { 168e705c121SKalle Valo dma_addr_t dma; 169e705c121SKalle Valo void *addr; 170e705c121SKalle Valo size_t size; 171e705c121SKalle Valo }; 172e705c121SKalle Valo 173e705c121SKalle Valo /** 174e705c121SKalle Valo * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 175e705c121SKalle Valo * @index -- current index 176e705c121SKalle Valo */ 177e705c121SKalle Valo static inline int iwl_queue_inc_wrap(int index) 178e705c121SKalle Valo { 179e705c121SKalle Valo return ++index & (TFD_QUEUE_SIZE_MAX - 1); 180e705c121SKalle Valo } 181e705c121SKalle Valo 182e705c121SKalle Valo /** 183e705c121SKalle Valo * iwl_queue_dec_wrap - decrement queue index, wrap back to end 184e705c121SKalle Valo * @index -- current index 185e705c121SKalle Valo */ 186e705c121SKalle Valo static inline int iwl_queue_dec_wrap(int index) 187e705c121SKalle Valo { 188e705c121SKalle Valo return --index & (TFD_QUEUE_SIZE_MAX - 1); 189e705c121SKalle Valo } 190e705c121SKalle Valo 191e705c121SKalle Valo struct iwl_cmd_meta { 192e705c121SKalle Valo /* only for SYNC commands, iff the reply skb is wanted */ 193e705c121SKalle Valo struct iwl_host_cmd *source; 194e705c121SKalle Valo u32 flags; 195e705c121SKalle Valo }; 196e705c121SKalle Valo 197e705c121SKalle Valo /* 198e705c121SKalle Valo * Generic queue structure 199e705c121SKalle Valo * 200e705c121SKalle Valo * Contains common data for Rx and Tx queues. 201e705c121SKalle Valo * 202e705c121SKalle Valo * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 203e705c121SKalle Valo * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 204e705c121SKalle Valo * there might be HW changes in the future). For the normal TX 205e705c121SKalle Valo * queues, n_window, which is the size of the software queue data 206e705c121SKalle Valo * is also 256; however, for the command queue, n_window is only 207e705c121SKalle Valo * 32 since we don't need so many commands pending. Since the HW 208e705c121SKalle Valo * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. As a result, 209e705c121SKalle Valo * the software buffers (in the variables @meta, @txb in struct 210e705c121SKalle Valo * iwl_txq) only have 32 entries, while the HW buffers (@tfds in 211e705c121SKalle Valo * the same struct) have 256. 212e705c121SKalle Valo * This means that we end up with the following: 213e705c121SKalle Valo * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 214e705c121SKalle Valo * SW entries: | 0 | ... | 31 | 215e705c121SKalle Valo * where N is a number between 0 and 7. This means that the SW 216e705c121SKalle Valo * data is a window overlayed over the HW queue. 217e705c121SKalle Valo */ 218e705c121SKalle Valo struct iwl_queue { 219e705c121SKalle Valo int write_ptr; /* 1-st empty entry (index) host_w*/ 220e705c121SKalle Valo int read_ptr; /* last used entry (index) host_r*/ 221e705c121SKalle Valo /* use for monitoring and recovering the stuck queue */ 222e705c121SKalle Valo dma_addr_t dma_addr; /* physical addr for BD's */ 223e705c121SKalle Valo int n_window; /* safe queue window */ 224e705c121SKalle Valo u32 id; 225e705c121SKalle Valo int low_mark; /* low watermark, resume queue if free 226e705c121SKalle Valo * space more than this */ 227e705c121SKalle Valo int high_mark; /* high watermark, stop queue if free 228e705c121SKalle Valo * space less than this */ 229e705c121SKalle Valo }; 230e705c121SKalle Valo 231e705c121SKalle Valo #define TFD_TX_CMD_SLOTS 256 232e705c121SKalle Valo #define TFD_CMD_SLOTS 32 233e705c121SKalle Valo 234e705c121SKalle Valo /* 2358de437c7SSara Sharon * The FH will write back to the first TB only, so we need to copy some data 2368de437c7SSara Sharon * into the buffer regardless of whether it should be mapped or not. 2378de437c7SSara Sharon * This indicates how big the first TB must be to include the scratch buffer 2388de437c7SSara Sharon * and the assigned PN. 2398de437c7SSara Sharon * Since PN location is 16 bytes at offset 24, it's 40 now. 2408de437c7SSara Sharon * If we make it bigger then allocations will be bigger and copy slower, so 2418de437c7SSara Sharon * that's probably not useful. 242e705c121SKalle Valo */ 2438de437c7SSara Sharon #define IWL_FIRST_TB_SIZE 40 2448de437c7SSara Sharon #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 245e705c121SKalle Valo 246e705c121SKalle Valo struct iwl_pcie_txq_entry { 247e705c121SKalle Valo struct iwl_device_cmd *cmd; 248e705c121SKalle Valo struct sk_buff *skb; 249e705c121SKalle Valo /* buffer to free after command completes */ 250e705c121SKalle Valo const void *free_buf; 251e705c121SKalle Valo struct iwl_cmd_meta meta; 252e705c121SKalle Valo }; 253e705c121SKalle Valo 2548de437c7SSara Sharon struct iwl_pcie_first_tb_buf { 2558de437c7SSara Sharon u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 256e705c121SKalle Valo }; 257e705c121SKalle Valo 258e705c121SKalle Valo /** 259e705c121SKalle Valo * struct iwl_txq - Tx Queue for DMA 260e705c121SKalle Valo * @q: generic Rx/Tx queue descriptor 261e705c121SKalle Valo * @tfds: transmit frame descriptors (DMA memory) 2628de437c7SSara Sharon * @first_tb_bufs: start of command headers, including scratch buffers, for 263e705c121SKalle Valo * the writeback -- this is DMA memory and an array holding one buffer 264e705c121SKalle Valo * for each command on the queue 2658de437c7SSara Sharon * @first_tb_dma: DMA address for the first_tb_bufs start 266e705c121SKalle Valo * @entries: transmit entries (driver state) 267e705c121SKalle Valo * @lock: queue lock 268e705c121SKalle Valo * @stuck_timer: timer that fires if queue gets stuck 269e705c121SKalle Valo * @trans_pcie: pointer back to transport (for timer) 270e705c121SKalle Valo * @need_update: indicates need to update read/write index 271e705c121SKalle Valo * @active: stores if queue is active 272e705c121SKalle Valo * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 273e705c121SKalle Valo * @wd_timeout: queue watchdog timeout (jiffies) - per queue 274e705c121SKalle Valo * @frozen: tx stuck queue timer is frozen 275e705c121SKalle Valo * @frozen_expiry_remainder: remember how long until the timer fires 276e705c121SKalle Valo * 277e705c121SKalle Valo * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 278e705c121SKalle Valo * descriptors) and required locking structures. 279e705c121SKalle Valo */ 280e705c121SKalle Valo struct iwl_txq { 281e705c121SKalle Valo struct iwl_queue q; 282e705c121SKalle Valo struct iwl_tfd *tfds; 2838de437c7SSara Sharon struct iwl_pcie_first_tb_buf *first_tb_bufs; 2848de437c7SSara Sharon dma_addr_t first_tb_dma; 285e705c121SKalle Valo struct iwl_pcie_txq_entry *entries; 286e705c121SKalle Valo spinlock_t lock; 287e705c121SKalle Valo unsigned long frozen_expiry_remainder; 288e705c121SKalle Valo struct timer_list stuck_timer; 289e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 290e705c121SKalle Valo bool need_update; 291e705c121SKalle Valo bool frozen; 292e705c121SKalle Valo u8 active; 293e705c121SKalle Valo bool ampdu; 2940cd58eaaSEmmanuel Grumbach bool block; 295e705c121SKalle Valo unsigned long wd_timeout; 2963955525dSEmmanuel Grumbach struct sk_buff_head overflow_q; 297e705c121SKalle Valo }; 298e705c121SKalle Valo 299e705c121SKalle Valo static inline dma_addr_t 3008de437c7SSara Sharon iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx) 301e705c121SKalle Valo { 3028de437c7SSara Sharon return txq->first_tb_dma + 3038de437c7SSara Sharon sizeof(struct iwl_pcie_first_tb_buf) * idx; 304e705c121SKalle Valo } 305e705c121SKalle Valo 3066eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page { 3076eb5e529SEmmanuel Grumbach struct page *page; 3086eb5e529SEmmanuel Grumbach u8 *pos; 3096eb5e529SEmmanuel Grumbach }; 3106eb5e529SEmmanuel Grumbach 311e705c121SKalle Valo /** 312e705c121SKalle Valo * struct iwl_trans_pcie - PCIe transport specific data 313e705c121SKalle Valo * @rxq: all the RX queue data 31478485054SSara Sharon * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 31596a6497bSSara Sharon * @global_table: table mapping received VID from hw to rxb 316e705c121SKalle Valo * @rba: allocator for RX replenishing 317e705c121SKalle Valo * @drv - pointer to iwl_drv 318e705c121SKalle Valo * @trans: pointer to the generic transport area 319e705c121SKalle Valo * @scd_base_addr: scheduler sram base address in SRAM 320e705c121SKalle Valo * @scd_bc_tbls: pointer to the byte count table of the scheduler 321e705c121SKalle Valo * @kw: keep warm address 322e705c121SKalle Valo * @pci_dev: basic pci-network driver stuff 323e705c121SKalle Valo * @hw_base: pci hardware address support 324e705c121SKalle Valo * @ucode_write_complete: indicates that the ucode has been copied. 325e705c121SKalle Valo * @ucode_write_waitq: wait queue for uCode load 326e705c121SKalle Valo * @cmd_queue - command queue number 3276c4fbcbcSEmmanuel Grumbach * @rx_buf_size: Rx buffer size 328e705c121SKalle Valo * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 329e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 330e705c121SKalle Valo * @wide_cmd_header: true when ucode supports wide command header format 33141837ca9SEmmanuel Grumbach * @sw_csum_tx: if true, then the transport will compute the csum of the TXed 33241837ca9SEmmanuel Grumbach * frame. 333e705c121SKalle Valo * @rx_page_order: page order for receive buffer size 334e705c121SKalle Valo * @reg_lock: protect hw register access 335e705c121SKalle Valo * @mutex: to protect stop_device / start_fw / start_hw 336e705c121SKalle Valo * @cmd_in_flight: true when we have a host command in flight 337e705c121SKalle Valo * @fw_mon_phys: physical address of the buffer for the firmware monitor 338e705c121SKalle Valo * @fw_mon_page: points to the first page of the buffer for the firmware monitor 339e705c121SKalle Valo * @fw_mon_size: size of the buffer for the firmware monitor 3402e5d4a8fSHaim Dreyfuss * @msix_entries: array of MSI-X entries 3412e5d4a8fSHaim Dreyfuss * @msix_enabled: true if managed to enable MSI-X 3422e5d4a8fSHaim Dreyfuss * @allocated_vector: the number of interrupt vector allocated by the OS 3432e5d4a8fSHaim Dreyfuss * @default_irq_num: default irq for non rx interrupt 3442e5d4a8fSHaim Dreyfuss * @fh_init_mask: initial unmasked fh causes 3452e5d4a8fSHaim Dreyfuss * @hw_init_mask: initial unmasked hw causes 3462e5d4a8fSHaim Dreyfuss * @fh_mask: current unmasked fh causes 3472e5d4a8fSHaim Dreyfuss * @hw_mask: current unmasked hw causes 348e705c121SKalle Valo */ 349e705c121SKalle Valo struct iwl_trans_pcie { 35078485054SSara Sharon struct iwl_rxq *rxq; 3517b542436SSara Sharon struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE]; 35243146925SSara Sharon struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE]; 353e705c121SKalle Valo struct iwl_rb_allocator rba; 354e705c121SKalle Valo struct iwl_trans *trans; 355e705c121SKalle Valo struct iwl_drv *drv; 356e705c121SKalle Valo 357e705c121SKalle Valo struct net_device napi_dev; 358e705c121SKalle Valo 3596eb5e529SEmmanuel Grumbach struct __percpu iwl_tso_hdr_page *tso_hdr_page; 3606eb5e529SEmmanuel Grumbach 361e705c121SKalle Valo /* INT ICT Table */ 362e705c121SKalle Valo __le32 *ict_tbl; 363e705c121SKalle Valo dma_addr_t ict_tbl_dma; 364e705c121SKalle Valo int ict_index; 365e705c121SKalle Valo bool use_ict; 366e705c121SKalle Valo bool is_down; 367e705c121SKalle Valo struct isr_statistics isr_stats; 368e705c121SKalle Valo 369e705c121SKalle Valo spinlock_t irq_lock; 370e705c121SKalle Valo struct mutex mutex; 371e705c121SKalle Valo u32 inta_mask; 372e705c121SKalle Valo u32 scd_base_addr; 373e705c121SKalle Valo struct iwl_dma_ptr scd_bc_tbls; 374e705c121SKalle Valo struct iwl_dma_ptr kw; 375e705c121SKalle Valo 376e705c121SKalle Valo struct iwl_txq *txq; 377e705c121SKalle Valo unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 378e705c121SKalle Valo unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 379e705c121SKalle Valo 380e705c121SKalle Valo /* PCI bus related data */ 381e705c121SKalle Valo struct pci_dev *pci_dev; 382e705c121SKalle Valo void __iomem *hw_base; 383e705c121SKalle Valo 384e705c121SKalle Valo bool ucode_write_complete; 385e705c121SKalle Valo wait_queue_head_t ucode_write_waitq; 386e705c121SKalle Valo wait_queue_head_t wait_command_queue; 3874cbb8e50SLuciano Coelho wait_queue_head_t d0i3_waitq; 388e705c121SKalle Valo 38921cb3222SJohannes Berg u8 page_offs, dev_cmd_offs; 39021cb3222SJohannes Berg 391e705c121SKalle Valo u8 cmd_queue; 392e705c121SKalle Valo u8 cmd_fifo; 393e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 394e705c121SKalle Valo u8 n_no_reclaim_cmds; 395e705c121SKalle Valo u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 396e705c121SKalle Valo 3976c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 398e705c121SKalle Valo bool bc_table_dword; 399e705c121SKalle Valo bool scd_set_active; 400e705c121SKalle Valo bool wide_cmd_header; 40141837ca9SEmmanuel Grumbach bool sw_csum_tx; 402e705c121SKalle Valo u32 rx_page_order; 403e705c121SKalle Valo 404e705c121SKalle Valo /*protect hw register */ 405e705c121SKalle Valo spinlock_t reg_lock; 406e705c121SKalle Valo bool cmd_hold_nic_awake; 407e705c121SKalle Valo bool ref_cmd_in_flight; 408e705c121SKalle Valo 409e705c121SKalle Valo dma_addr_t fw_mon_phys; 410e705c121SKalle Valo struct page *fw_mon_page; 411e705c121SKalle Valo u32 fw_mon_size; 4122e5d4a8fSHaim Dreyfuss 4132e5d4a8fSHaim Dreyfuss struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 4142e5d4a8fSHaim Dreyfuss bool msix_enabled; 4152e5d4a8fSHaim Dreyfuss u32 allocated_vector; 4162e5d4a8fSHaim Dreyfuss u32 default_irq_num; 4172e5d4a8fSHaim Dreyfuss u32 fh_init_mask; 4182e5d4a8fSHaim Dreyfuss u32 hw_init_mask; 4192e5d4a8fSHaim Dreyfuss u32 fh_mask; 4202e5d4a8fSHaim Dreyfuss u32 hw_mask; 421e705c121SKalle Valo }; 422e705c121SKalle Valo 42385e5a387SJohannes Berg static inline struct iwl_trans_pcie * 42485e5a387SJohannes Berg IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 42585e5a387SJohannes Berg { 42685e5a387SJohannes Berg return (void *)trans->trans_specific; 42785e5a387SJohannes Berg } 428e705c121SKalle Valo 429e705c121SKalle Valo static inline struct iwl_trans * 430e705c121SKalle Valo iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 431e705c121SKalle Valo { 432e705c121SKalle Valo return container_of((void *)trans_pcie, struct iwl_trans, 433e705c121SKalle Valo trans_specific); 434e705c121SKalle Valo } 435e705c121SKalle Valo 436e705c121SKalle Valo /* 437e705c121SKalle Valo * Convention: trans API functions: iwl_trans_pcie_XXX 438e705c121SKalle Valo * Other functions: iwl_pcie_XXX 439e705c121SKalle Valo */ 440e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 441e705c121SKalle Valo const struct pci_device_id *ent, 442e705c121SKalle Valo const struct iwl_cfg *cfg); 443e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans); 444e705c121SKalle Valo 445e705c121SKalle Valo /***************************************************** 446e705c121SKalle Valo * RX 447e705c121SKalle Valo ******************************************************/ 448e705c121SKalle Valo int iwl_pcie_rx_init(struct iwl_trans *trans); 4492e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 450e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 4512e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 4522e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 453e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans); 454e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans); 455e705c121SKalle Valo 456e705c121SKalle Valo /***************************************************** 457e705c121SKalle Valo * ICT - interrupt handling 458e705c121SKalle Valo ******************************************************/ 459e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data); 460e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans); 461e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans); 462e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans); 463e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans); 464e705c121SKalle Valo 465e705c121SKalle Valo /***************************************************** 466e705c121SKalle Valo * TX / HCMD 467e705c121SKalle Valo ******************************************************/ 468e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans); 469e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 470e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans); 471e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans); 472e705c121SKalle Valo void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 473e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 474e705c121SKalle Valo unsigned int wdg_timeout); 475e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 476e705c121SKalle Valo bool configure_scd); 47742db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 47842db09c1SLiad Kaufman bool shared_mode); 47938398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, 48038398efbSSara Sharon struct iwl_txq *txq); 481e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 482e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id); 483e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 484e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 485e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 486e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb); 487e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 488e705c121SKalle Valo struct sk_buff_head *skbs); 489e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 490e705c121SKalle Valo 491e705c121SKalle Valo static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) 492e705c121SKalle Valo { 493e705c121SKalle Valo struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 494e705c121SKalle Valo 495e705c121SKalle Valo return le16_to_cpu(tb->hi_n_len) >> 4; 496e705c121SKalle Valo } 497e705c121SKalle Valo 498e705c121SKalle Valo /***************************************************** 499e705c121SKalle Valo * Error handling 500e705c121SKalle Valo ******************************************************/ 501e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans); 502e705c121SKalle Valo 503e705c121SKalle Valo /***************************************************** 504e705c121SKalle Valo * Helpers 505e705c121SKalle Valo ******************************************************/ 506f16c3ebfSEmmanuel Grumbach static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 507e705c121SKalle Valo { 5082e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 509e705c121SKalle Valo 5102e5d4a8fSHaim Dreyfuss clear_bit(STATUS_INT_ENABLED, &trans->status); 5112e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 512e705c121SKalle Valo /* disable interrupts from uCode/NIC to host */ 513e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 514e705c121SKalle Valo 515e705c121SKalle Valo /* acknowledge/clear/reset any interrupts still pending 516e705c121SKalle Valo * from uCode or flow handler (Rx/Tx DMA) */ 517e705c121SKalle Valo iwl_write32(trans, CSR_INT, 0xffffffff); 518e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 5192e5d4a8fSHaim Dreyfuss } else { 5202e5d4a8fSHaim Dreyfuss /* disable all the interrupt we might use */ 5212e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 5222e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 5232e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 5242e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 5252e5d4a8fSHaim Dreyfuss } 526e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 527e705c121SKalle Valo } 528e705c121SKalle Valo 529f16c3ebfSEmmanuel Grumbach static inline void iwl_disable_interrupts(struct iwl_trans *trans) 530f16c3ebfSEmmanuel Grumbach { 531f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 532f16c3ebfSEmmanuel Grumbach 533f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 534f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 535f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 536f16c3ebfSEmmanuel Grumbach } 537f16c3ebfSEmmanuel Grumbach 538f16c3ebfSEmmanuel Grumbach static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 539e705c121SKalle Valo { 540e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 541e705c121SKalle Valo 542e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 543e705c121SKalle Valo set_bit(STATUS_INT_ENABLED, &trans->status); 5442e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 545e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 546e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 5472e5d4a8fSHaim Dreyfuss } else { 5482e5d4a8fSHaim Dreyfuss /* 5492e5d4a8fSHaim Dreyfuss * fh/hw_mask keeps all the unmasked causes. 5502e5d4a8fSHaim Dreyfuss * Unlike msi, in msix cause is enabled when it is unset. 5512e5d4a8fSHaim Dreyfuss */ 5522e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 5532e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 5542e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 5552e5d4a8fSHaim Dreyfuss ~trans_pcie->fh_mask); 5562e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 5572e5d4a8fSHaim Dreyfuss ~trans_pcie->hw_mask); 5582e5d4a8fSHaim Dreyfuss } 5592e5d4a8fSHaim Dreyfuss } 5602e5d4a8fSHaim Dreyfuss 561f16c3ebfSEmmanuel Grumbach static inline void iwl_enable_interrupts(struct iwl_trans *trans) 562f16c3ebfSEmmanuel Grumbach { 563f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 564f16c3ebfSEmmanuel Grumbach 565f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 566f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 567f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 568f16c3ebfSEmmanuel Grumbach } 5692e5d4a8fSHaim Dreyfuss static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 5702e5d4a8fSHaim Dreyfuss { 5712e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 5722e5d4a8fSHaim Dreyfuss 5732e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 5742e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = msk; 5752e5d4a8fSHaim Dreyfuss } 5762e5d4a8fSHaim Dreyfuss 5772e5d4a8fSHaim Dreyfuss static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 5782e5d4a8fSHaim Dreyfuss { 5792e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 5802e5d4a8fSHaim Dreyfuss 5812e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 5822e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = msk; 583e705c121SKalle Valo } 584e705c121SKalle Valo 585a6bd005fSEmmanuel Grumbach static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 586a6bd005fSEmmanuel Grumbach { 587a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 588a6bd005fSEmmanuel Grumbach 589a6bd005fSEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 5902e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 591a6bd005fSEmmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 592a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 5932e5d4a8fSHaim Dreyfuss } else { 5942e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 5952e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 5962e5d4a8fSHaim Dreyfuss iwl_enable_fh_int_msk_msix(trans, 5972e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 5982e5d4a8fSHaim Dreyfuss } 599a6bd005fSEmmanuel Grumbach } 600a6bd005fSEmmanuel Grumbach 601e705c121SKalle Valo static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 602e705c121SKalle Valo { 603e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 604e705c121SKalle Valo 605e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 6062e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 607e705c121SKalle Valo trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 608e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 6092e5d4a8fSHaim Dreyfuss } else { 6102e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 6112e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 6122e5d4a8fSHaim Dreyfuss iwl_enable_hw_int_msk_msix(trans, 6132e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_RF_KILL); 6142e5d4a8fSHaim Dreyfuss } 615e705c121SKalle Valo } 616e705c121SKalle Valo 617e705c121SKalle Valo static inline void iwl_wake_queue(struct iwl_trans *trans, 618e705c121SKalle Valo struct iwl_txq *txq) 619e705c121SKalle Valo { 620e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 621e705c121SKalle Valo 622e705c121SKalle Valo if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) { 623e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id); 624e705c121SKalle Valo iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id); 625e705c121SKalle Valo } 626e705c121SKalle Valo } 627e705c121SKalle Valo 628e705c121SKalle Valo static inline void iwl_stop_queue(struct iwl_trans *trans, 629e705c121SKalle Valo struct iwl_txq *txq) 630e705c121SKalle Valo { 631e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 632e705c121SKalle Valo 633e705c121SKalle Valo if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) { 634e705c121SKalle Valo iwl_op_mode_queue_full(trans->op_mode, txq->q.id); 635e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id); 636e705c121SKalle Valo } else 637e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 638e705c121SKalle Valo txq->q.id); 639e705c121SKalle Valo } 640e705c121SKalle Valo 641e705c121SKalle Valo static inline bool iwl_queue_used(const struct iwl_queue *q, int i) 642e705c121SKalle Valo { 643e705c121SKalle Valo return q->write_ptr >= q->read_ptr ? 644e705c121SKalle Valo (i >= q->read_ptr && i < q->write_ptr) : 645e705c121SKalle Valo !(i < q->read_ptr && i >= q->write_ptr); 646e705c121SKalle Valo } 647e705c121SKalle Valo 648e705c121SKalle Valo static inline u8 get_cmd_index(struct iwl_queue *q, u32 index) 649e705c121SKalle Valo { 650e705c121SKalle Valo return index & (q->n_window - 1); 651e705c121SKalle Valo } 652e705c121SKalle Valo 653e705c121SKalle Valo static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 654e705c121SKalle Valo { 655e705c121SKalle Valo return !(iwl_read32(trans, CSR_GP_CNTRL) & 656e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 657e705c121SKalle Valo } 658e705c121SKalle Valo 659e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 660e705c121SKalle Valo u32 reg, u32 mask, u32 value) 661e705c121SKalle Valo { 662e705c121SKalle Valo u32 v; 663e705c121SKalle Valo 664e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 665e705c121SKalle Valo WARN_ON_ONCE(value & ~mask); 666e705c121SKalle Valo #endif 667e705c121SKalle Valo 668e705c121SKalle Valo v = iwl_read32(trans, reg); 669e705c121SKalle Valo v &= ~mask; 670e705c121SKalle Valo v |= value; 671e705c121SKalle Valo iwl_write32(trans, reg, v); 672e705c121SKalle Valo } 673e705c121SKalle Valo 674e705c121SKalle Valo static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 675e705c121SKalle Valo u32 reg, u32 mask) 676e705c121SKalle Valo { 677e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 678e705c121SKalle Valo } 679e705c121SKalle Valo 680e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 681e705c121SKalle Valo u32 reg, u32 mask) 682e705c121SKalle Valo { 683e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 684e705c121SKalle Valo } 685e705c121SKalle Valo 686e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 687e705c121SKalle Valo 688f8a1edb7SJohannes Berg #ifdef CONFIG_IWLWIFI_DEBUGFS 689f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 690f8a1edb7SJohannes Berg #else 691f8a1edb7SJohannes Berg static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 692f8a1edb7SJohannes Berg { 693f8a1edb7SJohannes Berg return 0; 694f8a1edb7SJohannes Berg } 695f8a1edb7SJohannes Berg #endif 696f8a1edb7SJohannes Berg 6974cbb8e50SLuciano Coelho int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans); 6984cbb8e50SLuciano Coelho int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans); 6994cbb8e50SLuciano Coelho 7001316d595SSara Sharon void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable); 7011316d595SSara Sharon 702e705c121SKalle Valo #endif /* __iwl_trans_int_pcie_h__ */ 703