1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3cefec29eSJohannes Berg * This file is provided under a dual BSD/GPLv2 license. When using or 4cefec29eSJohannes Berg * redistributing this file, you may do so under either license. 5cefec29eSJohannes Berg * 6cefec29eSJohannes Berg * GPL LICENSE SUMMARY 7cefec29eSJohannes Berg * 8e705c121SKalle Valo * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 116cc6ba3aSTriebitz * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 14e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 18e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20e705c121SKalle Valo * more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 23cefec29eSJohannes Berg * file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29cefec29eSJohannes Berg * BSD LICENSE 30cefec29eSJohannes Berg * 31cefec29eSJohannes Berg * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 32cefec29eSJohannes Berg * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33cefec29eSJohannes Berg * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 346cc6ba3aSTriebitz * Copyright(c) 2018 - 2019 Intel Corporation 35cefec29eSJohannes Berg * All rights reserved. 36cefec29eSJohannes Berg * 37cefec29eSJohannes Berg * Redistribution and use in source and binary forms, with or without 38cefec29eSJohannes Berg * modification, are permitted provided that the following conditions 39cefec29eSJohannes Berg * are met: 40cefec29eSJohannes Berg * 41cefec29eSJohannes Berg * * Redistributions of source code must retain the above copyright 42cefec29eSJohannes Berg * notice, this list of conditions and the following disclaimer. 43cefec29eSJohannes Berg * * Redistributions in binary form must reproduce the above copyright 44cefec29eSJohannes Berg * notice, this list of conditions and the following disclaimer in 45cefec29eSJohannes Berg * the documentation and/or other materials provided with the 46cefec29eSJohannes Berg * distribution. 47cefec29eSJohannes Berg * * Neither the name Intel Corporation nor the names of its 48cefec29eSJohannes Berg * contributors may be used to endorse or promote products derived 49cefec29eSJohannes Berg * from this software without specific prior written permission. 50cefec29eSJohannes Berg * 51cefec29eSJohannes Berg * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52cefec29eSJohannes Berg * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53cefec29eSJohannes Berg * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54cefec29eSJohannes Berg * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55cefec29eSJohannes Berg * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56cefec29eSJohannes Berg * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57cefec29eSJohannes Berg * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58cefec29eSJohannes Berg * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59cefec29eSJohannes Berg * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60cefec29eSJohannes Berg * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61cefec29eSJohannes Berg * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62cefec29eSJohannes Berg * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #ifndef __iwl_trans_int_pcie_h__ 65e705c121SKalle Valo #define __iwl_trans_int_pcie_h__ 66e705c121SKalle Valo 67e705c121SKalle Valo #include <linux/spinlock.h> 68e705c121SKalle Valo #include <linux/interrupt.h> 69e705c121SKalle Valo #include <linux/skbuff.h> 70e705c121SKalle Valo #include <linux/wait.h> 71e705c121SKalle Valo #include <linux/pci.h> 72e705c121SKalle Valo #include <linux/timer.h> 737c8d91ebSHaim Dreyfuss #include <linux/cpu.h> 74e705c121SKalle Valo 75e705c121SKalle Valo #include "iwl-fh.h" 76e705c121SKalle Valo #include "iwl-csr.h" 77e705c121SKalle Valo #include "iwl-trans.h" 78e705c121SKalle Valo #include "iwl-debug.h" 79e705c121SKalle Valo #include "iwl-io.h" 80e705c121SKalle Valo #include "iwl-op-mode.h" 81ff932f61SGolan Ben Ami #include "iwl-drv.h" 820cd1ad2dSMordechay Goodstein #include "queue/tx.h" 83e705c121SKalle Valo 84e705c121SKalle Valo /* 85e705c121SKalle Valo * RX related structures and functions 86e705c121SKalle Valo */ 87e705c121SKalle Valo #define RX_NUM_QUEUES 1 88e705c121SKalle Valo #define RX_POST_REQ_ALLOC 2 89e705c121SKalle Valo #define RX_CLAIM_REQ_ALLOC 8 9078485054SSara Sharon #define RX_PENDING_WATERMARK 16 911b493e30SGolan Ben Ami #define FIRST_RX_QUEUE 512 92e705c121SKalle Valo 93e705c121SKalle Valo struct iwl_host_cmd; 94e705c121SKalle Valo 95e705c121SKalle Valo /*This file includes the declaration that are internal to the 96e705c121SKalle Valo * trans_pcie layer */ 97e705c121SKalle Valo 9896a6497bSSara Sharon /** 9996a6497bSSara Sharon * struct iwl_rx_mem_buffer 10096a6497bSSara Sharon * @page_dma: bus address of rxb page 10196a6497bSSara Sharon * @page: driver's pointer to the rxb page 102b1753c62SSara Sharon * @invalid: rxb is in driver ownership - not owned by HW 10396a6497bSSara Sharon * @vid: index of this rxb in the global table 104cfdc20efSJohannes Berg * @offset: indicates which offset of the page (in bytes) 105cfdc20efSJohannes Berg * this buffer uses (if multiple RBs fit into one page) 10696a6497bSSara Sharon */ 107e705c121SKalle Valo struct iwl_rx_mem_buffer { 108e705c121SKalle Valo dma_addr_t page_dma; 109e705c121SKalle Valo struct page *page; 11096a6497bSSara Sharon u16 vid; 111b1753c62SSara Sharon bool invalid; 112e705c121SKalle Valo struct list_head list; 113cfdc20efSJohannes Berg u32 offset; 114e705c121SKalle Valo }; 115e705c121SKalle Valo 116e705c121SKalle Valo /** 117e705c121SKalle Valo * struct isr_statistics - interrupt statistics 118e705c121SKalle Valo * 119e705c121SKalle Valo */ 120e705c121SKalle Valo struct isr_statistics { 121e705c121SKalle Valo u32 hw; 122e705c121SKalle Valo u32 sw; 123e705c121SKalle Valo u32 err_code; 124e705c121SKalle Valo u32 sch; 125e705c121SKalle Valo u32 alive; 126e705c121SKalle Valo u32 rfkill; 127e705c121SKalle Valo u32 ctkill; 128e705c121SKalle Valo u32 wakeup; 129e705c121SKalle Valo u32 rx; 130e705c121SKalle Valo u32 tx; 131e705c121SKalle Valo u32 unhandled; 132e705c121SKalle Valo }; 133e705c121SKalle Valo 134cf495496SGolan Ben Ami /** 135cf495496SGolan Ben Ami * struct iwl_rx_transfer_desc - transfer descriptor 136cf495496SGolan Ben Ami * @addr: ptr to free buffer start address 137cf495496SGolan Ben Ami * @rbid: unique tag of the buffer 138cf495496SGolan Ben Ami * @reserved: reserved 139cf495496SGolan Ben Ami */ 140cf495496SGolan Ben Ami struct iwl_rx_transfer_desc { 141cf495496SGolan Ben Ami __le16 rbid; 142f826faaaSJohannes Berg __le16 reserved[3]; 143f826faaaSJohannes Berg __le64 addr; 144cf495496SGolan Ben Ami } __packed; 145cf495496SGolan Ben Ami 146f826faaaSJohannes Berg #define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0) 147cf495496SGolan Ben Ami 148cf495496SGolan Ben Ami /** 149cf495496SGolan Ben Ami * struct iwl_rx_completion_desc - completion descriptor 150cf495496SGolan Ben Ami * @reserved1: reserved 151cf495496SGolan Ben Ami * @rbid: unique tag of the received buffer 152f826faaaSJohannes Berg * @flags: flags (0: fragmented, all others: reserved) 153cf495496SGolan Ben Ami * @reserved2: reserved 154cf495496SGolan Ben Ami */ 155cf495496SGolan Ben Ami struct iwl_rx_completion_desc { 156f826faaaSJohannes Berg __le32 reserved1; 157cf495496SGolan Ben Ami __le16 rbid; 158f826faaaSJohannes Berg u8 flags; 159f826faaaSJohannes Berg u8 reserved2[25]; 160cf495496SGolan Ben Ami } __packed; 161cf495496SGolan Ben Ami 162e705c121SKalle Valo /** 163e705c121SKalle Valo * struct iwl_rxq - Rx queue 16496a6497bSSara Sharon * @id: queue index 16596a6497bSSara Sharon * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 16696a6497bSSara Sharon * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 1673681021fSJohannes Berg * In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's 168e705c121SKalle Valo * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 16996a6497bSSara Sharon * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd) 17096a6497bSSara Sharon * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd) 1711b493e30SGolan Ben Ami * @tr_tail: driver's pointer to the transmission ring tail buffer 1721b493e30SGolan Ben Ami * @tr_tail_dma: physical address of the buffer for the transmission ring tail 1731b493e30SGolan Ben Ami * @cr_tail: driver's pointer to the completion ring tail buffer 1741b493e30SGolan Ben Ami * @cr_tail_dma: physical address of the buffer for the completion ring tail 175e705c121SKalle Valo * @read: Shared index to newest available Rx buffer 176e705c121SKalle Valo * @write: Shared index to oldest written Rx packet 177e705c121SKalle Valo * @free_count: Number of pre-allocated buffers in rx_free 178e705c121SKalle Valo * @used_count: Number of RBDs handled to allocator to use for allocation 179e705c121SKalle Valo * @write_actual: 180e705c121SKalle Valo * @rx_free: list of RBDs with allocated RB ready for use 181e705c121SKalle Valo * @rx_used: list of RBDs with no RB attached 182e705c121SKalle Valo * @need_update: flag to indicate we need to update read/write index 183e705c121SKalle Valo * @rb_stts: driver's pointer to receive buffer status 184e705c121SKalle Valo * @rb_stts_dma: bus address of receive buffer status 185e705c121SKalle Valo * @lock: 18696a6497bSSara Sharon * @queue: actual rx queue. Not used for multi-rx queue. 187b1c860f6SJohannes Berg * @next_rb_is_fragment: indicates that the previous RB that we handled set 188b1c860f6SJohannes Berg * the fragmented flag, so the next one is still another fragment 189e705c121SKalle Valo * 190e705c121SKalle Valo * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 191e705c121SKalle Valo */ 192e705c121SKalle Valo struct iwl_rxq { 19396a6497bSSara Sharon int id; 19496a6497bSSara Sharon void *bd; 195e705c121SKalle Valo dma_addr_t bd_dma; 196b2a58c97SSara Sharon union { 1970307c839SGolan Ben Ami void *used_bd; 198b2a58c97SSara Sharon __le32 *bd_32; 199b2a58c97SSara Sharon struct iwl_rx_completion_desc *cd; 200b2a58c97SSara Sharon }; 20196a6497bSSara Sharon dma_addr_t used_bd_dma; 2021b493e30SGolan Ben Ami __le16 *tr_tail; 2031b493e30SGolan Ben Ami dma_addr_t tr_tail_dma; 2041b493e30SGolan Ben Ami __le16 *cr_tail; 2051b493e30SGolan Ben Ami dma_addr_t cr_tail_dma; 206e705c121SKalle Valo u32 read; 207e705c121SKalle Valo u32 write; 208e705c121SKalle Valo u32 free_count; 209e705c121SKalle Valo u32 used_count; 210e705c121SKalle Valo u32 write_actual; 21196a6497bSSara Sharon u32 queue_size; 212e705c121SKalle Valo struct list_head rx_free; 213e705c121SKalle Valo struct list_head rx_used; 214b1c860f6SJohannes Berg bool need_update, next_rb_is_fragment; 2150307c839SGolan Ben Ami void *rb_stts; 216e705c121SKalle Valo dma_addr_t rb_stts_dma; 217e705c121SKalle Valo spinlock_t lock; 218bce97731SSara Sharon struct napi_struct napi; 219e705c121SKalle Valo struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 220e705c121SKalle Valo }; 221e705c121SKalle Valo 222e705c121SKalle Valo /** 223e705c121SKalle Valo * struct iwl_rb_allocator - Rx allocator 224e705c121SKalle Valo * @req_pending: number of requests the allcator had not processed yet 225e705c121SKalle Valo * @req_ready: number of requests honored and ready for claiming 226e705c121SKalle Valo * @rbd_allocated: RBDs with pages allocated and ready to be handled to 227e705c121SKalle Valo * the queue. This is a list of &struct iwl_rx_mem_buffer 228e705c121SKalle Valo * @rbd_empty: RBDs with no page attached for allocator use. This is a list 229e705c121SKalle Valo * of &struct iwl_rx_mem_buffer 230e705c121SKalle Valo * @lock: protects the rbd_allocated and rbd_empty lists 231e705c121SKalle Valo * @alloc_wq: work queue for background calls 232e705c121SKalle Valo * @rx_alloc: work struct for background calls 233e705c121SKalle Valo */ 234e705c121SKalle Valo struct iwl_rb_allocator { 235e705c121SKalle Valo atomic_t req_pending; 236e705c121SKalle Valo atomic_t req_ready; 237e705c121SKalle Valo struct list_head rbd_allocated; 238e705c121SKalle Valo struct list_head rbd_empty; 239e705c121SKalle Valo spinlock_t lock; 240e705c121SKalle Valo struct workqueue_struct *alloc_wq; 241e705c121SKalle Valo struct work_struct rx_alloc; 242e705c121SKalle Valo }; 243e705c121SKalle Valo 244e705c121SKalle Valo /** 2450307c839SGolan Ben Ami * iwl_get_closed_rb_stts - get closed rb stts from different structs 2460307c839SGolan Ben Ami * @rxq - the rxq to get the rb stts from 2470307c839SGolan Ben Ami */ 2480307c839SGolan Ben Ami static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans, 2490307c839SGolan Ben Ami struct iwl_rxq *rxq) 2500307c839SGolan Ben Ami { 2513681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 2520307c839SGolan Ben Ami __le16 *rb_stts = rxq->rb_stts; 2530307c839SGolan Ben Ami 2540307c839SGolan Ben Ami return READ_ONCE(*rb_stts); 2550307c839SGolan Ben Ami } else { 2560307c839SGolan Ben Ami struct iwl_rb_status *rb_stts = rxq->rb_stts; 2570307c839SGolan Ben Ami 2580307c839SGolan Ben Ami return READ_ONCE(rb_stts->closed_rb_num); 2590307c839SGolan Ben Ami } 2600307c839SGolan Ben Ami } 2610307c839SGolan Ben Ami 262f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 263f7805b33SLior Cohen /** 264f7805b33SLior Cohen * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data 265f7805b33SLior Cohen * debugfs file 266f7805b33SLior Cohen * 267f7805b33SLior Cohen * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed. 268f7805b33SLior Cohen * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open. 269f7805b33SLior Cohen * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is 270f7805b33SLior Cohen * set the file can no longer be used. 271f7805b33SLior Cohen */ 272f7805b33SLior Cohen enum iwl_fw_mon_dbgfs_state { 273f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_CLOSED, 274f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_OPEN, 275f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED, 276f7805b33SLior Cohen }; 277f7805b33SLior Cohen #endif 278f7805b33SLior Cohen 279e705c121SKalle Valo /** 280496d83caSHaim Dreyfuss * enum iwl_shared_irq_flags - level of sharing for irq 281496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 282496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 283496d83caSHaim Dreyfuss */ 284496d83caSHaim Dreyfuss enum iwl_shared_irq_flags { 285496d83caSHaim Dreyfuss IWL_SHARED_IRQ_NON_RX = BIT(0), 286496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 287496d83caSHaim Dreyfuss }; 288496d83caSHaim Dreyfuss 289496d83caSHaim Dreyfuss /** 2909b58419eSGolan Ben Ami * enum iwl_image_response_code - image response values 2919b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_DEF: the default value of the register 2929b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully 2939b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_FAIL: iml reading failed 2949b58419eSGolan Ben Ami */ 2959b58419eSGolan Ben Ami enum iwl_image_response_code { 2969b58419eSGolan Ben Ami IWL_IMAGE_RESP_DEF = 0, 2979b58419eSGolan Ben Ami IWL_IMAGE_RESP_SUCCESS = 1, 2989b58419eSGolan Ben Ami IWL_IMAGE_RESP_FAIL = 2, 2999b58419eSGolan Ben Ami }; 3009b58419eSGolan Ben Ami 3019b58419eSGolan Ben Ami /** 302f7805b33SLior Cohen * struct cont_rec: continuous recording data structure 303f7805b33SLior Cohen * @prev_wr_ptr: the last address that was read in monitor_data 304f7805b33SLior Cohen * debugfs file 305f7805b33SLior Cohen * @prev_wrap_cnt: the wrap count that was used during the last read in 306f7805b33SLior Cohen * monitor_data debugfs file 307f7805b33SLior Cohen * @state: the state of monitor_data debugfs file as described 308f7805b33SLior Cohen * in &iwl_fw_mon_dbgfs_state enum 309f7805b33SLior Cohen * @mutex: locked while reading from monitor_data debugfs file 310f7805b33SLior Cohen */ 311f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 312f7805b33SLior Cohen struct cont_rec { 313f7805b33SLior Cohen u32 prev_wr_ptr; 314f7805b33SLior Cohen u32 prev_wrap_cnt; 315f7805b33SLior Cohen u8 state; 316f7805b33SLior Cohen /* Used to sync monitor_data debugfs file with driver unload flow */ 317f7805b33SLior Cohen struct mutex mutex; 318f7805b33SLior Cohen }; 319f7805b33SLior Cohen #endif 320f7805b33SLior Cohen 321f7805b33SLior Cohen /** 322e705c121SKalle Valo * struct iwl_trans_pcie - PCIe transport specific data 323e705c121SKalle Valo * @rxq: all the RX queue data 32478485054SSara Sharon * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 32596a6497bSSara Sharon * @global_table: table mapping received VID from hw to rxb 326e705c121SKalle Valo * @rba: allocator for RX replenishing 327eda50cdeSSara Sharon * @ctxt_info: context information for FW self init 3282ee82402SGolan Ben Ami * @ctxt_info_gen3: context information for gen3 devices 3292ee82402SGolan Ben Ami * @prph_info: prph info for self init 3302ee82402SGolan Ben Ami * @prph_scratch: prph scratch for self init 3312ee82402SGolan Ben Ami * @ctxt_info_dma_addr: dma addr of context information 3322ee82402SGolan Ben Ami * @prph_info_dma_addr: dma addr of prph info 3332ee82402SGolan Ben Ami * @prph_scratch_dma_addr: dma addr of prph scratch 334eda50cdeSSara Sharon * @ctxt_info_dma_addr: dma addr of context information 335eda50cdeSSara Sharon * @init_dram: DRAM data of firmware image (including paging). 336eda50cdeSSara Sharon * Context information addresses will be taken from here. 337eda50cdeSSara Sharon * This is driver's local copy for keeping track of size and 338eda50cdeSSara Sharon * count for allocating and freeing the memory. 339e705c121SKalle Valo * @trans: pointer to the generic transport area 340e705c121SKalle Valo * @scd_base_addr: scheduler sram base address in SRAM 341e705c121SKalle Valo * @scd_bc_tbls: pointer to the byte count table of the scheduler 342e705c121SKalle Valo * @kw: keep warm address 343e705c121SKalle Valo * @pci_dev: basic pci-network driver stuff 344e705c121SKalle Valo * @hw_base: pci hardware address support 345e705c121SKalle Valo * @ucode_write_complete: indicates that the ucode has been copied. 346e705c121SKalle Valo * @ucode_write_waitq: wait queue for uCode load 347e705c121SKalle Valo * @cmd_queue - command queue number 3489416560eSGolan Ben Ami * @def_rx_queue - default rx queue number 3496c4fbcbcSEmmanuel Grumbach * @rx_buf_size: Rx buffer size 350e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 35141837ca9SEmmanuel Grumbach * @sw_csum_tx: if true, then the transport will compute the csum of the TXed 35241837ca9SEmmanuel Grumbach * frame. 353e705c121SKalle Valo * @rx_page_order: page order for receive buffer size 35480084e35SJohannes Berg * @rx_buf_bytes: RX buffer (RB) size in bytes 355e705c121SKalle Valo * @reg_lock: protect hw register access 356e705c121SKalle Valo * @mutex: to protect stop_device / start_fw / start_hw 357e705c121SKalle Valo * @cmd_in_flight: true when we have a host command in flight 358f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 359f7805b33SLior Cohen * @fw_mon_data: fw continuous recording data 360f7805b33SLior Cohen #endif 3612e5d4a8fSHaim Dreyfuss * @msix_entries: array of MSI-X entries 3622e5d4a8fSHaim Dreyfuss * @msix_enabled: true if managed to enable MSI-X 363496d83caSHaim Dreyfuss * @shared_vec_mask: the type of causes the shared vector handles 364496d83caSHaim Dreyfuss * (see iwl_shared_irq_flags). 365496d83caSHaim Dreyfuss * @alloc_vecs: the number of interrupt vectors allocated by the OS 366496d83caSHaim Dreyfuss * @def_irq: default irq for non rx causes 3672e5d4a8fSHaim Dreyfuss * @fh_init_mask: initial unmasked fh causes 3682e5d4a8fSHaim Dreyfuss * @hw_init_mask: initial unmasked hw causes 3692e5d4a8fSHaim Dreyfuss * @fh_mask: current unmasked fh causes 3702e5d4a8fSHaim Dreyfuss * @hw_mask: current unmasked hw causes 37149564a80SLuca Coelho * @in_rescan: true if we have triggered a device rescan 3726cc6ba3aSTriebitz * @base_rb_stts: base virtual address of receive buffer status for all queues 3736cc6ba3aSTriebitz * @base_rb_stts_dma: base physical address of receive buffer status 374cfdc20efSJohannes Berg * @supported_dma_mask: DMA mask to validate the actual address against, 375cfdc20efSJohannes Berg * will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device 376cfdc20efSJohannes Berg * @alloc_page_lock: spinlock for the page allocator 377cfdc20efSJohannes Berg * @alloc_page: allocated page to still use parts of 378cfdc20efSJohannes Berg * @alloc_page_used: how much of the allocated page was already used (bytes) 379e705c121SKalle Valo */ 380e705c121SKalle Valo struct iwl_trans_pcie { 38178485054SSara Sharon struct iwl_rxq *rxq; 382c042f0c7SJohannes Berg struct iwl_rx_mem_buffer *rx_pool; 383c042f0c7SJohannes Berg struct iwl_rx_mem_buffer **global_table; 384e705c121SKalle Valo struct iwl_rb_allocator rba; 3852ee82402SGolan Ben Ami union { 386eda50cdeSSara Sharon struct iwl_context_info *ctxt_info; 3872ee82402SGolan Ben Ami struct iwl_context_info_gen3 *ctxt_info_gen3; 3882ee82402SGolan Ben Ami }; 3892ee82402SGolan Ben Ami struct iwl_prph_info *prph_info; 3902ee82402SGolan Ben Ami struct iwl_prph_scratch *prph_scratch; 391eda50cdeSSara Sharon dma_addr_t ctxt_info_dma_addr; 3922ee82402SGolan Ben Ami dma_addr_t prph_info_dma_addr; 3932ee82402SGolan Ben Ami dma_addr_t prph_scratch_dma_addr; 3942ee82402SGolan Ben Ami dma_addr_t iml_dma_addr; 395e705c121SKalle Valo struct iwl_trans *trans; 396e705c121SKalle Valo 397e705c121SKalle Valo struct net_device napi_dev; 398e705c121SKalle Valo 399e705c121SKalle Valo /* INT ICT Table */ 400e705c121SKalle Valo __le32 *ict_tbl; 401e705c121SKalle Valo dma_addr_t ict_tbl_dma; 402e705c121SKalle Valo int ict_index; 403e705c121SKalle Valo bool use_ict; 404326477e4SJohannes Berg bool is_down, opmode_down; 405c5bf4fa1SJohannes Berg s8 debug_rfkill; 406e705c121SKalle Valo struct isr_statistics isr_stats; 407e705c121SKalle Valo 408e705c121SKalle Valo spinlock_t irq_lock; 409e705c121SKalle Valo struct mutex mutex; 410e705c121SKalle Valo u32 inta_mask; 411e705c121SKalle Valo u32 scd_base_addr; 412e705c121SKalle Valo struct iwl_dma_ptr scd_bc_tbls; 413e705c121SKalle Valo struct iwl_dma_ptr kw; 414e705c121SKalle Valo 415b2a3b1c1SSara Sharon struct iwl_txq *txq_memory; 416e705c121SKalle Valo 417e705c121SKalle Valo /* PCI bus related data */ 418e705c121SKalle Valo struct pci_dev *pci_dev; 419e705c121SKalle Valo void __iomem *hw_base; 420e705c121SKalle Valo 421e705c121SKalle Valo bool ucode_write_complete; 422e5f3f215SHaim Dreyfuss bool sx_complete; 423e705c121SKalle Valo wait_queue_head_t ucode_write_waitq; 424e705c121SKalle Valo wait_queue_head_t wait_command_queue; 425e5f3f215SHaim Dreyfuss wait_queue_head_t sx_waitq; 426e705c121SKalle Valo 4279416560eSGolan Ben Ami u8 def_rx_queue; 428e705c121SKalle Valo u8 n_no_reclaim_cmds; 429e705c121SKalle Valo u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 430c042f0c7SJohannes Berg u16 num_rx_bufs; 431e705c121SKalle Valo 4326c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 433e705c121SKalle Valo bool scd_set_active; 43441837ca9SEmmanuel Grumbach bool sw_csum_tx; 435a6d24fadSRajat Jain bool pcie_dbg_dumped_once; 436e705c121SKalle Valo u32 rx_page_order; 43780084e35SJohannes Berg u32 rx_buf_bytes; 438cfdc20efSJohannes Berg u32 supported_dma_mask; 439cfdc20efSJohannes Berg 440cfdc20efSJohannes Berg /* allocator lock for the two values below */ 441cfdc20efSJohannes Berg spinlock_t alloc_page_lock; 442cfdc20efSJohannes Berg struct page *alloc_page; 443cfdc20efSJohannes Berg u32 alloc_page_used; 444e705c121SKalle Valo 445e705c121SKalle Valo /*protect hw register */ 446e705c121SKalle Valo spinlock_t reg_lock; 447e705c121SKalle Valo bool cmd_hold_nic_awake; 448e705c121SKalle Valo 449f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 450f7805b33SLior Cohen struct cont_rec fw_mon_data; 451f7805b33SLior Cohen #endif 452f7805b33SLior Cohen 4532e5d4a8fSHaim Dreyfuss struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 4542e5d4a8fSHaim Dreyfuss bool msix_enabled; 455496d83caSHaim Dreyfuss u8 shared_vec_mask; 456496d83caSHaim Dreyfuss u32 alloc_vecs; 457496d83caSHaim Dreyfuss u32 def_irq; 4582e5d4a8fSHaim Dreyfuss u32 fh_init_mask; 4592e5d4a8fSHaim Dreyfuss u32 hw_init_mask; 4602e5d4a8fSHaim Dreyfuss u32 fh_mask; 4612e5d4a8fSHaim Dreyfuss u32 hw_mask; 4627c8d91ebSHaim Dreyfuss cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 46349564a80SLuca Coelho u16 tx_cmd_queue_size; 46449564a80SLuca Coelho bool in_rescan; 4656cc6ba3aSTriebitz 4666cc6ba3aSTriebitz void *base_rb_stts; 4676cc6ba3aSTriebitz dma_addr_t base_rb_stts_dma; 468e705c121SKalle Valo }; 469e705c121SKalle Valo 47085e5a387SJohannes Berg static inline struct iwl_trans_pcie * 47185e5a387SJohannes Berg IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 47285e5a387SJohannes Berg { 47385e5a387SJohannes Berg return (void *)trans->trans_specific; 47485e5a387SJohannes Berg } 475e705c121SKalle Valo 476ff932f61SGolan Ben Ami static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, 477ff932f61SGolan Ben Ami struct msix_entry *entry) 478ff932f61SGolan Ben Ami { 479ff932f61SGolan Ben Ami /* 480ff932f61SGolan Ben Ami * Before sending the interrupt the HW disables it to prevent 481ff932f61SGolan Ben Ami * a nested interrupt. This is done by writing 1 to the corresponding 482ff932f61SGolan Ben Ami * bit in the mask register. After handling the interrupt, it should be 483ff932f61SGolan Ben Ami * re-enabled by clearing this bit. This register is defined as 484ff932f61SGolan Ben Ami * write 1 clear (W1C) register, meaning that it's being clear 485ff932f61SGolan Ben Ami * by writing 1 to the bit. 486ff932f61SGolan Ben Ami */ 487ff932f61SGolan Ben Ami iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); 488ff932f61SGolan Ben Ami } 489ff932f61SGolan Ben Ami 490e705c121SKalle Valo static inline struct iwl_trans * 491e705c121SKalle Valo iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 492e705c121SKalle Valo { 493e705c121SKalle Valo return container_of((void *)trans_pcie, struct iwl_trans, 494e705c121SKalle Valo trans_specific); 495e705c121SKalle Valo } 496e705c121SKalle Valo 497e705c121SKalle Valo /* 498e705c121SKalle Valo * Convention: trans API functions: iwl_trans_pcie_XXX 499e705c121SKalle Valo * Other functions: iwl_pcie_XXX 500e705c121SKalle Valo */ 5017e8258c0SLuca Coelho struct iwl_trans 5027e8258c0SLuca Coelho *iwl_trans_pcie_alloc(struct pci_dev *pdev, 503e705c121SKalle Valo const struct pci_device_id *ent, 5047e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans); 505e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans); 506e705c121SKalle Valo 507e705c121SKalle Valo /***************************************************** 508e705c121SKalle Valo * RX 509e705c121SKalle Valo ******************************************************/ 510e705c121SKalle Valo int iwl_pcie_rx_init(struct iwl_trans *trans); 511eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 5122e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 513e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 5142e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 5152e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 516e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans); 517e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans); 518ff932f61SGolan Ben Ami void iwl_pcie_free_rbs_pool(struct iwl_trans *trans); 519ff932f61SGolan Ben Ami void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq); 520ff932f61SGolan Ben Ami int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget); 521ff932f61SGolan Ben Ami void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 522ff932f61SGolan Ben Ami struct iwl_rxq *rxq); 523e705c121SKalle Valo 524e705c121SKalle Valo /***************************************************** 525e705c121SKalle Valo * ICT - interrupt handling 526e705c121SKalle Valo ******************************************************/ 527e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data); 528e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans); 529e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans); 530e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans); 531e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans); 532e705c121SKalle Valo 533e705c121SKalle Valo /***************************************************** 534e705c121SKalle Valo * TX / HCMD 535e705c121SKalle Valo ******************************************************/ 536e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans); 537e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 538e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans); 539e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans); 540dcfbd67bSEmmanuel Grumbach bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 541e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 542e705c121SKalle Valo unsigned int wdg_timeout); 543e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 544e705c121SKalle Valo bool configure_scd); 54542db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 54642db09c1SLiad Kaufman bool shared_mode); 547e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 548a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd, int txq_id); 549e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 550e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 551e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 552e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb); 553e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 554e705c121SKalle Valo struct sk_buff_head *skbs); 555ba7136f3SAlex Malamud void iwl_trans_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr); 556e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 557e705c121SKalle Valo 558cc2f41f8SJohannes Berg static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd, 5596983ba69SSara Sharon u8 idx) 560e705c121SKalle Valo { 561286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 562cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 563cc2f41f8SJohannes Berg struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 5646983ba69SSara Sharon 5656983ba69SSara Sharon return le16_to_cpu(tb->tb_len); 566cc2f41f8SJohannes Berg } else { 567cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 568cc2f41f8SJohannes Berg struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 569e705c121SKalle Valo 570e705c121SKalle Valo return le16_to_cpu(tb->hi_n_len) >> 4; 571e705c121SKalle Valo } 572cc2f41f8SJohannes Berg } 573e705c121SKalle Valo 574e705c121SKalle Valo /***************************************************** 575e705c121SKalle Valo * Error handling 576e705c121SKalle Valo ******************************************************/ 577e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans); 578e705c121SKalle Valo 579e705c121SKalle Valo /***************************************************** 580e705c121SKalle Valo * Helpers 581e705c121SKalle Valo ******************************************************/ 582f16c3ebfSEmmanuel Grumbach static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 583e705c121SKalle Valo { 5842e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 585e705c121SKalle Valo 5862e5d4a8fSHaim Dreyfuss clear_bit(STATUS_INT_ENABLED, &trans->status); 5872e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 588e705c121SKalle Valo /* disable interrupts from uCode/NIC to host */ 589e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000); 590e705c121SKalle Valo 591e705c121SKalle Valo /* acknowledge/clear/reset any interrupts still pending 592e705c121SKalle Valo * from uCode or flow handler (Rx/Tx DMA) */ 593e705c121SKalle Valo iwl_write32(trans, CSR_INT, 0xffffffff); 594e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 5952e5d4a8fSHaim Dreyfuss } else { 5962e5d4a8fSHaim Dreyfuss /* disable all the interrupt we might use */ 5972e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 5982e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 5992e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 6002e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 6012e5d4a8fSHaim Dreyfuss } 602e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 603e705c121SKalle Valo } 604e705c121SKalle Valo 6052ee82402SGolan Ben Ami #define IWL_NUM_OF_COMPLETION_RINGS 31 6062ee82402SGolan Ben Ami #define IWL_NUM_OF_TRANSFER_RINGS 527 6072ee82402SGolan Ben Ami 6082ee82402SGolan Ben Ami static inline int iwl_pcie_get_num_sections(const struct fw_img *fw, 6092ee82402SGolan Ben Ami int start) 6102ee82402SGolan Ben Ami { 6112ee82402SGolan Ben Ami int i = 0; 6122ee82402SGolan Ben Ami 6132ee82402SGolan Ben Ami while (start < fw->num_sec && 6142ee82402SGolan Ben Ami fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && 6152ee82402SGolan Ben Ami fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { 6162ee82402SGolan Ben Ami start++; 6172ee82402SGolan Ben Ami i++; 6182ee82402SGolan Ben Ami } 6192ee82402SGolan Ben Ami 6202ee82402SGolan Ben Ami return i; 6212ee82402SGolan Ben Ami } 6222ee82402SGolan Ben Ami 6232ee82402SGolan Ben Ami static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans) 6242ee82402SGolan Ben Ami { 625505a00c0SShahar S Matityahu struct iwl_self_init_dram *dram = &trans->init_dram; 6262ee82402SGolan Ben Ami int i; 6272ee82402SGolan Ben Ami 6282ee82402SGolan Ben Ami if (!dram->fw) { 6292ee82402SGolan Ben Ami WARN_ON(dram->fw_cnt); 6302ee82402SGolan Ben Ami return; 6312ee82402SGolan Ben Ami } 6322ee82402SGolan Ben Ami 6332ee82402SGolan Ben Ami for (i = 0; i < dram->fw_cnt; i++) 6342ee82402SGolan Ben Ami dma_free_coherent(trans->dev, dram->fw[i].size, 6352ee82402SGolan Ben Ami dram->fw[i].block, dram->fw[i].physical); 6362ee82402SGolan Ben Ami 6372ee82402SGolan Ben Ami kfree(dram->fw); 6382ee82402SGolan Ben Ami dram->fw_cnt = 0; 6392ee82402SGolan Ben Ami dram->fw = NULL; 6402ee82402SGolan Ben Ami } 6412ee82402SGolan Ben Ami 642f16c3ebfSEmmanuel Grumbach static inline void iwl_disable_interrupts(struct iwl_trans *trans) 643f16c3ebfSEmmanuel Grumbach { 644f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 645f16c3ebfSEmmanuel Grumbach 646f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 647f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans); 648f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 649f16c3ebfSEmmanuel Grumbach } 650f16c3ebfSEmmanuel Grumbach 651f16c3ebfSEmmanuel Grumbach static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 652e705c121SKalle Valo { 653e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 654e705c121SKalle Valo 655e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 656e705c121SKalle Valo set_bit(STATUS_INT_ENABLED, &trans->status); 6572e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 658e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 659e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 6602e5d4a8fSHaim Dreyfuss } else { 6612e5d4a8fSHaim Dreyfuss /* 6622e5d4a8fSHaim Dreyfuss * fh/hw_mask keeps all the unmasked causes. 6632e5d4a8fSHaim Dreyfuss * Unlike msi, in msix cause is enabled when it is unset. 6642e5d4a8fSHaim Dreyfuss */ 6652e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 6662e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 6672e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 6682e5d4a8fSHaim Dreyfuss ~trans_pcie->fh_mask); 6692e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 6702e5d4a8fSHaim Dreyfuss ~trans_pcie->hw_mask); 6712e5d4a8fSHaim Dreyfuss } 6722e5d4a8fSHaim Dreyfuss } 6732e5d4a8fSHaim Dreyfuss 674f16c3ebfSEmmanuel Grumbach static inline void iwl_enable_interrupts(struct iwl_trans *trans) 675f16c3ebfSEmmanuel Grumbach { 676f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 677f16c3ebfSEmmanuel Grumbach 678f16c3ebfSEmmanuel Grumbach spin_lock(&trans_pcie->irq_lock); 679f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans); 680f16c3ebfSEmmanuel Grumbach spin_unlock(&trans_pcie->irq_lock); 681f16c3ebfSEmmanuel Grumbach } 6822e5d4a8fSHaim Dreyfuss static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 6832e5d4a8fSHaim Dreyfuss { 6842e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 6852e5d4a8fSHaim Dreyfuss 6862e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 6872e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = msk; 6882e5d4a8fSHaim Dreyfuss } 6892e5d4a8fSHaim Dreyfuss 6902e5d4a8fSHaim Dreyfuss static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 6912e5d4a8fSHaim Dreyfuss { 6922e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 6932e5d4a8fSHaim Dreyfuss 6942e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 6952e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = msk; 696e705c121SKalle Valo } 697e705c121SKalle Valo 698a6bd005fSEmmanuel Grumbach static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 699a6bd005fSEmmanuel Grumbach { 700a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 701a6bd005fSEmmanuel Grumbach 702a6bd005fSEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 7032e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 704a6bd005fSEmmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 705a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 7062e5d4a8fSHaim Dreyfuss } else { 7072e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 7082e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask); 7092e5d4a8fSHaim Dreyfuss iwl_enable_fh_int_msk_msix(trans, 7102e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 7112e5d4a8fSHaim Dreyfuss } 712a6bd005fSEmmanuel Grumbach } 713a6bd005fSEmmanuel Grumbach 714ed3e4c6dSEmmanuel Grumbach static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans) 715ed3e4c6dSEmmanuel Grumbach { 716ed3e4c6dSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 717ed3e4c6dSEmmanuel Grumbach 718ed3e4c6dSEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n"); 719ed3e4c6dSEmmanuel Grumbach 720ed3e4c6dSEmmanuel Grumbach if (!trans_pcie->msix_enabled) { 721ed3e4c6dSEmmanuel Grumbach /* 722ed3e4c6dSEmmanuel Grumbach * When we'll receive the ALIVE interrupt, the ISR will call 723ed3e4c6dSEmmanuel Grumbach * iwl_enable_fw_load_int_ctx_info again to set the ALIVE 724ed3e4c6dSEmmanuel Grumbach * interrupt (which is not really needed anymore) but also the 725ed3e4c6dSEmmanuel Grumbach * RX interrupt which will allow us to receive the ALIVE 726ed3e4c6dSEmmanuel Grumbach * notification (which is Rx) and continue the flow. 727ed3e4c6dSEmmanuel Grumbach */ 728ed3e4c6dSEmmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX; 729ed3e4c6dSEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 730ed3e4c6dSEmmanuel Grumbach } else { 731ed3e4c6dSEmmanuel Grumbach iwl_enable_hw_int_msk_msix(trans, 732ed3e4c6dSEmmanuel Grumbach MSIX_HW_INT_CAUSES_REG_ALIVE); 733ed3e4c6dSEmmanuel Grumbach /* 734ed3e4c6dSEmmanuel Grumbach * Leave all the FH causes enabled to get the ALIVE 735ed3e4c6dSEmmanuel Grumbach * notification. 736ed3e4c6dSEmmanuel Grumbach */ 737ed3e4c6dSEmmanuel Grumbach iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask); 738ed3e4c6dSEmmanuel Grumbach } 739ed3e4c6dSEmmanuel Grumbach } 740ed3e4c6dSEmmanuel Grumbach 741ff932f61SGolan Ben Ami static inline const char *queue_name(struct device *dev, 742ff932f61SGolan Ben Ami struct iwl_trans_pcie *trans_p, int i) 743ff932f61SGolan Ben Ami { 744ff932f61SGolan Ben Ami if (trans_p->shared_vec_mask) { 745ff932f61SGolan Ben Ami int vec = trans_p->shared_vec_mask & 746ff932f61SGolan Ben Ami IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 747ff932f61SGolan Ben Ami 748ff932f61SGolan Ben Ami if (i == 0) 749ff932f61SGolan Ben Ami return DRV_NAME ": shared IRQ"; 750ff932f61SGolan Ben Ami 751ff932f61SGolan Ben Ami return devm_kasprintf(dev, GFP_KERNEL, 752ff932f61SGolan Ben Ami DRV_NAME ": queue %d", i + vec); 753ff932f61SGolan Ben Ami } 754ff932f61SGolan Ben Ami if (i == 0) 755ff932f61SGolan Ben Ami return DRV_NAME ": default queue"; 756ff932f61SGolan Ben Ami 757ff932f61SGolan Ben Ami if (i == trans_p->alloc_vecs - 1) 758ff932f61SGolan Ben Ami return DRV_NAME ": exception"; 759ff932f61SGolan Ben Ami 760ff932f61SGolan Ben Ami return devm_kasprintf(dev, GFP_KERNEL, 761ff932f61SGolan Ben Ami DRV_NAME ": queue %d", i); 762ff932f61SGolan Ben Ami } 763ff932f61SGolan Ben Ami 764e705c121SKalle Valo static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 765e705c121SKalle Valo { 766e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 767e705c121SKalle Valo 768e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 7692e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) { 770e705c121SKalle Valo trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 771e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 7722e5d4a8fSHaim Dreyfuss } else { 7732e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 7742e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask); 7752e5d4a8fSHaim Dreyfuss iwl_enable_hw_int_msk_msix(trans, 7762e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_RF_KILL); 7772e5d4a8fSHaim Dreyfuss } 778ae5bb2a6SJohannes Berg 779286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) { 780ae5bb2a6SJohannes Berg /* 781ae5bb2a6SJohannes Berg * On 9000-series devices this bit isn't enabled by default, so 782ae5bb2a6SJohannes Berg * when we power down the device we need set the bit to allow it 783ae5bb2a6SJohannes Berg * to wake up the PCI-E bus for RF-kill interrupts. 784ae5bb2a6SJohannes Berg */ 785ae5bb2a6SJohannes Berg iwl_set_bit(trans, CSR_GP_CNTRL, 786ae5bb2a6SJohannes Berg CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 787ae5bb2a6SJohannes Berg } 788e705c121SKalle Valo } 789e705c121SKalle Valo 790fa4de7f7SJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans); 791fa4de7f7SJohannes Berg 792e705c121SKalle Valo static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 793e705c121SKalle Valo { 794fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 795fa4de7f7SJohannes Berg 796fa4de7f7SJohannes Berg lockdep_assert_held(&trans_pcie->mutex); 797fa4de7f7SJohannes Berg 798c5bf4fa1SJohannes Berg if (trans_pcie->debug_rfkill == 1) 799fa4de7f7SJohannes Berg return true; 80023aeea94SJohannes Berg 801e705c121SKalle Valo return !(iwl_read32(trans, CSR_GP_CNTRL) & 802e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 803e705c121SKalle Valo } 804e705c121SKalle Valo 805e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 806e705c121SKalle Valo u32 reg, u32 mask, u32 value) 807e705c121SKalle Valo { 808e705c121SKalle Valo u32 v; 809e705c121SKalle Valo 810e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 811e705c121SKalle Valo WARN_ON_ONCE(value & ~mask); 812e705c121SKalle Valo #endif 813e705c121SKalle Valo 814e705c121SKalle Valo v = iwl_read32(trans, reg); 815e705c121SKalle Valo v &= ~mask; 816e705c121SKalle Valo v |= value; 817e705c121SKalle Valo iwl_write32(trans, reg, v); 818e705c121SKalle Valo } 819e705c121SKalle Valo 820e705c121SKalle Valo static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 821e705c121SKalle Valo u32 reg, u32 mask) 822e705c121SKalle Valo { 823e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 824e705c121SKalle Valo } 825e705c121SKalle Valo 826e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 827e705c121SKalle Valo u32 reg, u32 mask) 828e705c121SKalle Valo { 829e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 830e705c121SKalle Valo } 831e705c121SKalle Valo 8327a14c23dSSara Sharon static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans) 8337a14c23dSSara Sharon { 834a1af4c48SShahar S Matityahu return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans)); 8357a14c23dSSara Sharon } 8367a14c23dSSara Sharon 837e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 8384290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans); 839d1967ce6SShahar S Matityahu void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans); 840e705c121SKalle Valo 841f8a1edb7SJohannes Berg #ifdef CONFIG_IWLWIFI_DEBUGFS 842cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 843f8a1edb7SJohannes Berg #else 844cf5d5663SGreg Kroah-Hartman static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { } 845f8a1edb7SJohannes Berg #endif 846f8a1edb7SJohannes Berg 84710a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data); 84810a54d81SLuca Coelho 849eda50cdeSSara Sharon /* common functions that are used by gen2 transport */ 850b6fe2757SGolan Ben Ami int iwl_pcie_gen2_apm_init(struct iwl_trans *trans); 851eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans); 852eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 853eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 8549ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans); 855326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 856326477e4SJohannes Berg bool was_in_rfkill); 8576b35ff91SSara Sharon void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq); 858e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans); 85977c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 86013a3a390SSara Sharon int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 86113a3a390SSara Sharon struct iwl_dma_ptr *ptr, size_t size); 86213a3a390SSara Sharon void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr); 863c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans); 864eda50cdeSSara Sharon 8659f358c17SGolan Ben Ami /* common functions that are used by gen3 transport */ 8669f358c17SGolan Ben Ami void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power); 8679f358c17SGolan Ben Ami 868eda50cdeSSara Sharon /* transport gen 2 exported functions */ 869eda50cdeSSara Sharon int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 870eda50cdeSSara Sharon const struct fw_img *fw, bool run_in_rfkill); 871eda50cdeSSara Sharon void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr); 872ca60da2eSSara Sharon int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 873ca60da2eSSara Sharon struct iwl_host_cmd *cmd); 874bab3cb92SEmmanuel Grumbach void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans); 875bab3cb92SEmmanuel Grumbach void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans); 876e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 877e5f3f215SHaim Dreyfuss bool test, bool reset); 878e705c121SKalle Valo #endif /* __iwl_trans_int_pcie_h__ */ 879