1 /******************************************************************************
2  *
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * GPL LICENSE SUMMARY
7  *
8  * Copyright(c) 2017 Intel Deutschland GmbH
9  * Copyright(c) 2018 Intel Corporation
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of version 2 of the GNU General Public License as
13  * published by the Free Software Foundation.
14  *
15  * This program is distributed in the hope that it will be useful, but
16  * WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  * General Public License for more details.
19  *
20  * BSD LICENSE
21  *
22  * Copyright(c) 2017 Intel Deutschland GmbH
23  * Copyright(c) 2018 Intel Corporation
24  * All rights reserved.
25  *
26  * Redistribution and use in source and binary forms, with or without
27  * modification, are permitted provided that the following conditions
28  * are met:
29  *
30  *  * Redistributions of source code must retain the above copyright
31  *    notice, this list of conditions and the following disclaimer.
32  *  * Redistributions in binary form must reproduce the above copyright
33  *    notice, this list of conditions and the following disclaimer in
34  *    the documentation and/or other materials provided with the
35  *    distribution.
36  *  * Neither the name Intel Corporation nor the names of its
37  *    contributors may be used to endorse or promote products derived
38  *    from this software without specific prior written permission.
39  *
40  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51  *
52  *****************************************************************************/
53 
54 #include "iwl-trans.h"
55 #include "iwl-fh.h"
56 #include "iwl-context-info.h"
57 #include "internal.h"
58 #include "iwl-prph.h"
59 
60 void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans)
61 {
62 	struct iwl_self_init_dram *dram = &trans->init_dram;
63 	int i;
64 
65 	if (!dram->paging) {
66 		WARN_ON(dram->paging_cnt);
67 		return;
68 	}
69 
70 	/* free paging*/
71 	for (i = 0; i < dram->paging_cnt; i++)
72 		dma_free_coherent(trans->dev, dram->paging[i].size,
73 				  dram->paging[i].block,
74 				  dram->paging[i].physical);
75 
76 	kfree(dram->paging);
77 	dram->paging_cnt = 0;
78 	dram->paging = NULL;
79 }
80 
81 int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
82 			 const struct fw_img *fw,
83 			 struct iwl_context_info_dram *ctxt_dram)
84 {
85 	struct iwl_self_init_dram *dram = &trans->init_dram;
86 	int i, ret, lmac_cnt, umac_cnt, paging_cnt;
87 
88 	if (WARN(dram->paging,
89 		 "paging shouldn't already be initialized (%d pages)\n",
90 		 dram->paging_cnt))
91 		iwl_pcie_ctxt_info_free_paging(trans);
92 
93 	lmac_cnt = iwl_pcie_get_num_sections(fw, 0);
94 	/* add 1 due to separator */
95 	umac_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + 1);
96 	/* add 2 due to separators */
97 	paging_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + umac_cnt + 2);
98 
99 	dram->fw = kcalloc(umac_cnt + lmac_cnt, sizeof(*dram->fw), GFP_KERNEL);
100 	if (!dram->fw)
101 		return -ENOMEM;
102 	dram->paging = kcalloc(paging_cnt, sizeof(*dram->paging), GFP_KERNEL);
103 	if (!dram->paging)
104 		return -ENOMEM;
105 
106 	/* initialize lmac sections */
107 	for (i = 0; i < lmac_cnt; i++) {
108 		ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[i],
109 						   &dram->fw[dram->fw_cnt]);
110 		if (ret)
111 			return ret;
112 		ctxt_dram->lmac_img[i] =
113 			cpu_to_le64(dram->fw[dram->fw_cnt].physical);
114 		dram->fw_cnt++;
115 	}
116 
117 	/* initialize umac sections */
118 	for (i = 0; i < umac_cnt; i++) {
119 		/* access FW with +1 to make up for lmac separator */
120 		ret = iwl_pcie_ctxt_info_alloc_dma(trans,
121 						   &fw->sec[dram->fw_cnt + 1],
122 						   &dram->fw[dram->fw_cnt]);
123 		if (ret)
124 			return ret;
125 		ctxt_dram->umac_img[i] =
126 			cpu_to_le64(dram->fw[dram->fw_cnt].physical);
127 		dram->fw_cnt++;
128 	}
129 
130 	/*
131 	 * Initialize paging.
132 	 * Paging memory isn't stored in dram->fw as the umac and lmac - it is
133 	 * stored separately.
134 	 * This is since the timing of its release is different -
135 	 * while fw memory can be released on alive, the paging memory can be
136 	 * freed only when the device goes down.
137 	 * Given that, the logic here in accessing the fw image is a bit
138 	 * different - fw_cnt isn't changing so loop counter is added to it.
139 	 */
140 	for (i = 0; i < paging_cnt; i++) {
141 		/* access FW with +2 to make up for lmac & umac separators */
142 		int fw_idx = dram->fw_cnt + i + 2;
143 
144 		ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[fw_idx],
145 						   &dram->paging[i]);
146 		if (ret)
147 			return ret;
148 
149 		ctxt_dram->virtual_img[i] =
150 			cpu_to_le64(dram->paging[i].physical);
151 		dram->paging_cnt++;
152 	}
153 
154 	return 0;
155 }
156 
157 int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
158 			    const struct fw_img *fw)
159 {
160 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
161 	struct iwl_context_info *ctxt_info;
162 	struct iwl_context_info_rbd_cfg *rx_cfg;
163 	u32 control_flags = 0, rb_size;
164 	int ret;
165 
166 	ctxt_info = dma_alloc_coherent(trans->dev, sizeof(*ctxt_info),
167 				       &trans_pcie->ctxt_info_dma_addr,
168 				       GFP_KERNEL);
169 	if (!ctxt_info)
170 		return -ENOMEM;
171 
172 	ctxt_info->version.version = 0;
173 	ctxt_info->version.mac_id =
174 		cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
175 	/* size is in DWs */
176 	ctxt_info->version.size = cpu_to_le16(sizeof(*ctxt_info) / 4);
177 
178 	switch (trans_pcie->rx_buf_size) {
179 	case IWL_AMSDU_2K:
180 		rb_size = IWL_CTXT_INFO_RB_SIZE_2K;
181 		break;
182 	case IWL_AMSDU_4K:
183 		rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
184 		break;
185 	case IWL_AMSDU_8K:
186 		rb_size = IWL_CTXT_INFO_RB_SIZE_8K;
187 		break;
188 	case IWL_AMSDU_12K:
189 		rb_size = IWL_CTXT_INFO_RB_SIZE_12K;
190 		break;
191 	default:
192 		WARN_ON(1);
193 		rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
194 	}
195 
196 	BUILD_BUG_ON(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) > 0xF);
197 	control_flags = IWL_CTXT_INFO_TFD_FORMAT_LONG |
198 			(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) <<
199 			 IWL_CTXT_INFO_RB_CB_SIZE_POS) |
200 			(rb_size << IWL_CTXT_INFO_RB_SIZE_POS);
201 	ctxt_info->control.control_flags = cpu_to_le32(control_flags);
202 
203 	/* initialize RX default queue */
204 	rx_cfg = &ctxt_info->rbd_cfg;
205 	rx_cfg->free_rbd_addr = cpu_to_le64(trans_pcie->rxq->bd_dma);
206 	rx_cfg->used_rbd_addr = cpu_to_le64(trans_pcie->rxq->used_bd_dma);
207 	rx_cfg->status_wr_ptr = cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
208 
209 	/* initialize TX command queue */
210 	ctxt_info->hcmd_cfg.cmd_queue_addr =
211 		cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
212 	ctxt_info->hcmd_cfg.cmd_queue_size =
213 		TFD_QUEUE_CB_SIZE(TFD_CMD_SLOTS);
214 
215 	/* allocate ucode sections in dram and set addresses */
216 	ret = iwl_pcie_init_fw_sec(trans, fw, &ctxt_info->dram);
217 	if (ret) {
218 		dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
219 				  ctxt_info, trans_pcie->ctxt_info_dma_addr);
220 		return ret;
221 	}
222 
223 	trans_pcie->ctxt_info = ctxt_info;
224 
225 	iwl_enable_interrupts(trans);
226 
227 	/* Configure debug, if exists */
228 	if (iwl_pcie_dbg_on(trans))
229 		iwl_pcie_apply_destination(trans);
230 
231 	/* kick FW self load */
232 	iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
233 	iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
234 
235 	/* Context info will be released upon alive or failure to get one */
236 
237 	return 0;
238 }
239 
240 void iwl_pcie_ctxt_info_free(struct iwl_trans *trans)
241 {
242 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
243 
244 	if (!trans_pcie->ctxt_info)
245 		return;
246 
247 	dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
248 			  trans_pcie->ctxt_info,
249 			  trans_pcie->ctxt_info_dma_addr);
250 	trans_pcie->ctxt_info_dma_addr = 0;
251 	trans_pcie->ctxt_info = NULL;
252 
253 	iwl_pcie_ctxt_info_free_fw_img(trans);
254 }
255