18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
28e99ea8dSJohannes Berg /*
38e99ea8dSJohannes Berg * Copyright (C) 2017 Intel Deutschland GmbH
4*5f408503SAlon Giladi * Copyright (C) 2018-2022 Intel Corporation
58e99ea8dSJohannes Berg */
6eda50cdeSSara Sharon #include "iwl-trans.h"
7eda50cdeSSara Sharon #include "iwl-fh.h"
8eda50cdeSSara Sharon #include "iwl-context-info.h"
9eda50cdeSSara Sharon #include "internal.h"
10eda50cdeSSara Sharon #include "iwl-prph.h"
11eda50cdeSSara Sharon
_iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans * trans,size_t size,dma_addr_t * phys,int depth)12d84a7a65SJohannes Berg static void *_iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
13d84a7a65SJohannes Berg size_t size,
14d84a7a65SJohannes Berg dma_addr_t *phys,
15d84a7a65SJohannes Berg int depth)
16d84a7a65SJohannes Berg {
17d84a7a65SJohannes Berg void *result;
18d84a7a65SJohannes Berg
19d84a7a65SJohannes Berg if (WARN(depth > 2,
20d84a7a65SJohannes Berg "failed to allocate DMA memory not crossing 2^32 boundary"))
21d84a7a65SJohannes Berg return NULL;
22d84a7a65SJohannes Berg
23d84a7a65SJohannes Berg result = dma_alloc_coherent(trans->dev, size, phys, GFP_KERNEL);
24d84a7a65SJohannes Berg
25d84a7a65SJohannes Berg if (!result)
26d84a7a65SJohannes Berg return NULL;
27d84a7a65SJohannes Berg
280cd1ad2dSMordechay Goodstein if (unlikely(iwl_txq_crosses_4g_boundary(*phys, size))) {
29d84a7a65SJohannes Berg void *old = result;
30d84a7a65SJohannes Berg dma_addr_t oldphys = *phys;
31d84a7a65SJohannes Berg
32d84a7a65SJohannes Berg result = _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size,
33d84a7a65SJohannes Berg phys,
34d84a7a65SJohannes Berg depth + 1);
35d84a7a65SJohannes Berg dma_free_coherent(trans->dev, size, old, oldphys);
36d84a7a65SJohannes Berg }
37d84a7a65SJohannes Berg
38d84a7a65SJohannes Berg return result;
39d84a7a65SJohannes Berg }
40d84a7a65SJohannes Berg
iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans * trans,size_t size,dma_addr_t * phys)41*5f408503SAlon Giladi void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
42d84a7a65SJohannes Berg size_t size,
43d84a7a65SJohannes Berg dma_addr_t *phys)
44d84a7a65SJohannes Berg {
45d84a7a65SJohannes Berg return _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size, phys, 0);
46d84a7a65SJohannes Berg }
47d84a7a65SJohannes Berg
iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans * trans,const void * data,u32 len,struct iwl_dram_data * dram)486654cd4eSLuca Coelho int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
496654cd4eSLuca Coelho const void *data, u32 len,
5063417549SJohannes Berg struct iwl_dram_data *dram)
5163417549SJohannes Berg {
526654cd4eSLuca Coelho dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len,
5363417549SJohannes Berg &dram->physical);
5463417549SJohannes Berg if (!dram->block)
5563417549SJohannes Berg return -ENOMEM;
5663417549SJohannes Berg
576654cd4eSLuca Coelho dram->size = len;
586654cd4eSLuca Coelho memcpy(dram->block, data, len);
5963417549SJohannes Berg
6063417549SJohannes Berg return 0;
6163417549SJohannes Berg }
6263417549SJohannes Berg
iwl_pcie_ctxt_info_free_paging(struct iwl_trans * trans)63eda50cdeSSara Sharon void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans)
64eda50cdeSSara Sharon {
65505a00c0SShahar S Matityahu struct iwl_self_init_dram *dram = &trans->init_dram;
66eda50cdeSSara Sharon int i;
67eda50cdeSSara Sharon
68eda50cdeSSara Sharon if (!dram->paging) {
69eda50cdeSSara Sharon WARN_ON(dram->paging_cnt);
70eda50cdeSSara Sharon return;
71eda50cdeSSara Sharon }
72eda50cdeSSara Sharon
73eda50cdeSSara Sharon /* free paging*/
74eda50cdeSSara Sharon for (i = 0; i < dram->paging_cnt; i++)
75eda50cdeSSara Sharon dma_free_coherent(trans->dev, dram->paging[i].size,
76eda50cdeSSara Sharon dram->paging[i].block,
77eda50cdeSSara Sharon dram->paging[i].physical);
78eda50cdeSSara Sharon
79eda50cdeSSara Sharon kfree(dram->paging);
80eda50cdeSSara Sharon dram->paging_cnt = 0;
8187fc0302SJohannes Berg dram->paging = NULL;
82eda50cdeSSara Sharon }
83eda50cdeSSara Sharon
iwl_pcie_init_fw_sec(struct iwl_trans * trans,const struct fw_img * fw,struct iwl_context_info_dram * ctxt_dram)842ee82402SGolan Ben Ami int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
85eda50cdeSSara Sharon const struct fw_img *fw,
862ee82402SGolan Ben Ami struct iwl_context_info_dram *ctxt_dram)
87eda50cdeSSara Sharon {
88505a00c0SShahar S Matityahu struct iwl_self_init_dram *dram = &trans->init_dram;
89eda50cdeSSara Sharon int i, ret, lmac_cnt, umac_cnt, paging_cnt;
90eda50cdeSSara Sharon
91f0fea2b7SJohannes Berg if (WARN(dram->paging,
92f0fea2b7SJohannes Berg "paging shouldn't already be initialized (%d pages)\n",
93f0fea2b7SJohannes Berg dram->paging_cnt))
94f0fea2b7SJohannes Berg iwl_pcie_ctxt_info_free_paging(trans);
95f0fea2b7SJohannes Berg
96eda50cdeSSara Sharon lmac_cnt = iwl_pcie_get_num_sections(fw, 0);
97eda50cdeSSara Sharon /* add 1 due to separator */
98eda50cdeSSara Sharon umac_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + 1);
99eda50cdeSSara Sharon /* add 2 due to separators */
100eda50cdeSSara Sharon paging_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + umac_cnt + 2);
101eda50cdeSSara Sharon
102eda50cdeSSara Sharon dram->fw = kcalloc(umac_cnt + lmac_cnt, sizeof(*dram->fw), GFP_KERNEL);
103eda50cdeSSara Sharon if (!dram->fw)
104eda50cdeSSara Sharon return -ENOMEM;
105eda50cdeSSara Sharon dram->paging = kcalloc(paging_cnt, sizeof(*dram->paging), GFP_KERNEL);
106eda50cdeSSara Sharon if (!dram->paging)
107eda50cdeSSara Sharon return -ENOMEM;
108eda50cdeSSara Sharon
109eda50cdeSSara Sharon /* initialize lmac sections */
110eda50cdeSSara Sharon for (i = 0; i < lmac_cnt; i++) {
1116654cd4eSLuca Coelho ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[i].data,
1126654cd4eSLuca Coelho fw->sec[i].len,
113eda50cdeSSara Sharon &dram->fw[dram->fw_cnt]);
114eda50cdeSSara Sharon if (ret)
115eda50cdeSSara Sharon return ret;
116eda50cdeSSara Sharon ctxt_dram->lmac_img[i] =
117eda50cdeSSara Sharon cpu_to_le64(dram->fw[dram->fw_cnt].physical);
118eda50cdeSSara Sharon dram->fw_cnt++;
119eda50cdeSSara Sharon }
120eda50cdeSSara Sharon
121eda50cdeSSara Sharon /* initialize umac sections */
122eda50cdeSSara Sharon for (i = 0; i < umac_cnt; i++) {
123eda50cdeSSara Sharon /* access FW with +1 to make up for lmac separator */
124eda50cdeSSara Sharon ret = iwl_pcie_ctxt_info_alloc_dma(trans,
1256654cd4eSLuca Coelho fw->sec[dram->fw_cnt + 1].data,
1266654cd4eSLuca Coelho fw->sec[dram->fw_cnt + 1].len,
127eda50cdeSSara Sharon &dram->fw[dram->fw_cnt]);
128eda50cdeSSara Sharon if (ret)
129eda50cdeSSara Sharon return ret;
130eda50cdeSSara Sharon ctxt_dram->umac_img[i] =
131eda50cdeSSara Sharon cpu_to_le64(dram->fw[dram->fw_cnt].physical);
132eda50cdeSSara Sharon dram->fw_cnt++;
133eda50cdeSSara Sharon }
134eda50cdeSSara Sharon
135eda50cdeSSara Sharon /*
136eda50cdeSSara Sharon * Initialize paging.
137eda50cdeSSara Sharon * Paging memory isn't stored in dram->fw as the umac and lmac - it is
138eda50cdeSSara Sharon * stored separately.
139eda50cdeSSara Sharon * This is since the timing of its release is different -
140eda50cdeSSara Sharon * while fw memory can be released on alive, the paging memory can be
141eda50cdeSSara Sharon * freed only when the device goes down.
142eda50cdeSSara Sharon * Given that, the logic here in accessing the fw image is a bit
143eda50cdeSSara Sharon * different - fw_cnt isn't changing so loop counter is added to it.
144eda50cdeSSara Sharon */
145eda50cdeSSara Sharon for (i = 0; i < paging_cnt; i++) {
146eda50cdeSSara Sharon /* access FW with +2 to make up for lmac & umac separators */
147eda50cdeSSara Sharon int fw_idx = dram->fw_cnt + i + 2;
148eda50cdeSSara Sharon
1496654cd4eSLuca Coelho ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[fw_idx].data,
1506654cd4eSLuca Coelho fw->sec[fw_idx].len,
151eda50cdeSSara Sharon &dram->paging[i]);
152eda50cdeSSara Sharon if (ret)
153eda50cdeSSara Sharon return ret;
154eda50cdeSSara Sharon
155eda50cdeSSara Sharon ctxt_dram->virtual_img[i] =
156eda50cdeSSara Sharon cpu_to_le64(dram->paging[i].physical);
157eda50cdeSSara Sharon dram->paging_cnt++;
158eda50cdeSSara Sharon }
159eda50cdeSSara Sharon
160eda50cdeSSara Sharon return 0;
161eda50cdeSSara Sharon }
162eda50cdeSSara Sharon
iwl_pcie_ctxt_info_init(struct iwl_trans * trans,const struct fw_img * fw)163eda50cdeSSara Sharon int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
164eda50cdeSSara Sharon const struct fw_img *fw)
165eda50cdeSSara Sharon {
166eda50cdeSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
167eda50cdeSSara Sharon struct iwl_context_info *ctxt_info;
168eda50cdeSSara Sharon struct iwl_context_info_rbd_cfg *rx_cfg;
169753e9761SShaul Triebitz u32 control_flags = 0, rb_size;
170d84a7a65SJohannes Berg dma_addr_t phys;
171eda50cdeSSara Sharon int ret;
172eda50cdeSSara Sharon
173d84a7a65SJohannes Berg ctxt_info = iwl_pcie_ctxt_info_dma_alloc_coherent(trans,
174d84a7a65SJohannes Berg sizeof(*ctxt_info),
175d84a7a65SJohannes Berg &phys);
176eda50cdeSSara Sharon if (!ctxt_info)
177eda50cdeSSara Sharon return -ENOMEM;
178eda50cdeSSara Sharon
179d84a7a65SJohannes Berg trans_pcie->ctxt_info_dma_addr = phys;
180d84a7a65SJohannes Berg
181eda50cdeSSara Sharon ctxt_info->version.version = 0;
182eda50cdeSSara Sharon ctxt_info->version.mac_id =
183eda50cdeSSara Sharon cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
184eda50cdeSSara Sharon /* size is in DWs */
185eda50cdeSSara Sharon ctxt_info->version.size = cpu_to_le16(sizeof(*ctxt_info) / 4);
186eda50cdeSSara Sharon
187753e9761SShaul Triebitz switch (trans_pcie->rx_buf_size) {
188753e9761SShaul Triebitz case IWL_AMSDU_2K:
189753e9761SShaul Triebitz rb_size = IWL_CTXT_INFO_RB_SIZE_2K;
190753e9761SShaul Triebitz break;
191753e9761SShaul Triebitz case IWL_AMSDU_4K:
192753e9761SShaul Triebitz rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
193753e9761SShaul Triebitz break;
194753e9761SShaul Triebitz case IWL_AMSDU_8K:
195753e9761SShaul Triebitz rb_size = IWL_CTXT_INFO_RB_SIZE_8K;
196753e9761SShaul Triebitz break;
197753e9761SShaul Triebitz case IWL_AMSDU_12K:
1983fa965c2SJohannes Berg rb_size = IWL_CTXT_INFO_RB_SIZE_16K;
199753e9761SShaul Triebitz break;
200753e9761SShaul Triebitz default:
201753e9761SShaul Triebitz WARN_ON(1);
202753e9761SShaul Triebitz rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
203753e9761SShaul Triebitz }
204753e9761SShaul Triebitz
205c042f0c7SJohannes Berg WARN_ON(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds) > 12);
206c042f0c7SJohannes Berg control_flags = IWL_CTXT_INFO_TFD_FORMAT_LONG;
207c042f0c7SJohannes Berg control_flags |=
208c042f0c7SJohannes Berg u32_encode_bits(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds),
209c042f0c7SJohannes Berg IWL_CTXT_INFO_RB_CB_SIZE);
210c042f0c7SJohannes Berg control_flags |= u32_encode_bits(rb_size, IWL_CTXT_INFO_RB_SIZE);
211eda50cdeSSara Sharon ctxt_info->control.control_flags = cpu_to_le32(control_flags);
212eda50cdeSSara Sharon
213eda50cdeSSara Sharon /* initialize RX default queue */
214eda50cdeSSara Sharon rx_cfg = &ctxt_info->rbd_cfg;
215eda50cdeSSara Sharon rx_cfg->free_rbd_addr = cpu_to_le64(trans_pcie->rxq->bd_dma);
216eda50cdeSSara Sharon rx_cfg->used_rbd_addr = cpu_to_le64(trans_pcie->rxq->used_bd_dma);
217eda50cdeSSara Sharon rx_cfg->status_wr_ptr = cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
218eda50cdeSSara Sharon
219eda50cdeSSara Sharon /* initialize TX command queue */
220eda50cdeSSara Sharon ctxt_info->hcmd_cfg.cmd_queue_addr =
2214f4822b7SMordechay Goodstein cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
222eda50cdeSSara Sharon ctxt_info->hcmd_cfg.cmd_queue_size =
223718a8b23SShaul Triebitz TFD_QUEUE_CB_SIZE(IWL_CMD_QUEUE_SIZE);
224eda50cdeSSara Sharon
225eda50cdeSSara Sharon /* allocate ucode sections in dram and set addresses */
2262ee82402SGolan Ben Ami ret = iwl_pcie_init_fw_sec(trans, fw, &ctxt_info->dram);
227718ceb22SJohannes Berg if (ret) {
228718ceb22SJohannes Berg dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
229718ceb22SJohannes Berg ctxt_info, trans_pcie->ctxt_info_dma_addr);
230eda50cdeSSara Sharon return ret;
231718ceb22SJohannes Berg }
232eda50cdeSSara Sharon
233eda50cdeSSara Sharon trans_pcie->ctxt_info = ctxt_info;
234eda50cdeSSara Sharon
235ed3e4c6dSEmmanuel Grumbach iwl_enable_fw_load_int_ctx_info(trans);
236eda50cdeSSara Sharon
237c9be849dSLiad Kaufman /* Configure debug, if exists */
2387a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans))
239c9be849dSLiad Kaufman iwl_pcie_apply_destination(trans);
240c9be849dSLiad Kaufman
241eda50cdeSSara Sharon /* kick FW self load */
242eda50cdeSSara Sharon iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
243eda50cdeSSara Sharon
244eda50cdeSSara Sharon /* Context info will be released upon alive or failure to get one */
245eda50cdeSSara Sharon
246eda50cdeSSara Sharon return 0;
247eda50cdeSSara Sharon }
248eda50cdeSSara Sharon
iwl_pcie_ctxt_info_free(struct iwl_trans * trans)249eda50cdeSSara Sharon void iwl_pcie_ctxt_info_free(struct iwl_trans *trans)
250eda50cdeSSara Sharon {
251eda50cdeSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
252eda50cdeSSara Sharon
253eda50cdeSSara Sharon if (!trans_pcie->ctxt_info)
254eda50cdeSSara Sharon return;
255eda50cdeSSara Sharon
256eda50cdeSSara Sharon dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
257eda50cdeSSara Sharon trans_pcie->ctxt_info,
258eda50cdeSSara Sharon trans_pcie->ctxt_info_dma_addr);
259eda50cdeSSara Sharon trans_pcie->ctxt_info_dma_addr = 0;
260eda50cdeSSara Sharon trans_pcie->ctxt_info = NULL;
261eda50cdeSSara Sharon
262eda50cdeSSara Sharon iwl_pcie_ctxt_info_free_fw_img(trans);
263eda50cdeSSara Sharon }
264