1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2018-2020 Intel Corporation
4  */
5 #include "iwl-trans.h"
6 #include "iwl-fh.h"
7 #include "iwl-context-info-gen3.h"
8 #include "internal.h"
9 #include "iwl-prph.h"
10 
11 static void
12 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans,
13 			      struct iwl_prph_scratch_hwm_cfg *dbg_cfg,
14 			      u32 *control_flags)
15 {
16 	enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
17 	struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
18 	u32 dbg_flags = 0;
19 
20 	if (!iwl_trans_dbg_ini_valid(trans)) {
21 		struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
22 
23 		iwl_pcie_alloc_fw_monitor(trans, 0);
24 
25 		if (fw_mon->size) {
26 			dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
27 
28 			IWL_DEBUG_FW(trans,
29 				     "WRT: Applying DRAM buffer destination\n");
30 
31 			dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical);
32 			dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size);
33 		}
34 
35 		goto out;
36 	}
37 
38 	fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id];
39 
40 	switch (le32_to_cpu(fw_mon_cfg->buf_location)) {
41 	case IWL_FW_INI_LOCATION_SRAM_PATH:
42 		dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL;
43 		IWL_DEBUG_FW(trans,
44 				"WRT: Applying SMEM buffer destination\n");
45 		break;
46 
47 	case IWL_FW_INI_LOCATION_NPK_PATH:
48 		dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF;
49 		IWL_DEBUG_FW(trans,
50 			     "WRT: Applying NPK buffer destination\n");
51 		break;
52 
53 	case IWL_FW_INI_LOCATION_DRAM_PATH:
54 		if (trans->dbg.fw_mon_ini[alloc_id].num_frags) {
55 			struct iwl_dram_data *frag =
56 				&trans->dbg.fw_mon_ini[alloc_id].frags[0];
57 			dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
58 			dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical);
59 			dbg_cfg->hwm_size = cpu_to_le32(frag->size);
60 			IWL_DEBUG_FW(trans,
61 				     "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n",
62 				     alloc_id,
63 				     trans->dbg.fw_mon_ini[alloc_id].num_frags);
64 		}
65 		break;
66 	default:
67 		IWL_ERR(trans, "WRT: Invalid buffer destination\n");
68 	}
69 out:
70 	if (dbg_flags)
71 		*control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags;
72 }
73 
74 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
75 				 const struct fw_img *fw)
76 {
77 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78 	struct iwl_context_info_gen3 *ctxt_info_gen3;
79 	struct iwl_prph_scratch *prph_scratch;
80 	struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
81 	struct iwl_prph_info *prph_info;
82 	void *iml_img;
83 	u32 control_flags = 0;
84 	int ret;
85 	int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
86 			      trans->cfg->min_txq_size);
87 
88 	switch (trans_pcie->rx_buf_size) {
89 	case IWL_AMSDU_DEF:
90 		return -EINVAL;
91 	case IWL_AMSDU_2K:
92 		break;
93 	case IWL_AMSDU_4K:
94 		control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
95 		break;
96 	case IWL_AMSDU_8K:
97 		control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
98 		/* if firmware supports the ext size, tell it */
99 		control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K;
100 		break;
101 	case IWL_AMSDU_12K:
102 		control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
103 		/* if firmware supports the ext size, tell it */
104 		control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K;
105 		break;
106 	}
107 
108 	/* Allocate prph scratch */
109 	prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
110 					  &trans_pcie->prph_scratch_dma_addr,
111 					  GFP_KERNEL);
112 	if (!prph_scratch)
113 		return -ENOMEM;
114 
115 	prph_sc_ctrl = &prph_scratch->ctrl_cfg;
116 
117 	prph_sc_ctrl->version.version = 0;
118 	prph_sc_ctrl->version.mac_id =
119 		cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
120 	prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
121 
122 	control_flags |= IWL_PRPH_SCRATCH_MTR_MODE;
123 	control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT;
124 
125 	/* initialize RX default queue */
126 	prph_sc_ctrl->rbd_cfg.free_rbd_addr =
127 		cpu_to_le64(trans_pcie->rxq->bd_dma);
128 
129 	iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg,
130 				      &control_flags);
131 	prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
132 
133 	/* allocate ucode sections in dram and set addresses */
134 	ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
135 	if (ret)
136 		goto err_free_prph_scratch;
137 
138 
139 	/* Allocate prph information
140 	 * currently we don't assign to the prph info anything, but it would get
141 	 * assigned later */
142 	prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info),
143 				       &trans_pcie->prph_info_dma_addr,
144 				       GFP_KERNEL);
145 	if (!prph_info) {
146 		ret = -ENOMEM;
147 		goto err_free_prph_scratch;
148 	}
149 
150 	/* Allocate context info */
151 	ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
152 					    sizeof(*ctxt_info_gen3),
153 					    &trans_pcie->ctxt_info_dma_addr,
154 					    GFP_KERNEL);
155 	if (!ctxt_info_gen3) {
156 		ret = -ENOMEM;
157 		goto err_free_prph_info;
158 	}
159 
160 	ctxt_info_gen3->prph_info_base_addr =
161 		cpu_to_le64(trans_pcie->prph_info_dma_addr);
162 	ctxt_info_gen3->prph_scratch_base_addr =
163 		cpu_to_le64(trans_pcie->prph_scratch_dma_addr);
164 	ctxt_info_gen3->prph_scratch_size =
165 		cpu_to_le32(sizeof(*prph_scratch));
166 	ctxt_info_gen3->cr_head_idx_arr_base_addr =
167 		cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
168 	ctxt_info_gen3->tr_tail_idx_arr_base_addr =
169 		cpu_to_le64(trans_pcie->rxq->tr_tail_dma);
170 	ctxt_info_gen3->cr_tail_idx_arr_base_addr =
171 		cpu_to_le64(trans_pcie->rxq->cr_tail_dma);
172 	ctxt_info_gen3->cr_idx_arr_size =
173 		cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS);
174 	ctxt_info_gen3->tr_idx_arr_size =
175 		cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS);
176 	ctxt_info_gen3->mtr_base_addr =
177 		cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
178 	ctxt_info_gen3->mcr_base_addr =
179 		cpu_to_le64(trans_pcie->rxq->used_bd_dma);
180 	ctxt_info_gen3->mtr_size =
181 		cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size));
182 	ctxt_info_gen3->mcr_size =
183 		cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds));
184 
185 	trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
186 	trans_pcie->prph_info = prph_info;
187 	trans_pcie->prph_scratch = prph_scratch;
188 
189 	/* Allocate IML */
190 	iml_img = dma_alloc_coherent(trans->dev, trans->iml_len,
191 				     &trans_pcie->iml_dma_addr, GFP_KERNEL);
192 	if (!iml_img)
193 		return -ENOMEM;
194 
195 	memcpy(iml_img, trans->iml, trans->iml_len);
196 
197 	iwl_enable_fw_load_int_ctx_info(trans);
198 
199 	/* kick FW self load */
200 	iwl_write64(trans, CSR_CTXT_INFO_ADDR,
201 		    trans_pcie->ctxt_info_dma_addr);
202 	iwl_write64(trans, CSR_IML_DATA_ADDR,
203 		    trans_pcie->iml_dma_addr);
204 	iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len);
205 
206 	iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
207 		    CSR_AUTO_FUNC_BOOT_ENA);
208 
209 	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
210 		/*
211 		 * The firmware initializes this again later (to a smaller
212 		 * value), but for the boot process initialize the LTR to
213 		 * ~250 usec.
214 		 */
215 		u32 val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
216 			  u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
217 					  CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
218 			  u32_encode_bits(250,
219 					  CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
220 			  CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
221 			  u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
222 					  CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
223 			  u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
224 
225 		iwl_write32(trans, CSR_LTR_LONG_VAL_AD, val);
226 	}
227 
228 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
229 		iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
230 	else
231 		iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT);
232 
233 	return 0;
234 
235 err_free_prph_info:
236 	dma_free_coherent(trans->dev,
237 			  sizeof(*prph_info),
238 			prph_info,
239 			trans_pcie->prph_info_dma_addr);
240 
241 err_free_prph_scratch:
242 	dma_free_coherent(trans->dev,
243 			  sizeof(*prph_scratch),
244 			prph_scratch,
245 			trans_pcie->prph_scratch_dma_addr);
246 	return ret;
247 
248 }
249 
250 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans)
251 {
252 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
253 
254 	if (!trans_pcie->ctxt_info_gen3)
255 		return;
256 
257 	dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
258 			  trans_pcie->ctxt_info_gen3,
259 			  trans_pcie->ctxt_info_dma_addr);
260 	trans_pcie->ctxt_info_dma_addr = 0;
261 	trans_pcie->ctxt_info_gen3 = NULL;
262 
263 	iwl_pcie_ctxt_info_free_fw_img(trans);
264 
265 	dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch),
266 			  trans_pcie->prph_scratch,
267 			  trans_pcie->prph_scratch_dma_addr);
268 	trans_pcie->prph_scratch_dma_addr = 0;
269 	trans_pcie->prph_scratch = NULL;
270 
271 	dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info),
272 			  trans_pcie->prph_info,
273 			  trans_pcie->prph_info_dma_addr);
274 	trans_pcie->prph_info_dma_addr = 0;
275 	trans_pcie->prph_info = NULL;
276 }
277 
278 int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
279 					  const void *data, u32 len)
280 {
281 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
282 	struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
283 		&trans_pcie->prph_scratch->ctrl_cfg;
284 	int ret;
285 
286 	if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
287 		return 0;
288 
289 	ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
290 					   &trans_pcie->pnvm_dram);
291 	if (ret < 0) {
292 		IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n",
293 			     ret);
294 		return ret;
295 	}
296 
297 	prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
298 		cpu_to_le64(trans_pcie->pnvm_dram.physical);
299 	prph_sc_ctrl->pnvm_cfg.pnvm_size =
300 		cpu_to_le32(trans_pcie->pnvm_dram.size);
301 
302 	return 0;
303 }
304