1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2023 Intel Corporation 4 */ 5 #include "iwl-trans.h" 6 #include "iwl-fh.h" 7 #include "iwl-context-info-gen3.h" 8 #include "internal.h" 9 #include "iwl-prph.h" 10 11 static void 12 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, 13 struct iwl_prph_scratch_hwm_cfg *dbg_cfg, 14 u32 *control_flags) 15 { 16 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 17 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 18 u32 dbg_flags = 0; 19 20 if (!iwl_trans_dbg_ini_valid(trans)) { 21 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 22 23 iwl_pcie_alloc_fw_monitor(trans, 0); 24 25 if (fw_mon->size) { 26 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 27 28 IWL_DEBUG_FW(trans, 29 "WRT: Applying DRAM buffer destination\n"); 30 31 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); 32 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); 33 } 34 35 goto out; 36 } 37 38 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; 39 40 switch (le32_to_cpu(fw_mon_cfg->buf_location)) { 41 case IWL_FW_INI_LOCATION_SRAM_PATH: 42 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; 43 IWL_DEBUG_FW(trans, 44 "WRT: Applying SMEM buffer destination\n"); 45 break; 46 47 case IWL_FW_INI_LOCATION_NPK_PATH: 48 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF; 49 IWL_DEBUG_FW(trans, 50 "WRT: Applying NPK buffer destination\n"); 51 break; 52 53 case IWL_FW_INI_LOCATION_DRAM_PATH: 54 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { 55 struct iwl_dram_data *frag = 56 &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 57 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 58 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); 59 dbg_cfg->hwm_size = cpu_to_le32(frag->size); 60 dbg_cfg->debug_token_config = cpu_to_le32(trans->dbg.ucode_preset); 61 IWL_DEBUG_FW(trans, 62 "WRT: Applying DRAM destination (debug_token_config=%u)\n", 63 dbg_cfg->debug_token_config); 64 IWL_DEBUG_FW(trans, 65 "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", 66 alloc_id, 67 trans->dbg.fw_mon_ini[alloc_id].num_frags); 68 } 69 break; 70 default: 71 IWL_DEBUG_FW(trans, "WRT: Invalid buffer destination (%d)\n", 72 le32_to_cpu(fw_mon_cfg->buf_location)); 73 } 74 out: 75 if (dbg_flags) 76 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; 77 } 78 79 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 80 const struct fw_img *fw) 81 { 82 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 83 struct iwl_context_info_gen3 *ctxt_info_gen3; 84 struct iwl_prph_scratch *prph_scratch; 85 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 86 struct iwl_prph_info *prph_info; 87 u32 control_flags = 0; 88 int ret; 89 int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 90 trans->cfg->min_txq_size); 91 92 switch (trans_pcie->rx_buf_size) { 93 case IWL_AMSDU_DEF: 94 return -EINVAL; 95 case IWL_AMSDU_2K: 96 break; 97 case IWL_AMSDU_4K: 98 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 99 break; 100 case IWL_AMSDU_8K: 101 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 102 /* if firmware supports the ext size, tell it */ 103 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K; 104 break; 105 case IWL_AMSDU_12K: 106 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 107 /* if firmware supports the ext size, tell it */ 108 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K; 109 break; 110 } 111 112 /* Allocate prph scratch */ 113 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 114 &trans_pcie->prph_scratch_dma_addr, 115 GFP_KERNEL); 116 if (!prph_scratch) 117 return -ENOMEM; 118 119 prph_sc_ctrl = &prph_scratch->ctrl_cfg; 120 121 prph_sc_ctrl->version.version = 0; 122 prph_sc_ctrl->version.mac_id = 123 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); 124 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 125 126 control_flags |= IWL_PRPH_SCRATCH_MTR_MODE; 127 control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT; 128 129 if (trans->trans_cfg->imr_enabled) 130 control_flags |= IWL_PRPH_SCRATCH_IMR_DEBUG_EN; 131 132 /* initialize RX default queue */ 133 prph_sc_ctrl->rbd_cfg.free_rbd_addr = 134 cpu_to_le64(trans_pcie->rxq->bd_dma); 135 136 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, 137 &control_flags); 138 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 139 140 /* initialize the Step equalizer data */ 141 prph_sc_ctrl->step_cfg.mbx_addr_0 = cpu_to_le32(trans->mbx_addr_0_step); 142 prph_sc_ctrl->step_cfg.mbx_addr_1 = cpu_to_le32(trans->mbx_addr_1_step); 143 144 /* allocate ucode sections in dram and set addresses */ 145 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 146 if (ret) 147 goto err_free_prph_scratch; 148 149 150 /* Allocate prph information 151 * currently we don't assign to the prph info anything, but it would get 152 * assigned later 153 * 154 * We also use the second half of this page to give the device some 155 * dummy TR/CR tail pointers - which shouldn't be necessary as we don't 156 * use this, but the hardware still reads/writes there and we can't let 157 * it go do that with a NULL pointer. 158 */ 159 BUILD_BUG_ON(sizeof(*prph_info) > PAGE_SIZE / 2); 160 prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE, 161 &trans_pcie->prph_info_dma_addr, 162 GFP_KERNEL); 163 if (!prph_info) { 164 ret = -ENOMEM; 165 goto err_free_prph_scratch; 166 } 167 168 /* Allocate context info */ 169 ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 170 sizeof(*ctxt_info_gen3), 171 &trans_pcie->ctxt_info_dma_addr, 172 GFP_KERNEL); 173 if (!ctxt_info_gen3) { 174 ret = -ENOMEM; 175 goto err_free_prph_info; 176 } 177 178 ctxt_info_gen3->prph_info_base_addr = 179 cpu_to_le64(trans_pcie->prph_info_dma_addr); 180 ctxt_info_gen3->prph_scratch_base_addr = 181 cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 182 ctxt_info_gen3->prph_scratch_size = 183 cpu_to_le32(sizeof(*prph_scratch)); 184 ctxt_info_gen3->cr_head_idx_arr_base_addr = 185 cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 186 ctxt_info_gen3->tr_tail_idx_arr_base_addr = 187 cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2); 188 ctxt_info_gen3->cr_tail_idx_arr_base_addr = 189 cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4); 190 ctxt_info_gen3->mtr_base_addr = 191 cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr); 192 ctxt_info_gen3->mcr_base_addr = 193 cpu_to_le64(trans_pcie->rxq->used_bd_dma); 194 ctxt_info_gen3->mtr_size = 195 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); 196 ctxt_info_gen3->mcr_size = 197 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); 198 199 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 200 trans_pcie->prph_info = prph_info; 201 trans_pcie->prph_scratch = prph_scratch; 202 203 /* Allocate IML */ 204 trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len, 205 &trans_pcie->iml_dma_addr, 206 GFP_KERNEL); 207 if (!trans_pcie->iml) { 208 ret = -ENOMEM; 209 goto err_free_ctxt_info; 210 } 211 212 memcpy(trans_pcie->iml, trans->iml, trans->iml_len); 213 214 iwl_enable_fw_load_int_ctx_info(trans); 215 216 /* kick FW self load */ 217 iwl_write64(trans, CSR_CTXT_INFO_ADDR, 218 trans_pcie->ctxt_info_dma_addr); 219 iwl_write64(trans, CSR_IML_DATA_ADDR, 220 trans_pcie->iml_dma_addr); 221 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 222 223 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, 224 CSR_AUTO_FUNC_BOOT_ENA); 225 226 return 0; 227 228 err_free_ctxt_info: 229 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 230 trans_pcie->ctxt_info_gen3, 231 trans_pcie->ctxt_info_dma_addr); 232 trans_pcie->ctxt_info_gen3 = NULL; 233 err_free_prph_info: 234 dma_free_coherent(trans->dev, PAGE_SIZE, prph_info, 235 trans_pcie->prph_info_dma_addr); 236 237 err_free_prph_scratch: 238 dma_free_coherent(trans->dev, 239 sizeof(*prph_scratch), 240 prph_scratch, 241 trans_pcie->prph_scratch_dma_addr); 242 return ret; 243 244 } 245 246 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive) 247 { 248 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 249 250 if (trans_pcie->iml) { 251 dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml, 252 trans_pcie->iml_dma_addr); 253 trans_pcie->iml_dma_addr = 0; 254 trans_pcie->iml = NULL; 255 } 256 257 iwl_pcie_ctxt_info_free_fw_img(trans); 258 259 if (alive) 260 return; 261 262 if (!trans_pcie->ctxt_info_gen3) 263 return; 264 265 /* ctxt_info_gen3 and prph_scratch are still needed for PNVM load */ 266 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 267 trans_pcie->ctxt_info_gen3, 268 trans_pcie->ctxt_info_dma_addr); 269 trans_pcie->ctxt_info_dma_addr = 0; 270 trans_pcie->ctxt_info_gen3 = NULL; 271 272 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 273 trans_pcie->prph_scratch, 274 trans_pcie->prph_scratch_dma_addr); 275 trans_pcie->prph_scratch_dma_addr = 0; 276 trans_pcie->prph_scratch = NULL; 277 278 /* this is needed for the entire lifetime */ 279 dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info, 280 trans_pcie->prph_info_dma_addr); 281 trans_pcie->prph_info_dma_addr = 0; 282 trans_pcie->prph_info = NULL; 283 } 284 285 static int iwl_pcie_load_payloads_continuously(struct iwl_trans *trans, 286 const struct iwl_pnvm_image *pnvm_data, 287 struct iwl_dram_data *dram) 288 { 289 u32 len, len0, len1; 290 291 if (pnvm_data->n_chunks != UNFRAGMENTED_PNVM_PAYLOADS_NUMBER) { 292 IWL_DEBUG_FW(trans, "expected 2 payloads, got %d.\n", 293 pnvm_data->n_chunks); 294 return -EINVAL; 295 } 296 297 len0 = pnvm_data->chunks[0].len; 298 len1 = pnvm_data->chunks[1].len; 299 if (len1 > 0xFFFFFFFF - len0) { 300 IWL_DEBUG_FW(trans, "sizes of payloads overflow.\n"); 301 return -EINVAL; 302 } 303 len = len0 + len1; 304 305 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len, 306 &dram->physical); 307 if (!dram->block) { 308 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n"); 309 return -ENOMEM; 310 } 311 312 dram->size = len; 313 memcpy(dram->block, pnvm_data->chunks[0].data, len0); 314 memcpy((u8 *)dram->block + len0, pnvm_data->chunks[1].data, len1); 315 316 return 0; 317 } 318 319 static int iwl_pcie_load_payloads_segments 320 (struct iwl_trans *trans, 321 struct iwl_dram_regions *dram_regions, 322 const struct iwl_pnvm_image *pnvm_data) 323 { 324 struct iwl_dram_data *cur_payload_dram = &dram_regions->drams[0]; 325 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; 326 struct iwl_prph_scrath_mem_desc_addr_array *addresses; 327 const void *data; 328 u32 len; 329 int i; 330 331 /* allocate and init DRAM descriptors array */ 332 len = sizeof(struct iwl_prph_scrath_mem_desc_addr_array); 333 desc_dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent 334 (trans, 335 len, 336 &desc_dram->physical); 337 if (!desc_dram->block) { 338 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n"); 339 return -ENOMEM; 340 } 341 desc_dram->size = len; 342 memset(desc_dram->block, 0, len); 343 344 /* allocate DRAM region for each payload */ 345 dram_regions->n_regions = 0; 346 for (i = 0; i < pnvm_data->n_chunks; i++) { 347 len = pnvm_data->chunks[i].len; 348 data = pnvm_data->chunks[i].data; 349 350 if (iwl_pcie_ctxt_info_alloc_dma(trans, 351 data, 352 len, 353 cur_payload_dram)) { 354 iwl_trans_pcie_free_pnvm_dram_regions(dram_regions, 355 trans->dev); 356 return -ENOMEM; 357 } 358 359 dram_regions->n_regions++; 360 cur_payload_dram++; 361 } 362 363 /* fill desc with the DRAM payloads addresses */ 364 addresses = desc_dram->block; 365 for (i = 0; i < pnvm_data->n_chunks; i++) { 366 addresses->mem_descs[i] = 367 cpu_to_le64(dram_regions->drams[i].physical); 368 } 369 370 return 0; 371 372 } 373 374 int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans, 375 const struct iwl_pnvm_image *pnvm_payloads, 376 const struct iwl_ucode_capabilities *capa) 377 { 378 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 379 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 380 &trans_pcie->prph_scratch->ctrl_cfg; 381 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data; 382 int ret = 0; 383 384 /* only allocate the DRAM if not allocated yet */ 385 if (trans->pnvm_loaded) 386 return 0; 387 388 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) 389 return -EBUSY; 390 391 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 392 return 0; 393 394 if (!pnvm_payloads->n_chunks) { 395 IWL_DEBUG_FW(trans, "no payloads\n"); 396 return -EINVAL; 397 } 398 399 /* save payloads in several DRAM sections */ 400 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) { 401 ret = iwl_pcie_load_payloads_segments(trans, 402 dram_regions, 403 pnvm_payloads); 404 if (!ret) 405 trans->pnvm_loaded = true; 406 } else { 407 /* save only in one DRAM section */ 408 ret = iwl_pcie_load_payloads_continuously 409 (trans, 410 pnvm_payloads, 411 &dram_regions->drams[0]); 412 if (!ret) { 413 dram_regions->n_regions = 1; 414 trans->pnvm_loaded = true; 415 } 416 } 417 418 return ret; 419 } 420 421 static inline size_t 422 iwl_dram_regions_size(const struct iwl_dram_regions *dram_regions) 423 { 424 size_t total_size = 0; 425 int i; 426 427 for (i = 0; i < dram_regions->n_regions; i++) 428 total_size += dram_regions->drams[i].size; 429 430 return total_size; 431 } 432 433 static void iwl_pcie_set_pnvm_segments(struct iwl_trans *trans) 434 { 435 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 436 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 437 &trans_pcie->prph_scratch->ctrl_cfg; 438 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data; 439 440 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 441 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical); 442 prph_sc_ctrl->pnvm_cfg.pnvm_size = 443 cpu_to_le32(iwl_dram_regions_size(dram_regions)); 444 } 445 446 static void iwl_pcie_set_continuous_pnvm(struct iwl_trans *trans) 447 { 448 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 449 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 450 &trans_pcie->prph_scratch->ctrl_cfg; 451 452 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 453 cpu_to_le64(trans_pcie->pnvm_data.drams[0].physical); 454 prph_sc_ctrl->pnvm_cfg.pnvm_size = 455 cpu_to_le32(trans_pcie->pnvm_data.drams[0].size); 456 } 457 458 void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 459 const struct iwl_ucode_capabilities *capa) 460 { 461 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 462 return; 463 464 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) 465 iwl_pcie_set_pnvm_segments(trans); 466 else 467 iwl_pcie_set_continuous_pnvm(trans); 468 } 469 470 int iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans, 471 const struct iwl_pnvm_image *payloads, 472 const struct iwl_ucode_capabilities *capa) 473 { 474 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 475 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 476 &trans_pcie->prph_scratch->ctrl_cfg; 477 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data; 478 int ret = 0; 479 480 /* only allocate the DRAM if not allocated yet */ 481 if (trans->reduce_power_loaded) 482 return 0; 483 484 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 485 return 0; 486 487 if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size)) 488 return -EBUSY; 489 490 if (!payloads->n_chunks) { 491 IWL_DEBUG_FW(trans, "no payloads\n"); 492 return -EINVAL; 493 } 494 495 /* save payloads in several DRAM sections */ 496 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) { 497 ret = iwl_pcie_load_payloads_segments(trans, 498 dram_regions, 499 payloads); 500 if (!ret) 501 trans->reduce_power_loaded = true; 502 } else { 503 /* save only in one DRAM section */ 504 ret = iwl_pcie_load_payloads_continuously 505 (trans, 506 payloads, 507 &dram_regions->drams[0]); 508 if (!ret) { 509 dram_regions->n_regions = 1; 510 trans->reduce_power_loaded = true; 511 } 512 } 513 514 return ret; 515 } 516 517 static void iwl_pcie_set_reduce_power_segments(struct iwl_trans *trans) 518 { 519 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 520 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 521 &trans_pcie->prph_scratch->ctrl_cfg; 522 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data; 523 524 prph_sc_ctrl->reduce_power_cfg.base_addr = 525 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical); 526 prph_sc_ctrl->reduce_power_cfg.size = 527 cpu_to_le32(iwl_dram_regions_size(dram_regions)); 528 } 529 530 static void iwl_pcie_set_continuous_reduce_power(struct iwl_trans *trans) 531 { 532 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 533 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 534 &trans_pcie->prph_scratch->ctrl_cfg; 535 536 prph_sc_ctrl->reduce_power_cfg.base_addr = 537 cpu_to_le64(trans_pcie->reduced_tables_data.drams[0].physical); 538 prph_sc_ctrl->reduce_power_cfg.size = 539 cpu_to_le32(trans_pcie->reduced_tables_data.drams[0].size); 540 } 541 542 void 543 iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, 544 const struct iwl_ucode_capabilities *capa) 545 { 546 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 547 return; 548 549 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) 550 iwl_pcie_set_reduce_power_segments(trans); 551 else 552 iwl_pcie_set_continuous_reduce_power(trans); 553 } 554 555