1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2018 Intel Corporation 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * BSD LICENSE 20 * 21 * Copyright(c) 2018 Intel Corporation 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 28 * * Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * * Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in 32 * the documentation and/or other materials provided with the 33 * distribution. 34 * * Neither the name Intel Corporation nor the names of its 35 * contributors may be used to endorse or promote products derived 36 * from this software without specific prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 * 50 *****************************************************************************/ 51 52 #include "iwl-trans.h" 53 #include "iwl-fh.h" 54 #include "iwl-context-info-gen3.h" 55 #include "internal.h" 56 #include "iwl-prph.h" 57 58 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 59 const struct fw_img *fw) 60 { 61 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 62 struct iwl_context_info_gen3 *ctxt_info_gen3; 63 struct iwl_prph_scratch *prph_scratch; 64 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 65 struct iwl_prph_info *prph_info; 66 void *iml_img; 67 u32 control_flags = 0; 68 int ret; 69 70 /* Allocate prph scratch */ 71 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 72 &trans_pcie->prph_scratch_dma_addr, 73 GFP_KERNEL); 74 if (!prph_scratch) 75 return -ENOMEM; 76 77 prph_sc_ctrl = &prph_scratch->ctrl_cfg; 78 79 prph_sc_ctrl->version.version = 0; 80 prph_sc_ctrl->version.mac_id = 81 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); 82 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 83 84 control_flags = IWL_PRPH_SCRATCH_RB_SIZE_4K | 85 IWL_PRPH_SCRATCH_MTR_MODE | 86 (IWL_PRPH_MTR_FORMAT_256B & 87 IWL_PRPH_SCRATCH_MTR_FORMAT) | 88 IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | 89 IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 90 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 91 92 /* initialize RX default queue */ 93 prph_sc_ctrl->rbd_cfg.free_rbd_addr = 94 cpu_to_le64(trans_pcie->rxq->bd_dma); 95 96 /* Configure debug, for integration */ 97 iwl_pcie_alloc_fw_monitor(trans, 0); 98 prph_sc_ctrl->hwm_cfg.hwm_base_addr = 99 cpu_to_le64(trans_pcie->fw_mon_phys); 100 prph_sc_ctrl->hwm_cfg.hwm_size = 101 cpu_to_le32(trans_pcie->fw_mon_size); 102 103 /* allocate ucode sections in dram and set addresses */ 104 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 105 if (ret) { 106 dma_free_coherent(trans->dev, 107 sizeof(*prph_scratch), 108 prph_scratch, 109 trans_pcie->prph_scratch_dma_addr); 110 return ret; 111 } 112 113 /* Allocate prph information 114 * currently we don't assign to the prph info anything, but it would get 115 * assigned later */ 116 prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info), 117 &trans_pcie->prph_info_dma_addr, 118 GFP_KERNEL); 119 if (!prph_info) 120 return -ENOMEM; 121 122 /* Allocate context info */ 123 ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 124 sizeof(*ctxt_info_gen3), 125 &trans_pcie->ctxt_info_dma_addr, 126 GFP_KERNEL); 127 if (!ctxt_info_gen3) 128 return -ENOMEM; 129 130 ctxt_info_gen3->prph_info_base_addr = 131 cpu_to_le64(trans_pcie->prph_info_dma_addr); 132 ctxt_info_gen3->prph_scratch_base_addr = 133 cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 134 ctxt_info_gen3->prph_scratch_size = 135 cpu_to_le32(sizeof(*prph_scratch)); 136 ctxt_info_gen3->cr_head_idx_arr_base_addr = 137 cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 138 ctxt_info_gen3->tr_tail_idx_arr_base_addr = 139 cpu_to_le64(trans_pcie->rxq->tr_tail_dma); 140 ctxt_info_gen3->cr_tail_idx_arr_base_addr = 141 cpu_to_le64(trans_pcie->rxq->cr_tail_dma); 142 ctxt_info_gen3->cr_idx_arr_size = 143 cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS); 144 ctxt_info_gen3->tr_idx_arr_size = 145 cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS); 146 ctxt_info_gen3->mtr_base_addr = 147 cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr); 148 ctxt_info_gen3->mcr_base_addr = 149 cpu_to_le64(trans_pcie->rxq->used_bd_dma); 150 ctxt_info_gen3->mtr_size = 151 cpu_to_le16(TFD_QUEUE_CB_SIZE(TFD_CMD_SLOTS)); 152 ctxt_info_gen3->mcr_size = 153 cpu_to_le16(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE)); 154 155 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 156 trans_pcie->prph_info = prph_info; 157 trans_pcie->prph_scratch = prph_scratch; 158 159 /* Allocate IML */ 160 iml_img = dma_alloc_coherent(trans->dev, trans->iml_len, 161 &trans_pcie->iml_dma_addr, GFP_KERNEL); 162 if (!iml_img) 163 return -ENOMEM; 164 165 memcpy(iml_img, trans->iml, trans->iml_len); 166 167 iwl_enable_interrupts(trans); 168 169 /* kick FW self load */ 170 iwl_write64(trans, CSR_CTXT_INFO_ADDR, 171 trans_pcie->ctxt_info_dma_addr); 172 iwl_write64(trans, CSR_IML_DATA_ADDR, 173 trans_pcie->iml_dma_addr); 174 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 175 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, CSR_AUTO_FUNC_BOOT_ENA); 176 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT); 177 178 return 0; 179 } 180 181 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans) 182 { 183 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 184 185 if (!trans_pcie->ctxt_info_gen3) 186 return; 187 188 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 189 trans_pcie->ctxt_info_gen3, 190 trans_pcie->ctxt_info_dma_addr); 191 trans_pcie->ctxt_info_dma_addr = 0; 192 trans_pcie->ctxt_info_gen3 = NULL; 193 194 iwl_pcie_ctxt_info_free_fw_img(trans); 195 196 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 197 trans_pcie->prph_scratch, 198 trans_pcie->prph_scratch_dma_addr); 199 trans_pcie->prph_scratch_dma_addr = 0; 200 trans_pcie->prph_scratch = NULL; 201 202 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info), 203 trans_pcie->prph_info, 204 trans_pcie->prph_info_dma_addr); 205 trans_pcie->prph_info_dma_addr = 0; 206 trans_pcie->prph_info = NULL; 207 } 208