1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2018 - 2019 Intel Corporation 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * BSD LICENSE 20 * 21 * Copyright(c) 2018 - 2019 Intel Corporation 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 28 * * Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * * Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in 32 * the documentation and/or other materials provided with the 33 * distribution. 34 * * Neither the name Intel Corporation nor the names of its 35 * contributors may be used to endorse or promote products derived 36 * from this software without specific prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 * 50 *****************************************************************************/ 51 52 #include "iwl-trans.h" 53 #include "iwl-fh.h" 54 #include "iwl-context-info-gen3.h" 55 #include "internal.h" 56 #include "iwl-prph.h" 57 58 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 59 const struct fw_img *fw) 60 { 61 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 62 struct iwl_context_info_gen3 *ctxt_info_gen3; 63 struct iwl_prph_scratch *prph_scratch; 64 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 65 struct iwl_prph_info *prph_info; 66 void *iml_img; 67 u32 control_flags = 0; 68 int ret; 69 int cmdq_size = max_t(u32, TFD_CMD_SLOTS, trans->cfg->min_txq_size); 70 71 /* Allocate prph scratch */ 72 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 73 &trans_pcie->prph_scratch_dma_addr, 74 GFP_KERNEL); 75 if (!prph_scratch) 76 return -ENOMEM; 77 78 prph_sc_ctrl = &prph_scratch->ctrl_cfg; 79 80 prph_sc_ctrl->version.version = 0; 81 prph_sc_ctrl->version.mac_id = 82 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); 83 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 84 85 control_flags = IWL_PRPH_SCRATCH_RB_SIZE_4K | 86 IWL_PRPH_SCRATCH_MTR_MODE | 87 (IWL_PRPH_MTR_FORMAT_256B & 88 IWL_PRPH_SCRATCH_MTR_FORMAT) | 89 IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | 90 IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 91 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 92 93 /* initialize RX default queue */ 94 prph_sc_ctrl->rbd_cfg.free_rbd_addr = 95 cpu_to_le64(trans_pcie->rxq->bd_dma); 96 97 /* Configure debug, for integration */ 98 if (!trans->ini_valid) 99 iwl_pcie_alloc_fw_monitor(trans, 0); 100 if (trans->num_blocks) { 101 prph_sc_ctrl->hwm_cfg.hwm_base_addr = 102 cpu_to_le64(trans->fw_mon[0].physical); 103 prph_sc_ctrl->hwm_cfg.hwm_size = 104 cpu_to_le32(trans->fw_mon[0].size); 105 } 106 107 /* allocate ucode sections in dram and set addresses */ 108 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 109 if (ret) { 110 dma_free_coherent(trans->dev, 111 sizeof(*prph_scratch), 112 prph_scratch, 113 trans_pcie->prph_scratch_dma_addr); 114 return ret; 115 } 116 117 /* Allocate prph information 118 * currently we don't assign to the prph info anything, but it would get 119 * assigned later */ 120 prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info), 121 &trans_pcie->prph_info_dma_addr, 122 GFP_KERNEL); 123 if (!prph_info) 124 return -ENOMEM; 125 126 /* Allocate context info */ 127 ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 128 sizeof(*ctxt_info_gen3), 129 &trans_pcie->ctxt_info_dma_addr, 130 GFP_KERNEL); 131 if (!ctxt_info_gen3) 132 return -ENOMEM; 133 134 ctxt_info_gen3->prph_info_base_addr = 135 cpu_to_le64(trans_pcie->prph_info_dma_addr); 136 ctxt_info_gen3->prph_scratch_base_addr = 137 cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 138 ctxt_info_gen3->prph_scratch_size = 139 cpu_to_le32(sizeof(*prph_scratch)); 140 ctxt_info_gen3->cr_head_idx_arr_base_addr = 141 cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 142 ctxt_info_gen3->tr_tail_idx_arr_base_addr = 143 cpu_to_le64(trans_pcie->rxq->tr_tail_dma); 144 ctxt_info_gen3->cr_tail_idx_arr_base_addr = 145 cpu_to_le64(trans_pcie->rxq->cr_tail_dma); 146 ctxt_info_gen3->cr_idx_arr_size = 147 cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS); 148 ctxt_info_gen3->tr_idx_arr_size = 149 cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS); 150 ctxt_info_gen3->mtr_base_addr = 151 cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr); 152 ctxt_info_gen3->mcr_base_addr = 153 cpu_to_le64(trans_pcie->rxq->used_bd_dma); 154 ctxt_info_gen3->mtr_size = 155 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); 156 ctxt_info_gen3->mcr_size = 157 cpu_to_le16(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE)); 158 159 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 160 trans_pcie->prph_info = prph_info; 161 trans_pcie->prph_scratch = prph_scratch; 162 163 /* Allocate IML */ 164 iml_img = dma_alloc_coherent(trans->dev, trans->iml_len, 165 &trans_pcie->iml_dma_addr, GFP_KERNEL); 166 if (!iml_img) 167 return -ENOMEM; 168 169 memcpy(iml_img, trans->iml, trans->iml_len); 170 171 iwl_enable_interrupts(trans); 172 173 /* kick FW self load */ 174 iwl_write64(trans, CSR_CTXT_INFO_ADDR, 175 trans_pcie->ctxt_info_dma_addr); 176 iwl_write64(trans, CSR_IML_DATA_ADDR, 177 trans_pcie->iml_dma_addr); 178 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 179 180 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, 181 CSR_AUTO_FUNC_BOOT_ENA); 182 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 183 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1); 184 else 185 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT); 186 187 return 0; 188 } 189 190 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans) 191 { 192 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 193 194 if (!trans_pcie->ctxt_info_gen3) 195 return; 196 197 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 198 trans_pcie->ctxt_info_gen3, 199 trans_pcie->ctxt_info_dma_addr); 200 trans_pcie->ctxt_info_dma_addr = 0; 201 trans_pcie->ctxt_info_gen3 = NULL; 202 203 iwl_pcie_ctxt_info_free_fw_img(trans); 204 205 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 206 trans_pcie->prph_scratch, 207 trans_pcie->prph_scratch_dma_addr); 208 trans_pcie->prph_scratch_dma_addr = 0; 209 trans_pcie->prph_scratch = NULL; 210 211 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info), 212 trans_pcie->prph_info, 213 trans_pcie->prph_info_dma_addr); 214 trans_pcie->prph_info_dma_addr = 0; 215 trans_pcie->prph_info = NULL; 216 } 217