12ee82402SGolan Ben Ami /****************************************************************************** 22ee82402SGolan Ben Ami * 32ee82402SGolan Ben Ami * This file is provided under a dual BSD/GPLv2 license. When using or 42ee82402SGolan Ben Ami * redistributing this file, you may do so under either license. 52ee82402SGolan Ben Ami * 62ee82402SGolan Ben Ami * GPL LICENSE SUMMARY 72ee82402SGolan Ben Ami * 8cbc63655SGil Adam * Copyright(c) 2018 - 2020 Intel Corporation 92ee82402SGolan Ben Ami * 102ee82402SGolan Ben Ami * This program is free software; you can redistribute it and/or modify 112ee82402SGolan Ben Ami * it under the terms of version 2 of the GNU General Public License as 122ee82402SGolan Ben Ami * published by the Free Software Foundation. 132ee82402SGolan Ben Ami * 142ee82402SGolan Ben Ami * This program is distributed in the hope that it will be useful, but 152ee82402SGolan Ben Ami * WITHOUT ANY WARRANTY; without even the implied warranty of 162ee82402SGolan Ben Ami * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 172ee82402SGolan Ben Ami * General Public License for more details. 182ee82402SGolan Ben Ami * 192ee82402SGolan Ben Ami * BSD LICENSE 202ee82402SGolan Ben Ami * 21cbc63655SGil Adam * Copyright(c) 2018 - 2020 Intel Corporation 222ee82402SGolan Ben Ami * All rights reserved. 232ee82402SGolan Ben Ami * 242ee82402SGolan Ben Ami * Redistribution and use in source and binary forms, with or without 252ee82402SGolan Ben Ami * modification, are permitted provided that the following conditions 262ee82402SGolan Ben Ami * are met: 272ee82402SGolan Ben Ami * 282ee82402SGolan Ben Ami * * Redistributions of source code must retain the above copyright 292ee82402SGolan Ben Ami * notice, this list of conditions and the following disclaimer. 302ee82402SGolan Ben Ami * * Redistributions in binary form must reproduce the above copyright 312ee82402SGolan Ben Ami * notice, this list of conditions and the following disclaimer in 322ee82402SGolan Ben Ami * the documentation and/or other materials provided with the 332ee82402SGolan Ben Ami * distribution. 342ee82402SGolan Ben Ami * * Neither the name Intel Corporation nor the names of its 352ee82402SGolan Ben Ami * contributors may be used to endorse or promote products derived 362ee82402SGolan Ben Ami * from this software without specific prior written permission. 372ee82402SGolan Ben Ami * 382ee82402SGolan Ben Ami * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 392ee82402SGolan Ben Ami * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 402ee82402SGolan Ben Ami * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 412ee82402SGolan Ben Ami * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 422ee82402SGolan Ben Ami * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 432ee82402SGolan Ben Ami * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 442ee82402SGolan Ben Ami * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 452ee82402SGolan Ben Ami * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 462ee82402SGolan Ben Ami * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 472ee82402SGolan Ben Ami * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 482ee82402SGolan Ben Ami * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 492ee82402SGolan Ben Ami * 502ee82402SGolan Ben Ami *****************************************************************************/ 512ee82402SGolan Ben Ami 522ee82402SGolan Ben Ami #include "iwl-trans.h" 532ee82402SGolan Ben Ami #include "iwl-fh.h" 542ee82402SGolan Ben Ami #include "iwl-context-info-gen3.h" 552ee82402SGolan Ben Ami #include "internal.h" 562ee82402SGolan Ben Ami #include "iwl-prph.h" 572ee82402SGolan Ben Ami 58593fae3eSShahar S Matityahu static void 59593fae3eSShahar S Matityahu iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, 60593fae3eSShahar S Matityahu struct iwl_prph_scratch_hwm_cfg *dbg_cfg, 61593fae3eSShahar S Matityahu u32 *control_flags) 62593fae3eSShahar S Matityahu { 63593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 64593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 65593fae3eSShahar S Matityahu u32 dbg_flags = 0; 66593fae3eSShahar S Matityahu 67593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) { 68593fae3eSShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 69593fae3eSShahar S Matityahu 70593fae3eSShahar S Matityahu iwl_pcie_alloc_fw_monitor(trans, 0); 71593fae3eSShahar S Matityahu 72593fae3eSShahar S Matityahu if (fw_mon->size) { 73593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 74593fae3eSShahar S Matityahu 75593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, 76593fae3eSShahar S Matityahu "WRT: Applying DRAM buffer destination\n"); 77593fae3eSShahar S Matityahu 78593fae3eSShahar S Matityahu dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); 79593fae3eSShahar S Matityahu dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); 80593fae3eSShahar S Matityahu } 81593fae3eSShahar S Matityahu 82593fae3eSShahar S Matityahu goto out; 83593fae3eSShahar S Matityahu } 84593fae3eSShahar S Matityahu 85593fae3eSShahar S Matityahu fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; 86593fae3eSShahar S Matityahu 87cbc63655SGil Adam switch (le32_to_cpu(fw_mon_cfg->buf_location)) { 88cbc63655SGil Adam case IWL_FW_INI_LOCATION_SRAM_PATH: 89593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; 90593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, 91593fae3eSShahar S Matityahu "WRT: Applying SMEM buffer destination\n"); 92cbc63655SGil Adam break; 93593fae3eSShahar S Matityahu 94cbc63655SGil Adam case IWL_FW_INI_LOCATION_NPK_PATH: 95cbc63655SGil Adam dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF; 96cbc63655SGil Adam IWL_DEBUG_FW(trans, 97cbc63655SGil Adam "WRT: Applying NPK buffer destination\n"); 98cbc63655SGil Adam break; 99593fae3eSShahar S Matityahu 100cbc63655SGil Adam case IWL_FW_INI_LOCATION_DRAM_PATH: 101cbc63655SGil Adam if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { 102593fae3eSShahar S Matityahu struct iwl_dram_data *frag = 103593fae3eSShahar S Matityahu &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 104593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 105593fae3eSShahar S Matityahu dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); 106593fae3eSShahar S Matityahu dbg_cfg->hwm_size = cpu_to_le32(frag->size); 107cbc63655SGil Adam IWL_DEBUG_FW(trans, 108cbc63655SGil Adam "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", 109cbc63655SGil Adam alloc_id, 110cbc63655SGil Adam trans->dbg.fw_mon_ini[alloc_id].num_frags); 111593fae3eSShahar S Matityahu } 112cbc63655SGil Adam break; 113cbc63655SGil Adam default: 114cbc63655SGil Adam IWL_ERR(trans, "WRT: Invalid buffer destination\n"); 115cbc63655SGil Adam } 116593fae3eSShahar S Matityahu out: 117593fae3eSShahar S Matityahu if (dbg_flags) 118593fae3eSShahar S Matityahu *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; 119593fae3eSShahar S Matityahu } 120593fae3eSShahar S Matityahu 1212ee82402SGolan Ben Ami int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 1222ee82402SGolan Ben Ami const struct fw_img *fw) 1232ee82402SGolan Ben Ami { 1242ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1252ee82402SGolan Ben Ami struct iwl_context_info_gen3 *ctxt_info_gen3; 1262ee82402SGolan Ben Ami struct iwl_prph_scratch *prph_scratch; 1272ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 1282ee82402SGolan Ben Ami struct iwl_prph_info *prph_info; 1292ee82402SGolan Ben Ami void *iml_img; 1302ee82402SGolan Ben Ami u32 control_flags = 0; 1312ee82402SGolan Ben Ami int ret; 132718a8b23SShaul Triebitz int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 133718a8b23SShaul Triebitz trans->cfg->min_txq_size); 1342ee82402SGolan Ben Ami 135d8d66397SJohannes Berg switch (trans_pcie->rx_buf_size) { 136d8d66397SJohannes Berg case IWL_AMSDU_DEF: 137d8d66397SJohannes Berg return -EINVAL; 138d8d66397SJohannes Berg case IWL_AMSDU_2K: 139d8d66397SJohannes Berg break; 140d8d66397SJohannes Berg case IWL_AMSDU_4K: 14161576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 14261576240SJohannes Berg break; 143d8d66397SJohannes Berg case IWL_AMSDU_8K: 14461576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 14561576240SJohannes Berg /* if firmware supports the ext size, tell it */ 14661576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K; 14761576240SJohannes Berg break; 148d8d66397SJohannes Berg case IWL_AMSDU_12K: 149d8d66397SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 15061576240SJohannes Berg /* if firmware supports the ext size, tell it */ 15161576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K; 152d8d66397SJohannes Berg break; 153d8d66397SJohannes Berg } 154d8d66397SJohannes Berg 1552ee82402SGolan Ben Ami /* Allocate prph scratch */ 1562ee82402SGolan Ben Ami prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 1572ee82402SGolan Ben Ami &trans_pcie->prph_scratch_dma_addr, 1582ee82402SGolan Ben Ami GFP_KERNEL); 1592ee82402SGolan Ben Ami if (!prph_scratch) 1602ee82402SGolan Ben Ami return -ENOMEM; 1612ee82402SGolan Ben Ami 1622ee82402SGolan Ben Ami prph_sc_ctrl = &prph_scratch->ctrl_cfg; 1632ee82402SGolan Ben Ami 1642ee82402SGolan Ben Ami prph_sc_ctrl->version.version = 0; 1652ee82402SGolan Ben Ami prph_sc_ctrl->version.mac_id = 1662ee82402SGolan Ben Ami cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); 1672ee82402SGolan Ben Ami prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 1682ee82402SGolan Ben Ami 169d8d66397SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_MTR_MODE; 170d8d66397SJohannes Berg control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT; 1712ee82402SGolan Ben Ami 1722ee82402SGolan Ben Ami /* initialize RX default queue */ 1732ee82402SGolan Ben Ami prph_sc_ctrl->rbd_cfg.free_rbd_addr = 1742ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->bd_dma); 1752ee82402SGolan Ben Ami 176593fae3eSShahar S Matityahu iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, 177593fae3eSShahar S Matityahu &control_flags); 178593fae3eSShahar S Matityahu prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 1799f358c17SGolan Ben Ami 1802ee82402SGolan Ben Ami /* allocate ucode sections in dram and set addresses */ 1812ee82402SGolan Ben Ami ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 1820f4f1994SNavid Emamdoost if (ret) 1830f4f1994SNavid Emamdoost goto err_free_prph_scratch; 1840f4f1994SNavid Emamdoost 1852ee82402SGolan Ben Ami 1862ee82402SGolan Ben Ami /* Allocate prph information 1872ee82402SGolan Ben Ami * currently we don't assign to the prph info anything, but it would get 1882ee82402SGolan Ben Ami * assigned later */ 1892ee82402SGolan Ben Ami prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info), 1902ee82402SGolan Ben Ami &trans_pcie->prph_info_dma_addr, 1912ee82402SGolan Ben Ami GFP_KERNEL); 1920f4f1994SNavid Emamdoost if (!prph_info) { 1930f4f1994SNavid Emamdoost ret = -ENOMEM; 1940f4f1994SNavid Emamdoost goto err_free_prph_scratch; 1950f4f1994SNavid Emamdoost } 1962ee82402SGolan Ben Ami 1972ee82402SGolan Ben Ami /* Allocate context info */ 1982ee82402SGolan Ben Ami ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 1992ee82402SGolan Ben Ami sizeof(*ctxt_info_gen3), 2002ee82402SGolan Ben Ami &trans_pcie->ctxt_info_dma_addr, 2012ee82402SGolan Ben Ami GFP_KERNEL); 2020f4f1994SNavid Emamdoost if (!ctxt_info_gen3) { 2030f4f1994SNavid Emamdoost ret = -ENOMEM; 2040f4f1994SNavid Emamdoost goto err_free_prph_info; 2050f4f1994SNavid Emamdoost } 2062ee82402SGolan Ben Ami 2072ee82402SGolan Ben Ami ctxt_info_gen3->prph_info_base_addr = 2082ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_info_dma_addr); 2092ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_base_addr = 2102ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 2112ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_size = 2122ee82402SGolan Ben Ami cpu_to_le32(sizeof(*prph_scratch)); 2132ee82402SGolan Ben Ami ctxt_info_gen3->cr_head_idx_arr_base_addr = 2142ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 2152ee82402SGolan Ben Ami ctxt_info_gen3->tr_tail_idx_arr_base_addr = 2162ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->tr_tail_dma); 2172ee82402SGolan Ben Ami ctxt_info_gen3->cr_tail_idx_arr_base_addr = 2182ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->cr_tail_dma); 2192ee82402SGolan Ben Ami ctxt_info_gen3->cr_idx_arr_size = 2202ee82402SGolan Ben Ami cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS); 2212ee82402SGolan Ben Ami ctxt_info_gen3->tr_idx_arr_size = 2222ee82402SGolan Ben Ami cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS); 2232ee82402SGolan Ben Ami ctxt_info_gen3->mtr_base_addr = 2244f4822b7SMordechay Goodstein cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr); 2252ee82402SGolan Ben Ami ctxt_info_gen3->mcr_base_addr = 2262ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->used_bd_dma); 2272ee82402SGolan Ben Ami ctxt_info_gen3->mtr_size = 228ff911dcaSShaul Triebitz cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); 2292ee82402SGolan Ben Ami ctxt_info_gen3->mcr_size = 230c042f0c7SJohannes Berg cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); 2312ee82402SGolan Ben Ami 2322ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 2332ee82402SGolan Ben Ami trans_pcie->prph_info = prph_info; 2342ee82402SGolan Ben Ami trans_pcie->prph_scratch = prph_scratch; 2352ee82402SGolan Ben Ami 2362ee82402SGolan Ben Ami /* Allocate IML */ 2372ee82402SGolan Ben Ami iml_img = dma_alloc_coherent(trans->dev, trans->iml_len, 2382ee82402SGolan Ben Ami &trans_pcie->iml_dma_addr, GFP_KERNEL); 2392ee82402SGolan Ben Ami if (!iml_img) 2402ee82402SGolan Ben Ami return -ENOMEM; 2412ee82402SGolan Ben Ami 2422ee82402SGolan Ben Ami memcpy(iml_img, trans->iml, trans->iml_len); 2432ee82402SGolan Ben Ami 244ed3e4c6dSEmmanuel Grumbach iwl_enable_fw_load_int_ctx_info(trans); 2452ee82402SGolan Ben Ami 2462ee82402SGolan Ben Ami /* kick FW self load */ 2472ee82402SGolan Ben Ami iwl_write64(trans, CSR_CTXT_INFO_ADDR, 2482ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 2492ee82402SGolan Ben Ami iwl_write64(trans, CSR_IML_DATA_ADDR, 2502ee82402SGolan Ben Ami trans_pcie->iml_dma_addr); 2512ee82402SGolan Ben Ami iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 252ff911dcaSShaul Triebitz 253ff911dcaSShaul Triebitz iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, 254ff911dcaSShaul Triebitz CSR_AUTO_FUNC_BOOT_ENA); 255*edb62520SJohannes Berg 256*edb62520SJohannes Berg if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) { 257*edb62520SJohannes Berg /* 258*edb62520SJohannes Berg * The firmware initializes this again later (to a smaller 259*edb62520SJohannes Berg * value), but for the boot process initialize the LTR to 260*edb62520SJohannes Berg * ~250 usec. 261*edb62520SJohannes Berg */ 262*edb62520SJohannes Berg u32 val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ | 263*edb62520SJohannes Berg u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 264*edb62520SJohannes Berg CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) | 265*edb62520SJohannes Berg u32_encode_bits(250, 266*edb62520SJohannes Berg CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) | 267*edb62520SJohannes Berg CSR_LTR_LONG_VAL_AD_SNOOP_REQ | 268*edb62520SJohannes Berg u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 269*edb62520SJohannes Berg CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) | 270*edb62520SJohannes Berg u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL); 271*edb62520SJohannes Berg 272*edb62520SJohannes Berg iwl_write32(trans, CSR_LTR_LONG_VAL_AD, val); 273*edb62520SJohannes Berg } 274*edb62520SJohannes Berg 275286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 276ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1); 277ea695b7cSShaul Triebitz else 2782ee82402SGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT); 2792ee82402SGolan Ben Ami 2802ee82402SGolan Ben Ami return 0; 2810f4f1994SNavid Emamdoost 2820f4f1994SNavid Emamdoost err_free_prph_info: 2830f4f1994SNavid Emamdoost dma_free_coherent(trans->dev, 2840f4f1994SNavid Emamdoost sizeof(*prph_info), 2850f4f1994SNavid Emamdoost prph_info, 2860f4f1994SNavid Emamdoost trans_pcie->prph_info_dma_addr); 2870f4f1994SNavid Emamdoost 2880f4f1994SNavid Emamdoost err_free_prph_scratch: 2890f4f1994SNavid Emamdoost dma_free_coherent(trans->dev, 2900f4f1994SNavid Emamdoost sizeof(*prph_scratch), 2910f4f1994SNavid Emamdoost prph_scratch, 2920f4f1994SNavid Emamdoost trans_pcie->prph_scratch_dma_addr); 2930f4f1994SNavid Emamdoost return ret; 2940f4f1994SNavid Emamdoost 2952ee82402SGolan Ben Ami } 2962ee82402SGolan Ben Ami 2972ee82402SGolan Ben Ami void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans) 2982ee82402SGolan Ben Ami { 2992ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3002ee82402SGolan Ben Ami 3012ee82402SGolan Ben Ami if (!trans_pcie->ctxt_info_gen3) 3022ee82402SGolan Ben Ami return; 3032ee82402SGolan Ben Ami 3042ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 3052ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3, 3062ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 3072ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr = 0; 3082ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = NULL; 3092ee82402SGolan Ben Ami 3102ee82402SGolan Ben Ami iwl_pcie_ctxt_info_free_fw_img(trans); 3112ee82402SGolan Ben Ami 3122ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 3132ee82402SGolan Ben Ami trans_pcie->prph_scratch, 3142ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr); 3152ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr = 0; 3162ee82402SGolan Ben Ami trans_pcie->prph_scratch = NULL; 3172ee82402SGolan Ben Ami 3182ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info), 3192ee82402SGolan Ben Ami trans_pcie->prph_info, 3202ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr); 3212ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr = 0; 3222ee82402SGolan Ben Ami trans_pcie->prph_info = NULL; 3236654cd4eSLuca Coelho } 3246654cd4eSLuca Coelho 3256654cd4eSLuca Coelho int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 3266654cd4eSLuca Coelho const void *data, u32 len) 3276654cd4eSLuca Coelho { 3286654cd4eSLuca Coelho struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3296654cd4eSLuca Coelho struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 3306654cd4eSLuca Coelho &trans_pcie->prph_scratch->ctrl_cfg; 3316654cd4eSLuca Coelho int ret; 3326654cd4eSLuca Coelho 3336654cd4eSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 3346654cd4eSLuca Coelho return 0; 3356654cd4eSLuca Coelho 3366654cd4eSLuca Coelho ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len, 3376654cd4eSLuca Coelho &trans_pcie->pnvm_dram); 3386654cd4eSLuca Coelho if (ret < 0) { 3396654cd4eSLuca Coelho IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n", 3406654cd4eSLuca Coelho ret); 3416654cd4eSLuca Coelho return ret; 3426654cd4eSLuca Coelho } 3436654cd4eSLuca Coelho 3446654cd4eSLuca Coelho prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 3456654cd4eSLuca Coelho cpu_to_le64(trans_pcie->pnvm_dram.physical); 3466654cd4eSLuca Coelho prph_sc_ctrl->pnvm_cfg.pnvm_size = 3476654cd4eSLuca Coelho cpu_to_le32(trans_pcie->pnvm_dram.size); 3486654cd4eSLuca Coelho 3496654cd4eSLuca Coelho return 0; 3502ee82402SGolan Ben Ami } 351