18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 38e99ea8dSJohannes Berg * Copyright (C) 2018-2020 Intel Corporation 48e99ea8dSJohannes Berg */ 52ee82402SGolan Ben Ami #include "iwl-trans.h" 62ee82402SGolan Ben Ami #include "iwl-fh.h" 72ee82402SGolan Ben Ami #include "iwl-context-info-gen3.h" 82ee82402SGolan Ben Ami #include "internal.h" 92ee82402SGolan Ben Ami #include "iwl-prph.h" 102ee82402SGolan Ben Ami 11593fae3eSShahar S Matityahu static void 12593fae3eSShahar S Matityahu iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, 13593fae3eSShahar S Matityahu struct iwl_prph_scratch_hwm_cfg *dbg_cfg, 14593fae3eSShahar S Matityahu u32 *control_flags) 15593fae3eSShahar S Matityahu { 16593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 17593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 18593fae3eSShahar S Matityahu u32 dbg_flags = 0; 19593fae3eSShahar S Matityahu 20593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) { 21593fae3eSShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 22593fae3eSShahar S Matityahu 23593fae3eSShahar S Matityahu iwl_pcie_alloc_fw_monitor(trans, 0); 24593fae3eSShahar S Matityahu 25593fae3eSShahar S Matityahu if (fw_mon->size) { 26593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 27593fae3eSShahar S Matityahu 28593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, 29593fae3eSShahar S Matityahu "WRT: Applying DRAM buffer destination\n"); 30593fae3eSShahar S Matityahu 31593fae3eSShahar S Matityahu dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); 32593fae3eSShahar S Matityahu dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); 33593fae3eSShahar S Matityahu } 34593fae3eSShahar S Matityahu 35593fae3eSShahar S Matityahu goto out; 36593fae3eSShahar S Matityahu } 37593fae3eSShahar S Matityahu 38593fae3eSShahar S Matityahu fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; 39593fae3eSShahar S Matityahu 40cbc63655SGil Adam switch (le32_to_cpu(fw_mon_cfg->buf_location)) { 41cbc63655SGil Adam case IWL_FW_INI_LOCATION_SRAM_PATH: 42593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; 43593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, 44593fae3eSShahar S Matityahu "WRT: Applying SMEM buffer destination\n"); 45cbc63655SGil Adam break; 46593fae3eSShahar S Matityahu 47cbc63655SGil Adam case IWL_FW_INI_LOCATION_NPK_PATH: 48cbc63655SGil Adam dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF; 49cbc63655SGil Adam IWL_DEBUG_FW(trans, 50cbc63655SGil Adam "WRT: Applying NPK buffer destination\n"); 51cbc63655SGil Adam break; 52593fae3eSShahar S Matityahu 53cbc63655SGil Adam case IWL_FW_INI_LOCATION_DRAM_PATH: 54cbc63655SGil Adam if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { 55593fae3eSShahar S Matityahu struct iwl_dram_data *frag = 56593fae3eSShahar S Matityahu &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 57593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 58593fae3eSShahar S Matityahu dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); 59593fae3eSShahar S Matityahu dbg_cfg->hwm_size = cpu_to_le32(frag->size); 60cbc63655SGil Adam IWL_DEBUG_FW(trans, 61cbc63655SGil Adam "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", 62cbc63655SGil Adam alloc_id, 63cbc63655SGil Adam trans->dbg.fw_mon_ini[alloc_id].num_frags); 64593fae3eSShahar S Matityahu } 65cbc63655SGil Adam break; 66cbc63655SGil Adam default: 67cbc63655SGil Adam IWL_ERR(trans, "WRT: Invalid buffer destination\n"); 68cbc63655SGil Adam } 69593fae3eSShahar S Matityahu out: 70593fae3eSShahar S Matityahu if (dbg_flags) 71593fae3eSShahar S Matityahu *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; 72593fae3eSShahar S Matityahu } 73593fae3eSShahar S Matityahu 742ee82402SGolan Ben Ami int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 752ee82402SGolan Ben Ami const struct fw_img *fw) 762ee82402SGolan Ben Ami { 772ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 78*ed0022daSJohannes Berg u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ | 79*ed0022daSJohannes Berg u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 80*ed0022daSJohannes Berg CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) | 81*ed0022daSJohannes Berg u32_encode_bits(250, 82*ed0022daSJohannes Berg CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) | 83*ed0022daSJohannes Berg CSR_LTR_LONG_VAL_AD_SNOOP_REQ | 84*ed0022daSJohannes Berg u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 85*ed0022daSJohannes Berg CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) | 86*ed0022daSJohannes Berg u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL); 872ee82402SGolan Ben Ami struct iwl_context_info_gen3 *ctxt_info_gen3; 882ee82402SGolan Ben Ami struct iwl_prph_scratch *prph_scratch; 892ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 902ee82402SGolan Ben Ami struct iwl_prph_info *prph_info; 912ee82402SGolan Ben Ami void *iml_img; 922ee82402SGolan Ben Ami u32 control_flags = 0; 932ee82402SGolan Ben Ami int ret; 94718a8b23SShaul Triebitz int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 95718a8b23SShaul Triebitz trans->cfg->min_txq_size); 962ee82402SGolan Ben Ami 97d8d66397SJohannes Berg switch (trans_pcie->rx_buf_size) { 98d8d66397SJohannes Berg case IWL_AMSDU_DEF: 99d8d66397SJohannes Berg return -EINVAL; 100d8d66397SJohannes Berg case IWL_AMSDU_2K: 101d8d66397SJohannes Berg break; 102d8d66397SJohannes Berg case IWL_AMSDU_4K: 10361576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 10461576240SJohannes Berg break; 105d8d66397SJohannes Berg case IWL_AMSDU_8K: 10661576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 10761576240SJohannes Berg /* if firmware supports the ext size, tell it */ 10861576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K; 10961576240SJohannes Berg break; 110d8d66397SJohannes Berg case IWL_AMSDU_12K: 111d8d66397SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 11261576240SJohannes Berg /* if firmware supports the ext size, tell it */ 1133fa965c2SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K; 114d8d66397SJohannes Berg break; 115d8d66397SJohannes Berg } 116d8d66397SJohannes Berg 1172ee82402SGolan Ben Ami /* Allocate prph scratch */ 1182ee82402SGolan Ben Ami prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 1192ee82402SGolan Ben Ami &trans_pcie->prph_scratch_dma_addr, 1202ee82402SGolan Ben Ami GFP_KERNEL); 1212ee82402SGolan Ben Ami if (!prph_scratch) 1222ee82402SGolan Ben Ami return -ENOMEM; 1232ee82402SGolan Ben Ami 1242ee82402SGolan Ben Ami prph_sc_ctrl = &prph_scratch->ctrl_cfg; 1252ee82402SGolan Ben Ami 1262ee82402SGolan Ben Ami prph_sc_ctrl->version.version = 0; 1272ee82402SGolan Ben Ami prph_sc_ctrl->version.mac_id = 1282ee82402SGolan Ben Ami cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); 1292ee82402SGolan Ben Ami prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 1302ee82402SGolan Ben Ami 131d8d66397SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_MTR_MODE; 132d8d66397SJohannes Berg control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT; 1332ee82402SGolan Ben Ami 1342ee82402SGolan Ben Ami /* initialize RX default queue */ 1352ee82402SGolan Ben Ami prph_sc_ctrl->rbd_cfg.free_rbd_addr = 1362ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->bd_dma); 1372ee82402SGolan Ben Ami 138593fae3eSShahar S Matityahu iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, 139593fae3eSShahar S Matityahu &control_flags); 140593fae3eSShahar S Matityahu prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 1419f358c17SGolan Ben Ami 1422ee82402SGolan Ben Ami /* allocate ucode sections in dram and set addresses */ 1432ee82402SGolan Ben Ami ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 1440f4f1994SNavid Emamdoost if (ret) 1450f4f1994SNavid Emamdoost goto err_free_prph_scratch; 1460f4f1994SNavid Emamdoost 1472ee82402SGolan Ben Ami 1482ee82402SGolan Ben Ami /* Allocate prph information 1492ee82402SGolan Ben Ami * currently we don't assign to the prph info anything, but it would get 1502ee82402SGolan Ben Ami * assigned later */ 1512ee82402SGolan Ben Ami prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info), 1522ee82402SGolan Ben Ami &trans_pcie->prph_info_dma_addr, 1532ee82402SGolan Ben Ami GFP_KERNEL); 1540f4f1994SNavid Emamdoost if (!prph_info) { 1550f4f1994SNavid Emamdoost ret = -ENOMEM; 1560f4f1994SNavid Emamdoost goto err_free_prph_scratch; 1570f4f1994SNavid Emamdoost } 1582ee82402SGolan Ben Ami 1592ee82402SGolan Ben Ami /* Allocate context info */ 1602ee82402SGolan Ben Ami ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 1612ee82402SGolan Ben Ami sizeof(*ctxt_info_gen3), 1622ee82402SGolan Ben Ami &trans_pcie->ctxt_info_dma_addr, 1632ee82402SGolan Ben Ami GFP_KERNEL); 1640f4f1994SNavid Emamdoost if (!ctxt_info_gen3) { 1650f4f1994SNavid Emamdoost ret = -ENOMEM; 1660f4f1994SNavid Emamdoost goto err_free_prph_info; 1670f4f1994SNavid Emamdoost } 1682ee82402SGolan Ben Ami 1692ee82402SGolan Ben Ami ctxt_info_gen3->prph_info_base_addr = 1702ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_info_dma_addr); 1712ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_base_addr = 1722ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 1732ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_size = 1742ee82402SGolan Ben Ami cpu_to_le32(sizeof(*prph_scratch)); 1752ee82402SGolan Ben Ami ctxt_info_gen3->cr_head_idx_arr_base_addr = 1762ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 1772ee82402SGolan Ben Ami ctxt_info_gen3->tr_tail_idx_arr_base_addr = 1782ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->tr_tail_dma); 1792ee82402SGolan Ben Ami ctxt_info_gen3->cr_tail_idx_arr_base_addr = 1802ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->cr_tail_dma); 1812ee82402SGolan Ben Ami ctxt_info_gen3->cr_idx_arr_size = 1822ee82402SGolan Ben Ami cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS); 1832ee82402SGolan Ben Ami ctxt_info_gen3->tr_idx_arr_size = 1842ee82402SGolan Ben Ami cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS); 1852ee82402SGolan Ben Ami ctxt_info_gen3->mtr_base_addr = 1864f4822b7SMordechay Goodstein cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr); 1872ee82402SGolan Ben Ami ctxt_info_gen3->mcr_base_addr = 1882ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->used_bd_dma); 1892ee82402SGolan Ben Ami ctxt_info_gen3->mtr_size = 190ff911dcaSShaul Triebitz cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); 1912ee82402SGolan Ben Ami ctxt_info_gen3->mcr_size = 192c042f0c7SJohannes Berg cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); 1932ee82402SGolan Ben Ami 1942ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 1952ee82402SGolan Ben Ami trans_pcie->prph_info = prph_info; 1962ee82402SGolan Ben Ami trans_pcie->prph_scratch = prph_scratch; 1972ee82402SGolan Ben Ami 1982ee82402SGolan Ben Ami /* Allocate IML */ 1992ee82402SGolan Ben Ami iml_img = dma_alloc_coherent(trans->dev, trans->iml_len, 2002ee82402SGolan Ben Ami &trans_pcie->iml_dma_addr, GFP_KERNEL); 2012ee82402SGolan Ben Ami if (!iml_img) 2022ee82402SGolan Ben Ami return -ENOMEM; 2032ee82402SGolan Ben Ami 2042ee82402SGolan Ben Ami memcpy(iml_img, trans->iml, trans->iml_len); 2052ee82402SGolan Ben Ami 206ed3e4c6dSEmmanuel Grumbach iwl_enable_fw_load_int_ctx_info(trans); 2072ee82402SGolan Ben Ami 2082ee82402SGolan Ben Ami /* kick FW self load */ 2092ee82402SGolan Ben Ami iwl_write64(trans, CSR_CTXT_INFO_ADDR, 2102ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 2112ee82402SGolan Ben Ami iwl_write64(trans, CSR_IML_DATA_ADDR, 2122ee82402SGolan Ben Ami trans_pcie->iml_dma_addr); 2132ee82402SGolan Ben Ami iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 214ff911dcaSShaul Triebitz 215ff911dcaSShaul Triebitz iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, 216ff911dcaSShaul Triebitz CSR_AUTO_FUNC_BOOT_ENA); 217edb62520SJohannes Berg 218edb62520SJohannes Berg /* 219*ed0022daSJohannes Berg * To workaround hardware latency issues during the boot process, 220*ed0022daSJohannes Berg * initialize the LTR to ~250 usec (see ltr_val above). 221*ed0022daSJohannes Berg * The firmware initializes this again later (to a smaller value). 222edb62520SJohannes Berg */ 223*ed0022daSJohannes Berg if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 || 224*ed0022daSJohannes Berg trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) && 225*ed0022daSJohannes Berg !trans->trans_cfg->integrated) { 226*ed0022daSJohannes Berg iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val); 227*ed0022daSJohannes Berg } else if (trans->trans_cfg->integrated && 228*ed0022daSJohannes Berg trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) { 229*ed0022daSJohannes Berg iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL); 230*ed0022daSJohannes Berg iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val); 231edb62520SJohannes Berg } 232edb62520SJohannes Berg 233286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 234ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1); 235ea695b7cSShaul Triebitz else 2362ee82402SGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT); 2372ee82402SGolan Ben Ami 2382ee82402SGolan Ben Ami return 0; 2390f4f1994SNavid Emamdoost 2400f4f1994SNavid Emamdoost err_free_prph_info: 2410f4f1994SNavid Emamdoost dma_free_coherent(trans->dev, 2420f4f1994SNavid Emamdoost sizeof(*prph_info), 2430f4f1994SNavid Emamdoost prph_info, 2440f4f1994SNavid Emamdoost trans_pcie->prph_info_dma_addr); 2450f4f1994SNavid Emamdoost 2460f4f1994SNavid Emamdoost err_free_prph_scratch: 2470f4f1994SNavid Emamdoost dma_free_coherent(trans->dev, 2480f4f1994SNavid Emamdoost sizeof(*prph_scratch), 2490f4f1994SNavid Emamdoost prph_scratch, 2500f4f1994SNavid Emamdoost trans_pcie->prph_scratch_dma_addr); 2510f4f1994SNavid Emamdoost return ret; 2520f4f1994SNavid Emamdoost 2532ee82402SGolan Ben Ami } 2542ee82402SGolan Ben Ami 2552ee82402SGolan Ben Ami void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans) 2562ee82402SGolan Ben Ami { 2572ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2582ee82402SGolan Ben Ami 2592ee82402SGolan Ben Ami if (!trans_pcie->ctxt_info_gen3) 2602ee82402SGolan Ben Ami return; 2612ee82402SGolan Ben Ami 2622ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 2632ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3, 2642ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 2652ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr = 0; 2662ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = NULL; 2672ee82402SGolan Ben Ami 2682ee82402SGolan Ben Ami iwl_pcie_ctxt_info_free_fw_img(trans); 2692ee82402SGolan Ben Ami 2702ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 2712ee82402SGolan Ben Ami trans_pcie->prph_scratch, 2722ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr); 2732ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr = 0; 2742ee82402SGolan Ben Ami trans_pcie->prph_scratch = NULL; 2752ee82402SGolan Ben Ami 2762ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info), 2772ee82402SGolan Ben Ami trans_pcie->prph_info, 2782ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr); 2792ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr = 0; 2802ee82402SGolan Ben Ami trans_pcie->prph_info = NULL; 2816654cd4eSLuca Coelho } 2826654cd4eSLuca Coelho 2836654cd4eSLuca Coelho int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 2846654cd4eSLuca Coelho const void *data, u32 len) 2856654cd4eSLuca Coelho { 2866654cd4eSLuca Coelho struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2876654cd4eSLuca Coelho struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 2886654cd4eSLuca Coelho &trans_pcie->prph_scratch->ctrl_cfg; 2896654cd4eSLuca Coelho int ret; 2906654cd4eSLuca Coelho 2916654cd4eSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 2926654cd4eSLuca Coelho return 0; 2936654cd4eSLuca Coelho 2946654cd4eSLuca Coelho ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len, 2956654cd4eSLuca Coelho &trans_pcie->pnvm_dram); 2966654cd4eSLuca Coelho if (ret < 0) { 2976654cd4eSLuca Coelho IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n", 2986654cd4eSLuca Coelho ret); 2996654cd4eSLuca Coelho return ret; 3006654cd4eSLuca Coelho } 3016654cd4eSLuca Coelho 30234b9434cSJohannes Berg if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) 30334b9434cSJohannes Berg return -EBUSY; 30434b9434cSJohannes Berg 3056654cd4eSLuca Coelho prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 3066654cd4eSLuca Coelho cpu_to_le64(trans_pcie->pnvm_dram.physical); 3076654cd4eSLuca Coelho prph_sc_ctrl->pnvm_cfg.pnvm_size = 3086654cd4eSLuca Coelho cpu_to_le32(trans_pcie->pnvm_dram.size); 3096654cd4eSLuca Coelho 3106654cd4eSLuca Coelho return 0; 3112ee82402SGolan Ben Ami } 312