12ee82402SGolan Ben Ami /****************************************************************************** 22ee82402SGolan Ben Ami * 32ee82402SGolan Ben Ami * This file is provided under a dual BSD/GPLv2 license. When using or 42ee82402SGolan Ben Ami * redistributing this file, you may do so under either license. 52ee82402SGolan Ben Ami * 62ee82402SGolan Ben Ami * GPL LICENSE SUMMARY 72ee82402SGolan Ben Ami * 8ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 92ee82402SGolan Ben Ami * 102ee82402SGolan Ben Ami * This program is free software; you can redistribute it and/or modify 112ee82402SGolan Ben Ami * it under the terms of version 2 of the GNU General Public License as 122ee82402SGolan Ben Ami * published by the Free Software Foundation. 132ee82402SGolan Ben Ami * 142ee82402SGolan Ben Ami * This program is distributed in the hope that it will be useful, but 152ee82402SGolan Ben Ami * WITHOUT ANY WARRANTY; without even the implied warranty of 162ee82402SGolan Ben Ami * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 172ee82402SGolan Ben Ami * General Public License for more details. 182ee82402SGolan Ben Ami * 192ee82402SGolan Ben Ami * BSD LICENSE 202ee82402SGolan Ben Ami * 21ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 222ee82402SGolan Ben Ami * All rights reserved. 232ee82402SGolan Ben Ami * 242ee82402SGolan Ben Ami * Redistribution and use in source and binary forms, with or without 252ee82402SGolan Ben Ami * modification, are permitted provided that the following conditions 262ee82402SGolan Ben Ami * are met: 272ee82402SGolan Ben Ami * 282ee82402SGolan Ben Ami * * Redistributions of source code must retain the above copyright 292ee82402SGolan Ben Ami * notice, this list of conditions and the following disclaimer. 302ee82402SGolan Ben Ami * * Redistributions in binary form must reproduce the above copyright 312ee82402SGolan Ben Ami * notice, this list of conditions and the following disclaimer in 322ee82402SGolan Ben Ami * the documentation and/or other materials provided with the 332ee82402SGolan Ben Ami * distribution. 342ee82402SGolan Ben Ami * * Neither the name Intel Corporation nor the names of its 352ee82402SGolan Ben Ami * contributors may be used to endorse or promote products derived 362ee82402SGolan Ben Ami * from this software without specific prior written permission. 372ee82402SGolan Ben Ami * 382ee82402SGolan Ben Ami * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 392ee82402SGolan Ben Ami * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 402ee82402SGolan Ben Ami * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 412ee82402SGolan Ben Ami * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 422ee82402SGolan Ben Ami * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 432ee82402SGolan Ben Ami * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 442ee82402SGolan Ben Ami * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 452ee82402SGolan Ben Ami * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 462ee82402SGolan Ben Ami * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 472ee82402SGolan Ben Ami * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 482ee82402SGolan Ben Ami * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 492ee82402SGolan Ben Ami * 502ee82402SGolan Ben Ami *****************************************************************************/ 512ee82402SGolan Ben Ami 522ee82402SGolan Ben Ami #include "iwl-trans.h" 532ee82402SGolan Ben Ami #include "iwl-fh.h" 542ee82402SGolan Ben Ami #include "iwl-context-info-gen3.h" 552ee82402SGolan Ben Ami #include "internal.h" 562ee82402SGolan Ben Ami #include "iwl-prph.h" 572ee82402SGolan Ben Ami 58593fae3eSShahar S Matityahu static void 59593fae3eSShahar S Matityahu iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, 60593fae3eSShahar S Matityahu struct iwl_prph_scratch_hwm_cfg *dbg_cfg, 61593fae3eSShahar S Matityahu u32 *control_flags) 62593fae3eSShahar S Matityahu { 63593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 64593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 65593fae3eSShahar S Matityahu u32 dbg_flags = 0; 66593fae3eSShahar S Matityahu 67593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) { 68593fae3eSShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 69593fae3eSShahar S Matityahu 70593fae3eSShahar S Matityahu iwl_pcie_alloc_fw_monitor(trans, 0); 71593fae3eSShahar S Matityahu 72593fae3eSShahar S Matityahu if (fw_mon->size) { 73593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 74593fae3eSShahar S Matityahu 75593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, 76593fae3eSShahar S Matityahu "WRT: Applying DRAM buffer destination\n"); 77593fae3eSShahar S Matityahu 78593fae3eSShahar S Matityahu dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); 79593fae3eSShahar S Matityahu dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); 80593fae3eSShahar S Matityahu } 81593fae3eSShahar S Matityahu 82593fae3eSShahar S Matityahu goto out; 83593fae3eSShahar S Matityahu } 84593fae3eSShahar S Matityahu 85593fae3eSShahar S Matityahu fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; 86593fae3eSShahar S Matityahu 87593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 88593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_SRAM_PATH) { 89593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; 90593fae3eSShahar S Matityahu 91593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, 92593fae3eSShahar S Matityahu "WRT: Applying SMEM buffer destination\n"); 93593fae3eSShahar S Matityahu 94593fae3eSShahar S Matityahu goto out; 95593fae3eSShahar S Matityahu } 96593fae3eSShahar S Matityahu 97593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 98593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_DRAM_PATH && 99593fae3eSShahar S Matityahu trans->dbg.fw_mon_ini[alloc_id].num_frags) { 100593fae3eSShahar S Matityahu struct iwl_dram_data *frag = 101593fae3eSShahar S Matityahu &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 102593fae3eSShahar S Matityahu 103593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 104593fae3eSShahar S Matityahu 105593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, 106593fae3eSShahar S Matityahu "WRT: Applying DRAM destination (alloc_id=%u)\n", 107593fae3eSShahar S Matityahu alloc_id); 108593fae3eSShahar S Matityahu 109593fae3eSShahar S Matityahu dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); 110593fae3eSShahar S Matityahu dbg_cfg->hwm_size = cpu_to_le32(frag->size); 111593fae3eSShahar S Matityahu } 112593fae3eSShahar S Matityahu 113593fae3eSShahar S Matityahu out: 114593fae3eSShahar S Matityahu if (dbg_flags) 115593fae3eSShahar S Matityahu *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; 116593fae3eSShahar S Matityahu } 117593fae3eSShahar S Matityahu 1182ee82402SGolan Ben Ami int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 1192ee82402SGolan Ben Ami const struct fw_img *fw) 1202ee82402SGolan Ben Ami { 1212ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1222ee82402SGolan Ben Ami struct iwl_context_info_gen3 *ctxt_info_gen3; 1232ee82402SGolan Ben Ami struct iwl_prph_scratch *prph_scratch; 1242ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 1252ee82402SGolan Ben Ami struct iwl_prph_info *prph_info; 1262ee82402SGolan Ben Ami void *iml_img; 1272ee82402SGolan Ben Ami u32 control_flags = 0; 1282ee82402SGolan Ben Ami int ret; 129718a8b23SShaul Triebitz int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 130718a8b23SShaul Triebitz trans->cfg->min_txq_size); 1312ee82402SGolan Ben Ami 1322ee82402SGolan Ben Ami /* Allocate prph scratch */ 1332ee82402SGolan Ben Ami prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 1342ee82402SGolan Ben Ami &trans_pcie->prph_scratch_dma_addr, 1352ee82402SGolan Ben Ami GFP_KERNEL); 1362ee82402SGolan Ben Ami if (!prph_scratch) 1372ee82402SGolan Ben Ami return -ENOMEM; 1382ee82402SGolan Ben Ami 1392ee82402SGolan Ben Ami prph_sc_ctrl = &prph_scratch->ctrl_cfg; 1402ee82402SGolan Ben Ami 1412ee82402SGolan Ben Ami prph_sc_ctrl->version.version = 0; 1422ee82402SGolan Ben Ami prph_sc_ctrl->version.mac_id = 1432ee82402SGolan Ben Ami cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); 1442ee82402SGolan Ben Ami prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 1452ee82402SGolan Ben Ami 1462ee82402SGolan Ben Ami control_flags = IWL_PRPH_SCRATCH_RB_SIZE_4K | 1472ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_MTR_MODE | 1482ee82402SGolan Ben Ami (IWL_PRPH_MTR_FORMAT_256B & 149593fae3eSShahar S Matityahu IWL_PRPH_SCRATCH_MTR_FORMAT); 1502ee82402SGolan Ben Ami 1512ee82402SGolan Ben Ami /* initialize RX default queue */ 1522ee82402SGolan Ben Ami prph_sc_ctrl->rbd_cfg.free_rbd_addr = 1532ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->bd_dma); 1542ee82402SGolan Ben Ami 155593fae3eSShahar S Matityahu iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, 156593fae3eSShahar S Matityahu &control_flags); 157593fae3eSShahar S Matityahu prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 1589f358c17SGolan Ben Ami 1592ee82402SGolan Ben Ami /* allocate ucode sections in dram and set addresses */ 1602ee82402SGolan Ben Ami ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 1610f4f1994SNavid Emamdoost if (ret) 1620f4f1994SNavid Emamdoost goto err_free_prph_scratch; 1630f4f1994SNavid Emamdoost 1642ee82402SGolan Ben Ami 1652ee82402SGolan Ben Ami /* Allocate prph information 1662ee82402SGolan Ben Ami * currently we don't assign to the prph info anything, but it would get 1672ee82402SGolan Ben Ami * assigned later */ 1682ee82402SGolan Ben Ami prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info), 1692ee82402SGolan Ben Ami &trans_pcie->prph_info_dma_addr, 1702ee82402SGolan Ben Ami GFP_KERNEL); 1710f4f1994SNavid Emamdoost if (!prph_info) { 1720f4f1994SNavid Emamdoost ret = -ENOMEM; 1730f4f1994SNavid Emamdoost goto err_free_prph_scratch; 1740f4f1994SNavid Emamdoost } 1752ee82402SGolan Ben Ami 1762ee82402SGolan Ben Ami /* Allocate context info */ 1772ee82402SGolan Ben Ami ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 1782ee82402SGolan Ben Ami sizeof(*ctxt_info_gen3), 1792ee82402SGolan Ben Ami &trans_pcie->ctxt_info_dma_addr, 1802ee82402SGolan Ben Ami GFP_KERNEL); 1810f4f1994SNavid Emamdoost if (!ctxt_info_gen3) { 1820f4f1994SNavid Emamdoost ret = -ENOMEM; 1830f4f1994SNavid Emamdoost goto err_free_prph_info; 1840f4f1994SNavid Emamdoost } 1852ee82402SGolan Ben Ami 1862ee82402SGolan Ben Ami ctxt_info_gen3->prph_info_base_addr = 1872ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_info_dma_addr); 1882ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_base_addr = 1892ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 1902ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_size = 1912ee82402SGolan Ben Ami cpu_to_le32(sizeof(*prph_scratch)); 1922ee82402SGolan Ben Ami ctxt_info_gen3->cr_head_idx_arr_base_addr = 1932ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 1942ee82402SGolan Ben Ami ctxt_info_gen3->tr_tail_idx_arr_base_addr = 1952ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->tr_tail_dma); 1962ee82402SGolan Ben Ami ctxt_info_gen3->cr_tail_idx_arr_base_addr = 1972ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->cr_tail_dma); 1982ee82402SGolan Ben Ami ctxt_info_gen3->cr_idx_arr_size = 1992ee82402SGolan Ben Ami cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS); 2002ee82402SGolan Ben Ami ctxt_info_gen3->tr_idx_arr_size = 2012ee82402SGolan Ben Ami cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS); 2022ee82402SGolan Ben Ami ctxt_info_gen3->mtr_base_addr = 2032ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr); 2042ee82402SGolan Ben Ami ctxt_info_gen3->mcr_base_addr = 2052ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->used_bd_dma); 2062ee82402SGolan Ben Ami ctxt_info_gen3->mtr_size = 207ff911dcaSShaul Triebitz cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); 2082ee82402SGolan Ben Ami ctxt_info_gen3->mcr_size = 209c042f0c7SJohannes Berg cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); 2102ee82402SGolan Ben Ami 2112ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 2122ee82402SGolan Ben Ami trans_pcie->prph_info = prph_info; 2132ee82402SGolan Ben Ami trans_pcie->prph_scratch = prph_scratch; 2142ee82402SGolan Ben Ami 2152ee82402SGolan Ben Ami /* Allocate IML */ 2162ee82402SGolan Ben Ami iml_img = dma_alloc_coherent(trans->dev, trans->iml_len, 2172ee82402SGolan Ben Ami &trans_pcie->iml_dma_addr, GFP_KERNEL); 2182ee82402SGolan Ben Ami if (!iml_img) 2192ee82402SGolan Ben Ami return -ENOMEM; 2202ee82402SGolan Ben Ami 2212ee82402SGolan Ben Ami memcpy(iml_img, trans->iml, trans->iml_len); 2222ee82402SGolan Ben Ami 223ed3e4c6dSEmmanuel Grumbach iwl_enable_fw_load_int_ctx_info(trans); 2242ee82402SGolan Ben Ami 2252ee82402SGolan Ben Ami /* kick FW self load */ 2262ee82402SGolan Ben Ami iwl_write64(trans, CSR_CTXT_INFO_ADDR, 2272ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 2282ee82402SGolan Ben Ami iwl_write64(trans, CSR_IML_DATA_ADDR, 2292ee82402SGolan Ben Ami trans_pcie->iml_dma_addr); 2302ee82402SGolan Ben Ami iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 231ff911dcaSShaul Triebitz 232ff911dcaSShaul Triebitz iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, 233ff911dcaSShaul Triebitz CSR_AUTO_FUNC_BOOT_ENA); 234286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 235ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1); 236ea695b7cSShaul Triebitz else 2372ee82402SGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT); 2382ee82402SGolan Ben Ami 2392ee82402SGolan Ben Ami return 0; 2400f4f1994SNavid Emamdoost 2410f4f1994SNavid Emamdoost err_free_prph_info: 2420f4f1994SNavid Emamdoost dma_free_coherent(trans->dev, 2430f4f1994SNavid Emamdoost sizeof(*prph_info), 2440f4f1994SNavid Emamdoost prph_info, 2450f4f1994SNavid Emamdoost trans_pcie->prph_info_dma_addr); 2460f4f1994SNavid Emamdoost 2470f4f1994SNavid Emamdoost err_free_prph_scratch: 2480f4f1994SNavid Emamdoost dma_free_coherent(trans->dev, 2490f4f1994SNavid Emamdoost sizeof(*prph_scratch), 2500f4f1994SNavid Emamdoost prph_scratch, 2510f4f1994SNavid Emamdoost trans_pcie->prph_scratch_dma_addr); 2520f4f1994SNavid Emamdoost return ret; 2530f4f1994SNavid Emamdoost 2542ee82402SGolan Ben Ami } 2552ee82402SGolan Ben Ami 2562ee82402SGolan Ben Ami void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans) 2572ee82402SGolan Ben Ami { 2582ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2592ee82402SGolan Ben Ami 2602ee82402SGolan Ben Ami if (!trans_pcie->ctxt_info_gen3) 2612ee82402SGolan Ben Ami return; 2622ee82402SGolan Ben Ami 2632ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 2642ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3, 2652ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 2662ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr = 0; 2672ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = NULL; 2682ee82402SGolan Ben Ami 2692ee82402SGolan Ben Ami iwl_pcie_ctxt_info_free_fw_img(trans); 2702ee82402SGolan Ben Ami 2712ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 2722ee82402SGolan Ben Ami trans_pcie->prph_scratch, 2732ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr); 2742ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr = 0; 2752ee82402SGolan Ben Ami trans_pcie->prph_scratch = NULL; 2762ee82402SGolan Ben Ami 2772ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info), 2782ee82402SGolan Ben Ami trans_pcie->prph_info, 2792ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr); 2802ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr = 0; 2812ee82402SGolan Ben Ami trans_pcie->prph_info = NULL; 2822ee82402SGolan Ben Ami } 283