12ee82402SGolan Ben Ami /****************************************************************************** 22ee82402SGolan Ben Ami * 32ee82402SGolan Ben Ami * This file is provided under a dual BSD/GPLv2 license. When using or 42ee82402SGolan Ben Ami * redistributing this file, you may do so under either license. 52ee82402SGolan Ben Ami * 62ee82402SGolan Ben Ami * GPL LICENSE SUMMARY 72ee82402SGolan Ben Ami * 82ee82402SGolan Ben Ami * Copyright(c) 2018 Intel Corporation 92ee82402SGolan Ben Ami * 102ee82402SGolan Ben Ami * This program is free software; you can redistribute it and/or modify 112ee82402SGolan Ben Ami * it under the terms of version 2 of the GNU General Public License as 122ee82402SGolan Ben Ami * published by the Free Software Foundation. 132ee82402SGolan Ben Ami * 142ee82402SGolan Ben Ami * This program is distributed in the hope that it will be useful, but 152ee82402SGolan Ben Ami * WITHOUT ANY WARRANTY; without even the implied warranty of 162ee82402SGolan Ben Ami * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 172ee82402SGolan Ben Ami * General Public License for more details. 182ee82402SGolan Ben Ami * 192ee82402SGolan Ben Ami * BSD LICENSE 202ee82402SGolan Ben Ami * 212ee82402SGolan Ben Ami * Copyright(c) 2018 Intel Corporation 222ee82402SGolan Ben Ami * All rights reserved. 232ee82402SGolan Ben Ami * 242ee82402SGolan Ben Ami * Redistribution and use in source and binary forms, with or without 252ee82402SGolan Ben Ami * modification, are permitted provided that the following conditions 262ee82402SGolan Ben Ami * are met: 272ee82402SGolan Ben Ami * 282ee82402SGolan Ben Ami * * Redistributions of source code must retain the above copyright 292ee82402SGolan Ben Ami * notice, this list of conditions and the following disclaimer. 302ee82402SGolan Ben Ami * * Redistributions in binary form must reproduce the above copyright 312ee82402SGolan Ben Ami * notice, this list of conditions and the following disclaimer in 322ee82402SGolan Ben Ami * the documentation and/or other materials provided with the 332ee82402SGolan Ben Ami * distribution. 342ee82402SGolan Ben Ami * * Neither the name Intel Corporation nor the names of its 352ee82402SGolan Ben Ami * contributors may be used to endorse or promote products derived 362ee82402SGolan Ben Ami * from this software without specific prior written permission. 372ee82402SGolan Ben Ami * 382ee82402SGolan Ben Ami * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 392ee82402SGolan Ben Ami * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 402ee82402SGolan Ben Ami * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 412ee82402SGolan Ben Ami * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 422ee82402SGolan Ben Ami * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 432ee82402SGolan Ben Ami * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 442ee82402SGolan Ben Ami * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 452ee82402SGolan Ben Ami * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 462ee82402SGolan Ben Ami * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 472ee82402SGolan Ben Ami * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 482ee82402SGolan Ben Ami * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 492ee82402SGolan Ben Ami * 502ee82402SGolan Ben Ami *****************************************************************************/ 512ee82402SGolan Ben Ami 522ee82402SGolan Ben Ami #include "iwl-trans.h" 532ee82402SGolan Ben Ami #include "iwl-fh.h" 542ee82402SGolan Ben Ami #include "iwl-context-info-gen3.h" 552ee82402SGolan Ben Ami #include "internal.h" 562ee82402SGolan Ben Ami #include "iwl-prph.h" 572ee82402SGolan Ben Ami 582ee82402SGolan Ben Ami int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 592ee82402SGolan Ben Ami const struct fw_img *fw) 602ee82402SGolan Ben Ami { 612ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 622ee82402SGolan Ben Ami struct iwl_context_info_gen3 *ctxt_info_gen3; 632ee82402SGolan Ben Ami struct iwl_prph_scratch *prph_scratch; 642ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 652ee82402SGolan Ben Ami struct iwl_prph_info *prph_info; 662ee82402SGolan Ben Ami void *iml_img; 672ee82402SGolan Ben Ami u32 control_flags = 0; 682ee82402SGolan Ben Ami int ret; 692ee82402SGolan Ben Ami 702ee82402SGolan Ben Ami /* Allocate prph scratch */ 712ee82402SGolan Ben Ami prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 722ee82402SGolan Ben Ami &trans_pcie->prph_scratch_dma_addr, 732ee82402SGolan Ben Ami GFP_KERNEL); 742ee82402SGolan Ben Ami if (!prph_scratch) 752ee82402SGolan Ben Ami return -ENOMEM; 762ee82402SGolan Ben Ami 772ee82402SGolan Ben Ami prph_sc_ctrl = &prph_scratch->ctrl_cfg; 782ee82402SGolan Ben Ami 792ee82402SGolan Ben Ami prph_sc_ctrl->version.version = 0; 802ee82402SGolan Ben Ami prph_sc_ctrl->version.mac_id = 812ee82402SGolan Ben Ami cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); 822ee82402SGolan Ben Ami prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 832ee82402SGolan Ben Ami 842ee82402SGolan Ben Ami control_flags = IWL_PRPH_SCRATCH_RB_SIZE_4K | 852ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_MTR_MODE | 862ee82402SGolan Ben Ami (IWL_PRPH_MTR_FORMAT_256B & 87*9f358c17SGolan Ben Ami IWL_PRPH_SCRATCH_MTR_FORMAT) | 88*9f358c17SGolan Ben Ami IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | 89*9f358c17SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 902ee82402SGolan Ben Ami prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 912ee82402SGolan Ben Ami 922ee82402SGolan Ben Ami /* initialize RX default queue */ 932ee82402SGolan Ben Ami prph_sc_ctrl->rbd_cfg.free_rbd_addr = 942ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->bd_dma); 952ee82402SGolan Ben Ami 96*9f358c17SGolan Ben Ami /* Configure debug, for integration */ 97*9f358c17SGolan Ben Ami iwl_pcie_alloc_fw_monitor(trans, 0); 98*9f358c17SGolan Ben Ami prph_sc_ctrl->hwm_cfg.hwm_base_addr = 99*9f358c17SGolan Ben Ami cpu_to_le64(trans_pcie->fw_mon_phys); 100*9f358c17SGolan Ben Ami prph_sc_ctrl->hwm_cfg.hwm_size = 101*9f358c17SGolan Ben Ami cpu_to_le32(trans_pcie->fw_mon_size); 102*9f358c17SGolan Ben Ami 1032ee82402SGolan Ben Ami /* allocate ucode sections in dram and set addresses */ 1042ee82402SGolan Ben Ami ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 1052ee82402SGolan Ben Ami if (ret) { 1062ee82402SGolan Ben Ami dma_free_coherent(trans->dev, 1072ee82402SGolan Ben Ami sizeof(*prph_scratch), 1082ee82402SGolan Ben Ami prph_scratch, 1092ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr); 1102ee82402SGolan Ben Ami return ret; 1112ee82402SGolan Ben Ami } 1122ee82402SGolan Ben Ami 1132ee82402SGolan Ben Ami /* Allocate prph information 1142ee82402SGolan Ben Ami * currently we don't assign to the prph info anything, but it would get 1152ee82402SGolan Ben Ami * assigned later */ 1162ee82402SGolan Ben Ami prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info), 1172ee82402SGolan Ben Ami &trans_pcie->prph_info_dma_addr, 1182ee82402SGolan Ben Ami GFP_KERNEL); 1192ee82402SGolan Ben Ami if (!prph_info) 1202ee82402SGolan Ben Ami return -ENOMEM; 1212ee82402SGolan Ben Ami 1222ee82402SGolan Ben Ami /* Allocate context info */ 1232ee82402SGolan Ben Ami ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 1242ee82402SGolan Ben Ami sizeof(*ctxt_info_gen3), 1252ee82402SGolan Ben Ami &trans_pcie->ctxt_info_dma_addr, 1262ee82402SGolan Ben Ami GFP_KERNEL); 1272ee82402SGolan Ben Ami if (!ctxt_info_gen3) 1282ee82402SGolan Ben Ami return -ENOMEM; 1292ee82402SGolan Ben Ami 1302ee82402SGolan Ben Ami ctxt_info_gen3->prph_info_base_addr = 1312ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_info_dma_addr); 1322ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_base_addr = 1332ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 1342ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_size = 1352ee82402SGolan Ben Ami cpu_to_le32(sizeof(*prph_scratch)); 1362ee82402SGolan Ben Ami ctxt_info_gen3->cr_head_idx_arr_base_addr = 1372ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 1382ee82402SGolan Ben Ami ctxt_info_gen3->tr_tail_idx_arr_base_addr = 1392ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->tr_tail_dma); 1402ee82402SGolan Ben Ami ctxt_info_gen3->cr_tail_idx_arr_base_addr = 1412ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->cr_tail_dma); 1422ee82402SGolan Ben Ami ctxt_info_gen3->cr_idx_arr_size = 1432ee82402SGolan Ben Ami cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS); 1442ee82402SGolan Ben Ami ctxt_info_gen3->tr_idx_arr_size = 1452ee82402SGolan Ben Ami cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS); 1462ee82402SGolan Ben Ami ctxt_info_gen3->mtr_base_addr = 1472ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr); 1482ee82402SGolan Ben Ami ctxt_info_gen3->mcr_base_addr = 1492ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->used_bd_dma); 1502ee82402SGolan Ben Ami ctxt_info_gen3->mtr_size = 1512ee82402SGolan Ben Ami cpu_to_le16(TFD_QUEUE_CB_SIZE(TFD_CMD_SLOTS)); 1522ee82402SGolan Ben Ami ctxt_info_gen3->mcr_size = 1532ee82402SGolan Ben Ami cpu_to_le16(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE)); 1542ee82402SGolan Ben Ami 1552ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 1562ee82402SGolan Ben Ami trans_pcie->prph_info = prph_info; 1572ee82402SGolan Ben Ami trans_pcie->prph_scratch = prph_scratch; 1582ee82402SGolan Ben Ami 1592ee82402SGolan Ben Ami /* Allocate IML */ 1602ee82402SGolan Ben Ami iml_img = dma_alloc_coherent(trans->dev, trans->iml_len, 1612ee82402SGolan Ben Ami &trans_pcie->iml_dma_addr, GFP_KERNEL); 1622ee82402SGolan Ben Ami if (!iml_img) 1632ee82402SGolan Ben Ami return -ENOMEM; 1642ee82402SGolan Ben Ami 1652ee82402SGolan Ben Ami memcpy(iml_img, trans->iml, trans->iml_len); 1662ee82402SGolan Ben Ami 1672ee82402SGolan Ben Ami iwl_enable_interrupts(trans); 1682ee82402SGolan Ben Ami 1692ee82402SGolan Ben Ami /* kick FW self load */ 1702ee82402SGolan Ben Ami iwl_write64(trans, CSR_CTXT_INFO_ADDR, 1712ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 1722ee82402SGolan Ben Ami iwl_write64(trans, CSR_IML_DATA_ADDR, 1732ee82402SGolan Ben Ami trans_pcie->iml_dma_addr); 1742ee82402SGolan Ben Ami iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 1752ee82402SGolan Ben Ami iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, CSR_AUTO_FUNC_BOOT_ENA); 1762ee82402SGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT); 1772ee82402SGolan Ben Ami 1782ee82402SGolan Ben Ami return 0; 1792ee82402SGolan Ben Ami } 1802ee82402SGolan Ben Ami 1812ee82402SGolan Ben Ami void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans) 1822ee82402SGolan Ben Ami { 1832ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1842ee82402SGolan Ben Ami 1852ee82402SGolan Ben Ami if (!trans_pcie->ctxt_info_gen3) 1862ee82402SGolan Ben Ami return; 1872ee82402SGolan Ben Ami 1882ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 1892ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3, 1902ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 1912ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr = 0; 1922ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = NULL; 1932ee82402SGolan Ben Ami 1942ee82402SGolan Ben Ami iwl_pcie_ctxt_info_free_fw_img(trans); 1952ee82402SGolan Ben Ami 1962ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 1972ee82402SGolan Ben Ami trans_pcie->prph_scratch, 1982ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr); 1992ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr = 0; 2002ee82402SGolan Ben Ami trans_pcie->prph_scratch = NULL; 2012ee82402SGolan Ben Ami 2022ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info), 2032ee82402SGolan Ben Ami trans_pcie->prph_info, 2042ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr); 2052ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr = 0; 2062ee82402SGolan Ben Ami trans_pcie->prph_info = NULL; 2072ee82402SGolan Ben Ami } 208