18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 325628bc0SJohannes Berg * Copyright (C) 2018-2021 Intel Corporation 48e99ea8dSJohannes Berg */ 52ee82402SGolan Ben Ami #include "iwl-trans.h" 62ee82402SGolan Ben Ami #include "iwl-fh.h" 72ee82402SGolan Ben Ami #include "iwl-context-info-gen3.h" 82ee82402SGolan Ben Ami #include "internal.h" 92ee82402SGolan Ben Ami #include "iwl-prph.h" 102ee82402SGolan Ben Ami 11593fae3eSShahar S Matityahu static void 12593fae3eSShahar S Matityahu iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, 13593fae3eSShahar S Matityahu struct iwl_prph_scratch_hwm_cfg *dbg_cfg, 14593fae3eSShahar S Matityahu u32 *control_flags) 15593fae3eSShahar S Matityahu { 16593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 17593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 18593fae3eSShahar S Matityahu u32 dbg_flags = 0; 19593fae3eSShahar S Matityahu 20593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) { 21593fae3eSShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 22593fae3eSShahar S Matityahu 23593fae3eSShahar S Matityahu iwl_pcie_alloc_fw_monitor(trans, 0); 24593fae3eSShahar S Matityahu 25593fae3eSShahar S Matityahu if (fw_mon->size) { 26593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 27593fae3eSShahar S Matityahu 28593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, 29593fae3eSShahar S Matityahu "WRT: Applying DRAM buffer destination\n"); 30593fae3eSShahar S Matityahu 31593fae3eSShahar S Matityahu dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); 32593fae3eSShahar S Matityahu dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); 33593fae3eSShahar S Matityahu } 34593fae3eSShahar S Matityahu 35593fae3eSShahar S Matityahu goto out; 36593fae3eSShahar S Matityahu } 37593fae3eSShahar S Matityahu 38593fae3eSShahar S Matityahu fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; 39593fae3eSShahar S Matityahu 40cbc63655SGil Adam switch (le32_to_cpu(fw_mon_cfg->buf_location)) { 41cbc63655SGil Adam case IWL_FW_INI_LOCATION_SRAM_PATH: 42593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; 43593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, 44593fae3eSShahar S Matityahu "WRT: Applying SMEM buffer destination\n"); 45cbc63655SGil Adam break; 46593fae3eSShahar S Matityahu 47cbc63655SGil Adam case IWL_FW_INI_LOCATION_NPK_PATH: 48cbc63655SGil Adam dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF; 49cbc63655SGil Adam IWL_DEBUG_FW(trans, 50cbc63655SGil Adam "WRT: Applying NPK buffer destination\n"); 51cbc63655SGil Adam break; 52593fae3eSShahar S Matityahu 53cbc63655SGil Adam case IWL_FW_INI_LOCATION_DRAM_PATH: 54cbc63655SGil Adam if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { 55593fae3eSShahar S Matityahu struct iwl_dram_data *frag = 56593fae3eSShahar S Matityahu &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 57593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 58593fae3eSShahar S Matityahu dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); 59593fae3eSShahar S Matityahu dbg_cfg->hwm_size = cpu_to_le32(frag->size); 60cbc63655SGil Adam IWL_DEBUG_FW(trans, 61cbc63655SGil Adam "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", 62cbc63655SGil Adam alloc_id, 63cbc63655SGil Adam trans->dbg.fw_mon_ini[alloc_id].num_frags); 64593fae3eSShahar S Matityahu } 65cbc63655SGil Adam break; 66cbc63655SGil Adam default: 67cbc63655SGil Adam IWL_ERR(trans, "WRT: Invalid buffer destination\n"); 68cbc63655SGil Adam } 69593fae3eSShahar S Matityahu out: 70593fae3eSShahar S Matityahu if (dbg_flags) 71593fae3eSShahar S Matityahu *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; 72593fae3eSShahar S Matityahu } 73593fae3eSShahar S Matityahu 742ee82402SGolan Ben Ami int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 752ee82402SGolan Ben Ami const struct fw_img *fw) 762ee82402SGolan Ben Ami { 772ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 782ee82402SGolan Ben Ami struct iwl_context_info_gen3 *ctxt_info_gen3; 792ee82402SGolan Ben Ami struct iwl_prph_scratch *prph_scratch; 802ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 812ee82402SGolan Ben Ami struct iwl_prph_info *prph_info; 822ee82402SGolan Ben Ami u32 control_flags = 0; 832ee82402SGolan Ben Ami int ret; 84718a8b23SShaul Triebitz int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 85718a8b23SShaul Triebitz trans->cfg->min_txq_size); 862ee82402SGolan Ben Ami 87d8d66397SJohannes Berg switch (trans_pcie->rx_buf_size) { 88d8d66397SJohannes Berg case IWL_AMSDU_DEF: 89d8d66397SJohannes Berg return -EINVAL; 90d8d66397SJohannes Berg case IWL_AMSDU_2K: 91d8d66397SJohannes Berg break; 92d8d66397SJohannes Berg case IWL_AMSDU_4K: 9361576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 9461576240SJohannes Berg break; 95d8d66397SJohannes Berg case IWL_AMSDU_8K: 9661576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 9761576240SJohannes Berg /* if firmware supports the ext size, tell it */ 9861576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K; 9961576240SJohannes Berg break; 100d8d66397SJohannes Berg case IWL_AMSDU_12K: 101d8d66397SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 10261576240SJohannes Berg /* if firmware supports the ext size, tell it */ 1033fa965c2SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K; 104d8d66397SJohannes Berg break; 105d8d66397SJohannes Berg } 106d8d66397SJohannes Berg 1072ee82402SGolan Ben Ami /* Allocate prph scratch */ 1082ee82402SGolan Ben Ami prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 1092ee82402SGolan Ben Ami &trans_pcie->prph_scratch_dma_addr, 1102ee82402SGolan Ben Ami GFP_KERNEL); 1112ee82402SGolan Ben Ami if (!prph_scratch) 1122ee82402SGolan Ben Ami return -ENOMEM; 1132ee82402SGolan Ben Ami 1142ee82402SGolan Ben Ami prph_sc_ctrl = &prph_scratch->ctrl_cfg; 1152ee82402SGolan Ben Ami 1162ee82402SGolan Ben Ami prph_sc_ctrl->version.version = 0; 1172ee82402SGolan Ben Ami prph_sc_ctrl->version.mac_id = 1182ee82402SGolan Ben Ami cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); 1192ee82402SGolan Ben Ami prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 1202ee82402SGolan Ben Ami 121d8d66397SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_MTR_MODE; 122d8d66397SJohannes Berg control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT; 1232ee82402SGolan Ben Ami 1242ee82402SGolan Ben Ami /* initialize RX default queue */ 1252ee82402SGolan Ben Ami prph_sc_ctrl->rbd_cfg.free_rbd_addr = 1262ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->bd_dma); 1272ee82402SGolan Ben Ami 128593fae3eSShahar S Matityahu iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, 129593fae3eSShahar S Matityahu &control_flags); 130593fae3eSShahar S Matityahu prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 1319f358c17SGolan Ben Ami 1322ee82402SGolan Ben Ami /* allocate ucode sections in dram and set addresses */ 1332ee82402SGolan Ben Ami ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 1340f4f1994SNavid Emamdoost if (ret) 1350f4f1994SNavid Emamdoost goto err_free_prph_scratch; 1360f4f1994SNavid Emamdoost 1372ee82402SGolan Ben Ami 1382ee82402SGolan Ben Ami /* Allocate prph information 1392ee82402SGolan Ben Ami * currently we don't assign to the prph info anything, but it would get 1408e08e191SJohannes Berg * assigned later 1418e08e191SJohannes Berg * 1428e08e191SJohannes Berg * We also use the second half of this page to give the device some 1438e08e191SJohannes Berg * dummy TR/CR tail pointers - which shouldn't be necessary as we don't 1448e08e191SJohannes Berg * use this, but the hardware still reads/writes there and we can't let 1458e08e191SJohannes Berg * it go do that with a NULL pointer. 1468e08e191SJohannes Berg */ 1478e08e191SJohannes Berg BUILD_BUG_ON(sizeof(*prph_info) > PAGE_SIZE / 2); 1488e08e191SJohannes Berg prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE, 1492ee82402SGolan Ben Ami &trans_pcie->prph_info_dma_addr, 1502ee82402SGolan Ben Ami GFP_KERNEL); 1510f4f1994SNavid Emamdoost if (!prph_info) { 1520f4f1994SNavid Emamdoost ret = -ENOMEM; 1530f4f1994SNavid Emamdoost goto err_free_prph_scratch; 1540f4f1994SNavid Emamdoost } 1552ee82402SGolan Ben Ami 1562ee82402SGolan Ben Ami /* Allocate context info */ 1572ee82402SGolan Ben Ami ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 1582ee82402SGolan Ben Ami sizeof(*ctxt_info_gen3), 1592ee82402SGolan Ben Ami &trans_pcie->ctxt_info_dma_addr, 1602ee82402SGolan Ben Ami GFP_KERNEL); 1610f4f1994SNavid Emamdoost if (!ctxt_info_gen3) { 1620f4f1994SNavid Emamdoost ret = -ENOMEM; 1630f4f1994SNavid Emamdoost goto err_free_prph_info; 1640f4f1994SNavid Emamdoost } 1652ee82402SGolan Ben Ami 1662ee82402SGolan Ben Ami ctxt_info_gen3->prph_info_base_addr = 1672ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_info_dma_addr); 1682ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_base_addr = 1692ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 1702ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_size = 1712ee82402SGolan Ben Ami cpu_to_le32(sizeof(*prph_scratch)); 1722ee82402SGolan Ben Ami ctxt_info_gen3->cr_head_idx_arr_base_addr = 1732ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 1742ee82402SGolan Ben Ami ctxt_info_gen3->tr_tail_idx_arr_base_addr = 1758e08e191SJohannes Berg cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2); 1762ee82402SGolan Ben Ami ctxt_info_gen3->cr_tail_idx_arr_base_addr = 1778e08e191SJohannes Berg cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4); 1782ee82402SGolan Ben Ami ctxt_info_gen3->mtr_base_addr = 1794f4822b7SMordechay Goodstein cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr); 1802ee82402SGolan Ben Ami ctxt_info_gen3->mcr_base_addr = 1812ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->used_bd_dma); 1822ee82402SGolan Ben Ami ctxt_info_gen3->mtr_size = 183ff911dcaSShaul Triebitz cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); 1842ee82402SGolan Ben Ami ctxt_info_gen3->mcr_size = 185c042f0c7SJohannes Berg cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); 1862ee82402SGolan Ben Ami 1872ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 1882ee82402SGolan Ben Ami trans_pcie->prph_info = prph_info; 1892ee82402SGolan Ben Ami trans_pcie->prph_scratch = prph_scratch; 1902ee82402SGolan Ben Ami 1912ee82402SGolan Ben Ami /* Allocate IML */ 192310f60f5SJohannes Berg trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len, 193310f60f5SJohannes Berg &trans_pcie->iml_dma_addr, 194310f60f5SJohannes Berg GFP_KERNEL); 195310f60f5SJohannes Berg if (!trans_pcie->iml) { 1962d6bc752SJohannes Berg ret = -ENOMEM; 1972d6bc752SJohannes Berg goto err_free_ctxt_info; 1982d6bc752SJohannes Berg } 1992ee82402SGolan Ben Ami 200310f60f5SJohannes Berg memcpy(trans_pcie->iml, trans->iml, trans->iml_len); 2012ee82402SGolan Ben Ami 202ed3e4c6dSEmmanuel Grumbach iwl_enable_fw_load_int_ctx_info(trans); 2032ee82402SGolan Ben Ami 2042ee82402SGolan Ben Ami /* kick FW self load */ 2052ee82402SGolan Ben Ami iwl_write64(trans, CSR_CTXT_INFO_ADDR, 2062ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 2072ee82402SGolan Ben Ami iwl_write64(trans, CSR_IML_DATA_ADDR, 2082ee82402SGolan Ben Ami trans_pcie->iml_dma_addr); 2092ee82402SGolan Ben Ami iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 210ff911dcaSShaul Triebitz 211ff911dcaSShaul Triebitz iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, 212ff911dcaSShaul Triebitz CSR_AUTO_FUNC_BOOT_ENA); 213edb62520SJohannes Berg 2142ee82402SGolan Ben Ami return 0; 2150f4f1994SNavid Emamdoost 2162d6bc752SJohannes Berg err_free_ctxt_info: 2172d6bc752SJohannes Berg dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 2182d6bc752SJohannes Berg trans_pcie->ctxt_info_gen3, 2192d6bc752SJohannes Berg trans_pcie->ctxt_info_dma_addr); 2202d6bc752SJohannes Berg trans_pcie->ctxt_info_gen3 = NULL; 2210f4f1994SNavid Emamdoost err_free_prph_info: 2228e08e191SJohannes Berg dma_free_coherent(trans->dev, PAGE_SIZE, prph_info, 2230f4f1994SNavid Emamdoost trans_pcie->prph_info_dma_addr); 2240f4f1994SNavid Emamdoost 2250f4f1994SNavid Emamdoost err_free_prph_scratch: 2260f4f1994SNavid Emamdoost dma_free_coherent(trans->dev, 2270f4f1994SNavid Emamdoost sizeof(*prph_scratch), 2280f4f1994SNavid Emamdoost prph_scratch, 2290f4f1994SNavid Emamdoost trans_pcie->prph_scratch_dma_addr); 2300f4f1994SNavid Emamdoost return ret; 2310f4f1994SNavid Emamdoost 2322ee82402SGolan Ben Ami } 2332ee82402SGolan Ben Ami 23494768975SJohannes Berg void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive) 2352ee82402SGolan Ben Ami { 2362ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2372ee82402SGolan Ben Ami 23894768975SJohannes Berg if (trans_pcie->iml) { 23994768975SJohannes Berg dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml, 24094768975SJohannes Berg trans_pcie->iml_dma_addr); 24194768975SJohannes Berg trans_pcie->iml_dma_addr = 0; 24294768975SJohannes Berg trans_pcie->iml = NULL; 24394768975SJohannes Berg } 24494768975SJohannes Berg 24594768975SJohannes Berg iwl_pcie_ctxt_info_free_fw_img(trans); 24694768975SJohannes Berg 24794768975SJohannes Berg if (alive) 24894768975SJohannes Berg return; 24994768975SJohannes Berg 2502ee82402SGolan Ben Ami if (!trans_pcie->ctxt_info_gen3) 2512ee82402SGolan Ben Ami return; 2522ee82402SGolan Ben Ami 25394768975SJohannes Berg /* ctxt_info_gen3 and prph_scratch are still needed for PNVM load */ 2542ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 2552ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3, 2562ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 2572ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr = 0; 2582ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = NULL; 2592ee82402SGolan Ben Ami 2602ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 2612ee82402SGolan Ben Ami trans_pcie->prph_scratch, 2622ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr); 2632ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr = 0; 2642ee82402SGolan Ben Ami trans_pcie->prph_scratch = NULL; 2652ee82402SGolan Ben Ami 26694768975SJohannes Berg /* this is needed for the entire lifetime */ 2678e08e191SJohannes Berg dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info, 2682ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr); 2692ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr = 0; 2702ee82402SGolan Ben Ami trans_pcie->prph_info = NULL; 2716654cd4eSLuca Coelho } 2726654cd4eSLuca Coelho 2736654cd4eSLuca Coelho int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 2746654cd4eSLuca Coelho const void *data, u32 len) 2756654cd4eSLuca Coelho { 2766654cd4eSLuca Coelho struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2776654cd4eSLuca Coelho struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 2786654cd4eSLuca Coelho &trans_pcie->prph_scratch->ctrl_cfg; 2796654cd4eSLuca Coelho int ret; 2806654cd4eSLuca Coelho 2816654cd4eSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 2826654cd4eSLuca Coelho return 0; 2836654cd4eSLuca Coelho 2844a81598fSLuca Coelho /* only allocate the DRAM if not allocated yet */ 2854a81598fSLuca Coelho if (!trans->pnvm_loaded) { 2864a81598fSLuca Coelho if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) 2874a81598fSLuca Coelho return -EBUSY; 2884a81598fSLuca Coelho 2896654cd4eSLuca Coelho ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len, 2906654cd4eSLuca Coelho &trans_pcie->pnvm_dram); 2916654cd4eSLuca Coelho if (ret < 0) { 2926654cd4eSLuca Coelho IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n", 2936654cd4eSLuca Coelho ret); 2946654cd4eSLuca Coelho return ret; 2956654cd4eSLuca Coelho } 2964a81598fSLuca Coelho } 29734b9434cSJohannes Berg 2986654cd4eSLuca Coelho prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 2996654cd4eSLuca Coelho cpu_to_le64(trans_pcie->pnvm_dram.physical); 3006654cd4eSLuca Coelho prph_sc_ctrl->pnvm_cfg.pnvm_size = 3016654cd4eSLuca Coelho cpu_to_le32(trans_pcie->pnvm_dram.size); 3026654cd4eSLuca Coelho 3036654cd4eSLuca Coelho return 0; 3042ee82402SGolan Ben Ami } 305*9dad325fSLuca Coelho 306*9dad325fSLuca Coelho int iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, 307*9dad325fSLuca Coelho const void *data, u32 len) 308*9dad325fSLuca Coelho { 309*9dad325fSLuca Coelho struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 310*9dad325fSLuca Coelho struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 311*9dad325fSLuca Coelho &trans_pcie->prph_scratch->ctrl_cfg; 312*9dad325fSLuca Coelho int ret; 313*9dad325fSLuca Coelho 314*9dad325fSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 315*9dad325fSLuca Coelho return 0; 316*9dad325fSLuca Coelho 317*9dad325fSLuca Coelho /* only allocate the DRAM if not allocated yet */ 318*9dad325fSLuca Coelho if (!trans->reduce_power_loaded) { 319*9dad325fSLuca Coelho if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size)) 320*9dad325fSLuca Coelho return -EBUSY; 321*9dad325fSLuca Coelho 322*9dad325fSLuca Coelho ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len, 323*9dad325fSLuca Coelho &trans_pcie->reduce_power_dram); 324*9dad325fSLuca Coelho if (ret < 0) { 325*9dad325fSLuca Coelho IWL_DEBUG_FW(trans, 326*9dad325fSLuca Coelho "Failed to allocate reduce power DMA %d.\n", 327*9dad325fSLuca Coelho ret); 328*9dad325fSLuca Coelho return ret; 329*9dad325fSLuca Coelho } 330*9dad325fSLuca Coelho } 331*9dad325fSLuca Coelho 332*9dad325fSLuca Coelho prph_sc_ctrl->reduce_power_cfg.base_addr = 333*9dad325fSLuca Coelho cpu_to_le64(trans_pcie->reduce_power_dram.physical); 334*9dad325fSLuca Coelho prph_sc_ctrl->reduce_power_cfg.size = 335*9dad325fSLuca Coelho cpu_to_le32(trans_pcie->reduce_power_dram.size); 336*9dad325fSLuca Coelho 337*9dad325fSLuca Coelho return 0; 338*9dad325fSLuca Coelho } 339