18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 31c4db761SMukesh Sisodiya * Copyright (C) 2018-2022 Intel Corporation 48e99ea8dSJohannes Berg */ 52ee82402SGolan Ben Ami #include "iwl-trans.h" 62ee82402SGolan Ben Ami #include "iwl-fh.h" 72ee82402SGolan Ben Ami #include "iwl-context-info-gen3.h" 82ee82402SGolan Ben Ami #include "internal.h" 92ee82402SGolan Ben Ami #include "iwl-prph.h" 102ee82402SGolan Ben Ami 11593fae3eSShahar S Matityahu static void 12593fae3eSShahar S Matityahu iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, 13593fae3eSShahar S Matityahu struct iwl_prph_scratch_hwm_cfg *dbg_cfg, 14593fae3eSShahar S Matityahu u32 *control_flags) 15593fae3eSShahar S Matityahu { 16593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 17593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 18593fae3eSShahar S Matityahu u32 dbg_flags = 0; 19593fae3eSShahar S Matityahu 20593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) { 21593fae3eSShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 22593fae3eSShahar S Matityahu 23593fae3eSShahar S Matityahu iwl_pcie_alloc_fw_monitor(trans, 0); 24593fae3eSShahar S Matityahu 25593fae3eSShahar S Matityahu if (fw_mon->size) { 26593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 27593fae3eSShahar S Matityahu 28593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, 29593fae3eSShahar S Matityahu "WRT: Applying DRAM buffer destination\n"); 30593fae3eSShahar S Matityahu 31593fae3eSShahar S Matityahu dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); 32593fae3eSShahar S Matityahu dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); 33593fae3eSShahar S Matityahu } 34593fae3eSShahar S Matityahu 35593fae3eSShahar S Matityahu goto out; 36593fae3eSShahar S Matityahu } 37593fae3eSShahar S Matityahu 38593fae3eSShahar S Matityahu fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; 39593fae3eSShahar S Matityahu 40cbc63655SGil Adam switch (le32_to_cpu(fw_mon_cfg->buf_location)) { 41cbc63655SGil Adam case IWL_FW_INI_LOCATION_SRAM_PATH: 42593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; 43593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, 44593fae3eSShahar S Matityahu "WRT: Applying SMEM buffer destination\n"); 45cbc63655SGil Adam break; 46593fae3eSShahar S Matityahu 47cbc63655SGil Adam case IWL_FW_INI_LOCATION_NPK_PATH: 48cbc63655SGil Adam dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF; 49cbc63655SGil Adam IWL_DEBUG_FW(trans, 50cbc63655SGil Adam "WRT: Applying NPK buffer destination\n"); 51cbc63655SGil Adam break; 52593fae3eSShahar S Matityahu 53cbc63655SGil Adam case IWL_FW_INI_LOCATION_DRAM_PATH: 54cbc63655SGil Adam if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { 55593fae3eSShahar S Matityahu struct iwl_dram_data *frag = 56593fae3eSShahar S Matityahu &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 57593fae3eSShahar S Matityahu dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 58593fae3eSShahar S Matityahu dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); 59593fae3eSShahar S Matityahu dbg_cfg->hwm_size = cpu_to_le32(frag->size); 60f21baf24SMukesh Sisodiya dbg_cfg->debug_token_config = cpu_to_le32(trans->dbg.ucode_preset); 61f21baf24SMukesh Sisodiya IWL_DEBUG_FW(trans, 62f21baf24SMukesh Sisodiya "WRT: Applying DRAM destination (debug_token_config=%u)\n", 63f21baf24SMukesh Sisodiya dbg_cfg->debug_token_config); 64cbc63655SGil Adam IWL_DEBUG_FW(trans, 65cbc63655SGil Adam "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", 66cbc63655SGil Adam alloc_id, 67cbc63655SGil Adam trans->dbg.fw_mon_ini[alloc_id].num_frags); 68593fae3eSShahar S Matityahu } 69cbc63655SGil Adam break; 70cbc63655SGil Adam default: 71cbc63655SGil Adam IWL_ERR(trans, "WRT: Invalid buffer destination\n"); 72cbc63655SGil Adam } 73593fae3eSShahar S Matityahu out: 74593fae3eSShahar S Matityahu if (dbg_flags) 75593fae3eSShahar S Matityahu *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; 76593fae3eSShahar S Matityahu } 77593fae3eSShahar S Matityahu 782ee82402SGolan Ben Ami int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 792ee82402SGolan Ben Ami const struct fw_img *fw) 802ee82402SGolan Ben Ami { 812ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 822ee82402SGolan Ben Ami struct iwl_context_info_gen3 *ctxt_info_gen3; 832ee82402SGolan Ben Ami struct iwl_prph_scratch *prph_scratch; 842ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 852ee82402SGolan Ben Ami struct iwl_prph_info *prph_info; 862ee82402SGolan Ben Ami u32 control_flags = 0; 872ee82402SGolan Ben Ami int ret; 88718a8b23SShaul Triebitz int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 89718a8b23SShaul Triebitz trans->cfg->min_txq_size); 902ee82402SGolan Ben Ami 91d8d66397SJohannes Berg switch (trans_pcie->rx_buf_size) { 92d8d66397SJohannes Berg case IWL_AMSDU_DEF: 93d8d66397SJohannes Berg return -EINVAL; 94d8d66397SJohannes Berg case IWL_AMSDU_2K: 95d8d66397SJohannes Berg break; 96d8d66397SJohannes Berg case IWL_AMSDU_4K: 9761576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 9861576240SJohannes Berg break; 99d8d66397SJohannes Berg case IWL_AMSDU_8K: 10061576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 10161576240SJohannes Berg /* if firmware supports the ext size, tell it */ 10261576240SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K; 10361576240SJohannes Berg break; 104d8d66397SJohannes Berg case IWL_AMSDU_12K: 105d8d66397SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 10661576240SJohannes Berg /* if firmware supports the ext size, tell it */ 1073fa965c2SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K; 108d8d66397SJohannes Berg break; 109d8d66397SJohannes Berg } 110d8d66397SJohannes Berg 1112ee82402SGolan Ben Ami /* Allocate prph scratch */ 1122ee82402SGolan Ben Ami prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 1132ee82402SGolan Ben Ami &trans_pcie->prph_scratch_dma_addr, 1142ee82402SGolan Ben Ami GFP_KERNEL); 1152ee82402SGolan Ben Ami if (!prph_scratch) 1162ee82402SGolan Ben Ami return -ENOMEM; 1172ee82402SGolan Ben Ami 1182ee82402SGolan Ben Ami prph_sc_ctrl = &prph_scratch->ctrl_cfg; 1192ee82402SGolan Ben Ami 1202ee82402SGolan Ben Ami prph_sc_ctrl->version.version = 0; 1212ee82402SGolan Ben Ami prph_sc_ctrl->version.mac_id = 1222ee82402SGolan Ben Ami cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); 1232ee82402SGolan Ben Ami prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 1242ee82402SGolan Ben Ami 125d8d66397SJohannes Berg control_flags |= IWL_PRPH_SCRATCH_MTR_MODE; 126d8d66397SJohannes Berg control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT; 1272ee82402SGolan Ben Ami 1281c4db761SMukesh Sisodiya if (trans->trans_cfg->imr_enabled) 1291c4db761SMukesh Sisodiya control_flags |= IWL_PRPH_SCRATCH_IMR_DEBUG_EN; 1301c4db761SMukesh Sisodiya 1312ee82402SGolan Ben Ami /* initialize RX default queue */ 1322ee82402SGolan Ben Ami prph_sc_ctrl->rbd_cfg.free_rbd_addr = 1332ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->bd_dma); 1342ee82402SGolan Ben Ami 135593fae3eSShahar S Matityahu iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, 136593fae3eSShahar S Matityahu &control_flags); 137593fae3eSShahar S Matityahu prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 1389f358c17SGolan Ben Ami 13909b4c35dSAyala Barazani /* initialize the Step equalizer data */ 14009b4c35dSAyala Barazani prph_sc_ctrl->step_cfg.mbx_addr_0 = cpu_to_le32(trans->mbx_addr_0_step); 14109b4c35dSAyala Barazani prph_sc_ctrl->step_cfg.mbx_addr_1 = cpu_to_le32(trans->mbx_addr_1_step); 14209b4c35dSAyala Barazani 1432ee82402SGolan Ben Ami /* allocate ucode sections in dram and set addresses */ 1442ee82402SGolan Ben Ami ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 1450f4f1994SNavid Emamdoost if (ret) 1460f4f1994SNavid Emamdoost goto err_free_prph_scratch; 1470f4f1994SNavid Emamdoost 1482ee82402SGolan Ben Ami 1492ee82402SGolan Ben Ami /* Allocate prph information 1502ee82402SGolan Ben Ami * currently we don't assign to the prph info anything, but it would get 1518e08e191SJohannes Berg * assigned later 1528e08e191SJohannes Berg * 1538e08e191SJohannes Berg * We also use the second half of this page to give the device some 1548e08e191SJohannes Berg * dummy TR/CR tail pointers - which shouldn't be necessary as we don't 1558e08e191SJohannes Berg * use this, but the hardware still reads/writes there and we can't let 1568e08e191SJohannes Berg * it go do that with a NULL pointer. 1578e08e191SJohannes Berg */ 1588e08e191SJohannes Berg BUILD_BUG_ON(sizeof(*prph_info) > PAGE_SIZE / 2); 1598e08e191SJohannes Berg prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE, 1602ee82402SGolan Ben Ami &trans_pcie->prph_info_dma_addr, 1612ee82402SGolan Ben Ami GFP_KERNEL); 1620f4f1994SNavid Emamdoost if (!prph_info) { 1630f4f1994SNavid Emamdoost ret = -ENOMEM; 1640f4f1994SNavid Emamdoost goto err_free_prph_scratch; 1650f4f1994SNavid Emamdoost } 1662ee82402SGolan Ben Ami 1672ee82402SGolan Ben Ami /* Allocate context info */ 1682ee82402SGolan Ben Ami ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 1692ee82402SGolan Ben Ami sizeof(*ctxt_info_gen3), 1702ee82402SGolan Ben Ami &trans_pcie->ctxt_info_dma_addr, 1712ee82402SGolan Ben Ami GFP_KERNEL); 1720f4f1994SNavid Emamdoost if (!ctxt_info_gen3) { 1730f4f1994SNavid Emamdoost ret = -ENOMEM; 1740f4f1994SNavid Emamdoost goto err_free_prph_info; 1750f4f1994SNavid Emamdoost } 1762ee82402SGolan Ben Ami 1772ee82402SGolan Ben Ami ctxt_info_gen3->prph_info_base_addr = 1782ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_info_dma_addr); 1792ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_base_addr = 1802ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 1812ee82402SGolan Ben Ami ctxt_info_gen3->prph_scratch_size = 1822ee82402SGolan Ben Ami cpu_to_le32(sizeof(*prph_scratch)); 1832ee82402SGolan Ben Ami ctxt_info_gen3->cr_head_idx_arr_base_addr = 1842ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 1852ee82402SGolan Ben Ami ctxt_info_gen3->tr_tail_idx_arr_base_addr = 1868e08e191SJohannes Berg cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2); 1872ee82402SGolan Ben Ami ctxt_info_gen3->cr_tail_idx_arr_base_addr = 1888e08e191SJohannes Berg cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4); 1892ee82402SGolan Ben Ami ctxt_info_gen3->mtr_base_addr = 1904f4822b7SMordechay Goodstein cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr); 1912ee82402SGolan Ben Ami ctxt_info_gen3->mcr_base_addr = 1922ee82402SGolan Ben Ami cpu_to_le64(trans_pcie->rxq->used_bd_dma); 1932ee82402SGolan Ben Ami ctxt_info_gen3->mtr_size = 194ff911dcaSShaul Triebitz cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); 1952ee82402SGolan Ben Ami ctxt_info_gen3->mcr_size = 196c042f0c7SJohannes Berg cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); 1972ee82402SGolan Ben Ami 1982ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 1992ee82402SGolan Ben Ami trans_pcie->prph_info = prph_info; 2002ee82402SGolan Ben Ami trans_pcie->prph_scratch = prph_scratch; 2012ee82402SGolan Ben Ami 2022ee82402SGolan Ben Ami /* Allocate IML */ 203310f60f5SJohannes Berg trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len, 204310f60f5SJohannes Berg &trans_pcie->iml_dma_addr, 205310f60f5SJohannes Berg GFP_KERNEL); 206310f60f5SJohannes Berg if (!trans_pcie->iml) { 2072d6bc752SJohannes Berg ret = -ENOMEM; 2082d6bc752SJohannes Berg goto err_free_ctxt_info; 2092d6bc752SJohannes Berg } 2102ee82402SGolan Ben Ami 211310f60f5SJohannes Berg memcpy(trans_pcie->iml, trans->iml, trans->iml_len); 2122ee82402SGolan Ben Ami 213ed3e4c6dSEmmanuel Grumbach iwl_enable_fw_load_int_ctx_info(trans); 2142ee82402SGolan Ben Ami 2152ee82402SGolan Ben Ami /* kick FW self load */ 2162ee82402SGolan Ben Ami iwl_write64(trans, CSR_CTXT_INFO_ADDR, 2172ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 2182ee82402SGolan Ben Ami iwl_write64(trans, CSR_IML_DATA_ADDR, 2192ee82402SGolan Ben Ami trans_pcie->iml_dma_addr); 2202ee82402SGolan Ben Ami iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 221ff911dcaSShaul Triebitz 222ff911dcaSShaul Triebitz iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, 223ff911dcaSShaul Triebitz CSR_AUTO_FUNC_BOOT_ENA); 224edb62520SJohannes Berg 2252ee82402SGolan Ben Ami return 0; 2260f4f1994SNavid Emamdoost 2272d6bc752SJohannes Berg err_free_ctxt_info: 2282d6bc752SJohannes Berg dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 2292d6bc752SJohannes Berg trans_pcie->ctxt_info_gen3, 2302d6bc752SJohannes Berg trans_pcie->ctxt_info_dma_addr); 2312d6bc752SJohannes Berg trans_pcie->ctxt_info_gen3 = NULL; 2320f4f1994SNavid Emamdoost err_free_prph_info: 2338e08e191SJohannes Berg dma_free_coherent(trans->dev, PAGE_SIZE, prph_info, 2340f4f1994SNavid Emamdoost trans_pcie->prph_info_dma_addr); 2350f4f1994SNavid Emamdoost 2360f4f1994SNavid Emamdoost err_free_prph_scratch: 2370f4f1994SNavid Emamdoost dma_free_coherent(trans->dev, 2380f4f1994SNavid Emamdoost sizeof(*prph_scratch), 2390f4f1994SNavid Emamdoost prph_scratch, 2400f4f1994SNavid Emamdoost trans_pcie->prph_scratch_dma_addr); 2410f4f1994SNavid Emamdoost return ret; 2420f4f1994SNavid Emamdoost 2432ee82402SGolan Ben Ami } 2442ee82402SGolan Ben Ami 24594768975SJohannes Berg void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive) 2462ee82402SGolan Ben Ami { 2472ee82402SGolan Ben Ami struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2482ee82402SGolan Ben Ami 24994768975SJohannes Berg if (trans_pcie->iml) { 25094768975SJohannes Berg dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml, 25194768975SJohannes Berg trans_pcie->iml_dma_addr); 25294768975SJohannes Berg trans_pcie->iml_dma_addr = 0; 25394768975SJohannes Berg trans_pcie->iml = NULL; 25494768975SJohannes Berg } 25594768975SJohannes Berg 25694768975SJohannes Berg iwl_pcie_ctxt_info_free_fw_img(trans); 25794768975SJohannes Berg 25894768975SJohannes Berg if (alive) 25994768975SJohannes Berg return; 26094768975SJohannes Berg 2612ee82402SGolan Ben Ami if (!trans_pcie->ctxt_info_gen3) 2622ee82402SGolan Ben Ami return; 2632ee82402SGolan Ben Ami 26494768975SJohannes Berg /* ctxt_info_gen3 and prph_scratch are still needed for PNVM load */ 2652ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 2662ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3, 2672ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr); 2682ee82402SGolan Ben Ami trans_pcie->ctxt_info_dma_addr = 0; 2692ee82402SGolan Ben Ami trans_pcie->ctxt_info_gen3 = NULL; 2702ee82402SGolan Ben Ami 2712ee82402SGolan Ben Ami dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 2722ee82402SGolan Ben Ami trans_pcie->prph_scratch, 2732ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr); 2742ee82402SGolan Ben Ami trans_pcie->prph_scratch_dma_addr = 0; 2752ee82402SGolan Ben Ami trans_pcie->prph_scratch = NULL; 2762ee82402SGolan Ben Ami 27794768975SJohannes Berg /* this is needed for the entire lifetime */ 2788e08e191SJohannes Berg dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info, 2792ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr); 2802ee82402SGolan Ben Ami trans_pcie->prph_info_dma_addr = 0; 2812ee82402SGolan Ben Ami trans_pcie->prph_info = NULL; 2826654cd4eSLuca Coelho } 2836654cd4eSLuca Coelho 28433182810SAlon Giladi static int iwl_pcie_load_payloads_continuously(struct iwl_trans *trans, 28533182810SAlon Giladi const struct iwl_pnvm_image *pnvm_data, 28633182810SAlon Giladi struct iwl_dram_data *dram) 2876654cd4eSLuca Coelho { 288194d1f84SAlon Giladi u32 len, len0, len1; 2896654cd4eSLuca Coelho 29033182810SAlon Giladi if (pnvm_data->n_chunks != UNFRAGMENTED_PNVM_PAYLOADS_NUMBER) { 2915f408503SAlon Giladi IWL_DEBUG_FW(trans, "expected 2 payloads, got %d.\n", 29233182810SAlon Giladi pnvm_data->n_chunks); 2935f408503SAlon Giladi return -EINVAL; 2946654cd4eSLuca Coelho } 295194d1f84SAlon Giladi 29633182810SAlon Giladi len0 = pnvm_data->chunks[0].len; 29733182810SAlon Giladi len1 = pnvm_data->chunks[1].len; 2985f408503SAlon Giladi if (len1 > 0xFFFFFFFF - len0) { 2995f408503SAlon Giladi IWL_DEBUG_FW(trans, "sizes of payloads overflow.\n"); 3005f408503SAlon Giladi return -EINVAL; 3015f408503SAlon Giladi } 3025f408503SAlon Giladi len = len0 + len1; 3035f408503SAlon Giladi 304194d1f84SAlon Giladi dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len, 305194d1f84SAlon Giladi &dram->physical); 3065f408503SAlon Giladi if (!dram->block) { 3075f408503SAlon Giladi IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n"); 3085f408503SAlon Giladi return -ENOMEM; 3095f408503SAlon Giladi } 310194d1f84SAlon Giladi 3115f408503SAlon Giladi dram->size = len; 31233182810SAlon Giladi memcpy(dram->block, pnvm_data->chunks[0].data, len0); 31333182810SAlon Giladi memcpy((u8 *)dram->block + len0, pnvm_data->chunks[1].data, len1); 314194d1f84SAlon Giladi 315194d1f84SAlon Giladi return 0; 3164a81598fSLuca Coelho } 31734b9434cSJohannes Berg 318*63b9e7b9SAlon Giladi static int iwl_pcie_load_payloads_segments 319*63b9e7b9SAlon Giladi (struct iwl_trans *trans, 320*63b9e7b9SAlon Giladi const struct iwl_pnvm_image *pnvm_data) 32133182810SAlon Giladi { 322*63b9e7b9SAlon Giladi struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 323*63b9e7b9SAlon Giladi struct iwl_dram_data *cur_pnvm_dram = &trans_pcie->pnvm_dram[0], 324*63b9e7b9SAlon Giladi *desc_dram = &trans_pcie->pnvm_regions_desc_array; 325*63b9e7b9SAlon Giladi struct iwl_prph_scrath_mem_desc_addr_array *addresses; 326*63b9e7b9SAlon Giladi const void *data; 327*63b9e7b9SAlon Giladi u32 len; 328*63b9e7b9SAlon Giladi int i; 329*63b9e7b9SAlon Giladi 330*63b9e7b9SAlon Giladi /* allocate and init DRAM descriptors array */ 331*63b9e7b9SAlon Giladi len = sizeof(struct iwl_prph_scrath_mem_desc_addr_array); 332*63b9e7b9SAlon Giladi desc_dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent 333*63b9e7b9SAlon Giladi (trans, 334*63b9e7b9SAlon Giladi len, 335*63b9e7b9SAlon Giladi &desc_dram->physical); 336*63b9e7b9SAlon Giladi if (!desc_dram->block) { 337*63b9e7b9SAlon Giladi IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n"); 33833182810SAlon Giladi return -ENOMEM; 33933182810SAlon Giladi } 340*63b9e7b9SAlon Giladi desc_dram->size = len; 341*63b9e7b9SAlon Giladi memset(desc_dram->block, 0, len); 342*63b9e7b9SAlon Giladi 343*63b9e7b9SAlon Giladi /* allocate DRAM region for each payload */ 344*63b9e7b9SAlon Giladi trans_pcie->n_pnvm_regions = 0; 345*63b9e7b9SAlon Giladi for (i = 0; i < pnvm_data->n_chunks; i++) { 346*63b9e7b9SAlon Giladi len = pnvm_data->chunks[i].len; 347*63b9e7b9SAlon Giladi data = pnvm_data->chunks[i].data; 348*63b9e7b9SAlon Giladi 349*63b9e7b9SAlon Giladi if (iwl_pcie_ctxt_info_alloc_dma(trans, data, len, 350*63b9e7b9SAlon Giladi cur_pnvm_dram)) { 351*63b9e7b9SAlon Giladi iwl_trans_pcie_free_pnvm_dram(trans_pcie, trans->dev); 352*63b9e7b9SAlon Giladi return -ENOMEM; 353*63b9e7b9SAlon Giladi } 354*63b9e7b9SAlon Giladi 355*63b9e7b9SAlon Giladi trans_pcie->n_pnvm_regions++; 356*63b9e7b9SAlon Giladi cur_pnvm_dram++; 357*63b9e7b9SAlon Giladi } 358*63b9e7b9SAlon Giladi 359*63b9e7b9SAlon Giladi /* fill desc with the DRAM payloads addresses */ 360*63b9e7b9SAlon Giladi addresses = desc_dram->block; 361*63b9e7b9SAlon Giladi 362*63b9e7b9SAlon Giladi for (i = 0; i < pnvm_data->n_chunks; i++) { 363*63b9e7b9SAlon Giladi addresses->mem_descs[i] = 364*63b9e7b9SAlon Giladi cpu_to_le64(trans_pcie->pnvm_dram[i].physical); 365*63b9e7b9SAlon Giladi } 366*63b9e7b9SAlon Giladi 367*63b9e7b9SAlon Giladi trans->pnvm_loaded = true; 368*63b9e7b9SAlon Giladi return 0; 369*63b9e7b9SAlon Giladi 370*63b9e7b9SAlon Giladi } 37133182810SAlon Giladi 37233182810SAlon Giladi int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans, 37333182810SAlon Giladi const struct iwl_pnvm_image *pnvm_payloads, 37433182810SAlon Giladi const struct iwl_ucode_capabilities *capa) 37533182810SAlon Giladi { 37633182810SAlon Giladi struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 37733182810SAlon Giladi struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 37833182810SAlon Giladi &trans_pcie->prph_scratch->ctrl_cfg; 37933182810SAlon Giladi struct iwl_dram_data *dram = &trans_pcie->pnvm_dram[0]; 38033182810SAlon Giladi int ret = 0; 38133182810SAlon Giladi 38233182810SAlon Giladi /* only allocate the DRAM if not allocated yet */ 38333182810SAlon Giladi if (trans->pnvm_loaded) 38433182810SAlon Giladi return 0; 38533182810SAlon Giladi 38633182810SAlon Giladi if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) 38733182810SAlon Giladi return -EBUSY; 38833182810SAlon Giladi 38933182810SAlon Giladi if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 39033182810SAlon Giladi return 0; 39133182810SAlon Giladi 392*63b9e7b9SAlon Giladi if (!pnvm_payloads->n_chunks) { 393*63b9e7b9SAlon Giladi IWL_DEBUG_FW(trans, "no payloads\n"); 394*63b9e7b9SAlon Giladi return -EINVAL; 395*63b9e7b9SAlon Giladi } 396*63b9e7b9SAlon Giladi 397*63b9e7b9SAlon Giladi /* allocate several DRAM sections */ 39833182810SAlon Giladi if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) 39933182810SAlon Giladi return iwl_pcie_load_payloads_segments(trans, pnvm_payloads); 40033182810SAlon Giladi 401*63b9e7b9SAlon Giladi /* allocate one DRAM section */ 40233182810SAlon Giladi ret = iwl_pcie_load_payloads_continuously(trans, pnvm_payloads, dram); 40333182810SAlon Giladi if (!ret) { 40433182810SAlon Giladi trans_pcie->n_pnvm_regions = 1; 40533182810SAlon Giladi trans->pnvm_loaded = true; 40633182810SAlon Giladi } 40733182810SAlon Giladi 40833182810SAlon Giladi return ret; 40933182810SAlon Giladi } 41033182810SAlon Giladi 411*63b9e7b9SAlon Giladi static void iwl_pcie_set_pnvm_segments(struct iwl_trans *trans) 412*63b9e7b9SAlon Giladi { 413*63b9e7b9SAlon Giladi struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 414*63b9e7b9SAlon Giladi struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 415*63b9e7b9SAlon Giladi &trans_pcie->prph_scratch->ctrl_cfg; 416*63b9e7b9SAlon Giladi 417*63b9e7b9SAlon Giladi prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 418*63b9e7b9SAlon Giladi cpu_to_le64(trans_pcie->pnvm_regions_desc_array.physical); 419*63b9e7b9SAlon Giladi } 42033182810SAlon Giladi 42133182810SAlon Giladi static void iwl_pcie_set_continuous_pnvm(struct iwl_trans *trans) 422194d1f84SAlon Giladi { 423194d1f84SAlon Giladi struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 424194d1f84SAlon Giladi struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 425194d1f84SAlon Giladi &trans_pcie->prph_scratch->ctrl_cfg; 426194d1f84SAlon Giladi 4276654cd4eSLuca Coelho prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 428f6fa5835SAlon Giladi cpu_to_le64(trans_pcie->pnvm_dram[0].physical); 4296654cd4eSLuca Coelho prph_sc_ctrl->pnvm_cfg.pnvm_size = 430f6fa5835SAlon Giladi cpu_to_le32(trans_pcie->pnvm_dram[0].size); 43133182810SAlon Giladi } 4326654cd4eSLuca Coelho 43333182810SAlon Giladi void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 43433182810SAlon Giladi const struct iwl_ucode_capabilities *capa) 43533182810SAlon Giladi { 43633182810SAlon Giladi if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 43733182810SAlon Giladi return; 43833182810SAlon Giladi 43933182810SAlon Giladi if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) 44033182810SAlon Giladi iwl_pcie_set_pnvm_segments(trans); 44133182810SAlon Giladi else 44233182810SAlon Giladi iwl_pcie_set_continuous_pnvm(trans); 4432ee82402SGolan Ben Ami } 4449dad325fSLuca Coelho 4459dad325fSLuca Coelho int iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, 4469dad325fSLuca Coelho const void *data, u32 len) 4479dad325fSLuca Coelho { 4489dad325fSLuca Coelho struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4499dad325fSLuca Coelho struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 4509dad325fSLuca Coelho &trans_pcie->prph_scratch->ctrl_cfg; 4519dad325fSLuca Coelho int ret; 4529dad325fSLuca Coelho 4539dad325fSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 4549dad325fSLuca Coelho return 0; 4559dad325fSLuca Coelho 4569dad325fSLuca Coelho /* only allocate the DRAM if not allocated yet */ 4579dad325fSLuca Coelho if (!trans->reduce_power_loaded) { 4589dad325fSLuca Coelho if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size)) 4599dad325fSLuca Coelho return -EBUSY; 4609dad325fSLuca Coelho 4619dad325fSLuca Coelho ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len, 4629dad325fSLuca Coelho &trans_pcie->reduce_power_dram); 4639dad325fSLuca Coelho if (ret < 0) { 4649dad325fSLuca Coelho IWL_DEBUG_FW(trans, 4659dad325fSLuca Coelho "Failed to allocate reduce power DMA %d.\n", 4669dad325fSLuca Coelho ret); 4679dad325fSLuca Coelho return ret; 4689dad325fSLuca Coelho } 4699dad325fSLuca Coelho } 4709dad325fSLuca Coelho 4719dad325fSLuca Coelho prph_sc_ctrl->reduce_power_cfg.base_addr = 4729dad325fSLuca Coelho cpu_to_le64(trans_pcie->reduce_power_dram.physical); 4739dad325fSLuca Coelho prph_sc_ctrl->reduce_power_cfg.size = 4749dad325fSLuca Coelho cpu_to_le32(trans_pcie->reduce_power_dram.size); 4759dad325fSLuca Coelho 4769dad325fSLuca Coelho return 0; 4779dad325fSLuca Coelho } 47809b4c35dSAyala Barazani 479