1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <linuxwifi@intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * * Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * * Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * * Neither the name Intel Corporation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 *****************************************************************************/ 67 #include <linux/firmware.h> 68 #include <linux/rtnetlink.h> 69 #include "iwl-trans.h" 70 #include "iwl-csr.h" 71 #include "mvm.h" 72 #include "iwl-eeprom-parse.h" 73 #include "iwl-eeprom-read.h" 74 #include "iwl-nvm-parse.h" 75 #include "iwl-prph.h" 76 77 /* Default NVM size to read */ 78 #define IWL_NVM_DEFAULT_CHUNK_SIZE (2*1024) 79 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 80 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 81 82 #define NVM_WRITE_OPCODE 1 83 #define NVM_READ_OPCODE 0 84 85 /* load nvm chunk response */ 86 enum { 87 READ_NVM_CHUNK_SUCCEED = 0, 88 READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1 89 }; 90 91 /* 92 * prepare the NVM host command w/ the pointers to the nvm buffer 93 * and send it to fw 94 */ 95 static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section, 96 u16 offset, u16 length, const u8 *data) 97 { 98 struct iwl_nvm_access_cmd nvm_access_cmd = { 99 .offset = cpu_to_le16(offset), 100 .length = cpu_to_le16(length), 101 .type = cpu_to_le16(section), 102 .op_code = NVM_WRITE_OPCODE, 103 }; 104 struct iwl_host_cmd cmd = { 105 .id = NVM_ACCESS_CMD, 106 .len = { sizeof(struct iwl_nvm_access_cmd), length }, 107 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 108 .data = { &nvm_access_cmd, data }, 109 /* data may come from vmalloc, so use _DUP */ 110 .dataflags = { 0, IWL_HCMD_DFL_DUP }, 111 }; 112 struct iwl_rx_packet *pkt; 113 struct iwl_nvm_access_resp *nvm_resp; 114 int ret; 115 116 ret = iwl_mvm_send_cmd(mvm, &cmd); 117 if (ret) 118 return ret; 119 120 pkt = cmd.resp_pkt; 121 /* Extract & check NVM write response */ 122 nvm_resp = (void *)pkt->data; 123 if (le16_to_cpu(nvm_resp->status) != READ_NVM_CHUNK_SUCCEED) { 124 IWL_ERR(mvm, 125 "NVM access write command failed for section %u (status = 0x%x)\n", 126 section, le16_to_cpu(nvm_resp->status)); 127 ret = -EIO; 128 } 129 130 iwl_free_resp(&cmd); 131 return ret; 132 } 133 134 static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section, 135 u16 offset, u16 length, u8 *data) 136 { 137 struct iwl_nvm_access_cmd nvm_access_cmd = { 138 .offset = cpu_to_le16(offset), 139 .length = cpu_to_le16(length), 140 .type = cpu_to_le16(section), 141 .op_code = NVM_READ_OPCODE, 142 }; 143 struct iwl_nvm_access_resp *nvm_resp; 144 struct iwl_rx_packet *pkt; 145 struct iwl_host_cmd cmd = { 146 .id = NVM_ACCESS_CMD, 147 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 148 .data = { &nvm_access_cmd, }, 149 }; 150 int ret, bytes_read, offset_read; 151 u8 *resp_data; 152 153 cmd.len[0] = sizeof(struct iwl_nvm_access_cmd); 154 155 ret = iwl_mvm_send_cmd(mvm, &cmd); 156 if (ret) 157 return ret; 158 159 pkt = cmd.resp_pkt; 160 161 /* Extract NVM response */ 162 nvm_resp = (void *)pkt->data; 163 ret = le16_to_cpu(nvm_resp->status); 164 bytes_read = le16_to_cpu(nvm_resp->length); 165 offset_read = le16_to_cpu(nvm_resp->offset); 166 resp_data = nvm_resp->data; 167 if (ret) { 168 if ((offset != 0) && 169 (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) { 170 /* 171 * meaning of NOT_VALID_ADDRESS: 172 * driver try to read chunk from address that is 173 * multiple of 2K and got an error since addr is empty. 174 * meaning of (offset != 0): driver already 175 * read valid data from another chunk so this case 176 * is not an error. 177 */ 178 IWL_DEBUG_EEPROM(mvm->trans->dev, 179 "NVM access command failed on offset 0x%x since that section size is multiple 2K\n", 180 offset); 181 ret = 0; 182 } else { 183 IWL_DEBUG_EEPROM(mvm->trans->dev, 184 "NVM access command failed with status %d (device: %s)\n", 185 ret, mvm->cfg->name); 186 ret = -EIO; 187 } 188 goto exit; 189 } 190 191 if (offset_read != offset) { 192 IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n", 193 offset_read); 194 ret = -EINVAL; 195 goto exit; 196 } 197 198 /* Write data to NVM */ 199 memcpy(data + offset, resp_data, bytes_read); 200 ret = bytes_read; 201 202 exit: 203 iwl_free_resp(&cmd); 204 return ret; 205 } 206 207 static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section, 208 const u8 *data, u16 length) 209 { 210 int offset = 0; 211 212 /* copy data in chunks of 2k (and remainder if any) */ 213 214 while (offset < length) { 215 int chunk_size, ret; 216 217 chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE, 218 length - offset); 219 220 ret = iwl_nvm_write_chunk(mvm, section, offset, 221 chunk_size, data + offset); 222 if (ret < 0) 223 return ret; 224 225 offset += chunk_size; 226 } 227 228 return 0; 229 } 230 231 static void iwl_mvm_nvm_fixups(struct iwl_mvm *mvm, unsigned int section, 232 u8 *data, unsigned int len) 233 { 234 #define IWL_4165_DEVICE_ID 0x5501 235 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 236 237 if (section == NVM_SECTION_TYPE_PHY_SKU && 238 mvm->trans->hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 239 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 240 /* OTP 0x52 bug work around: it's a 1x1 device */ 241 data[3] = ANT_B | (ANT_B << 4); 242 } 243 244 /* 245 * Reads an NVM section completely. 246 * NICs prior to 7000 family doesn't have a real NVM, but just read 247 * section 0 which is the EEPROM. Because the EEPROM reading is unlimited 248 * by uCode, we need to manually check in this case that we don't 249 * overflow and try to read more than the EEPROM size. 250 * For 7000 family NICs, we supply the maximal size we can read, and 251 * the uCode fills the response with as much data as we can, 252 * without overflowing, so no check is needed. 253 */ 254 static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section, 255 u8 *data, u32 size_read) 256 { 257 u16 length, offset = 0; 258 int ret; 259 260 /* Set nvm section read length */ 261 length = IWL_NVM_DEFAULT_CHUNK_SIZE; 262 263 ret = length; 264 265 /* Read the NVM until exhausted (reading less than requested) */ 266 while (ret == length) { 267 /* Check no memory assumptions fail and cause an overflow */ 268 if ((size_read + offset + length) > 269 mvm->cfg->base_params->eeprom_size) { 270 IWL_ERR(mvm, "EEPROM size is too small for NVM\n"); 271 return -ENOBUFS; 272 } 273 274 ret = iwl_nvm_read_chunk(mvm, section, offset, length, data); 275 if (ret < 0) { 276 IWL_DEBUG_EEPROM(mvm->trans->dev, 277 "Cannot read NVM from section %d offset %d, length %d\n", 278 section, offset, length); 279 return ret; 280 } 281 offset += ret; 282 } 283 284 iwl_mvm_nvm_fixups(mvm, section, data, offset); 285 286 IWL_DEBUG_EEPROM(mvm->trans->dev, 287 "NVM section %d read completed\n", section); 288 return offset; 289 } 290 291 static struct iwl_nvm_data * 292 iwl_parse_nvm_sections(struct iwl_mvm *mvm) 293 { 294 struct iwl_nvm_section *sections = mvm->nvm_sections; 295 const __le16 *hw, *sw, *calib, *regulatory, *mac_override, *phy_sku; 296 bool lar_enabled; 297 298 /* Checking for required sections */ 299 if (!mvm->trans->cfg->ext_nvm) { 300 if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || 301 !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) { 302 IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n"); 303 return NULL; 304 } 305 } else { 306 /* SW and REGULATORY sections are mandatory */ 307 if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || 308 !mvm->nvm_sections[NVM_SECTION_TYPE_REGULATORY].data) { 309 IWL_ERR(mvm, 310 "Can't parse empty family 8000 OTP/NVM sections\n"); 311 return NULL; 312 } 313 /* MAC_OVERRIDE or at least HW section must exist */ 314 if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data && 315 !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) { 316 IWL_ERR(mvm, 317 "Can't parse mac_address, empty sections\n"); 318 return NULL; 319 } 320 321 /* PHY_SKU section is mandatory in B0 */ 322 if (!mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) { 323 IWL_ERR(mvm, 324 "Can't parse phy_sku in B0, empty sections\n"); 325 return NULL; 326 } 327 } 328 329 if (WARN_ON(!mvm->cfg)) 330 return NULL; 331 332 hw = (const __le16 *)sections[mvm->cfg->nvm_hw_section_num].data; 333 sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data; 334 calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data; 335 regulatory = (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data; 336 mac_override = 337 (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data; 338 phy_sku = (const __le16 *)sections[NVM_SECTION_TYPE_PHY_SKU].data; 339 340 lar_enabled = !iwlwifi_mod_params.lar_disable && 341 fw_has_capa(&mvm->fw->ucode_capa, 342 IWL_UCODE_TLV_CAPA_LAR_SUPPORT); 343 344 return iwl_parse_nvm_data(mvm->trans, mvm->cfg, hw, sw, calib, 345 regulatory, mac_override, phy_sku, 346 mvm->fw->valid_tx_ant, mvm->fw->valid_rx_ant, 347 lar_enabled); 348 } 349 350 #define MAX_NVM_FILE_LEN 16384 351 352 /* 353 * Reads external NVM from a file into mvm->nvm_sections 354 * 355 * HOW TO CREATE THE NVM FILE FORMAT: 356 * ------------------------------ 357 * 1. create hex file, format: 358 * 3800 -> header 359 * 0000 -> header 360 * 5a40 -> data 361 * 362 * rev - 6 bit (word1) 363 * len - 10 bit (word1) 364 * id - 4 bit (word2) 365 * rsv - 12 bit (word2) 366 * 367 * 2. flip 8bits with 8 bits per line to get the right NVM file format 368 * 369 * 3. create binary file from the hex file 370 * 371 * 4. save as "iNVM_xxx.bin" under /lib/firmware 372 */ 373 int iwl_mvm_read_external_nvm(struct iwl_mvm *mvm) 374 { 375 int ret, section_size; 376 u16 section_id; 377 const struct firmware *fw_entry; 378 const struct { 379 __le16 word1; 380 __le16 word2; 381 u8 data[]; 382 } *file_sec; 383 const u8 *eof; 384 u8 *temp; 385 int max_section_size; 386 const __le32 *dword_buff; 387 388 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 389 #define NVM_WORD2_ID(x) (x >> 12) 390 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 391 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 392 #define NVM_HEADER_0 (0x2A504C54) 393 #define NVM_HEADER_1 (0x4E564D2A) 394 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 395 396 IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from external NVM\n"); 397 398 /* Maximal size depends on NVM version */ 399 if (!mvm->trans->cfg->ext_nvm) 400 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 401 else 402 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 403 404 /* 405 * Obtain NVM image via request_firmware. Since we already used 406 * request_firmware_nowait() for the firmware binary load and only 407 * get here after that we assume the NVM request can be satisfied 408 * synchronously. 409 */ 410 ret = request_firmware(&fw_entry, mvm->nvm_file_name, 411 mvm->trans->dev); 412 if (ret) { 413 IWL_ERR(mvm, "ERROR: %s isn't available %d\n", 414 mvm->nvm_file_name, ret); 415 return ret; 416 } 417 418 IWL_INFO(mvm, "Loaded NVM file %s (%zu bytes)\n", 419 mvm->nvm_file_name, fw_entry->size); 420 421 if (fw_entry->size > MAX_NVM_FILE_LEN) { 422 IWL_ERR(mvm, "NVM file too large\n"); 423 ret = -EINVAL; 424 goto out; 425 } 426 427 eof = fw_entry->data + fw_entry->size; 428 dword_buff = (__le32 *)fw_entry->data; 429 430 /* some NVM file will contain a header. 431 * The header is identified by 2 dwords header as follow: 432 * dword[0] = 0x2A504C54 433 * dword[1] = 0x4E564D2A 434 * 435 * This header must be skipped when providing the NVM data to the FW. 436 */ 437 if (fw_entry->size > NVM_HEADER_SIZE && 438 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 439 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 440 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); 441 IWL_INFO(mvm, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 442 IWL_INFO(mvm, "NVM Manufacturing date %08X\n", 443 le32_to_cpu(dword_buff[3])); 444 445 /* nvm file validation, dword_buff[2] holds the file version */ 446 if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 && 447 CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_C_STEP && 448 le32_to_cpu(dword_buff[2]) < 0xE4A) { 449 ret = -EFAULT; 450 goto out; 451 } 452 } else { 453 file_sec = (void *)fw_entry->data; 454 } 455 456 while (true) { 457 if (file_sec->data > eof) { 458 IWL_ERR(mvm, 459 "ERROR - NVM file too short for section header\n"); 460 ret = -EINVAL; 461 break; 462 } 463 464 /* check for EOF marker */ 465 if (!file_sec->word1 && !file_sec->word2) { 466 ret = 0; 467 break; 468 } 469 470 if (!mvm->trans->cfg->ext_nvm) { 471 section_size = 472 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 473 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 474 } else { 475 section_size = 2 * EXT_NVM_WORD2_LEN( 476 le16_to_cpu(file_sec->word2)); 477 section_id = EXT_NVM_WORD1_ID( 478 le16_to_cpu(file_sec->word1)); 479 } 480 481 if (section_size > max_section_size) { 482 IWL_ERR(mvm, "ERROR - section too large (%d)\n", 483 section_size); 484 ret = -EINVAL; 485 break; 486 } 487 488 if (!section_size) { 489 IWL_ERR(mvm, "ERROR - section empty\n"); 490 ret = -EINVAL; 491 break; 492 } 493 494 if (file_sec->data + section_size > eof) { 495 IWL_ERR(mvm, 496 "ERROR - NVM file too short for section (%d bytes)\n", 497 section_size); 498 ret = -EINVAL; 499 break; 500 } 501 502 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 503 "Invalid NVM section ID %d\n", section_id)) { 504 ret = -EINVAL; 505 break; 506 } 507 508 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 509 if (!temp) { 510 ret = -ENOMEM; 511 break; 512 } 513 514 iwl_mvm_nvm_fixups(mvm, section_id, temp, section_size); 515 516 kfree(mvm->nvm_sections[section_id].data); 517 mvm->nvm_sections[section_id].data = temp; 518 mvm->nvm_sections[section_id].length = section_size; 519 520 /* advance to the next section */ 521 file_sec = (void *)(file_sec->data + section_size); 522 } 523 out: 524 release_firmware(fw_entry); 525 return ret; 526 } 527 528 /* Loads the NVM data stored in mvm->nvm_sections into the NIC */ 529 int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm) 530 { 531 int i, ret = 0; 532 struct iwl_nvm_section *sections = mvm->nvm_sections; 533 534 IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n"); 535 536 for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) { 537 if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length) 538 continue; 539 ret = iwl_nvm_write_section(mvm, i, sections[i].data, 540 sections[i].length); 541 if (ret < 0) { 542 IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret); 543 break; 544 } 545 } 546 return ret; 547 } 548 549 int iwl_mvm_nvm_get_from_fw(struct iwl_mvm *mvm) 550 { 551 struct iwl_nvm_get_info cmd = {}; 552 struct iwl_nvm_get_info_rsp *rsp; 553 struct iwl_trans *trans = mvm->trans; 554 struct iwl_host_cmd hcmd = { 555 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 556 .data = { &cmd, }, 557 .len = { sizeof(cmd) }, 558 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 559 }; 560 int ret; 561 bool lar_fw_supported = !iwlwifi_mod_params.lar_disable && 562 fw_has_capa(&mvm->fw->ucode_capa, 563 IWL_UCODE_TLV_CAPA_LAR_SUPPORT); 564 565 lockdep_assert_held(&mvm->mutex); 566 567 ret = iwl_mvm_send_cmd(mvm, &hcmd); 568 if (ret) 569 return ret; 570 571 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp), 572 "Invalid payload len in NVM response from FW %d", 573 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 574 ret = -EINVAL; 575 goto out; 576 } 577 578 rsp = (void *)hcmd.resp_pkt->data; 579 if (le32_to_cpu(rsp->general.flags)) { 580 IWL_ERR(mvm, "Invalid NVM data from FW\n"); 581 ret = -EINVAL; 582 goto out; 583 } 584 585 mvm->nvm_data = kzalloc(sizeof(*mvm->nvm_data) + 586 sizeof(struct ieee80211_channel) * 587 IWL_NUM_CHANNELS, GFP_KERNEL); 588 if (!mvm->nvm_data) { 589 ret = -ENOMEM; 590 goto out; 591 } 592 593 iwl_set_hw_address_from_csr(trans, mvm->nvm_data); 594 /* TODO: if platform NVM has MAC address - override it here */ 595 596 if (!is_valid_ether_addr(mvm->nvm_data->hw_addr)) { 597 IWL_ERR(trans, "no valid mac address was found\n"); 598 ret = -EINVAL; 599 goto err_free; 600 } 601 602 IWL_INFO(trans, "base HW address: %pM\n", mvm->nvm_data->hw_addr); 603 604 /* Initialize general data */ 605 mvm->nvm_data->nvm_version = le16_to_cpu(rsp->general.nvm_version); 606 607 /* Initialize MAC sku data */ 608 mvm->nvm_data->sku_cap_11ac_enable = 609 le32_to_cpu(rsp->mac_sku.enable_11ac); 610 mvm->nvm_data->sku_cap_11n_enable = 611 le32_to_cpu(rsp->mac_sku.enable_11n); 612 mvm->nvm_data->sku_cap_band_24GHz_enable = 613 le32_to_cpu(rsp->mac_sku.enable_24g); 614 mvm->nvm_data->sku_cap_band_52GHz_enable = 615 le32_to_cpu(rsp->mac_sku.enable_5g); 616 mvm->nvm_data->sku_cap_mimo_disabled = 617 le32_to_cpu(rsp->mac_sku.mimo_disable); 618 619 /* Initialize PHY sku data */ 620 mvm->nvm_data->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 621 mvm->nvm_data->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 622 623 /* Initialize regulatory data */ 624 mvm->nvm_data->lar_enabled = 625 le32_to_cpu(rsp->regulatory.lar_enabled) && lar_fw_supported; 626 627 iwl_init_sbands(trans->dev, trans->cfg, mvm->nvm_data, 628 rsp->regulatory.channel_profile, 629 mvm->nvm_data->valid_tx_ant & mvm->fw->valid_tx_ant, 630 mvm->nvm_data->valid_rx_ant & mvm->fw->valid_rx_ant, 631 rsp->regulatory.lar_enabled && lar_fw_supported); 632 633 iwl_free_resp(&hcmd); 634 return 0; 635 636 err_free: 637 kfree(mvm->nvm_data); 638 out: 639 iwl_free_resp(&hcmd); 640 return ret; 641 } 642 643 int iwl_nvm_init(struct iwl_mvm *mvm, bool read_nvm_from_nic) 644 { 645 int ret, section; 646 u32 size_read = 0; 647 u8 *nvm_buffer, *temp; 648 const char *nvm_file_C = mvm->cfg->default_nvm_file_C_step; 649 650 if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS)) 651 return -EINVAL; 652 653 /* load NVM values from nic */ 654 if (read_nvm_from_nic) { 655 /* Read From FW NVM */ 656 IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n"); 657 658 nvm_buffer = kmalloc(mvm->cfg->base_params->eeprom_size, 659 GFP_KERNEL); 660 if (!nvm_buffer) 661 return -ENOMEM; 662 for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) { 663 /* we override the constness for initial read */ 664 ret = iwl_nvm_read_section(mvm, section, nvm_buffer, 665 size_read); 666 if (ret < 0) 667 continue; 668 size_read += ret; 669 temp = kmemdup(nvm_buffer, ret, GFP_KERNEL); 670 if (!temp) { 671 ret = -ENOMEM; 672 break; 673 } 674 675 iwl_mvm_nvm_fixups(mvm, section, temp, ret); 676 677 mvm->nvm_sections[section].data = temp; 678 mvm->nvm_sections[section].length = ret; 679 680 #ifdef CONFIG_IWLWIFI_DEBUGFS 681 switch (section) { 682 case NVM_SECTION_TYPE_SW: 683 mvm->nvm_sw_blob.data = temp; 684 mvm->nvm_sw_blob.size = ret; 685 break; 686 case NVM_SECTION_TYPE_CALIBRATION: 687 mvm->nvm_calib_blob.data = temp; 688 mvm->nvm_calib_blob.size = ret; 689 break; 690 case NVM_SECTION_TYPE_PRODUCTION: 691 mvm->nvm_prod_blob.data = temp; 692 mvm->nvm_prod_blob.size = ret; 693 break; 694 case NVM_SECTION_TYPE_PHY_SKU: 695 mvm->nvm_phy_sku_blob.data = temp; 696 mvm->nvm_phy_sku_blob.size = ret; 697 break; 698 default: 699 if (section == mvm->cfg->nvm_hw_section_num) { 700 mvm->nvm_hw_blob.data = temp; 701 mvm->nvm_hw_blob.size = ret; 702 break; 703 } 704 } 705 #endif 706 } 707 if (!size_read) 708 IWL_ERR(mvm, "OTP is blank\n"); 709 kfree(nvm_buffer); 710 } 711 712 /* Only if PNVM selected in the mod param - load external NVM */ 713 if (mvm->nvm_file_name) { 714 /* read External NVM file from the mod param */ 715 ret = iwl_mvm_read_external_nvm(mvm); 716 if (ret) { 717 mvm->nvm_file_name = nvm_file_C; 718 719 if ((ret == -EFAULT || ret == -ENOENT) && 720 mvm->nvm_file_name) { 721 /* in case nvm file was failed try again */ 722 ret = iwl_mvm_read_external_nvm(mvm); 723 if (ret) 724 return ret; 725 } else { 726 return ret; 727 } 728 } 729 } 730 731 /* parse the relevant nvm sections */ 732 mvm->nvm_data = iwl_parse_nvm_sections(mvm); 733 if (!mvm->nvm_data) 734 return -ENODATA; 735 IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n", 736 mvm->nvm_data->nvm_version); 737 738 return 0; 739 } 740 741 struct iwl_mcc_update_resp * 742 iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2, 743 enum iwl_mcc_source src_id) 744 { 745 struct iwl_mcc_update_cmd mcc_update_cmd = { 746 .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]), 747 .source_id = (u8)src_id, 748 }; 749 struct iwl_mcc_update_resp *resp_cp; 750 struct iwl_rx_packet *pkt; 751 struct iwl_host_cmd cmd = { 752 .id = MCC_UPDATE_CMD, 753 .flags = CMD_WANT_SKB, 754 .data = { &mcc_update_cmd }, 755 }; 756 757 int ret; 758 u32 status; 759 int resp_len, n_channels; 760 u16 mcc; 761 bool resp_v2 = fw_has_capa(&mvm->fw->ucode_capa, 762 IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V2); 763 764 if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) 765 return ERR_PTR(-EOPNOTSUPP); 766 767 cmd.len[0] = sizeof(struct iwl_mcc_update_cmd); 768 if (!resp_v2) 769 cmd.len[0] = sizeof(struct iwl_mcc_update_cmd_v1); 770 771 IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c' src = %d\n", 772 alpha2[0], alpha2[1], src_id); 773 774 ret = iwl_mvm_send_cmd(mvm, &cmd); 775 if (ret) 776 return ERR_PTR(ret); 777 778 pkt = cmd.resp_pkt; 779 780 /* Extract MCC response */ 781 if (resp_v2) { 782 struct iwl_mcc_update_resp *mcc_resp = (void *)pkt->data; 783 784 n_channels = __le32_to_cpu(mcc_resp->n_channels); 785 resp_len = sizeof(struct iwl_mcc_update_resp) + 786 n_channels * sizeof(__le32); 787 resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL); 788 if (!resp_cp) { 789 resp_cp = ERR_PTR(-ENOMEM); 790 goto exit; 791 } 792 } else { 793 struct iwl_mcc_update_resp_v1 *mcc_resp_v1 = (void *)pkt->data; 794 795 n_channels = __le32_to_cpu(mcc_resp_v1->n_channels); 796 resp_len = sizeof(struct iwl_mcc_update_resp) + 797 n_channels * sizeof(__le32); 798 resp_cp = kzalloc(resp_len, GFP_KERNEL); 799 if (!resp_cp) { 800 resp_cp = ERR_PTR(-ENOMEM); 801 goto exit; 802 } 803 804 resp_cp->status = mcc_resp_v1->status; 805 resp_cp->mcc = mcc_resp_v1->mcc; 806 resp_cp->cap = mcc_resp_v1->cap; 807 resp_cp->source_id = mcc_resp_v1->source_id; 808 resp_cp->n_channels = mcc_resp_v1->n_channels; 809 memcpy(resp_cp->channels, mcc_resp_v1->channels, 810 n_channels * sizeof(__le32)); 811 } 812 813 status = le32_to_cpu(resp_cp->status); 814 815 mcc = le16_to_cpu(resp_cp->mcc); 816 817 /* W/A for a FW/NVM issue - returns 0x00 for the world domain */ 818 if (mcc == 0) { 819 mcc = 0x3030; /* "00" - world */ 820 resp_cp->mcc = cpu_to_le16(mcc); 821 } 822 823 IWL_DEBUG_LAR(mvm, 824 "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') change: %d n_chans: %d\n", 825 status, mcc, mcc >> 8, mcc & 0xff, 826 !!(status == MCC_RESP_NEW_CHAN_PROFILE), n_channels); 827 828 exit: 829 iwl_free_resp(&cmd); 830 return resp_cp; 831 } 832 833 int iwl_mvm_init_mcc(struct iwl_mvm *mvm) 834 { 835 bool tlv_lar; 836 bool nvm_lar; 837 int retval; 838 struct ieee80211_regdomain *regd; 839 char mcc[3]; 840 841 if (mvm->cfg->ext_nvm) { 842 tlv_lar = fw_has_capa(&mvm->fw->ucode_capa, 843 IWL_UCODE_TLV_CAPA_LAR_SUPPORT); 844 nvm_lar = mvm->nvm_data->lar_enabled; 845 if (tlv_lar != nvm_lar) 846 IWL_INFO(mvm, 847 "Conflict between TLV & NVM regarding enabling LAR (TLV = %s NVM =%s)\n", 848 tlv_lar ? "enabled" : "disabled", 849 nvm_lar ? "enabled" : "disabled"); 850 } 851 852 if (!iwl_mvm_is_lar_supported(mvm)) 853 return 0; 854 855 /* 856 * try to replay the last set MCC to FW. If it doesn't exist, 857 * queue an update to cfg80211 to retrieve the default alpha2 from FW. 858 */ 859 retval = iwl_mvm_init_fw_regd(mvm); 860 if (retval != -ENOENT) 861 return retval; 862 863 /* 864 * Driver regulatory hint for initial update, this also informs the 865 * firmware we support wifi location updates. 866 * Disallow scans that might crash the FW while the LAR regdomain 867 * is not set. 868 */ 869 mvm->lar_regdom_set = false; 870 871 regd = iwl_mvm_get_current_regdomain(mvm, NULL); 872 if (IS_ERR_OR_NULL(regd)) 873 return -EIO; 874 875 if (iwl_mvm_is_wifi_mcc_supported(mvm) && 876 !iwl_get_bios_mcc(mvm->dev, mcc)) { 877 kfree(regd); 878 regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, 879 MCC_SOURCE_BIOS, NULL); 880 if (IS_ERR_OR_NULL(regd)) 881 return -EIO; 882 } 883 884 retval = regulatory_set_wiphy_regd_sync_rtnl(mvm->hw->wiphy, regd); 885 kfree(regd); 886 return retval; 887 } 888 889 void iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm, 890 struct iwl_rx_cmd_buffer *rxb) 891 { 892 struct iwl_rx_packet *pkt = rxb_addr(rxb); 893 struct iwl_mcc_chub_notif *notif = (void *)pkt->data; 894 enum iwl_mcc_source src; 895 char mcc[3]; 896 struct ieee80211_regdomain *regd; 897 898 lockdep_assert_held(&mvm->mutex); 899 900 if (iwl_mvm_is_vif_assoc(mvm) && notif->source_id == MCC_SOURCE_WIFI) { 901 IWL_DEBUG_LAR(mvm, "Ignore mcc update while associated\n"); 902 return; 903 } 904 905 if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) 906 return; 907 908 mcc[0] = le16_to_cpu(notif->mcc) >> 8; 909 mcc[1] = le16_to_cpu(notif->mcc) & 0xff; 910 mcc[2] = '\0'; 911 src = notif->source_id; 912 913 IWL_DEBUG_LAR(mvm, 914 "RX: received chub update mcc cmd (mcc '%s' src %d)\n", 915 mcc, src); 916 regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, src, NULL); 917 if (IS_ERR_OR_NULL(regd)) 918 return; 919 920 regulatory_set_wiphy_regd(mvm->hw->wiphy, regd); 921 kfree(regd); 922 } 923