1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 1043413a97SSara Sharon * Copyright(c) 2016 Intel Deutschland GmbH 11e705c121SKalle Valo * 12e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 13e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 14e705c121SKalle Valo * published by the Free Software Foundation. 15e705c121SKalle Valo * 16e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 17e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 18e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19e705c121SKalle Valo * General Public License for more details. 20e705c121SKalle Valo * 21e705c121SKalle Valo * You should have received a copy of the GNU General Public License 22e705c121SKalle Valo * along with this program; if not, write to the Free Software 23e705c121SKalle Valo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24e705c121SKalle Valo * USA 25e705c121SKalle Valo * 26e705c121SKalle Valo * The full GNU General Public License is included in this distribution 27e705c121SKalle Valo * in the file called COPYING. 28e705c121SKalle Valo * 29e705c121SKalle Valo * Contact Information: 30cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 31e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32e705c121SKalle Valo * 33e705c121SKalle Valo * BSD LICENSE 34e705c121SKalle Valo * 35e705c121SKalle Valo * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 36e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 37e705c121SKalle Valo * All rights reserved. 38e705c121SKalle Valo * 39e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 40e705c121SKalle Valo * modification, are permitted provided that the following conditions 41e705c121SKalle Valo * are met: 42e705c121SKalle Valo * 43e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 45e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 46e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 47e705c121SKalle Valo * the documentation and/or other materials provided with the 48e705c121SKalle Valo * distribution. 49e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 50e705c121SKalle Valo * contributors may be used to endorse or promote products derived 51e705c121SKalle Valo * from this software without specific prior written permission. 52e705c121SKalle Valo * 53e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64e705c121SKalle Valo * 65e705c121SKalle Valo *****************************************************************************/ 66e705c121SKalle Valo #include <net/mac80211.h> 67e705c121SKalle Valo 68e705c121SKalle Valo #include "iwl-trans.h" 69e705c121SKalle Valo #include "iwl-op-mode.h" 70e705c121SKalle Valo #include "iwl-fw.h" 71e705c121SKalle Valo #include "iwl-debug.h" 72e705c121SKalle Valo #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ 73e705c121SKalle Valo #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ 74e705c121SKalle Valo #include "iwl-prph.h" 75e705c121SKalle Valo #include "iwl-eeprom-parse.h" 76e705c121SKalle Valo 77e705c121SKalle Valo #include "mvm.h" 782f89a5d7SGolan Ben-Ami #include "fw-dbg.h" 79e705c121SKalle Valo #include "iwl-phy-db.h" 80e705c121SKalle Valo 81e705c121SKalle Valo #define MVM_UCODE_ALIVE_TIMEOUT HZ 82e705c121SKalle Valo #define MVM_UCODE_CALIB_TIMEOUT (2*HZ) 83e705c121SKalle Valo 84e705c121SKalle Valo #define UCODE_VALID_OK cpu_to_le32(0x1) 85e705c121SKalle Valo 86e705c121SKalle Valo struct iwl_mvm_alive_data { 87e705c121SKalle Valo bool valid; 88e705c121SKalle Valo u32 scd_base_addr; 89e705c121SKalle Valo }; 90e705c121SKalle Valo 91e705c121SKalle Valo static inline const struct fw_img * 92e705c121SKalle Valo iwl_get_ucode_image(struct iwl_mvm *mvm, enum iwl_ucode_type ucode_type) 93e705c121SKalle Valo { 94e705c121SKalle Valo if (ucode_type >= IWL_UCODE_TYPE_MAX) 95e705c121SKalle Valo return NULL; 96e705c121SKalle Valo 97e705c121SKalle Valo return &mvm->fw->img[ucode_type]; 98e705c121SKalle Valo } 99e705c121SKalle Valo 100e705c121SKalle Valo static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) 101e705c121SKalle Valo { 102e705c121SKalle Valo struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { 103e705c121SKalle Valo .valid = cpu_to_le32(valid_tx_ant), 104e705c121SKalle Valo }; 105e705c121SKalle Valo 106e705c121SKalle Valo IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); 107e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, 108e705c121SKalle Valo sizeof(tx_ant_cmd), &tx_ant_cmd); 109e705c121SKalle Valo } 110e705c121SKalle Valo 11143413a97SSara Sharon static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm) 11243413a97SSara Sharon { 11343413a97SSara Sharon int i; 11443413a97SSara Sharon struct iwl_rss_config_cmd cmd = { 11543413a97SSara Sharon .flags = cpu_to_le32(IWL_RSS_ENABLE), 11643413a97SSara Sharon .hash_mask = IWL_RSS_HASH_TYPE_IPV4_TCP | 11743413a97SSara Sharon IWL_RSS_HASH_TYPE_IPV4_PAYLOAD | 11843413a97SSara Sharon IWL_RSS_HASH_TYPE_IPV6_TCP | 11943413a97SSara Sharon IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 12043413a97SSara Sharon }; 12143413a97SSara Sharon 12243413a97SSara Sharon for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++) 12343413a97SSara Sharon cmd.indirection_table[i] = i % mvm->trans->num_rx_queues; 124dd4d3161SSara Sharon memcpy(cmd.secret_key, mvm->secret_key, sizeof(cmd.secret_key)); 12543413a97SSara Sharon 12643413a97SSara Sharon return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd); 12743413a97SSara Sharon } 12843413a97SSara Sharon 129e705c121SKalle Valo static void iwl_free_fw_paging(struct iwl_mvm *mvm) 130e705c121SKalle Valo { 131e705c121SKalle Valo int i; 132e705c121SKalle Valo 133e705c121SKalle Valo if (!mvm->fw_paging_db[0].fw_paging_block) 134e705c121SKalle Valo return; 135e705c121SKalle Valo 136e705c121SKalle Valo for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) { 137e705c121SKalle Valo if (!mvm->fw_paging_db[i].fw_paging_block) { 138e705c121SKalle Valo IWL_DEBUG_FW(mvm, 139e705c121SKalle Valo "Paging: block %d already freed, continue to next page\n", 140e705c121SKalle Valo i); 141e705c121SKalle Valo 142e705c121SKalle Valo continue; 143e705c121SKalle Valo } 144e705c121SKalle Valo 145e705c121SKalle Valo __free_pages(mvm->fw_paging_db[i].fw_paging_block, 146e705c121SKalle Valo get_order(mvm->fw_paging_db[i].fw_paging_size)); 147e705c121SKalle Valo } 148e705c121SKalle Valo kfree(mvm->trans->paging_download_buf); 149e705c121SKalle Valo memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db)); 150e705c121SKalle Valo } 151e705c121SKalle Valo 152e705c121SKalle Valo static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image) 153e705c121SKalle Valo { 154e705c121SKalle Valo int sec_idx, idx; 155e705c121SKalle Valo u32 offset = 0; 156e705c121SKalle Valo 157e705c121SKalle Valo /* 158e705c121SKalle Valo * find where is the paging image start point: 159e705c121SKalle Valo * if CPU2 exist and it's in paging format, then the image looks like: 160e705c121SKalle Valo * CPU1 sections (2 or more) 161e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2 162e705c121SKalle Valo * CPU2 sections (not paged) 163e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2 164e705c121SKalle Valo * non paged to CPU2 paging sec 165e705c121SKalle Valo * CPU2 paging CSS 166e705c121SKalle Valo * CPU2 paging image (including instruction and data) 167e705c121SKalle Valo */ 168e705c121SKalle Valo for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) { 169e705c121SKalle Valo if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) { 170e705c121SKalle Valo sec_idx++; 171e705c121SKalle Valo break; 172e705c121SKalle Valo } 173e705c121SKalle Valo } 174e705c121SKalle Valo 175e705c121SKalle Valo if (sec_idx >= IWL_UCODE_SECTION_MAX) { 176e705c121SKalle Valo IWL_ERR(mvm, "driver didn't find paging image\n"); 177e705c121SKalle Valo iwl_free_fw_paging(mvm); 178e705c121SKalle Valo return -EINVAL; 179e705c121SKalle Valo } 180e705c121SKalle Valo 181e705c121SKalle Valo /* copy the CSS block to the dram */ 182e705c121SKalle Valo IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n", 183e705c121SKalle Valo sec_idx); 184e705c121SKalle Valo 185e705c121SKalle Valo memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block), 186e705c121SKalle Valo image->sec[sec_idx].data, 187e705c121SKalle Valo mvm->fw_paging_db[0].fw_paging_size); 188e705c121SKalle Valo 189e705c121SKalle Valo IWL_DEBUG_FW(mvm, 190e705c121SKalle Valo "Paging: copied %d CSS bytes to first block\n", 191e705c121SKalle Valo mvm->fw_paging_db[0].fw_paging_size); 192e705c121SKalle Valo 193e705c121SKalle Valo sec_idx++; 194e705c121SKalle Valo 195e705c121SKalle Valo /* 196e705c121SKalle Valo * copy the paging blocks to the dram 197e705c121SKalle Valo * loop index start from 1 since that CSS block already copied to dram 198e705c121SKalle Valo * and CSS index is 0. 199e705c121SKalle Valo * loop stop at num_of_paging_blk since that last block is not full. 200e705c121SKalle Valo */ 201e705c121SKalle Valo for (idx = 1; idx < mvm->num_of_paging_blk; idx++) { 202e705c121SKalle Valo memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), 203e705c121SKalle Valo image->sec[sec_idx].data + offset, 204e705c121SKalle Valo mvm->fw_paging_db[idx].fw_paging_size); 205e705c121SKalle Valo 206e705c121SKalle Valo IWL_DEBUG_FW(mvm, 207e705c121SKalle Valo "Paging: copied %d paging bytes to block %d\n", 208e705c121SKalle Valo mvm->fw_paging_db[idx].fw_paging_size, 209e705c121SKalle Valo idx); 210e705c121SKalle Valo 211e705c121SKalle Valo offset += mvm->fw_paging_db[idx].fw_paging_size; 212e705c121SKalle Valo } 213e705c121SKalle Valo 214e705c121SKalle Valo /* copy the last paging block */ 215e705c121SKalle Valo if (mvm->num_of_pages_in_last_blk > 0) { 216e705c121SKalle Valo memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), 217e705c121SKalle Valo image->sec[sec_idx].data + offset, 218e705c121SKalle Valo FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk); 219e705c121SKalle Valo 220e705c121SKalle Valo IWL_DEBUG_FW(mvm, 221e705c121SKalle Valo "Paging: copied %d pages in the last block %d\n", 222e705c121SKalle Valo mvm->num_of_pages_in_last_blk, idx); 223e705c121SKalle Valo } 224e705c121SKalle Valo 225e705c121SKalle Valo return 0; 226e705c121SKalle Valo } 227e705c121SKalle Valo 228e705c121SKalle Valo static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm, 229e705c121SKalle Valo const struct fw_img *image) 230e705c121SKalle Valo { 231e705c121SKalle Valo struct page *block; 232e705c121SKalle Valo dma_addr_t phys = 0; 233e705c121SKalle Valo int blk_idx = 0; 234e705c121SKalle Valo int order, num_of_pages; 235e705c121SKalle Valo int dma_enabled; 236e705c121SKalle Valo 237e705c121SKalle Valo if (mvm->fw_paging_db[0].fw_paging_block) 238e705c121SKalle Valo return 0; 239e705c121SKalle Valo 240e705c121SKalle Valo dma_enabled = is_device_dma_capable(mvm->trans->dev); 241e705c121SKalle Valo 242e705c121SKalle Valo /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */ 243e705c121SKalle Valo BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE); 244e705c121SKalle Valo 245e705c121SKalle Valo num_of_pages = image->paging_mem_size / FW_PAGING_SIZE; 246e705c121SKalle Valo mvm->num_of_paging_blk = ((num_of_pages - 1) / 247e705c121SKalle Valo NUM_OF_PAGE_PER_GROUP) + 1; 248e705c121SKalle Valo 249e705c121SKalle Valo mvm->num_of_pages_in_last_blk = 250e705c121SKalle Valo num_of_pages - 251e705c121SKalle Valo NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1); 252e705c121SKalle Valo 253e705c121SKalle Valo IWL_DEBUG_FW(mvm, 254e705c121SKalle Valo "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n", 255e705c121SKalle Valo mvm->num_of_paging_blk, 256e705c121SKalle Valo mvm->num_of_pages_in_last_blk); 257e705c121SKalle Valo 258e705c121SKalle Valo /* allocate block of 4Kbytes for paging CSS */ 259e705c121SKalle Valo order = get_order(FW_PAGING_SIZE); 260e705c121SKalle Valo block = alloc_pages(GFP_KERNEL, order); 261e705c121SKalle Valo if (!block) { 262e705c121SKalle Valo /* free all the previous pages since we failed */ 263e705c121SKalle Valo iwl_free_fw_paging(mvm); 264e705c121SKalle Valo return -ENOMEM; 265e705c121SKalle Valo } 266e705c121SKalle Valo 267e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_block = block; 268e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE; 269e705c121SKalle Valo 270e705c121SKalle Valo if (dma_enabled) { 271e705c121SKalle Valo phys = dma_map_page(mvm->trans->dev, block, 0, 272e705c121SKalle Valo PAGE_SIZE << order, DMA_BIDIRECTIONAL); 273e705c121SKalle Valo if (dma_mapping_error(mvm->trans->dev, phys)) { 274e705c121SKalle Valo /* 275e705c121SKalle Valo * free the previous pages and the current one since 276e705c121SKalle Valo * we failed to map_page. 277e705c121SKalle Valo */ 278e705c121SKalle Valo iwl_free_fw_paging(mvm); 279e705c121SKalle Valo return -ENOMEM; 280e705c121SKalle Valo } 281e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; 282e705c121SKalle Valo } else { 283e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG | 284e705c121SKalle Valo blk_idx << BLOCK_2_EXP_SIZE; 285e705c121SKalle Valo } 286e705c121SKalle Valo 287e705c121SKalle Valo IWL_DEBUG_FW(mvm, 288e705c121SKalle Valo "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n", 289e705c121SKalle Valo order); 290e705c121SKalle Valo 291e705c121SKalle Valo /* 292e705c121SKalle Valo * allocate blocks in dram. 293e705c121SKalle Valo * since that CSS allocated in fw_paging_db[0] loop start from index 1 294e705c121SKalle Valo */ 295e705c121SKalle Valo for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { 296e705c121SKalle Valo /* allocate block of PAGING_BLOCK_SIZE (32K) */ 297e705c121SKalle Valo order = get_order(PAGING_BLOCK_SIZE); 298e705c121SKalle Valo block = alloc_pages(GFP_KERNEL, order); 299e705c121SKalle Valo if (!block) { 300e705c121SKalle Valo /* free all the previous pages since we failed */ 301e705c121SKalle Valo iwl_free_fw_paging(mvm); 302e705c121SKalle Valo return -ENOMEM; 303e705c121SKalle Valo } 304e705c121SKalle Valo 305e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_block = block; 306e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE; 307e705c121SKalle Valo 308e705c121SKalle Valo if (dma_enabled) { 309e705c121SKalle Valo phys = dma_map_page(mvm->trans->dev, block, 0, 310e705c121SKalle Valo PAGE_SIZE << order, 311e705c121SKalle Valo DMA_BIDIRECTIONAL); 312e705c121SKalle Valo if (dma_mapping_error(mvm->trans->dev, phys)) { 313e705c121SKalle Valo /* 314e705c121SKalle Valo * free the previous pages and the current one 315e705c121SKalle Valo * since we failed to map_page. 316e705c121SKalle Valo */ 317e705c121SKalle Valo iwl_free_fw_paging(mvm); 318e705c121SKalle Valo return -ENOMEM; 319e705c121SKalle Valo } 320e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; 321e705c121SKalle Valo } else { 322e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_phys = 323e705c121SKalle Valo PAGING_ADDR_SIG | 324e705c121SKalle Valo blk_idx << BLOCK_2_EXP_SIZE; 325e705c121SKalle Valo } 326e705c121SKalle Valo 327e705c121SKalle Valo IWL_DEBUG_FW(mvm, 328e705c121SKalle Valo "Paging: allocated 32K bytes (order %d) for firmware paging.\n", 329e705c121SKalle Valo order); 330e705c121SKalle Valo } 331e705c121SKalle Valo 332e705c121SKalle Valo return 0; 333e705c121SKalle Valo } 334e705c121SKalle Valo 335e705c121SKalle Valo static int iwl_save_fw_paging(struct iwl_mvm *mvm, 336e705c121SKalle Valo const struct fw_img *fw) 337e705c121SKalle Valo { 338e705c121SKalle Valo int ret; 339e705c121SKalle Valo 340e705c121SKalle Valo ret = iwl_alloc_fw_paging_mem(mvm, fw); 341e705c121SKalle Valo if (ret) 342e705c121SKalle Valo return ret; 343e705c121SKalle Valo 344e705c121SKalle Valo return iwl_fill_paging_mem(mvm, fw); 345e705c121SKalle Valo } 346e705c121SKalle Valo 347e705c121SKalle Valo /* send paging cmd to FW in case CPU2 has paging image */ 348e705c121SKalle Valo static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw) 349e705c121SKalle Valo { 350e705c121SKalle Valo int blk_idx; 351e705c121SKalle Valo __le32 dev_phy_addr; 352e705c121SKalle Valo struct iwl_fw_paging_cmd fw_paging_cmd = { 353e705c121SKalle Valo .flags = 354e705c121SKalle Valo cpu_to_le32(PAGING_CMD_IS_SECURED | 355e705c121SKalle Valo PAGING_CMD_IS_ENABLED | 356e705c121SKalle Valo (mvm->num_of_pages_in_last_blk << 357e705c121SKalle Valo PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)), 358e705c121SKalle Valo .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE), 359e705c121SKalle Valo .block_num = cpu_to_le32(mvm->num_of_paging_blk), 360e705c121SKalle Valo }; 361e705c121SKalle Valo 362e705c121SKalle Valo /* loop for for all paging blocks + CSS block */ 363e705c121SKalle Valo for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { 364e705c121SKalle Valo dev_phy_addr = 365e705c121SKalle Valo cpu_to_le32(mvm->fw_paging_db[blk_idx].fw_paging_phys >> 366e705c121SKalle Valo PAGE_2_EXP_SIZE); 367e705c121SKalle Valo fw_paging_cmd.device_phy_addr[blk_idx] = dev_phy_addr; 368e705c121SKalle Valo } 369e705c121SKalle Valo 370e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD, 371e705c121SKalle Valo IWL_ALWAYS_LONG_GROUP, 0), 372e705c121SKalle Valo 0, sizeof(fw_paging_cmd), &fw_paging_cmd); 373e705c121SKalle Valo } 374e705c121SKalle Valo 375e705c121SKalle Valo /* 376e705c121SKalle Valo * Send paging item cmd to FW in case CPU2 has paging image 377e705c121SKalle Valo */ 378e705c121SKalle Valo static int iwl_trans_get_paging_item(struct iwl_mvm *mvm) 379e705c121SKalle Valo { 380e705c121SKalle Valo int ret; 381e705c121SKalle Valo struct iwl_fw_get_item_cmd fw_get_item_cmd = { 382e705c121SKalle Valo .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING), 383e705c121SKalle Valo }; 384e705c121SKalle Valo 385e705c121SKalle Valo struct iwl_fw_get_item_resp *item_resp; 386e705c121SKalle Valo struct iwl_host_cmd cmd = { 387e705c121SKalle Valo .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0), 388e705c121SKalle Valo .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 389e705c121SKalle Valo .data = { &fw_get_item_cmd, }, 390e705c121SKalle Valo }; 391e705c121SKalle Valo 392e705c121SKalle Valo cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd); 393e705c121SKalle Valo 394e705c121SKalle Valo ret = iwl_mvm_send_cmd(mvm, &cmd); 395e705c121SKalle Valo if (ret) { 396e705c121SKalle Valo IWL_ERR(mvm, 397e705c121SKalle Valo "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n", 398e705c121SKalle Valo ret); 399e705c121SKalle Valo return ret; 400e705c121SKalle Valo } 401e705c121SKalle Valo 402e705c121SKalle Valo item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data; 403e705c121SKalle Valo if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) { 404e705c121SKalle Valo IWL_ERR(mvm, 405e705c121SKalle Valo "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n", 406e705c121SKalle Valo le32_to_cpu(item_resp->item_id)); 407e705c121SKalle Valo ret = -EIO; 408e705c121SKalle Valo goto exit; 409e705c121SKalle Valo } 410e705c121SKalle Valo 411e705c121SKalle Valo mvm->trans->paging_download_buf = kzalloc(MAX_PAGING_IMAGE_SIZE, 412e705c121SKalle Valo GFP_KERNEL); 413e705c121SKalle Valo if (!mvm->trans->paging_download_buf) { 414e705c121SKalle Valo ret = -ENOMEM; 415e705c121SKalle Valo goto exit; 416e705c121SKalle Valo } 417e705c121SKalle Valo mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val); 418e705c121SKalle Valo mvm->trans->paging_db = mvm->fw_paging_db; 419e705c121SKalle Valo IWL_DEBUG_FW(mvm, 420e705c121SKalle Valo "Paging: got paging request address (paging_req_addr 0x%08x)\n", 421e705c121SKalle Valo mvm->trans->paging_req_addr); 422e705c121SKalle Valo 423e705c121SKalle Valo exit: 424e705c121SKalle Valo iwl_free_resp(&cmd); 425e705c121SKalle Valo 426e705c121SKalle Valo return ret; 427e705c121SKalle Valo } 428e705c121SKalle Valo 429e705c121SKalle Valo static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, 430e705c121SKalle Valo struct iwl_rx_packet *pkt, void *data) 431e705c121SKalle Valo { 432e705c121SKalle Valo struct iwl_mvm *mvm = 433e705c121SKalle Valo container_of(notif_wait, struct iwl_mvm, notif_wait); 434e705c121SKalle Valo struct iwl_mvm_alive_data *alive_data = data; 435e705c121SKalle Valo struct mvm_alive_resp_ver1 *palive1; 436e705c121SKalle Valo struct mvm_alive_resp_ver2 *palive2; 437e705c121SKalle Valo struct mvm_alive_resp *palive; 438e705c121SKalle Valo 439e705c121SKalle Valo if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) { 440e705c121SKalle Valo palive1 = (void *)pkt->data; 441e705c121SKalle Valo 442e705c121SKalle Valo mvm->support_umac_log = false; 443e705c121SKalle Valo mvm->error_event_table = 444e705c121SKalle Valo le32_to_cpu(palive1->error_event_table_ptr); 445e705c121SKalle Valo mvm->log_event_table = 446e705c121SKalle Valo le32_to_cpu(palive1->log_event_table_ptr); 447e705c121SKalle Valo alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr); 448e705c121SKalle Valo 449e705c121SKalle Valo alive_data->valid = le16_to_cpu(palive1->status) == 450e705c121SKalle Valo IWL_ALIVE_STATUS_OK; 451e705c121SKalle Valo IWL_DEBUG_FW(mvm, 452e705c121SKalle Valo "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", 453e705c121SKalle Valo le16_to_cpu(palive1->status), palive1->ver_type, 454e705c121SKalle Valo palive1->ver_subtype, palive1->flags); 455e705c121SKalle Valo } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) { 456e705c121SKalle Valo palive2 = (void *)pkt->data; 457e705c121SKalle Valo 458e705c121SKalle Valo mvm->error_event_table = 459e705c121SKalle Valo le32_to_cpu(palive2->error_event_table_ptr); 460e705c121SKalle Valo mvm->log_event_table = 461e705c121SKalle Valo le32_to_cpu(palive2->log_event_table_ptr); 462e705c121SKalle Valo alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr); 463e705c121SKalle Valo mvm->umac_error_event_table = 464e705c121SKalle Valo le32_to_cpu(palive2->error_info_addr); 465e705c121SKalle Valo mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr); 466e705c121SKalle Valo mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size); 467e705c121SKalle Valo 468e705c121SKalle Valo alive_data->valid = le16_to_cpu(palive2->status) == 469e705c121SKalle Valo IWL_ALIVE_STATUS_OK; 470e705c121SKalle Valo if (mvm->umac_error_event_table) 471e705c121SKalle Valo mvm->support_umac_log = true; 472e705c121SKalle Valo 473e705c121SKalle Valo IWL_DEBUG_FW(mvm, 474e705c121SKalle Valo "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", 475e705c121SKalle Valo le16_to_cpu(palive2->status), palive2->ver_type, 476e705c121SKalle Valo palive2->ver_subtype, palive2->flags); 477e705c121SKalle Valo 478e705c121SKalle Valo IWL_DEBUG_FW(mvm, 479e705c121SKalle Valo "UMAC version: Major - 0x%x, Minor - 0x%x\n", 480e705c121SKalle Valo palive2->umac_major, palive2->umac_minor); 481e705c121SKalle Valo } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) { 482e705c121SKalle Valo palive = (void *)pkt->data; 483e705c121SKalle Valo 484e705c121SKalle Valo mvm->error_event_table = 485e705c121SKalle Valo le32_to_cpu(palive->error_event_table_ptr); 486e705c121SKalle Valo mvm->log_event_table = 487e705c121SKalle Valo le32_to_cpu(palive->log_event_table_ptr); 488e705c121SKalle Valo alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr); 489e705c121SKalle Valo mvm->umac_error_event_table = 490e705c121SKalle Valo le32_to_cpu(palive->error_info_addr); 491e705c121SKalle Valo mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr); 492e705c121SKalle Valo mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size); 493e705c121SKalle Valo 494e705c121SKalle Valo alive_data->valid = le16_to_cpu(palive->status) == 495e705c121SKalle Valo IWL_ALIVE_STATUS_OK; 496e705c121SKalle Valo if (mvm->umac_error_event_table) 497e705c121SKalle Valo mvm->support_umac_log = true; 498e705c121SKalle Valo 499e705c121SKalle Valo IWL_DEBUG_FW(mvm, 500e705c121SKalle Valo "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", 501e705c121SKalle Valo le16_to_cpu(palive->status), palive->ver_type, 502e705c121SKalle Valo palive->ver_subtype, palive->flags); 503e705c121SKalle Valo 504e705c121SKalle Valo IWL_DEBUG_FW(mvm, 505e705c121SKalle Valo "UMAC version: Major - 0x%x, Minor - 0x%x\n", 506e705c121SKalle Valo le32_to_cpu(palive->umac_major), 507e705c121SKalle Valo le32_to_cpu(palive->umac_minor)); 508e705c121SKalle Valo } 509e705c121SKalle Valo 510e705c121SKalle Valo return true; 511e705c121SKalle Valo } 512e705c121SKalle Valo 513e705c121SKalle Valo static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, 514e705c121SKalle Valo struct iwl_rx_packet *pkt, void *data) 515e705c121SKalle Valo { 516e705c121SKalle Valo struct iwl_phy_db *phy_db = data; 517e705c121SKalle Valo 518e705c121SKalle Valo if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { 519e705c121SKalle Valo WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); 520e705c121SKalle Valo return true; 521e705c121SKalle Valo } 522e705c121SKalle Valo 523e705c121SKalle Valo WARN_ON(iwl_phy_db_set_section(phy_db, pkt, GFP_ATOMIC)); 524e705c121SKalle Valo 525e705c121SKalle Valo return false; 526e705c121SKalle Valo } 527e705c121SKalle Valo 528e705c121SKalle Valo static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, 529e705c121SKalle Valo enum iwl_ucode_type ucode_type) 530e705c121SKalle Valo { 531e705c121SKalle Valo struct iwl_notification_wait alive_wait; 532e705c121SKalle Valo struct iwl_mvm_alive_data alive_data; 533e705c121SKalle Valo const struct fw_img *fw; 534e705c121SKalle Valo int ret, i; 535e705c121SKalle Valo enum iwl_ucode_type old_type = mvm->cur_ucode; 536e705c121SKalle Valo static const u16 alive_cmd[] = { MVM_ALIVE }; 537e705c121SKalle Valo struct iwl_sf_region st_fwrd_space; 538e705c121SKalle Valo 539e705c121SKalle Valo if (ucode_type == IWL_UCODE_REGULAR && 5403d2d4422SGolan Ben-Ami iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) && 5413d2d4422SGolan Ben-Ami !(fw_has_capa(&mvm->fw->ucode_capa, 5423d2d4422SGolan Ben-Ami IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED))) 543e705c121SKalle Valo fw = iwl_get_ucode_image(mvm, IWL_UCODE_REGULAR_USNIFFER); 544e705c121SKalle Valo else 545e705c121SKalle Valo fw = iwl_get_ucode_image(mvm, ucode_type); 546e705c121SKalle Valo if (WARN_ON(!fw)) 547e705c121SKalle Valo return -EINVAL; 548e705c121SKalle Valo mvm->cur_ucode = ucode_type; 549e705c121SKalle Valo mvm->ucode_loaded = false; 550e705c121SKalle Valo 551e705c121SKalle Valo iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, 552e705c121SKalle Valo alive_cmd, ARRAY_SIZE(alive_cmd), 553e705c121SKalle Valo iwl_alive_fn, &alive_data); 554e705c121SKalle Valo 555e705c121SKalle Valo ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT); 556e705c121SKalle Valo if (ret) { 557e705c121SKalle Valo mvm->cur_ucode = old_type; 558e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &alive_wait); 559e705c121SKalle Valo return ret; 560e705c121SKalle Valo } 561e705c121SKalle Valo 562e705c121SKalle Valo /* 563e705c121SKalle Valo * Some things may run in the background now, but we 564e705c121SKalle Valo * just wait for the ALIVE notification here. 565e705c121SKalle Valo */ 566e705c121SKalle Valo ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, 567e705c121SKalle Valo MVM_UCODE_ALIVE_TIMEOUT); 568e705c121SKalle Valo if (ret) { 569e705c121SKalle Valo if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 570e705c121SKalle Valo IWL_ERR(mvm, 571e705c121SKalle Valo "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", 572e705c121SKalle Valo iwl_read_prph(mvm->trans, SB_CPU_1_STATUS), 573e705c121SKalle Valo iwl_read_prph(mvm->trans, SB_CPU_2_STATUS)); 574e705c121SKalle Valo mvm->cur_ucode = old_type; 575e705c121SKalle Valo return ret; 576e705c121SKalle Valo } 577e705c121SKalle Valo 578e705c121SKalle Valo if (!alive_data.valid) { 579e705c121SKalle Valo IWL_ERR(mvm, "Loaded ucode is not valid!\n"); 580e705c121SKalle Valo mvm->cur_ucode = old_type; 581e705c121SKalle Valo return -EIO; 582e705c121SKalle Valo } 583e705c121SKalle Valo 584e705c121SKalle Valo /* 585e705c121SKalle Valo * update the sdio allocation according to the pointer we get in the 586e705c121SKalle Valo * alive notification. 587e705c121SKalle Valo */ 588e705c121SKalle Valo st_fwrd_space.addr = mvm->sf_space.addr; 589e705c121SKalle Valo st_fwrd_space.size = mvm->sf_space.size; 590e705c121SKalle Valo ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space); 591e705c121SKalle Valo if (ret) { 592e705c121SKalle Valo IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret); 593e705c121SKalle Valo return ret; 594e705c121SKalle Valo } 595e705c121SKalle Valo 596e705c121SKalle Valo iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); 597e705c121SKalle Valo 598e705c121SKalle Valo /* 599e705c121SKalle Valo * configure and operate fw paging mechanism. 600e705c121SKalle Valo * driver configures the paging flow only once, CPU2 paging image 601e705c121SKalle Valo * included in the IWL_UCODE_INIT image. 602e705c121SKalle Valo */ 603e705c121SKalle Valo if (fw->paging_mem_size) { 604e705c121SKalle Valo /* 605e705c121SKalle Valo * When dma is not enabled, the driver needs to copy / write 606e705c121SKalle Valo * the downloaded / uploaded page to / from the smem. 607e705c121SKalle Valo * This gets the location of the place were the pages are 608e705c121SKalle Valo * stored. 609e705c121SKalle Valo */ 610e705c121SKalle Valo if (!is_device_dma_capable(mvm->trans->dev)) { 611e705c121SKalle Valo ret = iwl_trans_get_paging_item(mvm); 612e705c121SKalle Valo if (ret) { 613e705c121SKalle Valo IWL_ERR(mvm, "failed to get FW paging item\n"); 614e705c121SKalle Valo return ret; 615e705c121SKalle Valo } 616e705c121SKalle Valo } 617e705c121SKalle Valo 618e705c121SKalle Valo ret = iwl_save_fw_paging(mvm, fw); 619e705c121SKalle Valo if (ret) { 620e705c121SKalle Valo IWL_ERR(mvm, "failed to save the FW paging image\n"); 621e705c121SKalle Valo return ret; 622e705c121SKalle Valo } 623e705c121SKalle Valo 624e705c121SKalle Valo ret = iwl_send_paging_cmd(mvm, fw); 625e705c121SKalle Valo if (ret) { 626e705c121SKalle Valo IWL_ERR(mvm, "failed to send the paging cmd\n"); 627e705c121SKalle Valo iwl_free_fw_paging(mvm); 628e705c121SKalle Valo return ret; 629e705c121SKalle Valo } 630e705c121SKalle Valo } 631e705c121SKalle Valo 632e705c121SKalle Valo /* 633e705c121SKalle Valo * Note: all the queues are enabled as part of the interface 634e705c121SKalle Valo * initialization, but in firmware restart scenarios they 635e705c121SKalle Valo * could be stopped, so wake them up. In firmware restart, 636e705c121SKalle Valo * mac80211 will have the queues stopped as well until the 637e705c121SKalle Valo * reconfiguration completes. During normal startup, they 638e705c121SKalle Valo * will be empty. 639e705c121SKalle Valo */ 640e705c121SKalle Valo 641e705c121SKalle Valo memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); 642e705c121SKalle Valo mvm->queue_info[IWL_MVM_CMD_QUEUE].hw_queue_refcount = 1; 643e705c121SKalle Valo 644e705c121SKalle Valo for (i = 0; i < IEEE80211_MAX_QUEUES; i++) 645e705c121SKalle Valo atomic_set(&mvm->mac80211_queue_stop_count[i], 0); 646e705c121SKalle Valo 647e705c121SKalle Valo mvm->ucode_loaded = true; 648e705c121SKalle Valo 649e705c121SKalle Valo return 0; 650e705c121SKalle Valo } 651e705c121SKalle Valo 652e705c121SKalle Valo static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) 653e705c121SKalle Valo { 654e705c121SKalle Valo struct iwl_phy_cfg_cmd phy_cfg_cmd; 655e705c121SKalle Valo enum iwl_ucode_type ucode_type = mvm->cur_ucode; 656e705c121SKalle Valo 657e705c121SKalle Valo /* Set parameters */ 658e705c121SKalle Valo phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); 659e705c121SKalle Valo phy_cfg_cmd.calib_control.event_trigger = 660e705c121SKalle Valo mvm->fw->default_calib[ucode_type].event_trigger; 661e705c121SKalle Valo phy_cfg_cmd.calib_control.flow_trigger = 662e705c121SKalle Valo mvm->fw->default_calib[ucode_type].flow_trigger; 663e705c121SKalle Valo 664e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", 665e705c121SKalle Valo phy_cfg_cmd.phy_cfg); 666e705c121SKalle Valo 667e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, 668e705c121SKalle Valo sizeof(phy_cfg_cmd), &phy_cfg_cmd); 669e705c121SKalle Valo } 670e705c121SKalle Valo 671e705c121SKalle Valo int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) 672e705c121SKalle Valo { 673e705c121SKalle Valo struct iwl_notification_wait calib_wait; 674e705c121SKalle Valo static const u16 init_complete[] = { 675e705c121SKalle Valo INIT_COMPLETE_NOTIF, 676e705c121SKalle Valo CALIB_RES_NOTIF_PHY_DB 677e705c121SKalle Valo }; 678e705c121SKalle Valo int ret; 679e705c121SKalle Valo 680e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 681e705c121SKalle Valo 682e705c121SKalle Valo if (WARN_ON_ONCE(mvm->calibrating)) 683e705c121SKalle Valo return 0; 684e705c121SKalle Valo 685e705c121SKalle Valo iwl_init_notification_wait(&mvm->notif_wait, 686e705c121SKalle Valo &calib_wait, 687e705c121SKalle Valo init_complete, 688e705c121SKalle Valo ARRAY_SIZE(init_complete), 689e705c121SKalle Valo iwl_wait_phy_db_entry, 690e705c121SKalle Valo mvm->phy_db); 691e705c121SKalle Valo 692e705c121SKalle Valo /* Will also start the device */ 693e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); 694e705c121SKalle Valo if (ret) { 695e705c121SKalle Valo IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); 696e705c121SKalle Valo goto error; 697e705c121SKalle Valo } 698e705c121SKalle Valo 699e705c121SKalle Valo ret = iwl_send_bt_init_conf(mvm); 700e705c121SKalle Valo if (ret) 701e705c121SKalle Valo goto error; 702e705c121SKalle Valo 703e705c121SKalle Valo /* Read the NVM only at driver load time, no need to do this twice */ 704e705c121SKalle Valo if (read_nvm) { 705e705c121SKalle Valo /* Read nvm */ 706e705c121SKalle Valo ret = iwl_nvm_init(mvm, true); 707e705c121SKalle Valo if (ret) { 708e705c121SKalle Valo IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); 709e705c121SKalle Valo goto error; 710e705c121SKalle Valo } 711e705c121SKalle Valo } 712e705c121SKalle Valo 713e705c121SKalle Valo /* In case we read the NVM from external file, load it to the NIC */ 714e705c121SKalle Valo if (mvm->nvm_file_name) 715e705c121SKalle Valo iwl_mvm_load_nvm_to_nic(mvm); 716e705c121SKalle Valo 717e705c121SKalle Valo ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans); 718e705c121SKalle Valo WARN_ON(ret); 719e705c121SKalle Valo 720e705c121SKalle Valo /* 721e705c121SKalle Valo * abort after reading the nvm in case RF Kill is on, we will complete 722e705c121SKalle Valo * the init seq later when RF kill will switch to off 723e705c121SKalle Valo */ 724e705c121SKalle Valo if (iwl_mvm_is_radio_hw_killed(mvm)) { 725e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, 726e705c121SKalle Valo "jump over all phy activities due to RF kill\n"); 727e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &calib_wait); 728e705c121SKalle Valo ret = 1; 729e705c121SKalle Valo goto out; 730e705c121SKalle Valo } 731e705c121SKalle Valo 732e705c121SKalle Valo mvm->calibrating = true; 733e705c121SKalle Valo 734e705c121SKalle Valo /* Send TX valid antennas before triggering calibrations */ 735e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 736e705c121SKalle Valo if (ret) 737e705c121SKalle Valo goto error; 738e705c121SKalle Valo 739e705c121SKalle Valo /* 740e705c121SKalle Valo * Send phy configurations command to init uCode 741e705c121SKalle Valo * to start the 16.0 uCode init image internal calibrations. 742e705c121SKalle Valo */ 743e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 744e705c121SKalle Valo if (ret) { 745e705c121SKalle Valo IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", 746e705c121SKalle Valo ret); 747e705c121SKalle Valo goto error; 748e705c121SKalle Valo } 749e705c121SKalle Valo 750e705c121SKalle Valo /* 751e705c121SKalle Valo * Some things may run in the background now, but we 752e705c121SKalle Valo * just wait for the calibration complete notification. 753e705c121SKalle Valo */ 754e705c121SKalle Valo ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, 755e705c121SKalle Valo MVM_UCODE_CALIB_TIMEOUT); 756e705c121SKalle Valo 757e705c121SKalle Valo if (ret && iwl_mvm_is_radio_hw_killed(mvm)) { 758e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); 759e705c121SKalle Valo ret = 1; 760e705c121SKalle Valo } 761e705c121SKalle Valo goto out; 762e705c121SKalle Valo 763e705c121SKalle Valo error: 764e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &calib_wait); 765e705c121SKalle Valo out: 766e705c121SKalle Valo mvm->calibrating = false; 767e705c121SKalle Valo if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { 768e705c121SKalle Valo /* we want to debug INIT and we have no NVM - fake */ 769e705c121SKalle Valo mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + 770e705c121SKalle Valo sizeof(struct ieee80211_channel) + 771e705c121SKalle Valo sizeof(struct ieee80211_rate), 772e705c121SKalle Valo GFP_KERNEL); 773e705c121SKalle Valo if (!mvm->nvm_data) 774e705c121SKalle Valo return -ENOMEM; 775e705c121SKalle Valo mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; 776e705c121SKalle Valo mvm->nvm_data->bands[0].n_channels = 1; 777e705c121SKalle Valo mvm->nvm_data->bands[0].n_bitrates = 1; 778e705c121SKalle Valo mvm->nvm_data->bands[0].bitrates = 779e705c121SKalle Valo (void *)mvm->nvm_data->channels + 1; 780e705c121SKalle Valo mvm->nvm_data->bands[0].bitrates->hw_value = 10; 781e705c121SKalle Valo } 782e705c121SKalle Valo 783e705c121SKalle Valo return ret; 784e705c121SKalle Valo } 785e705c121SKalle Valo 786e705c121SKalle Valo static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm) 787e705c121SKalle Valo { 788e705c121SKalle Valo struct iwl_host_cmd cmd = { 789e705c121SKalle Valo .id = SHARED_MEM_CFG, 790e705c121SKalle Valo .flags = CMD_WANT_SKB, 791e705c121SKalle Valo .data = { NULL, }, 792e705c121SKalle Valo .len = { 0, }, 793e705c121SKalle Valo }; 794e705c121SKalle Valo struct iwl_rx_packet *pkt; 795e705c121SKalle Valo struct iwl_shared_mem_cfg *mem_cfg; 796e705c121SKalle Valo u32 i; 797e705c121SKalle Valo 798e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 799e705c121SKalle Valo 800e705c121SKalle Valo if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd))) 801e705c121SKalle Valo return; 802e705c121SKalle Valo 803e705c121SKalle Valo pkt = cmd.resp_pkt; 804e705c121SKalle Valo mem_cfg = (void *)pkt->data; 805e705c121SKalle Valo 806e705c121SKalle Valo mvm->shared_mem_cfg.shared_mem_addr = 807e705c121SKalle Valo le32_to_cpu(mem_cfg->shared_mem_addr); 808e705c121SKalle Valo mvm->shared_mem_cfg.shared_mem_size = 809e705c121SKalle Valo le32_to_cpu(mem_cfg->shared_mem_size); 810e705c121SKalle Valo mvm->shared_mem_cfg.sample_buff_addr = 811e705c121SKalle Valo le32_to_cpu(mem_cfg->sample_buff_addr); 812e705c121SKalle Valo mvm->shared_mem_cfg.sample_buff_size = 813e705c121SKalle Valo le32_to_cpu(mem_cfg->sample_buff_size); 814e705c121SKalle Valo mvm->shared_mem_cfg.txfifo_addr = le32_to_cpu(mem_cfg->txfifo_addr); 815e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++) 816e705c121SKalle Valo mvm->shared_mem_cfg.txfifo_size[i] = 817e705c121SKalle Valo le32_to_cpu(mem_cfg->txfifo_size[i]); 818e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++) 819e705c121SKalle Valo mvm->shared_mem_cfg.rxfifo_size[i] = 820e705c121SKalle Valo le32_to_cpu(mem_cfg->rxfifo_size[i]); 821e705c121SKalle Valo mvm->shared_mem_cfg.page_buff_addr = 822e705c121SKalle Valo le32_to_cpu(mem_cfg->page_buff_addr); 823e705c121SKalle Valo mvm->shared_mem_cfg.page_buff_size = 824e705c121SKalle Valo le32_to_cpu(mem_cfg->page_buff_size); 825e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n"); 826e705c121SKalle Valo 827e705c121SKalle Valo iwl_free_resp(&cmd); 828e705c121SKalle Valo } 829e705c121SKalle Valo 830e705c121SKalle Valo static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) 831e705c121SKalle Valo { 832e705c121SKalle Valo struct iwl_ltr_config_cmd cmd = { 833e705c121SKalle Valo .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), 834e705c121SKalle Valo }; 835e705c121SKalle Valo 836e705c121SKalle Valo if (!mvm->trans->ltr_enabled) 837e705c121SKalle Valo return 0; 838e705c121SKalle Valo 839e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, 840e705c121SKalle Valo sizeof(cmd), &cmd); 841e705c121SKalle Valo } 842e705c121SKalle Valo 843e705c121SKalle Valo int iwl_mvm_up(struct iwl_mvm *mvm) 844e705c121SKalle Valo { 845e705c121SKalle Valo int ret, i; 846e705c121SKalle Valo struct ieee80211_channel *chan; 847e705c121SKalle Valo struct cfg80211_chan_def chandef; 848e705c121SKalle Valo 849e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 850e705c121SKalle Valo 851e705c121SKalle Valo ret = iwl_trans_start_hw(mvm->trans); 852e705c121SKalle Valo if (ret) 853e705c121SKalle Valo return ret; 854e705c121SKalle Valo 855e705c121SKalle Valo /* 856e705c121SKalle Valo * If we haven't completed the run of the init ucode during 857e705c121SKalle Valo * module loading, load init ucode now 858e705c121SKalle Valo * (for example, if we were in RFKILL) 859e705c121SKalle Valo */ 860e705c121SKalle Valo ret = iwl_run_init_mvm_ucode(mvm, false); 861e705c121SKalle Valo if (ret && !iwlmvm_mod_params.init_dbg) { 862e705c121SKalle Valo IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); 863e705c121SKalle Valo /* this can't happen */ 864e705c121SKalle Valo if (WARN_ON(ret > 0)) 865e705c121SKalle Valo ret = -ERFKILL; 866e705c121SKalle Valo goto error; 867e705c121SKalle Valo } 868e705c121SKalle Valo if (!iwlmvm_mod_params.init_dbg) { 869e705c121SKalle Valo /* 870e705c121SKalle Valo * Stop and start the transport without entering low power 871e705c121SKalle Valo * mode. This will save the state of other components on the 872e705c121SKalle Valo * device that are triggered by the INIT firwmare (MFUART). 873e705c121SKalle Valo */ 874e705c121SKalle Valo _iwl_trans_stop_device(mvm->trans, false); 875e705c121SKalle Valo ret = _iwl_trans_start_hw(mvm->trans, false); 876e705c121SKalle Valo if (ret) 877e705c121SKalle Valo goto error; 878e705c121SKalle Valo } 879e705c121SKalle Valo 880e705c121SKalle Valo if (iwlmvm_mod_params.init_dbg) 881e705c121SKalle Valo return 0; 882e705c121SKalle Valo 883e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); 884e705c121SKalle Valo if (ret) { 885e705c121SKalle Valo IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); 886e705c121SKalle Valo goto error; 887e705c121SKalle Valo } 888e705c121SKalle Valo 889e705c121SKalle Valo iwl_mvm_get_shared_mem_conf(mvm); 890e705c121SKalle Valo 891e705c121SKalle Valo ret = iwl_mvm_sf_update(mvm, NULL, false); 892e705c121SKalle Valo if (ret) 893e705c121SKalle Valo IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); 894e705c121SKalle Valo 895e705c121SKalle Valo mvm->fw_dbg_conf = FW_DBG_INVALID; 896e705c121SKalle Valo /* if we have a destination, assume EARLY START */ 897e705c121SKalle Valo if (mvm->fw->dbg_dest_tlv) 898e705c121SKalle Valo mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE; 899e705c121SKalle Valo iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE); 900e705c121SKalle Valo 901e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 902e705c121SKalle Valo if (ret) 903e705c121SKalle Valo goto error; 904e705c121SKalle Valo 905e705c121SKalle Valo ret = iwl_send_bt_init_conf(mvm); 906e705c121SKalle Valo if (ret) 907e705c121SKalle Valo goto error; 908e705c121SKalle Valo 909e705c121SKalle Valo /* Send phy db control command and then phy db calibration*/ 910e705c121SKalle Valo ret = iwl_send_phy_db_data(mvm->phy_db); 911e705c121SKalle Valo if (ret) 912e705c121SKalle Valo goto error; 913e705c121SKalle Valo 914e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 915e705c121SKalle Valo if (ret) 916e705c121SKalle Valo goto error; 917e705c121SKalle Valo 91843413a97SSara Sharon /* Init RSS configuration */ 91943413a97SSara Sharon if (iwl_mvm_has_new_rx_api(mvm)) { 92043413a97SSara Sharon ret = iwl_send_rss_cfg_cmd(mvm); 92143413a97SSara Sharon if (ret) { 92243413a97SSara Sharon IWL_ERR(mvm, "Failed to configure RSS queues: %d\n", 92343413a97SSara Sharon ret); 92443413a97SSara Sharon goto error; 92543413a97SSara Sharon } 92643413a97SSara Sharon } 92743413a97SSara Sharon 928e705c121SKalle Valo /* init the fw <-> mac80211 STA mapping */ 929e705c121SKalle Valo for (i = 0; i < IWL_MVM_STATION_COUNT; i++) 930e705c121SKalle Valo RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); 931e705c121SKalle Valo 932e705c121SKalle Valo mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT; 933e705c121SKalle Valo 934e705c121SKalle Valo /* reset quota debouncing buffer - 0xff will yield invalid data */ 935e705c121SKalle Valo memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); 936e705c121SKalle Valo 937e705c121SKalle Valo /* Add auxiliary station for scanning */ 938e705c121SKalle Valo ret = iwl_mvm_add_aux_sta(mvm); 939e705c121SKalle Valo if (ret) 940e705c121SKalle Valo goto error; 941e705c121SKalle Valo 942e705c121SKalle Valo /* Add all the PHY contexts */ 943e705c121SKalle Valo chan = &mvm->hw->wiphy->bands[IEEE80211_BAND_2GHZ]->channels[0]; 944e705c121SKalle Valo cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); 945e705c121SKalle Valo for (i = 0; i < NUM_PHY_CTX; i++) { 946e705c121SKalle Valo /* 947e705c121SKalle Valo * The channel used here isn't relevant as it's 948e705c121SKalle Valo * going to be overwritten in the other flows. 949e705c121SKalle Valo * For now use the first channel we have. 950e705c121SKalle Valo */ 951e705c121SKalle Valo ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], 952e705c121SKalle Valo &chandef, 1, 1); 953e705c121SKalle Valo if (ret) 954e705c121SKalle Valo goto error; 955e705c121SKalle Valo } 956e705c121SKalle Valo 957c221daf2SChaya Rachel Ivgi #ifdef CONFIG_THERMAL 958c221daf2SChaya Rachel Ivgi if (iwl_mvm_is_tt_in_fw(mvm)) { 959c221daf2SChaya Rachel Ivgi /* in order to give the responsibility of ct-kill and 960c221daf2SChaya Rachel Ivgi * TX backoff to FW we need to send empty temperature reporting 961c221daf2SChaya Rachel Ivgi * cmd during init time 962c221daf2SChaya Rachel Ivgi */ 963c221daf2SChaya Rachel Ivgi iwl_mvm_send_temp_report_ths_cmd(mvm); 964c221daf2SChaya Rachel Ivgi } else { 965e705c121SKalle Valo /* Initialize tx backoffs to the minimal possible */ 966e705c121SKalle Valo iwl_mvm_tt_tx_backoff(mvm, 0); 967c221daf2SChaya Rachel Ivgi } 9685c89e7bcSChaya Rachel Ivgi 9695c89e7bcSChaya Rachel Ivgi /* TODO: read the budget from BIOS / Platform NVM */ 9705c89e7bcSChaya Rachel Ivgi if (iwl_mvm_is_ctdp_supported(mvm) && mvm->cooling_dev.cur_state > 0) 9715c89e7bcSChaya Rachel Ivgi ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START, 9725c89e7bcSChaya Rachel Ivgi mvm->cooling_dev.cur_state); 973c221daf2SChaya Rachel Ivgi #else 974c221daf2SChaya Rachel Ivgi /* Initialize tx backoffs to the minimal possible */ 975c221daf2SChaya Rachel Ivgi iwl_mvm_tt_tx_backoff(mvm, 0); 976c221daf2SChaya Rachel Ivgi #endif 977e705c121SKalle Valo 978e705c121SKalle Valo WARN_ON(iwl_mvm_config_ltr(mvm)); 979e705c121SKalle Valo 980e705c121SKalle Valo ret = iwl_mvm_power_update_device(mvm); 981e705c121SKalle Valo if (ret) 982e705c121SKalle Valo goto error; 983e705c121SKalle Valo 984e705c121SKalle Valo /* 985e705c121SKalle Valo * RTNL is not taken during Ct-kill, but we don't need to scan/Tx 986e705c121SKalle Valo * anyway, so don't init MCC. 987e705c121SKalle Valo */ 988e705c121SKalle Valo if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { 989e705c121SKalle Valo ret = iwl_mvm_init_mcc(mvm); 990e705c121SKalle Valo if (ret) 991e705c121SKalle Valo goto error; 992e705c121SKalle Valo } 993e705c121SKalle Valo 994e705c121SKalle Valo if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { 9954ca87a5fSEmmanuel Grumbach mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; 996e705c121SKalle Valo ret = iwl_mvm_config_scan(mvm); 997e705c121SKalle Valo if (ret) 998e705c121SKalle Valo goto error; 999e705c121SKalle Valo } 1000e705c121SKalle Valo 1001e705c121SKalle Valo if (iwl_mvm_is_csum_supported(mvm) && 1002e705c121SKalle Valo mvm->cfg->features & NETIF_F_RXCSUM) 1003e705c121SKalle Valo iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3); 1004e705c121SKalle Valo 1005e705c121SKalle Valo /* allow FW/transport low power modes if not during restart */ 1006e705c121SKalle Valo if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) 1007e705c121SKalle Valo iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN); 1008e705c121SKalle Valo 1009e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); 1010e705c121SKalle Valo return 0; 1011e705c121SKalle Valo error: 1012fcb6b92aSChaya Rachel Ivgi iwl_mvm_stop_device(mvm); 1013e705c121SKalle Valo return ret; 1014e705c121SKalle Valo } 1015e705c121SKalle Valo 1016e705c121SKalle Valo int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) 1017e705c121SKalle Valo { 1018e705c121SKalle Valo int ret, i; 1019e705c121SKalle Valo 1020e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 1021e705c121SKalle Valo 1022e705c121SKalle Valo ret = iwl_trans_start_hw(mvm->trans); 1023e705c121SKalle Valo if (ret) 1024e705c121SKalle Valo return ret; 1025e705c121SKalle Valo 1026e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); 1027e705c121SKalle Valo if (ret) { 1028e705c121SKalle Valo IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); 1029e705c121SKalle Valo goto error; 1030e705c121SKalle Valo } 1031e705c121SKalle Valo 1032e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 1033e705c121SKalle Valo if (ret) 1034e705c121SKalle Valo goto error; 1035e705c121SKalle Valo 1036e705c121SKalle Valo /* Send phy db control command and then phy db calibration*/ 1037e705c121SKalle Valo ret = iwl_send_phy_db_data(mvm->phy_db); 1038e705c121SKalle Valo if (ret) 1039e705c121SKalle Valo goto error; 1040e705c121SKalle Valo 1041e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 1042e705c121SKalle Valo if (ret) 1043e705c121SKalle Valo goto error; 1044e705c121SKalle Valo 1045e705c121SKalle Valo /* init the fw <-> mac80211 STA mapping */ 1046e705c121SKalle Valo for (i = 0; i < IWL_MVM_STATION_COUNT; i++) 1047e705c121SKalle Valo RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); 1048e705c121SKalle Valo 1049e705c121SKalle Valo /* Add auxiliary station for scanning */ 1050e705c121SKalle Valo ret = iwl_mvm_add_aux_sta(mvm); 1051e705c121SKalle Valo if (ret) 1052e705c121SKalle Valo goto error; 1053e705c121SKalle Valo 1054e705c121SKalle Valo return 0; 1055e705c121SKalle Valo error: 1056fcb6b92aSChaya Rachel Ivgi iwl_mvm_stop_device(mvm); 1057e705c121SKalle Valo return ret; 1058e705c121SKalle Valo } 1059e705c121SKalle Valo 1060e705c121SKalle Valo void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, 1061e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1062e705c121SKalle Valo { 1063e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1064e705c121SKalle Valo struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; 1065e705c121SKalle Valo u32 flags = le32_to_cpu(card_state_notif->flags); 1066e705c121SKalle Valo 1067e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", 1068e705c121SKalle Valo (flags & HW_CARD_DISABLED) ? "Kill" : "On", 1069e705c121SKalle Valo (flags & SW_CARD_DISABLED) ? "Kill" : "On", 1070e705c121SKalle Valo (flags & CT_KILL_CARD_DISABLED) ? 1071e705c121SKalle Valo "Reached" : "Not reached"); 1072e705c121SKalle Valo } 1073e705c121SKalle Valo 1074e705c121SKalle Valo void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, 1075e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1076e705c121SKalle Valo { 1077e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1078e705c121SKalle Valo struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; 1079e705c121SKalle Valo 1080e705c121SKalle Valo IWL_DEBUG_INFO(mvm, 1081e705c121SKalle Valo "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", 1082e705c121SKalle Valo le32_to_cpu(mfuart_notif->installed_ver), 1083e705c121SKalle Valo le32_to_cpu(mfuart_notif->external_ver), 1084e705c121SKalle Valo le32_to_cpu(mfuart_notif->status), 1085e705c121SKalle Valo le32_to_cpu(mfuart_notif->duration)); 1086e705c121SKalle Valo } 1087