1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 9bdccdb85SGolan Ben-Ami * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 10cceb4507SShahar S Matityahu * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation 11e705c121SKalle Valo * 12e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 13e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 14e705c121SKalle Valo * published by the Free Software Foundation. 15e705c121SKalle Valo * 16e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 17e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 18e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19e705c121SKalle Valo * General Public License for more details. 20e705c121SKalle Valo * 21e705c121SKalle Valo * The full GNU General Public License is included in this distribution 22e705c121SKalle Valo * in the file called COPYING. 23e705c121SKalle Valo * 24e705c121SKalle Valo * Contact Information: 25cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 26e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27e705c121SKalle Valo * 28e705c121SKalle Valo * BSD LICENSE 29e705c121SKalle Valo * 30e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 31bdccdb85SGolan Ben-Ami * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 32cceb4507SShahar S Matityahu * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation 33e705c121SKalle Valo * All rights reserved. 34e705c121SKalle Valo * 35e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 36e705c121SKalle Valo * modification, are permitted provided that the following conditions 37e705c121SKalle Valo * are met: 38e705c121SKalle Valo * 39e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 40e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 41e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 43e705c121SKalle Valo * the documentation and/or other materials provided with the 44e705c121SKalle Valo * distribution. 45e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 46e705c121SKalle Valo * contributors may be used to endorse or promote products derived 47e705c121SKalle Valo * from this software without specific prior written permission. 48e705c121SKalle Valo * 49e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 50e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 51e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 52e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 53e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 55e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 59e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60e705c121SKalle Valo * 61e705c121SKalle Valo *****************************************************************************/ 62e705c121SKalle Valo #include <net/mac80211.h> 63854d773eSSara Sharon #include <linux/netdevice.h> 64e705c121SKalle Valo 65e705c121SKalle Valo #include "iwl-trans.h" 66e705c121SKalle Valo #include "iwl-op-mode.h" 67d962f9b1SJohannes Berg #include "fw/img.h" 68e705c121SKalle Valo #include "iwl-debug.h" 69e705c121SKalle Valo #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ 70e705c121SKalle Valo #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ 71e705c121SKalle Valo #include "iwl-prph.h" 72813df5ceSLuca Coelho #include "fw/acpi.h" 73e705c121SKalle Valo 74e705c121SKalle Valo #include "mvm.h" 757174beb6SJohannes Berg #include "fw/dbg.h" 76e705c121SKalle Valo #include "iwl-phy-db.h" 779c4f7d51SShaul Triebitz #include "iwl-modparams.h" 789c4f7d51SShaul Triebitz #include "iwl-nvm-parse.h" 79e705c121SKalle Valo 80e705c121SKalle Valo #define MVM_UCODE_ALIVE_TIMEOUT HZ 81e705c121SKalle Valo #define MVM_UCODE_CALIB_TIMEOUT (2*HZ) 82e705c121SKalle Valo 83e705c121SKalle Valo #define UCODE_VALID_OK cpu_to_le32(0x1) 84e705c121SKalle Valo 85e705c121SKalle Valo struct iwl_mvm_alive_data { 86e705c121SKalle Valo bool valid; 87e705c121SKalle Valo u32 scd_base_addr; 88e705c121SKalle Valo }; 89e705c121SKalle Valo 90e705c121SKalle Valo static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) 91e705c121SKalle Valo { 92e705c121SKalle Valo struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { 93e705c121SKalle Valo .valid = cpu_to_le32(valid_tx_ant), 94e705c121SKalle Valo }; 95e705c121SKalle Valo 96e705c121SKalle Valo IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); 97e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, 98e705c121SKalle Valo sizeof(tx_ant_cmd), &tx_ant_cmd); 99e705c121SKalle Valo } 100e705c121SKalle Valo 10143413a97SSara Sharon static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm) 10243413a97SSara Sharon { 10343413a97SSara Sharon int i; 10443413a97SSara Sharon struct iwl_rss_config_cmd cmd = { 10543413a97SSara Sharon .flags = cpu_to_le32(IWL_RSS_ENABLE), 106608dce95SSara Sharon .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) | 107608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) | 108608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) | 109608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) | 110608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) | 111608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD), 11243413a97SSara Sharon }; 11343413a97SSara Sharon 114f43495fdSSara Sharon if (mvm->trans->num_rx_queues == 1) 115f43495fdSSara Sharon return 0; 116f43495fdSSara Sharon 117854d773eSSara Sharon /* Do not direct RSS traffic to Q 0 which is our fallback queue */ 11843413a97SSara Sharon for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++) 119854d773eSSara Sharon cmd.indirection_table[i] = 120854d773eSSara Sharon 1 + (i % (mvm->trans->num_rx_queues - 1)); 121854d773eSSara Sharon netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key)); 12243413a97SSara Sharon 12343413a97SSara Sharon return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd); 12443413a97SSara Sharon } 12543413a97SSara Sharon 1268edbfaa1SSara Sharon static int iwl_configure_rxq(struct iwl_mvm *mvm) 1278edbfaa1SSara Sharon { 128dbf592f3SJohannes Berg int i, num_queues, size, ret; 1298edbfaa1SSara Sharon struct iwl_rfh_queue_config *cmd; 130dbf592f3SJohannes Berg struct iwl_host_cmd hcmd = { 131dbf592f3SJohannes Berg .id = WIDE_ID(DATA_PATH_GROUP, RFH_QUEUE_CONFIG_CMD), 132dbf592f3SJohannes Berg .dataflags[0] = IWL_HCMD_DFL_NOCOPY, 133dbf592f3SJohannes Berg }; 1348edbfaa1SSara Sharon 1358edbfaa1SSara Sharon /* Do not configure default queue, it is configured via context info */ 1368edbfaa1SSara Sharon num_queues = mvm->trans->num_rx_queues - 1; 1378edbfaa1SSara Sharon 138dbf592f3SJohannes Berg size = struct_size(cmd, data, num_queues); 1398edbfaa1SSara Sharon 1408edbfaa1SSara Sharon cmd = kzalloc(size, GFP_KERNEL); 1418edbfaa1SSara Sharon if (!cmd) 1428edbfaa1SSara Sharon return -ENOMEM; 1438edbfaa1SSara Sharon 1448edbfaa1SSara Sharon cmd->num_queues = num_queues; 1458edbfaa1SSara Sharon 1468edbfaa1SSara Sharon for (i = 0; i < num_queues; i++) { 1478edbfaa1SSara Sharon struct iwl_trans_rxq_dma_data data; 1488edbfaa1SSara Sharon 1498edbfaa1SSara Sharon cmd->data[i].q_num = i + 1; 1508edbfaa1SSara Sharon iwl_trans_get_rxq_dma_data(mvm->trans, i + 1, &data); 1518edbfaa1SSara Sharon 1528edbfaa1SSara Sharon cmd->data[i].fr_bd_cb = cpu_to_le64(data.fr_bd_cb); 1538edbfaa1SSara Sharon cmd->data[i].urbd_stts_wrptr = 1548edbfaa1SSara Sharon cpu_to_le64(data.urbd_stts_wrptr); 1558edbfaa1SSara Sharon cmd->data[i].ur_bd_cb = cpu_to_le64(data.ur_bd_cb); 1568edbfaa1SSara Sharon cmd->data[i].fr_bd_wid = cpu_to_le32(data.fr_bd_wid); 1578edbfaa1SSara Sharon } 1588edbfaa1SSara Sharon 159dbf592f3SJohannes Berg hcmd.data[0] = cmd; 160dbf592f3SJohannes Berg hcmd.len[0] = size; 161dbf592f3SJohannes Berg 162dbf592f3SJohannes Berg ret = iwl_mvm_send_cmd(mvm, &hcmd); 163dbf592f3SJohannes Berg 164dbf592f3SJohannes Berg kfree(cmd); 165dbf592f3SJohannes Berg 166dbf592f3SJohannes Berg return ret; 1678edbfaa1SSara Sharon } 1688edbfaa1SSara Sharon 16997d5be7eSLiad Kaufman static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm) 17097d5be7eSLiad Kaufman { 17197d5be7eSLiad Kaufman struct iwl_dqa_enable_cmd dqa_cmd = { 17297d5be7eSLiad Kaufman .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE), 17397d5be7eSLiad Kaufman }; 17497d5be7eSLiad Kaufman u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0); 17597d5be7eSLiad Kaufman int ret; 17697d5be7eSLiad Kaufman 17797d5be7eSLiad Kaufman ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); 17897d5be7eSLiad Kaufman if (ret) 17997d5be7eSLiad Kaufman IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret); 18097d5be7eSLiad Kaufman else 18197d5be7eSLiad Kaufman IWL_DEBUG_FW(mvm, "Working in DQA mode\n"); 18297d5be7eSLiad Kaufman 18397d5be7eSLiad Kaufman return ret; 18497d5be7eSLiad Kaufman } 18597d5be7eSLiad Kaufman 186bdccdb85SGolan Ben-Ami void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm, 187bdccdb85SGolan Ben-Ami struct iwl_rx_cmd_buffer *rxb) 188bdccdb85SGolan Ben-Ami { 189bdccdb85SGolan Ben-Ami struct iwl_rx_packet *pkt = rxb_addr(rxb); 190bdccdb85SGolan Ben-Ami struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data; 191bdccdb85SGolan Ben-Ami __le32 *dump_data = mfu_dump_notif->data; 192bdccdb85SGolan Ben-Ami int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32); 193bdccdb85SGolan Ben-Ami int i; 194bdccdb85SGolan Ben-Ami 195bdccdb85SGolan Ben-Ami if (mfu_dump_notif->index_num == 0) 196bdccdb85SGolan Ben-Ami IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n", 197bdccdb85SGolan Ben-Ami le32_to_cpu(mfu_dump_notif->assert_id)); 198bdccdb85SGolan Ben-Ami 199bdccdb85SGolan Ben-Ami for (i = 0; i < n_words; i++) 200bdccdb85SGolan Ben-Ami IWL_DEBUG_INFO(mvm, 201bdccdb85SGolan Ben-Ami "MFUART assert dump, dword %u: 0x%08x\n", 202bdccdb85SGolan Ben-Ami le16_to_cpu(mfu_dump_notif->index_num) * 203bdccdb85SGolan Ben-Ami n_words + i, 204bdccdb85SGolan Ben-Ami le32_to_cpu(dump_data[i])); 205bdccdb85SGolan Ben-Ami } 206bdccdb85SGolan Ben-Ami 207e705c121SKalle Valo static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, 208e705c121SKalle Valo struct iwl_rx_packet *pkt, void *data) 209e705c121SKalle Valo { 210e705c121SKalle Valo struct iwl_mvm *mvm = 211e705c121SKalle Valo container_of(notif_wait, struct iwl_mvm, notif_wait); 212e705c121SKalle Valo struct iwl_mvm_alive_data *alive_data = data; 2135c228d63SSara Sharon struct mvm_alive_resp_v3 *palive3; 214e705c121SKalle Valo struct mvm_alive_resp *palive; 2155c228d63SSara Sharon struct iwl_umac_alive *umac; 2165c228d63SSara Sharon struct iwl_lmac_alive *lmac1; 2175c228d63SSara Sharon struct iwl_lmac_alive *lmac2 = NULL; 2185c228d63SSara Sharon u16 status; 219cfa5d0caSMordechay Goodstein u32 lmac_error_event_table, umac_error_table; 220e705c121SKalle Valo 2215c228d63SSara Sharon if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) { 222e705c121SKalle Valo palive = (void *)pkt->data; 2235c228d63SSara Sharon umac = &palive->umac_data; 2245c228d63SSara Sharon lmac1 = &palive->lmac_data[0]; 2255c228d63SSara Sharon lmac2 = &palive->lmac_data[1]; 2265c228d63SSara Sharon status = le16_to_cpu(palive->status); 2275c228d63SSara Sharon } else { 2285c228d63SSara Sharon palive3 = (void *)pkt->data; 2295c228d63SSara Sharon umac = &palive3->umac_data; 2305c228d63SSara Sharon lmac1 = &palive3->lmac_data; 2315c228d63SSara Sharon status = le16_to_cpu(palive3->status); 2325c228d63SSara Sharon } 233e705c121SKalle Valo 23422463857SShahar S Matityahu lmac_error_event_table = 23522463857SShahar S Matityahu le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr); 23622463857SShahar S Matityahu iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table); 237e705c121SKalle Valo 23822463857SShahar S Matityahu if (lmac2) 23991c28b83SShahar S Matityahu mvm->trans->dbg.lmac_error_event_table[1] = 24022463857SShahar S Matityahu le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr); 24122463857SShahar S Matityahu 242cfa5d0caSMordechay Goodstein umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr); 2435c228d63SSara Sharon 244cfa5d0caSMordechay Goodstein if (umac_error_table) { 245cfa5d0caSMordechay Goodstein if (umac_error_table >= 2463485e76eSLuca Coelho mvm->trans->cfg->min_umac_error_event_table) { 247cfa5d0caSMordechay Goodstein iwl_fw_umac_set_alive_err_table(mvm->trans, 248cfa5d0caSMordechay Goodstein umac_error_table); 2493485e76eSLuca Coelho } else { 250fb5b2846SLuca Coelho IWL_ERR(mvm, 251fb5b2846SLuca Coelho "Not valid error log pointer 0x%08X for %s uCode\n", 252cfa5d0caSMordechay Goodstein umac_error_table, 253fb5b2846SLuca Coelho (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ? 254fb5b2846SLuca Coelho "Init" : "RT"); 2553485e76eSLuca Coelho } 256cfa5d0caSMordechay Goodstein } 25722463857SShahar S Matityahu 25822463857SShahar S Matityahu alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr); 2595c228d63SSara Sharon alive_data->valid = status == IWL_ALIVE_STATUS_OK; 260e705c121SKalle Valo 261e705c121SKalle Valo IWL_DEBUG_FW(mvm, 2625c228d63SSara Sharon "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n", 2635c228d63SSara Sharon status, lmac1->ver_type, lmac1->ver_subtype); 2645c228d63SSara Sharon 2655c228d63SSara Sharon if (lmac2) 2665c228d63SSara Sharon IWL_DEBUG_FW(mvm, "Alive ucode CDB\n"); 267e705c121SKalle Valo 268e705c121SKalle Valo IWL_DEBUG_FW(mvm, 269e705c121SKalle Valo "UMAC version: Major - 0x%x, Minor - 0x%x\n", 2705c228d63SSara Sharon le32_to_cpu(umac->umac_major), 2715c228d63SSara Sharon le32_to_cpu(umac->umac_minor)); 272e705c121SKalle Valo 2730a3a3e9eSShahar S Matityahu iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac); 2740a3a3e9eSShahar S Matityahu 275e705c121SKalle Valo return true; 276e705c121SKalle Valo } 277e705c121SKalle Valo 2781f370650SSara Sharon static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait, 2791f370650SSara Sharon struct iwl_rx_packet *pkt, void *data) 2801f370650SSara Sharon { 2811f370650SSara Sharon WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); 2821f370650SSara Sharon 2831f370650SSara Sharon return true; 2841f370650SSara Sharon } 2851f370650SSara Sharon 286e705c121SKalle Valo static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, 287e705c121SKalle Valo struct iwl_rx_packet *pkt, void *data) 288e705c121SKalle Valo { 289e705c121SKalle Valo struct iwl_phy_db *phy_db = data; 290e705c121SKalle Valo 291e705c121SKalle Valo if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { 292e705c121SKalle Valo WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); 293e705c121SKalle Valo return true; 294e705c121SKalle Valo } 295e705c121SKalle Valo 296ce1f2778SSara Sharon WARN_ON(iwl_phy_db_set_section(phy_db, pkt)); 297e705c121SKalle Valo 298e705c121SKalle Valo return false; 299e705c121SKalle Valo } 300e705c121SKalle Valo 301e705c121SKalle Valo static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, 302e705c121SKalle Valo enum iwl_ucode_type ucode_type) 303e705c121SKalle Valo { 304e705c121SKalle Valo struct iwl_notification_wait alive_wait; 30594a8d87cSLuca Coelho struct iwl_mvm_alive_data alive_data = {}; 306e705c121SKalle Valo const struct fw_img *fw; 307cfbc6c4cSSara Sharon int ret; 308702e975dSJohannes Berg enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img; 309e705c121SKalle Valo static const u16 alive_cmd[] = { MVM_ALIVE }; 310b3500b47SEmmanuel Grumbach bool run_in_rfkill = 311b3500b47SEmmanuel Grumbach ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm); 312e705c121SKalle Valo 313e705c121SKalle Valo if (ucode_type == IWL_UCODE_REGULAR && 3143d2d4422SGolan Ben-Ami iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) && 3153d2d4422SGolan Ben-Ami !(fw_has_capa(&mvm->fw->ucode_capa, 3163d2d4422SGolan Ben-Ami IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED))) 317612da1efSSharon Dvir fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER); 318e705c121SKalle Valo else 319612da1efSSharon Dvir fw = iwl_get_ucode_image(mvm->fw, ucode_type); 320e705c121SKalle Valo if (WARN_ON(!fw)) 321e705c121SKalle Valo return -EINVAL; 322702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, ucode_type); 32365b280feSJohannes Berg clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); 324e705c121SKalle Valo 325e705c121SKalle Valo iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, 326e705c121SKalle Valo alive_cmd, ARRAY_SIZE(alive_cmd), 327e705c121SKalle Valo iwl_alive_fn, &alive_data); 328e705c121SKalle Valo 329b3500b47SEmmanuel Grumbach /* 330b3500b47SEmmanuel Grumbach * We want to load the INIT firmware even in RFKILL 331b3500b47SEmmanuel Grumbach * For the unified firmware case, the ucode_type is not 332b3500b47SEmmanuel Grumbach * INIT, but we still need to run it. 333b3500b47SEmmanuel Grumbach */ 334b3500b47SEmmanuel Grumbach ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill); 335e705c121SKalle Valo if (ret) { 336702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, old_type); 337e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &alive_wait); 338e705c121SKalle Valo return ret; 339e705c121SKalle Valo } 340e705c121SKalle Valo 341e705c121SKalle Valo /* 342e705c121SKalle Valo * Some things may run in the background now, but we 343e705c121SKalle Valo * just wait for the ALIVE notification here. 344e705c121SKalle Valo */ 345e705c121SKalle Valo ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, 346e705c121SKalle Valo MVM_UCODE_ALIVE_TIMEOUT); 347e705c121SKalle Valo if (ret) { 348d6be9c1dSSara Sharon struct iwl_trans *trans = mvm->trans; 349d6be9c1dSSara Sharon 35020f5aef5SJohannes Berg if (trans->trans_cfg->device_family >= 35120f5aef5SJohannes Berg IWL_DEVICE_FAMILY_22000) { 352e705c121SKalle Valo IWL_ERR(mvm, 353e705c121SKalle Valo "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", 354ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS), 355ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, 356ea695b7cSShaul Triebitz UMAG_SB_CPU_2_STATUS)); 35720f5aef5SJohannes Berg IWL_ERR(mvm, "UMAC PC: 0x%x\n", 35820f5aef5SJohannes Berg iwl_read_umac_prph(trans, 35920f5aef5SJohannes Berg UREG_UMAC_CURRENT_PC)); 36020f5aef5SJohannes Berg IWL_ERR(mvm, "LMAC PC: 0x%x\n", 36120f5aef5SJohannes Berg iwl_read_umac_prph(trans, 36220f5aef5SJohannes Berg UREG_LMAC1_CURRENT_PC)); 36320f5aef5SJohannes Berg if (iwl_mvm_is_cdb_supported(mvm)) 36420f5aef5SJohannes Berg IWL_ERR(mvm, "LMAC2 PC: 0x%x\n", 36520f5aef5SJohannes Berg iwl_read_umac_prph(trans, 36620f5aef5SJohannes Berg UREG_LMAC2_CURRENT_PC)); 36720f5aef5SJohannes Berg } else if (trans->trans_cfg->device_family >= 36820f5aef5SJohannes Berg IWL_DEVICE_FAMILY_8000) { 369d6be9c1dSSara Sharon IWL_ERR(mvm, 370d6be9c1dSSara Sharon "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", 371d6be9c1dSSara Sharon iwl_read_prph(trans, SB_CPU_1_STATUS), 372d6be9c1dSSara Sharon iwl_read_prph(trans, SB_CPU_2_STATUS)); 37320f5aef5SJohannes Berg } 37420f5aef5SJohannes Berg 37520f5aef5SJohannes Berg if (ret == -ETIMEDOUT) 37620f5aef5SJohannes Berg iwl_fw_dbg_error_collect(&mvm->fwrt, 37720f5aef5SJohannes Berg FW_DBG_TRIGGER_ALIVE_TIMEOUT); 37820f5aef5SJohannes Berg 379702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, old_type); 380e705c121SKalle Valo return ret; 381e705c121SKalle Valo } 382e705c121SKalle Valo 383e705c121SKalle Valo if (!alive_data.valid) { 384e705c121SKalle Valo IWL_ERR(mvm, "Loaded ucode is not valid!\n"); 385702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, old_type); 386e705c121SKalle Valo return -EIO; 387e705c121SKalle Valo } 388e705c121SKalle Valo 389e705c121SKalle Valo iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); 390e705c121SKalle Valo 391e705c121SKalle Valo /* 392e705c121SKalle Valo * Note: all the queues are enabled as part of the interface 393e705c121SKalle Valo * initialization, but in firmware restart scenarios they 394e705c121SKalle Valo * could be stopped, so wake them up. In firmware restart, 395e705c121SKalle Valo * mac80211 will have the queues stopped as well until the 396e705c121SKalle Valo * reconfiguration completes. During normal startup, they 397e705c121SKalle Valo * will be empty. 398e705c121SKalle Valo */ 399e705c121SKalle Valo 400e705c121SKalle Valo memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); 4011c14089eSJohannes Berg /* 4021c14089eSJohannes Berg * Set a 'fake' TID for the command queue, since we use the 4031c14089eSJohannes Berg * hweight() of the tid_bitmap as a refcount now. Not that 4041c14089eSJohannes Berg * we ever even consider the command queue as one we might 4051c14089eSJohannes Berg * want to reuse, but be safe nevertheless. 4061c14089eSJohannes Berg */ 4071c14089eSJohannes Berg mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap = 4081c14089eSJohannes Berg BIT(IWL_MAX_TID_COUNT + 2); 409e705c121SKalle Valo 41065b280feSJohannes Berg set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); 411f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 412f7805b33SLior Cohen iwl_fw_set_dbg_rec_on(&mvm->fwrt); 413f7805b33SLior Cohen #endif 414e705c121SKalle Valo 415e705c121SKalle Valo return 0; 416e705c121SKalle Valo } 417e705c121SKalle Valo 4188c5f47b1SJohannes Berg static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) 4198c5f47b1SJohannes Berg { 4208c5f47b1SJohannes Berg struct iwl_notification_wait init_wait; 4218c5f47b1SJohannes Berg struct iwl_nvm_access_complete_cmd nvm_complete = {}; 4228c5f47b1SJohannes Berg struct iwl_init_extended_cfg_cmd init_cfg = { 4238c5f47b1SJohannes Berg .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)), 4248c5f47b1SJohannes Berg }; 4258c5f47b1SJohannes Berg static const u16 init_complete[] = { 4268c5f47b1SJohannes Berg INIT_COMPLETE_NOTIF, 4278c5f47b1SJohannes Berg }; 4288c5f47b1SJohannes Berg int ret; 4298c5f47b1SJohannes Berg 430a4584729SHaim Dreyfuss if (mvm->trans->cfg->tx_with_siso_diversity) 431a4584729SHaim Dreyfuss init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY)); 432a4584729SHaim Dreyfuss 4338c5f47b1SJohannes Berg lockdep_assert_held(&mvm->mutex); 4348c5f47b1SJohannes Berg 43594022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 43694022562SEmmanuel Grumbach 4378c5f47b1SJohannes Berg iwl_init_notification_wait(&mvm->notif_wait, 4388c5f47b1SJohannes Berg &init_wait, 4398c5f47b1SJohannes Berg init_complete, 4408c5f47b1SJohannes Berg ARRAY_SIZE(init_complete), 4418c5f47b1SJohannes Berg iwl_wait_init_complete, 4428c5f47b1SJohannes Berg NULL); 4438c5f47b1SJohannes Berg 444b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); 44586ce5c74SShahar S Matityahu 4468c5f47b1SJohannes Berg /* Will also start the device */ 4478c5f47b1SJohannes Berg ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); 4488c5f47b1SJohannes Berg if (ret) { 4498c5f47b1SJohannes Berg IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); 4508c5f47b1SJohannes Berg goto error; 4518c5f47b1SJohannes Berg } 452b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, 453b108d8c7SShahar S Matityahu NULL); 4548c5f47b1SJohannes Berg 4558c5f47b1SJohannes Berg /* Send init config command to mark that we are sending NVM access 4568c5f47b1SJohannes Berg * commands 4578c5f47b1SJohannes Berg */ 4588c5f47b1SJohannes Berg ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP, 459b3500b47SEmmanuel Grumbach INIT_EXTENDED_CFG_CMD), 460b3500b47SEmmanuel Grumbach CMD_SEND_IN_RFKILL, 4618c5f47b1SJohannes Berg sizeof(init_cfg), &init_cfg); 4628c5f47b1SJohannes Berg if (ret) { 4638c5f47b1SJohannes Berg IWL_ERR(mvm, "Failed to run init config command: %d\n", 4648c5f47b1SJohannes Berg ret); 4658c5f47b1SJohannes Berg goto error; 4668c5f47b1SJohannes Berg } 4678c5f47b1SJohannes Berg 468e9e1ba3dSSara Sharon /* Load NVM to NIC if needed */ 469e9e1ba3dSSara Sharon if (mvm->nvm_file_name) { 4709c4f7d51SShaul Triebitz iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name, 4719c4f7d51SShaul Triebitz mvm->nvm_sections); 4728c5f47b1SJohannes Berg iwl_mvm_load_nvm_to_nic(mvm); 473e9e1ba3dSSara Sharon } 4748c5f47b1SJohannes Berg 475d4f3695eSSara Sharon if (IWL_MVM_PARSE_NVM && read_nvm) { 4765bd1d2c1SLuca Coelho ret = iwl_nvm_init(mvm); 477d4f3695eSSara Sharon if (ret) { 478d4f3695eSSara Sharon IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); 479d4f3695eSSara Sharon goto error; 480d4f3695eSSara Sharon } 481d4f3695eSSara Sharon } 482d4f3695eSSara Sharon 4838c5f47b1SJohannes Berg ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP, 484b3500b47SEmmanuel Grumbach NVM_ACCESS_COMPLETE), 485b3500b47SEmmanuel Grumbach CMD_SEND_IN_RFKILL, 4868c5f47b1SJohannes Berg sizeof(nvm_complete), &nvm_complete); 4878c5f47b1SJohannes Berg if (ret) { 4888c5f47b1SJohannes Berg IWL_ERR(mvm, "Failed to run complete NVM access: %d\n", 4898c5f47b1SJohannes Berg ret); 4908c5f47b1SJohannes Berg goto error; 4918c5f47b1SJohannes Berg } 4928c5f47b1SJohannes Berg 4938c5f47b1SJohannes Berg /* We wait for the INIT complete notification */ 494e9e1ba3dSSara Sharon ret = iwl_wait_notification(&mvm->notif_wait, &init_wait, 4958c5f47b1SJohannes Berg MVM_UCODE_ALIVE_TIMEOUT); 496e9e1ba3dSSara Sharon if (ret) 497e9e1ba3dSSara Sharon return ret; 498e9e1ba3dSSara Sharon 499e9e1ba3dSSara Sharon /* Read the NVM only at driver load time, no need to do this twice */ 500d4f3695eSSara Sharon if (!IWL_MVM_PARSE_NVM && read_nvm) { 5014c625c56SShaul Triebitz mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw); 502c135cb56SShaul Triebitz if (IS_ERR(mvm->nvm_data)) { 503c135cb56SShaul Triebitz ret = PTR_ERR(mvm->nvm_data); 504c135cb56SShaul Triebitz mvm->nvm_data = NULL; 505e9e1ba3dSSara Sharon IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); 506e9e1ba3dSSara Sharon return ret; 507e9e1ba3dSSara Sharon } 508e9e1ba3dSSara Sharon } 509e9e1ba3dSSara Sharon 510b3500b47SEmmanuel Grumbach mvm->rfkill_safe_init_done = true; 511b3500b47SEmmanuel Grumbach 512e9e1ba3dSSara Sharon return 0; 5138c5f47b1SJohannes Berg 5148c5f47b1SJohannes Berg error: 5158c5f47b1SJohannes Berg iwl_remove_notification(&mvm->notif_wait, &init_wait); 5168c5f47b1SJohannes Berg return ret; 5178c5f47b1SJohannes Berg } 5188c5f47b1SJohannes Berg 519c4ace426SGil Adam #ifdef CONFIG_ACPI 520c4ace426SGil Adam static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm, 521c4ace426SGil Adam struct iwl_phy_specific_cfg *phy_filters) 522c4ace426SGil Adam { 523c4ace426SGil Adam /* 524c4ace426SGil Adam * TODO: read specific phy config from BIOS 525c4ace426SGil Adam * ACPI table for this feature has not been defined yet, 526c4ace426SGil Adam * so for now we use hardcoded values. 527c4ace426SGil Adam */ 528c4ace426SGil Adam 529c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_A) { 530c4ace426SGil Adam phy_filters->filter_cfg_chain_a = 531c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A); 532c4ace426SGil Adam } 533c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_B) { 534c4ace426SGil Adam phy_filters->filter_cfg_chain_b = 535c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B); 536c4ace426SGil Adam } 537c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_C) { 538c4ace426SGil Adam phy_filters->filter_cfg_chain_c = 539c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C); 540c4ace426SGil Adam } 541c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_D) { 542c4ace426SGil Adam phy_filters->filter_cfg_chain_d = 543c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D); 544c4ace426SGil Adam } 545c4ace426SGil Adam } 546c4ace426SGil Adam 547c4ace426SGil Adam #else /* CONFIG_ACPI */ 548c4ace426SGil Adam 549c4ace426SGil Adam static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm, 550c4ace426SGil Adam struct iwl_phy_specific_cfg *phy_filters) 551c4ace426SGil Adam { 552c4ace426SGil Adam } 553c4ace426SGil Adam #endif /* CONFIG_ACPI */ 554c4ace426SGil Adam 555e705c121SKalle Valo static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) 556e705c121SKalle Valo { 557c4ace426SGil Adam struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd; 558702e975dSJohannes Berg enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img; 559c4ace426SGil Adam struct iwl_phy_specific_cfg phy_filters = {}; 560c4ace426SGil Adam u8 cmd_ver; 561c4ace426SGil Adam size_t cmd_size; 562e705c121SKalle Valo 563bb99ff9bSLuca Coelho if (iwl_mvm_has_unified_ucode(mvm) && 564d923b020SLuca Coelho !mvm->trans->cfg->tx_with_siso_diversity) 565bb99ff9bSLuca Coelho return 0; 566d923b020SLuca Coelho 567d923b020SLuca Coelho if (mvm->trans->cfg->tx_with_siso_diversity) { 568bb99ff9bSLuca Coelho /* 569bb99ff9bSLuca Coelho * TODO: currently we don't set the antenna but letting the NIC 570bb99ff9bSLuca Coelho * to decide which antenna to use. This should come from BIOS. 571bb99ff9bSLuca Coelho */ 572bb99ff9bSLuca Coelho phy_cfg_cmd.phy_cfg = 573bb99ff9bSLuca Coelho cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED); 574bb99ff9bSLuca Coelho } 575bb99ff9bSLuca Coelho 576e705c121SKalle Valo /* Set parameters */ 577e705c121SKalle Valo phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); 57886a2b204SLuca Coelho 57986a2b204SLuca Coelho /* set flags extra PHY configuration flags from the device's cfg */ 5807897dfa2SLuca Coelho phy_cfg_cmd.phy_cfg |= 5817897dfa2SLuca Coelho cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags); 58286a2b204SLuca Coelho 583e705c121SKalle Valo phy_cfg_cmd.calib_control.event_trigger = 584e705c121SKalle Valo mvm->fw->default_calib[ucode_type].event_trigger; 585e705c121SKalle Valo phy_cfg_cmd.calib_control.flow_trigger = 586e705c121SKalle Valo mvm->fw->default_calib[ucode_type].flow_trigger; 587e705c121SKalle Valo 588c4ace426SGil Adam cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, IWL_ALWAYS_LONG_GROUP, 589e80bfd11SMordechay Goodstein PHY_CONFIGURATION_CMD, 590e80bfd11SMordechay Goodstein IWL_FW_CMD_VER_UNKNOWN); 591c4ace426SGil Adam if (cmd_ver == 3) { 592c4ace426SGil Adam iwl_mvm_phy_filter_init(mvm, &phy_filters); 593c4ace426SGil Adam memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters, 594c4ace426SGil Adam sizeof(struct iwl_phy_specific_cfg)); 595c4ace426SGil Adam } 596c4ace426SGil Adam 597e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", 598e705c121SKalle Valo phy_cfg_cmd.phy_cfg); 599c4ace426SGil Adam cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) : 600c4ace426SGil Adam sizeof(struct iwl_phy_cfg_cmd_v1); 601e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, 602c4ace426SGil Adam cmd_size, &phy_cfg_cmd); 603e705c121SKalle Valo } 604e705c121SKalle Valo 605e705c121SKalle Valo int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) 606e705c121SKalle Valo { 607e705c121SKalle Valo struct iwl_notification_wait calib_wait; 608e705c121SKalle Valo static const u16 init_complete[] = { 609e705c121SKalle Valo INIT_COMPLETE_NOTIF, 610e705c121SKalle Valo CALIB_RES_NOTIF_PHY_DB 611e705c121SKalle Valo }; 612e705c121SKalle Valo int ret; 613e705c121SKalle Valo 6147d6222e2SJohannes Berg if (iwl_mvm_has_unified_ucode(mvm)) 6158c5f47b1SJohannes Berg return iwl_run_unified_mvm_ucode(mvm, true); 6168c5f47b1SJohannes Berg 617e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 618e705c121SKalle Valo 61994022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 620e705c121SKalle Valo 621e705c121SKalle Valo iwl_init_notification_wait(&mvm->notif_wait, 622e705c121SKalle Valo &calib_wait, 623e705c121SKalle Valo init_complete, 624e705c121SKalle Valo ARRAY_SIZE(init_complete), 625e705c121SKalle Valo iwl_wait_phy_db_entry, 626e705c121SKalle Valo mvm->phy_db); 627e705c121SKalle Valo 628e705c121SKalle Valo /* Will also start the device */ 629e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); 630e705c121SKalle Valo if (ret) { 631e705c121SKalle Valo IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); 63200e0c6c8SLuca Coelho goto remove_notif; 633e705c121SKalle Valo } 634e705c121SKalle Valo 6357d34a7d7SLuca Coelho if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) { 636b3de3ef4SEmmanuel Grumbach ret = iwl_mvm_send_bt_init_conf(mvm); 637e705c121SKalle Valo if (ret) 63800e0c6c8SLuca Coelho goto remove_notif; 639b3de3ef4SEmmanuel Grumbach } 640e705c121SKalle Valo 641e705c121SKalle Valo /* Read the NVM only at driver load time, no need to do this twice */ 642e705c121SKalle Valo if (read_nvm) { 6435bd1d2c1SLuca Coelho ret = iwl_nvm_init(mvm); 644e705c121SKalle Valo if (ret) { 645e705c121SKalle Valo IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); 64600e0c6c8SLuca Coelho goto remove_notif; 647e705c121SKalle Valo } 648e705c121SKalle Valo } 649e705c121SKalle Valo 650e705c121SKalle Valo /* In case we read the NVM from external file, load it to the NIC */ 651e705c121SKalle Valo if (mvm->nvm_file_name) 652e705c121SKalle Valo iwl_mvm_load_nvm_to_nic(mvm); 653e705c121SKalle Valo 65464866e5dSLuca Coelho WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver, 65564866e5dSLuca Coelho "Too old NVM version (0x%0x, required = 0x%0x)", 65664866e5dSLuca Coelho mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver); 657e705c121SKalle Valo 658e705c121SKalle Valo /* 659e705c121SKalle Valo * abort after reading the nvm in case RF Kill is on, we will complete 660e705c121SKalle Valo * the init seq later when RF kill will switch to off 661e705c121SKalle Valo */ 662e705c121SKalle Valo if (iwl_mvm_is_radio_hw_killed(mvm)) { 663e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, 664e705c121SKalle Valo "jump over all phy activities due to RF kill\n"); 66500e0c6c8SLuca Coelho goto remove_notif; 666e705c121SKalle Valo } 667e705c121SKalle Valo 668b3500b47SEmmanuel Grumbach mvm->rfkill_safe_init_done = true; 669e705c121SKalle Valo 670e705c121SKalle Valo /* Send TX valid antennas before triggering calibrations */ 671e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 672e705c121SKalle Valo if (ret) 67300e0c6c8SLuca Coelho goto remove_notif; 674e705c121SKalle Valo 675e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 676e705c121SKalle Valo if (ret) { 677e705c121SKalle Valo IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", 678e705c121SKalle Valo ret); 67900e0c6c8SLuca Coelho goto remove_notif; 680e705c121SKalle Valo } 681e705c121SKalle Valo 682e705c121SKalle Valo /* 683e705c121SKalle Valo * Some things may run in the background now, but we 684e705c121SKalle Valo * just wait for the calibration complete notification. 685e705c121SKalle Valo */ 686e705c121SKalle Valo ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, 687e705c121SKalle Valo MVM_UCODE_CALIB_TIMEOUT); 68800e0c6c8SLuca Coelho if (!ret) 689e705c121SKalle Valo goto out; 690e705c121SKalle Valo 69100e0c6c8SLuca Coelho if (iwl_mvm_is_radio_hw_killed(mvm)) { 69200e0c6c8SLuca Coelho IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); 69300e0c6c8SLuca Coelho ret = 0; 69400e0c6c8SLuca Coelho } else { 69500e0c6c8SLuca Coelho IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", 69600e0c6c8SLuca Coelho ret); 69700e0c6c8SLuca Coelho } 69800e0c6c8SLuca Coelho 69900e0c6c8SLuca Coelho goto out; 70000e0c6c8SLuca Coelho 70100e0c6c8SLuca Coelho remove_notif: 702e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &calib_wait); 703e705c121SKalle Valo out: 704b3500b47SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 705e705c121SKalle Valo if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { 706e705c121SKalle Valo /* we want to debug INIT and we have no NVM - fake */ 707e705c121SKalle Valo mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + 708e705c121SKalle Valo sizeof(struct ieee80211_channel) + 709e705c121SKalle Valo sizeof(struct ieee80211_rate), 710e705c121SKalle Valo GFP_KERNEL); 711e705c121SKalle Valo if (!mvm->nvm_data) 712e705c121SKalle Valo return -ENOMEM; 713e705c121SKalle Valo mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; 714e705c121SKalle Valo mvm->nvm_data->bands[0].n_channels = 1; 715e705c121SKalle Valo mvm->nvm_data->bands[0].n_bitrates = 1; 716e705c121SKalle Valo mvm->nvm_data->bands[0].bitrates = 717e705c121SKalle Valo (void *)mvm->nvm_data->channels + 1; 718e705c121SKalle Valo mvm->nvm_data->bands[0].bitrates->hw_value = 10; 719e705c121SKalle Valo } 720e705c121SKalle Valo 721e705c121SKalle Valo return ret; 722e705c121SKalle Valo } 723e705c121SKalle Valo 724e705c121SKalle Valo static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) 725e705c121SKalle Valo { 726e705c121SKalle Valo struct iwl_ltr_config_cmd cmd = { 727e705c121SKalle Valo .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), 728e705c121SKalle Valo }; 729e705c121SKalle Valo 730e705c121SKalle Valo if (!mvm->trans->ltr_enabled) 731e705c121SKalle Valo return 0; 732e705c121SKalle Valo 733e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, 734e705c121SKalle Valo sizeof(cmd), &cmd); 735e705c121SKalle Valo } 736e705c121SKalle Valo 737c386dacbSHaim Dreyfuss #ifdef CONFIG_ACPI 73842ce76d6SLuca Coelho int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b) 739da2830acSLuca Coelho { 740216cdfb5SLuca Coelho struct iwl_dev_tx_power_cmd cmd = { 741216cdfb5SLuca Coelho .common.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS), 74271e9378bSLuca Coelho }; 7439c08cef8SLuca Coelho __le16 *per_chain; 7441edd56e6SLuca Coelho int ret; 74539c1a972SIhab Zhaika u16 len = 0; 746fbb7957dSLuca Coelho u32 n_subbands; 747fbb7957dSLuca Coelho u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, LONG_GROUP, 748e80bfd11SMordechay Goodstein REDUCE_TX_POWER_CMD, 749e80bfd11SMordechay Goodstein IWL_FW_CMD_VER_UNKNOWN); 75042ce76d6SLuca Coelho 751fbb7957dSLuca Coelho if (cmd_ver == 6) { 752fbb7957dSLuca Coelho len = sizeof(cmd.v6); 753fbb7957dSLuca Coelho n_subbands = IWL_NUM_SUB_BANDS_V2; 754fbb7957dSLuca Coelho per_chain = cmd.v6.per_chain[0][0]; 755fbb7957dSLuca Coelho } else if (fw_has_api(&mvm->fw->ucode_capa, 7569c08cef8SLuca Coelho IWL_UCODE_TLV_API_REDUCE_TX_POWER)) { 7570791c2fcSHaim Dreyfuss len = sizeof(cmd.v5); 758fbb7957dSLuca Coelho n_subbands = IWL_NUM_SUB_BANDS; 7599c08cef8SLuca Coelho per_chain = cmd.v5.per_chain[0][0]; 7609c08cef8SLuca Coelho } else if (fw_has_capa(&mvm->fw->ucode_capa, 7619c08cef8SLuca Coelho IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) { 762216cdfb5SLuca Coelho len = sizeof(cmd.v4); 763fbb7957dSLuca Coelho n_subbands = IWL_NUM_SUB_BANDS; 7649c08cef8SLuca Coelho per_chain = cmd.v4.per_chain[0][0]; 7659c08cef8SLuca Coelho } else { 766216cdfb5SLuca Coelho len = sizeof(cmd.v3); 767fbb7957dSLuca Coelho n_subbands = IWL_NUM_SUB_BANDS; 7689c08cef8SLuca Coelho per_chain = cmd.v3.per_chain[0][0]; 7699c08cef8SLuca Coelho } 77055bfa4b9SLuca Coelho 771216cdfb5SLuca Coelho /* all structs have the same common part, add it */ 772216cdfb5SLuca Coelho len += sizeof(cmd.common); 77342ce76d6SLuca Coelho 7749c08cef8SLuca Coelho ret = iwl_sar_select_profile(&mvm->fwrt, per_chain, ACPI_SAR_NUM_TABLES, 775fbb7957dSLuca Coelho n_subbands, prof_a, prof_b); 7761edd56e6SLuca Coelho 7771edd56e6SLuca Coelho /* return on error or if the profile is disabled (positive number) */ 7781edd56e6SLuca Coelho if (ret) 7791edd56e6SLuca Coelho return ret; 7801edd56e6SLuca Coelho 78142ce76d6SLuca Coelho IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n"); 78242ce76d6SLuca Coelho return iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd); 78342ce76d6SLuca Coelho } 78442ce76d6SLuca Coelho 7857fe90e0eSHaim Dreyfuss int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) 7867fe90e0eSHaim Dreyfuss { 787dd2a1256SLuca Coelho union iwl_geo_tx_power_profiles_cmd geo_tx_cmd; 788f604324eSLuca Coelho struct iwl_geo_tx_power_profiles_resp *resp; 7890c3d7282SHaim Dreyfuss u16 len; 79039c1a972SIhab Zhaika int ret; 7910c3d7282SHaim Dreyfuss struct iwl_host_cmd cmd; 792e80bfd11SMordechay Goodstein u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP, 793e80bfd11SMordechay Goodstein GEO_TX_POWER_LIMIT, 794e80bfd11SMordechay Goodstein IWL_FW_CMD_VER_UNKNOWN); 7957fe90e0eSHaim Dreyfuss 796dd2a1256SLuca Coelho /* the ops field is at the same spot for all versions, so set in v1 */ 797dd2a1256SLuca Coelho geo_tx_cmd.v1.ops = 798dd2a1256SLuca Coelho cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE); 799dd2a1256SLuca Coelho 8000ea788edSLuca Coelho if (cmd_ver == 3) 8010ea788edSLuca Coelho len = sizeof(geo_tx_cmd.v3); 8020ea788edSLuca Coelho else if (fw_has_api(&mvm->fwrt.fw->ucode_capa, 803dd2a1256SLuca Coelho IWL_UCODE_TLV_API_SAR_TABLE_VER)) 804dd2a1256SLuca Coelho len = sizeof(geo_tx_cmd.v2); 805dd2a1256SLuca Coelho else 806dd2a1256SLuca Coelho len = sizeof(geo_tx_cmd.v1); 8070c3d7282SHaim Dreyfuss 80839c1a972SIhab Zhaika if (!iwl_sar_geo_support(&mvm->fwrt)) 80939c1a972SIhab Zhaika return -EOPNOTSUPP; 81039c1a972SIhab Zhaika 8110c3d7282SHaim Dreyfuss cmd = (struct iwl_host_cmd){ 8127fe90e0eSHaim Dreyfuss .id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT), 8130c3d7282SHaim Dreyfuss .len = { len, }, 8147fe90e0eSHaim Dreyfuss .flags = CMD_WANT_SKB, 81539c1a972SIhab Zhaika .data = { &geo_tx_cmd }, 8167fe90e0eSHaim Dreyfuss }; 8177fe90e0eSHaim Dreyfuss 8187fe90e0eSHaim Dreyfuss ret = iwl_mvm_send_cmd(mvm, &cmd); 8197fe90e0eSHaim Dreyfuss if (ret) { 8207fe90e0eSHaim Dreyfuss IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret); 8217fe90e0eSHaim Dreyfuss return ret; 8227fe90e0eSHaim Dreyfuss } 823f604324eSLuca Coelho 824f604324eSLuca Coelho resp = (void *)cmd.resp_pkt->data; 825f604324eSLuca Coelho ret = le32_to_cpu(resp->profile_idx); 826f604324eSLuca Coelho 827f604324eSLuca Coelho if (WARN_ON(ret > ACPI_NUM_GEO_PROFILES)) 828f604324eSLuca Coelho ret = -EIO; 829f604324eSLuca Coelho 8307fe90e0eSHaim Dreyfuss iwl_free_resp(&cmd); 8317fe90e0eSHaim Dreyfuss return ret; 8327fe90e0eSHaim Dreyfuss } 8337fe90e0eSHaim Dreyfuss 834a6bff3cbSHaim Dreyfuss static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) 835a6bff3cbSHaim Dreyfuss { 836dd2a1256SLuca Coelho union iwl_geo_tx_power_profiles_cmd cmd; 83739c1a972SIhab Zhaika u16 len; 8380433ae55SGolan Ben Ami int ret; 839e80bfd11SMordechay Goodstein u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP, 840e80bfd11SMordechay Goodstein GEO_TX_POWER_LIMIT, 841e80bfd11SMordechay Goodstein IWL_FW_CMD_VER_UNKNOWN); 842a6bff3cbSHaim Dreyfuss 843dd2a1256SLuca Coelho /* the table is also at the same position both in v1 and v2 */ 8440ea788edSLuca Coelho ret = iwl_sar_geo_init(&mvm->fwrt, &cmd.v1.table[0][0], 8450ea788edSLuca Coelho ACPI_WGDS_NUM_BANDS); 846eca1e56cSEmmanuel Grumbach 8470433ae55SGolan Ben Ami /* 8480433ae55SGolan Ben Ami * It is a valid scenario to not support SAR, or miss wgds table, 8490433ae55SGolan Ben Ami * but in that case there is no need to send the command. 8500433ae55SGolan Ben Ami */ 8510433ae55SGolan Ben Ami if (ret) 8520433ae55SGolan Ben Ami return 0; 853a6bff3cbSHaim Dreyfuss 854dd2a1256SLuca Coelho /* the ops field is at the same spot for all versions, so set in v1 */ 855dd2a1256SLuca Coelho cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES); 856a6bff3cbSHaim Dreyfuss 8570ea788edSLuca Coelho if (cmd_ver == 3) { 8580ea788edSLuca Coelho len = sizeof(cmd.v3); 8590ea788edSLuca Coelho cmd.v3.table_revision = cpu_to_le32(mvm->fwrt.geo_rev); 8600ea788edSLuca Coelho } else if (fw_has_api(&mvm->fwrt.fw->ucode_capa, 8610c3d7282SHaim Dreyfuss IWL_UCODE_TLV_API_SAR_TABLE_VER)) { 862dd2a1256SLuca Coelho len = sizeof(cmd.v2); 863dd2a1256SLuca Coelho cmd.v2.table_revision = cpu_to_le32(mvm->fwrt.geo_rev); 86439c1a972SIhab Zhaika } else { 865dd2a1256SLuca Coelho len = sizeof(cmd.v1); 8660c3d7282SHaim Dreyfuss } 8670c3d7282SHaim Dreyfuss 868dd2a1256SLuca Coelho return iwl_mvm_send_cmd_pdu(mvm, 869dd2a1256SLuca Coelho WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT), 870dd2a1256SLuca Coelho 0, len, &cmd); 871a6bff3cbSHaim Dreyfuss } 872a6bff3cbSHaim Dreyfuss 8736ce1e5c0SGil Adam static int iwl_mvm_get_ppag_table(struct iwl_mvm *mvm) 8746ce1e5c0SGil Adam { 8756ce1e5c0SGil Adam union acpi_object *wifi_pkg, *data, *enabled; 876f2134f66SGil Adam union iwl_ppag_table_cmd ppag_table; 877f2134f66SGil Adam int i, j, ret, tbl_rev, num_sub_bands; 8786ce1e5c0SGil Adam int idx = 2; 879f2134f66SGil Adam s8 *gain; 8806ce1e5c0SGil Adam 881f2134f66SGil Adam /* 882f2134f66SGil Adam * The 'enabled' field is the same in v1 and v2 so we can just 883f2134f66SGil Adam * use v1 to access it. 884f2134f66SGil Adam */ 885f2134f66SGil Adam mvm->fwrt.ppag_table.v1.enabled = cpu_to_le32(0); 8866ce1e5c0SGil Adam data = iwl_acpi_get_object(mvm->dev, ACPI_PPAG_METHOD); 8876ce1e5c0SGil Adam if (IS_ERR(data)) 8886ce1e5c0SGil Adam return PTR_ERR(data); 8896ce1e5c0SGil Adam 890f2134f66SGil Adam /* try to read ppag table revision 1 */ 8916ce1e5c0SGil Adam wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data, 892f2134f66SGil Adam ACPI_PPAG_WIFI_DATA_SIZE_V2, &tbl_rev); 893f2134f66SGil Adam if (!IS_ERR(wifi_pkg)) { 894f2134f66SGil Adam if (tbl_rev != 1) { 895f2134f66SGil Adam ret = -EINVAL; 8966ce1e5c0SGil Adam goto out_free; 8976ce1e5c0SGil Adam } 898f2134f66SGil Adam num_sub_bands = IWL_NUM_SUB_BANDS_V2; 899f2134f66SGil Adam gain = mvm->fwrt.ppag_table.v2.gain[0]; 900f2134f66SGil Adam mvm->fwrt.ppag_ver = 2; 901f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, "Reading PPAG table v2 (tbl_rev=1)\n"); 902f2134f66SGil Adam goto read_table; 903f2134f66SGil Adam } 9046ce1e5c0SGil Adam 905f2134f66SGil Adam /* try to read ppag table revision 0 */ 906f2134f66SGil Adam wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data, 907f2134f66SGil Adam ACPI_PPAG_WIFI_DATA_SIZE, &tbl_rev); 908f2134f66SGil Adam if (!IS_ERR(wifi_pkg)) { 9093ed83da3SLuca Coelho if (tbl_rev != 0) { 9103ed83da3SLuca Coelho ret = -EINVAL; 9113ed83da3SLuca Coelho goto out_free; 9123ed83da3SLuca Coelho } 913f2134f66SGil Adam num_sub_bands = IWL_NUM_SUB_BANDS; 914f2134f66SGil Adam gain = mvm->fwrt.ppag_table.v1.gain[0]; 915f2134f66SGil Adam mvm->fwrt.ppag_ver = 1; 916f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, "Reading PPAG table v1 (tbl_rev=0)\n"); 917f2134f66SGil Adam goto read_table; 918f2134f66SGil Adam } 919f2134f66SGil Adam ret = PTR_ERR(wifi_pkg); 920f2134f66SGil Adam goto out_free; 9213ed83da3SLuca Coelho 922f2134f66SGil Adam read_table: 9236ce1e5c0SGil Adam enabled = &wifi_pkg->package.elements[1]; 9246ce1e5c0SGil Adam if (enabled->type != ACPI_TYPE_INTEGER || 9256ce1e5c0SGil Adam (enabled->integer.value != 0 && enabled->integer.value != 1)) { 9266ce1e5c0SGil Adam ret = -EINVAL; 9276ce1e5c0SGil Adam goto out_free; 9286ce1e5c0SGil Adam } 9296ce1e5c0SGil Adam 930f2134f66SGil Adam ppag_table.v1.enabled = cpu_to_le32(enabled->integer.value); 931f2134f66SGil Adam if (!ppag_table.v1.enabled) { 9326ce1e5c0SGil Adam ret = 0; 9336ce1e5c0SGil Adam goto out_free; 9346ce1e5c0SGil Adam } 9356ce1e5c0SGil Adam 9366ce1e5c0SGil Adam /* 9376ce1e5c0SGil Adam * read, verify gain values and save them into the PPAG table. 9386ce1e5c0SGil Adam * first sub-band (j=0) corresponds to Low-Band (2.4GHz), and the 9396ce1e5c0SGil Adam * following sub-bands to High-Band (5GHz). 9406ce1e5c0SGil Adam */ 941f2134f66SGil Adam for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) { 942f2134f66SGil Adam for (j = 0; j < num_sub_bands; j++) { 9436ce1e5c0SGil Adam union acpi_object *ent; 9446ce1e5c0SGil Adam 9456ce1e5c0SGil Adam ent = &wifi_pkg->package.elements[idx++]; 9466ce1e5c0SGil Adam if (ent->type != ACPI_TYPE_INTEGER || 9476ce1e5c0SGil Adam (j == 0 && ent->integer.value > ACPI_PPAG_MAX_LB) || 9486ce1e5c0SGil Adam (j == 0 && ent->integer.value < ACPI_PPAG_MIN_LB) || 9496ce1e5c0SGil Adam (j != 0 && ent->integer.value > ACPI_PPAG_MAX_HB) || 9506ce1e5c0SGil Adam (j != 0 && ent->integer.value < ACPI_PPAG_MIN_HB)) { 951f2134f66SGil Adam ppag_table.v1.enabled = cpu_to_le32(0); 9526ce1e5c0SGil Adam ret = -EINVAL; 9536ce1e5c0SGil Adam goto out_free; 9546ce1e5c0SGil Adam } 955f2134f66SGil Adam gain[i * num_sub_bands + j] = ent->integer.value; 9566ce1e5c0SGil Adam } 9576ce1e5c0SGil Adam } 9586ce1e5c0SGil Adam ret = 0; 9596ce1e5c0SGil Adam out_free: 9606ce1e5c0SGil Adam kfree(data); 9616ce1e5c0SGil Adam return ret; 9626ce1e5c0SGil Adam } 9636ce1e5c0SGil Adam 9646ce1e5c0SGil Adam int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) 9656ce1e5c0SGil Adam { 966f2134f66SGil Adam u8 cmd_ver; 967f2134f66SGil Adam int i, j, ret, num_sub_bands, cmd_size; 968f2134f66SGil Adam union iwl_ppag_table_cmd ppag_table; 969f2134f66SGil Adam s8 *gain; 9706ce1e5c0SGil Adam 9716ce1e5c0SGil Adam if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) { 9726ce1e5c0SGil Adam IWL_DEBUG_RADIO(mvm, 9736ce1e5c0SGil Adam "PPAG capability not supported by FW, command not sent.\n"); 9746ce1e5c0SGil Adam return 0; 9756ce1e5c0SGil Adam } 976f2134f66SGil Adam if (!mvm->fwrt.ppag_table.v1.enabled) { 977f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, "PPAG not enabled, command not sent.\n"); 978160bab43SGil Adam return 0; 979160bab43SGil Adam } 980160bab43SGil Adam 981f2134f66SGil Adam cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP, 982e80bfd11SMordechay Goodstein PER_PLATFORM_ANT_GAIN_CMD, 983e80bfd11SMordechay Goodstein IWL_FW_CMD_VER_UNKNOWN); 984f2134f66SGil Adam if (cmd_ver == 1) { 985f2134f66SGil Adam num_sub_bands = IWL_NUM_SUB_BANDS; 986f2134f66SGil Adam gain = mvm->fwrt.ppag_table.v1.gain[0]; 987f2134f66SGil Adam cmd_size = sizeof(ppag_table.v1); 988f2134f66SGil Adam if (mvm->fwrt.ppag_ver == 2) { 989f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, 990f2134f66SGil Adam "PPAG table is v2 but FW supports v1, sending truncated table\n"); 991f2134f66SGil Adam } 992f2134f66SGil Adam } else if (cmd_ver == 2) { 993f2134f66SGil Adam num_sub_bands = IWL_NUM_SUB_BANDS_V2; 994f2134f66SGil Adam gain = mvm->fwrt.ppag_table.v2.gain[0]; 995f2134f66SGil Adam cmd_size = sizeof(ppag_table.v2); 996f2134f66SGil Adam if (mvm->fwrt.ppag_ver == 1) { 997f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, 998f2134f66SGil Adam "PPAG table is v1 but FW supports v2, sending padded table\n"); 999f2134f66SGil Adam } 1000f2134f66SGil Adam } else { 1001f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, "Unsupported PPAG command version\n"); 1002f2134f66SGil Adam return 0; 1003f2134f66SGil Adam } 10046ce1e5c0SGil Adam 1005f2134f66SGil Adam for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) { 1006f2134f66SGil Adam for (j = 0; j < num_sub_bands; j++) { 10076ce1e5c0SGil Adam IWL_DEBUG_RADIO(mvm, 10086ce1e5c0SGil Adam "PPAG table: chain[%d] band[%d]: gain = %d\n", 1009f2134f66SGil Adam i, j, gain[i * num_sub_bands + j]); 10106ce1e5c0SGil Adam } 10116ce1e5c0SGil Adam } 1012f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n"); 10136ce1e5c0SGil Adam ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP, 10146ce1e5c0SGil Adam PER_PLATFORM_ANT_GAIN_CMD), 1015f2134f66SGil Adam 0, cmd_size, &ppag_table); 10166ce1e5c0SGil Adam if (ret < 0) 10176ce1e5c0SGil Adam IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n", 10186ce1e5c0SGil Adam ret); 10196ce1e5c0SGil Adam 10206ce1e5c0SGil Adam return ret; 10216ce1e5c0SGil Adam } 10226ce1e5c0SGil Adam 10236ce1e5c0SGil Adam static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) 10246ce1e5c0SGil Adam { 10256ce1e5c0SGil Adam int ret; 10266ce1e5c0SGil Adam 10276ce1e5c0SGil Adam ret = iwl_mvm_get_ppag_table(mvm); 10286ce1e5c0SGil Adam if (ret < 0) { 10296ce1e5c0SGil Adam IWL_DEBUG_RADIO(mvm, 10306ce1e5c0SGil Adam "PPAG BIOS table invalid or unavailable. (%d)\n", 10316ce1e5c0SGil Adam ret); 10326ce1e5c0SGil Adam return 0; 10336ce1e5c0SGil Adam } 10346ce1e5c0SGil Adam return iwl_mvm_ppag_send_cmd(mvm); 10356ce1e5c0SGil Adam } 10366ce1e5c0SGil Adam 103728dd7ccdSMordechay Goodstein static void iwl_mvm_tas_init(struct iwl_mvm *mvm) 103828dd7ccdSMordechay Goodstein { 103928dd7ccdSMordechay Goodstein int ret; 104028dd7ccdSMordechay Goodstein struct iwl_tas_config_cmd cmd = {}; 104128dd7ccdSMordechay Goodstein int list_size; 104228dd7ccdSMordechay Goodstein 104328dd7ccdSMordechay Goodstein BUILD_BUG_ON(ARRAY_SIZE(cmd.black_list_array) < 104428dd7ccdSMordechay Goodstein APCI_WTAS_BLACK_LIST_MAX); 104528dd7ccdSMordechay Goodstein 104628dd7ccdSMordechay Goodstein if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) { 104728dd7ccdSMordechay Goodstein IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n"); 104828dd7ccdSMordechay Goodstein return; 104928dd7ccdSMordechay Goodstein } 105028dd7ccdSMordechay Goodstein 105128dd7ccdSMordechay Goodstein ret = iwl_acpi_get_tas(&mvm->fwrt, cmd.black_list_array, &list_size); 105228dd7ccdSMordechay Goodstein if (ret < 0) { 105328dd7ccdSMordechay Goodstein IWL_DEBUG_RADIO(mvm, 105428dd7ccdSMordechay Goodstein "TAS table invalid or unavailable. (%d)\n", 105528dd7ccdSMordechay Goodstein ret); 105628dd7ccdSMordechay Goodstein return; 105728dd7ccdSMordechay Goodstein } 105828dd7ccdSMordechay Goodstein 105928dd7ccdSMordechay Goodstein if (list_size < 0) 106028dd7ccdSMordechay Goodstein return; 106128dd7ccdSMordechay Goodstein 106228dd7ccdSMordechay Goodstein /* list size if TAS enabled can only be non-negative */ 106328dd7ccdSMordechay Goodstein cmd.black_list_size = cpu_to_le32((u32)list_size); 106428dd7ccdSMordechay Goodstein 106528dd7ccdSMordechay Goodstein ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP, 106628dd7ccdSMordechay Goodstein TAS_CONFIG), 106728dd7ccdSMordechay Goodstein 0, sizeof(cmd), &cmd); 106828dd7ccdSMordechay Goodstein if (ret < 0) 106928dd7ccdSMordechay Goodstein IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret); 107028dd7ccdSMordechay Goodstein } 1071f5b1cb2eSGil Adam 107202d31e9bSGil Adam static u8 iwl_mvm_eval_dsm_indonesia_5g2(struct iwl_mvm *mvm) 1073f5b1cb2eSGil Adam { 1074f5b1cb2eSGil Adam int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0, 1075f5b1cb2eSGil Adam DSM_FUNC_ENABLE_INDONESIA_5G2); 1076f5b1cb2eSGil Adam 107702d31e9bSGil Adam if (ret < 0) 1078f5b1cb2eSGil Adam IWL_DEBUG_RADIO(mvm, 107902d31e9bSGil Adam "Failed to evaluate DSM function ENABLE_INDONESIA_5G2, ret=%d\n", 1080f5b1cb2eSGil Adam ret); 1081f5b1cb2eSGil Adam 108202d31e9bSGil Adam else if (ret >= DSM_VALUE_INDONESIA_MAX) 108302d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 108402d31e9bSGil Adam "DSM function ENABLE_INDONESIA_5G2 return invalid value, ret=%d\n", 108502d31e9bSGil Adam ret); 108602d31e9bSGil Adam 108702d31e9bSGil Adam else if (ret == DSM_VALUE_INDONESIA_ENABLE) { 108802d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 108902d31e9bSGil Adam "Evaluated DSM function ENABLE_INDONESIA_5G2: Enabling 5g2\n"); 109002d31e9bSGil Adam return DSM_VALUE_INDONESIA_ENABLE; 109102d31e9bSGil Adam } 109202d31e9bSGil Adam /* default behaviour is disabled */ 109302d31e9bSGil Adam return DSM_VALUE_INDONESIA_DISABLE; 109402d31e9bSGil Adam } 109502d31e9bSGil Adam 109602d31e9bSGil Adam static u8 iwl_mvm_eval_dsm_disable_srd(struct iwl_mvm *mvm) 109702d31e9bSGil Adam { 109802d31e9bSGil Adam int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0, 109902d31e9bSGil Adam DSM_FUNC_DISABLE_SRD); 110002d31e9bSGil Adam 110102d31e9bSGil Adam if (ret < 0) 110202d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 110302d31e9bSGil Adam "Failed to evaluate DSM function DISABLE_SRD, ret=%d\n", 110402d31e9bSGil Adam ret); 110502d31e9bSGil Adam 110602d31e9bSGil Adam else if (ret >= DSM_VALUE_SRD_MAX) 110702d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 110802d31e9bSGil Adam "DSM function DISABLE_SRD return invalid value, ret=%d\n", 110902d31e9bSGil Adam ret); 111002d31e9bSGil Adam 111102d31e9bSGil Adam else if (ret == DSM_VALUE_SRD_PASSIVE) { 111202d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 111302d31e9bSGil Adam "Evaluated DSM function DISABLE_SRD: setting SRD to passive\n"); 111402d31e9bSGil Adam return DSM_VALUE_SRD_PASSIVE; 111502d31e9bSGil Adam 111602d31e9bSGil Adam } else if (ret == DSM_VALUE_SRD_DISABLE) { 111702d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 111802d31e9bSGil Adam "Evaluated DSM function DISABLE_SRD: disabling SRD\n"); 111902d31e9bSGil Adam return DSM_VALUE_SRD_DISABLE; 112002d31e9bSGil Adam } 112102d31e9bSGil Adam /* default behaviour is active */ 112202d31e9bSGil Adam return DSM_VALUE_SRD_ACTIVE; 1123f5b1cb2eSGil Adam } 1124f5b1cb2eSGil Adam 1125f5b1cb2eSGil Adam static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm) 1126f5b1cb2eSGil Adam { 112702d31e9bSGil Adam u8 ret; 112802d31e9bSGil Adam int cmd_ret; 1129f5b1cb2eSGil Adam struct iwl_lari_config_change_cmd cmd = {}; 1130f5b1cb2eSGil Adam 113102d31e9bSGil Adam if (iwl_mvm_eval_dsm_indonesia_5g2(mvm) == DSM_VALUE_INDONESIA_ENABLE) 1132f5b1cb2eSGil Adam cmd.config_bitmap |= 1133f5b1cb2eSGil Adam cpu_to_le32(LARI_CONFIG_ENABLE_5G2_IN_INDONESIA_MSK); 1134f5b1cb2eSGil Adam 113502d31e9bSGil Adam ret = iwl_mvm_eval_dsm_disable_srd(mvm); 113602d31e9bSGil Adam if (ret == DSM_VALUE_SRD_PASSIVE) 113702d31e9bSGil Adam cmd.config_bitmap |= 113802d31e9bSGil Adam cpu_to_le32(LARI_CONFIG_CHANGE_ETSI_TO_PASSIVE_MSK); 113902d31e9bSGil Adam 114002d31e9bSGil Adam else if (ret == DSM_VALUE_SRD_DISABLE) 114102d31e9bSGil Adam cmd.config_bitmap |= 114202d31e9bSGil Adam cpu_to_le32(LARI_CONFIG_CHANGE_ETSI_TO_DISABLED_MSK); 114302d31e9bSGil Adam 1144f5b1cb2eSGil Adam /* apply more config masks here */ 1145f5b1cb2eSGil Adam 1146f5b1cb2eSGil Adam if (cmd.config_bitmap) { 114702d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, "sending LARI_CONFIG_CHANGE\n"); 114802d31e9bSGil Adam cmd_ret = iwl_mvm_send_cmd_pdu(mvm, 1149f5b1cb2eSGil Adam WIDE_ID(REGULATORY_AND_NVM_GROUP, 1150f5b1cb2eSGil Adam LARI_CONFIG_CHANGE), 1151f5b1cb2eSGil Adam 0, sizeof(cmd), &cmd); 115202d31e9bSGil Adam if (cmd_ret < 0) 1153f5b1cb2eSGil Adam IWL_DEBUG_RADIO(mvm, 1154f5b1cb2eSGil Adam "Failed to send LARI_CONFIG_CHANGE (%d)\n", 115502d31e9bSGil Adam cmd_ret); 1156f5b1cb2eSGil Adam } 1157f5b1cb2eSGil Adam } 115869964905SLuca Coelho #else /* CONFIG_ACPI */ 115939c1a972SIhab Zhaika 116039c1a972SIhab Zhaika inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, 116139c1a972SIhab Zhaika int prof_a, int prof_b) 116269964905SLuca Coelho { 116369964905SLuca Coelho return -ENOENT; 116469964905SLuca Coelho } 116569964905SLuca Coelho 116639c1a972SIhab Zhaika inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) 11675d041c46SLuca Coelho { 11685d041c46SLuca Coelho return -ENOENT; 11695d041c46SLuca Coelho } 11705d041c46SLuca Coelho 1171a6bff3cbSHaim Dreyfuss static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) 1172a6bff3cbSHaim Dreyfuss { 1173a6bff3cbSHaim Dreyfuss return 0; 1174a6bff3cbSHaim Dreyfuss } 117518f1755dSLuca Coelho 11766ce1e5c0SGil Adam int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) 11776ce1e5c0SGil Adam { 11786ce1e5c0SGil Adam return -ENOENT; 11796ce1e5c0SGil Adam } 11806ce1e5c0SGil Adam 11816ce1e5c0SGil Adam static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) 11826ce1e5c0SGil Adam { 11837937fd32SJohannes Berg return 0; 11846ce1e5c0SGil Adam } 118528dd7ccdSMordechay Goodstein 118628dd7ccdSMordechay Goodstein static void iwl_mvm_tas_init(struct iwl_mvm *mvm) 118728dd7ccdSMordechay Goodstein { 118828dd7ccdSMordechay Goodstein } 1189f5b1cb2eSGil Adam 1190f5b1cb2eSGil Adam static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm) 1191f5b1cb2eSGil Adam { 1192f5b1cb2eSGil Adam } 119369964905SLuca Coelho #endif /* CONFIG_ACPI */ 119469964905SLuca Coelho 1195f130bb75SMordechay Goodstein void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags) 1196f130bb75SMordechay Goodstein { 1197f130bb75SMordechay Goodstein u32 error_log_size = mvm->fw->ucode_capa.error_log_size; 1198f130bb75SMordechay Goodstein int ret; 1199f130bb75SMordechay Goodstein u32 resp; 1200f130bb75SMordechay Goodstein 1201f130bb75SMordechay Goodstein struct iwl_fw_error_recovery_cmd recovery_cmd = { 1202f130bb75SMordechay Goodstein .flags = cpu_to_le32(flags), 1203f130bb75SMordechay Goodstein .buf_size = 0, 1204f130bb75SMordechay Goodstein }; 1205f130bb75SMordechay Goodstein struct iwl_host_cmd host_cmd = { 1206f130bb75SMordechay Goodstein .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD), 1207f130bb75SMordechay Goodstein .flags = CMD_WANT_SKB, 1208f130bb75SMordechay Goodstein .data = {&recovery_cmd, }, 1209f130bb75SMordechay Goodstein .len = {sizeof(recovery_cmd), }, 1210f130bb75SMordechay Goodstein }; 1211f130bb75SMordechay Goodstein 1212f130bb75SMordechay Goodstein /* no error log was defined in TLV */ 1213f130bb75SMordechay Goodstein if (!error_log_size) 1214f130bb75SMordechay Goodstein return; 1215f130bb75SMordechay Goodstein 1216f130bb75SMordechay Goodstein if (flags & ERROR_RECOVERY_UPDATE_DB) { 1217f130bb75SMordechay Goodstein /* no buf was allocated while HW reset */ 1218f130bb75SMordechay Goodstein if (!mvm->error_recovery_buf) 1219f130bb75SMordechay Goodstein return; 1220f130bb75SMordechay Goodstein 1221f130bb75SMordechay Goodstein host_cmd.data[1] = mvm->error_recovery_buf; 1222f130bb75SMordechay Goodstein host_cmd.len[1] = error_log_size; 1223f130bb75SMordechay Goodstein host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY; 1224f130bb75SMordechay Goodstein recovery_cmd.buf_size = cpu_to_le32(error_log_size); 1225f130bb75SMordechay Goodstein } 1226f130bb75SMordechay Goodstein 1227f130bb75SMordechay Goodstein ret = iwl_mvm_send_cmd(mvm, &host_cmd); 1228f130bb75SMordechay Goodstein kfree(mvm->error_recovery_buf); 1229f130bb75SMordechay Goodstein mvm->error_recovery_buf = NULL; 1230f130bb75SMordechay Goodstein 1231f130bb75SMordechay Goodstein if (ret) { 1232f130bb75SMordechay Goodstein IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret); 1233f130bb75SMordechay Goodstein return; 1234f130bb75SMordechay Goodstein } 1235f130bb75SMordechay Goodstein 1236f130bb75SMordechay Goodstein /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */ 1237f130bb75SMordechay Goodstein if (flags & ERROR_RECOVERY_UPDATE_DB) { 1238f130bb75SMordechay Goodstein resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data); 1239f130bb75SMordechay Goodstein if (resp) 1240f130bb75SMordechay Goodstein IWL_ERR(mvm, 1241f130bb75SMordechay Goodstein "Failed to send recovery cmd blob was invalid %d\n", 1242f130bb75SMordechay Goodstein resp); 1243f130bb75SMordechay Goodstein } 1244f130bb75SMordechay Goodstein } 1245f130bb75SMordechay Goodstein 124642ce76d6SLuca Coelho static int iwl_mvm_sar_init(struct iwl_mvm *mvm) 124742ce76d6SLuca Coelho { 124842ce76d6SLuca Coelho int ret; 124942ce76d6SLuca Coelho 125039c1a972SIhab Zhaika ret = iwl_sar_get_wrds_table(&mvm->fwrt); 1251da2830acSLuca Coelho if (ret < 0) { 1252da2830acSLuca Coelho IWL_DEBUG_RADIO(mvm, 125369964905SLuca Coelho "WRDS SAR BIOS table invalid or unavailable. (%d)\n", 1254da2830acSLuca Coelho ret); 12555d041c46SLuca Coelho /* 12565d041c46SLuca Coelho * If not available, don't fail and don't bother with EWRD. 12575d041c46SLuca Coelho * Return 1 to tell that we can't use WGDS either. 12585d041c46SLuca Coelho */ 12595d041c46SLuca Coelho return 1; 1260da2830acSLuca Coelho } 1261da2830acSLuca Coelho 126239c1a972SIhab Zhaika ret = iwl_sar_get_ewrd_table(&mvm->fwrt); 126369964905SLuca Coelho /* if EWRD is not available, we can still use WRDS, so don't fail */ 126469964905SLuca Coelho if (ret < 0) 126569964905SLuca Coelho IWL_DEBUG_RADIO(mvm, 126669964905SLuca Coelho "EWRD SAR BIOS table invalid or unavailable. (%d)\n", 126769964905SLuca Coelho ret); 126869964905SLuca Coelho 12691edd56e6SLuca Coelho return iwl_mvm_sar_select_profile(mvm, 1, 1); 1270da2830acSLuca Coelho } 1271da2830acSLuca Coelho 12721f370650SSara Sharon static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm) 12731f370650SSara Sharon { 12741f370650SSara Sharon int ret; 12751f370650SSara Sharon 12767d6222e2SJohannes Berg if (iwl_mvm_has_unified_ucode(mvm)) 12771f370650SSara Sharon return iwl_run_unified_mvm_ucode(mvm, false); 12781f370650SSara Sharon 12791f370650SSara Sharon ret = iwl_run_init_mvm_ucode(mvm, false); 12801f370650SSara Sharon 12811f370650SSara Sharon if (ret) { 12821f370650SSara Sharon IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); 1283f4744258SLiad Kaufman 1284f4744258SLiad Kaufman if (iwlmvm_mod_params.init_dbg) 1285f4744258SLiad Kaufman return 0; 12861f370650SSara Sharon return ret; 12871f370650SSara Sharon } 12881f370650SSara Sharon 1289203c83d3SShahar S Matityahu iwl_fw_dbg_stop_sync(&mvm->fwrt); 1290bab3cb92SEmmanuel Grumbach iwl_trans_stop_device(mvm->trans); 1291bab3cb92SEmmanuel Grumbach ret = iwl_trans_start_hw(mvm->trans); 12921f370650SSara Sharon if (ret) 12931f370650SSara Sharon return ret; 12941f370650SSara Sharon 1295b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); 1296da2eb669SSara Sharon 129794022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 12981f370650SSara Sharon ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); 12991f370650SSara Sharon if (ret) 13001f370650SSara Sharon return ret; 13011f370650SSara Sharon 130294022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = true; 130394022562SEmmanuel Grumbach 1304b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, 1305b108d8c7SShahar S Matityahu NULL); 1306da2eb669SSara Sharon 1307702e975dSJohannes Berg return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img); 13081f370650SSara Sharon } 13091f370650SSara Sharon 1310e705c121SKalle Valo int iwl_mvm_up(struct iwl_mvm *mvm) 1311e705c121SKalle Valo { 1312e705c121SKalle Valo int ret, i; 1313e705c121SKalle Valo struct ieee80211_channel *chan; 1314e705c121SKalle Valo struct cfg80211_chan_def chandef; 1315dd36a507STova Mussai struct ieee80211_supported_band *sband = NULL; 1316e705c121SKalle Valo 1317e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 1318e705c121SKalle Valo 1319e705c121SKalle Valo ret = iwl_trans_start_hw(mvm->trans); 1320e705c121SKalle Valo if (ret) 1321e705c121SKalle Valo return ret; 1322e705c121SKalle Valo 13231f370650SSara Sharon ret = iwl_mvm_load_rt_fw(mvm); 1324e705c121SKalle Valo if (ret) { 1325e705c121SKalle Valo IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); 132672d3c7bbSJohannes Berg if (ret != -ERFKILL) 132772d3c7bbSJohannes Berg iwl_fw_dbg_error_collect(&mvm->fwrt, 132872d3c7bbSJohannes Berg FW_DBG_TRIGGER_DRIVER); 1329e705c121SKalle Valo goto error; 1330e705c121SKalle Valo } 1331e705c121SKalle Valo 1332d0b813fcSJohannes Berg iwl_get_shared_mem_conf(&mvm->fwrt); 1333e705c121SKalle Valo 1334e705c121SKalle Valo ret = iwl_mvm_sf_update(mvm, NULL, false); 1335e705c121SKalle Valo if (ret) 1336e705c121SKalle Valo IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); 1337e705c121SKalle Valo 1338a1af4c48SShahar S Matityahu if (!iwl_trans_dbg_ini_valid(mvm->trans)) { 13397174beb6SJohannes Berg mvm->fwrt.dump.conf = FW_DBG_INVALID; 1340e705c121SKalle Valo /* if we have a destination, assume EARLY START */ 134117b809c9SSara Sharon if (mvm->fw->dbg.dest_tlv) 13427174beb6SJohannes Berg mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE; 13437174beb6SJohannes Berg iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE); 13447a14c23dSSara Sharon } 1345e705c121SKalle Valo 1346e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 1347e705c121SKalle Valo if (ret) 1348e705c121SKalle Valo goto error; 1349e705c121SKalle Valo 13507d6222e2SJohannes Berg if (!iwl_mvm_has_unified_ucode(mvm)) { 1351e705c121SKalle Valo /* Send phy db control command and then phy db calibration */ 1352e705c121SKalle Valo ret = iwl_send_phy_db_data(mvm->phy_db); 1353e705c121SKalle Valo if (ret) 1354e705c121SKalle Valo goto error; 1355bb99ff9bSLuca Coelho } 1356e705c121SKalle Valo 1357e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 1358e705c121SKalle Valo if (ret) 1359e705c121SKalle Valo goto error; 1360e705c121SKalle Valo 1361b3de3ef4SEmmanuel Grumbach ret = iwl_mvm_send_bt_init_conf(mvm); 1362b3de3ef4SEmmanuel Grumbach if (ret) 1363b3de3ef4SEmmanuel Grumbach goto error; 1364b3de3ef4SEmmanuel Grumbach 1365cceb4507SShahar S Matityahu if (fw_has_capa(&mvm->fw->ucode_capa, 1366cceb4507SShahar S Matityahu IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) { 1367a8eb340fSEmmanuel Grumbach ret = iwl_set_soc_latency(&mvm->fwrt); 1368cceb4507SShahar S Matityahu if (ret) 1369cceb4507SShahar S Matityahu goto error; 1370cceb4507SShahar S Matityahu } 1371cceb4507SShahar S Matityahu 137243413a97SSara Sharon /* Init RSS configuration */ 1373286ca8ebSLuca Coelho if (mvm->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) { 13748edbfaa1SSara Sharon ret = iwl_configure_rxq(mvm); 13758edbfaa1SSara Sharon if (ret) { 13768edbfaa1SSara Sharon IWL_ERR(mvm, "Failed to configure RX queues: %d\n", 13778edbfaa1SSara Sharon ret); 13788edbfaa1SSara Sharon goto error; 13798edbfaa1SSara Sharon } 13808edbfaa1SSara Sharon } 13818edbfaa1SSara Sharon 13828edbfaa1SSara Sharon if (iwl_mvm_has_new_rx_api(mvm)) { 138343413a97SSara Sharon ret = iwl_send_rss_cfg_cmd(mvm); 138443413a97SSara Sharon if (ret) { 138543413a97SSara Sharon IWL_ERR(mvm, "Failed to configure RSS queues: %d\n", 138643413a97SSara Sharon ret); 138743413a97SSara Sharon goto error; 138843413a97SSara Sharon } 138943413a97SSara Sharon } 139043413a97SSara Sharon 1391e705c121SKalle Valo /* init the fw <-> mac80211 STA mapping */ 13920ae98812SSara Sharon for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++) 1393e705c121SKalle Valo RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); 1394e705c121SKalle Valo 13950ae98812SSara Sharon mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA; 1396e705c121SKalle Valo 1397e705c121SKalle Valo /* reset quota debouncing buffer - 0xff will yield invalid data */ 1398e705c121SKalle Valo memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); 1399e705c121SKalle Valo 140079660869SIlia Lin if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) { 140197d5be7eSLiad Kaufman ret = iwl_mvm_send_dqa_cmd(mvm); 140297d5be7eSLiad Kaufman if (ret) 140397d5be7eSLiad Kaufman goto error; 140479660869SIlia Lin } 140597d5be7eSLiad Kaufman 1406e705c121SKalle Valo /* Add auxiliary station for scanning */ 1407e705c121SKalle Valo ret = iwl_mvm_add_aux_sta(mvm); 1408e705c121SKalle Valo if (ret) 1409e705c121SKalle Valo goto error; 1410e705c121SKalle Valo 1411e705c121SKalle Valo /* Add all the PHY contexts */ 1412dd36a507STova Mussai i = 0; 1413dd36a507STova Mussai while (!sband && i < NUM_NL80211_BANDS) 1414dd36a507STova Mussai sband = mvm->hw->wiphy->bands[i++]; 1415dd36a507STova Mussai 1416dd36a507STova Mussai if (WARN_ON_ONCE(!sband)) 1417dd36a507STova Mussai goto error; 1418dd36a507STova Mussai 1419dd36a507STova Mussai chan = &sband->channels[0]; 1420dd36a507STova Mussai 1421e705c121SKalle Valo cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); 1422e705c121SKalle Valo for (i = 0; i < NUM_PHY_CTX; i++) { 1423e705c121SKalle Valo /* 1424e705c121SKalle Valo * The channel used here isn't relevant as it's 1425e705c121SKalle Valo * going to be overwritten in the other flows. 1426e705c121SKalle Valo * For now use the first channel we have. 1427e705c121SKalle Valo */ 1428e705c121SKalle Valo ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], 1429e705c121SKalle Valo &chandef, 1, 1); 1430e705c121SKalle Valo if (ret) 1431e705c121SKalle Valo goto error; 1432e705c121SKalle Valo } 1433e705c121SKalle Valo 1434c221daf2SChaya Rachel Ivgi if (iwl_mvm_is_tt_in_fw(mvm)) { 1435c221daf2SChaya Rachel Ivgi /* in order to give the responsibility of ct-kill and 1436c221daf2SChaya Rachel Ivgi * TX backoff to FW we need to send empty temperature reporting 1437c221daf2SChaya Rachel Ivgi * cmd during init time 1438c221daf2SChaya Rachel Ivgi */ 1439c221daf2SChaya Rachel Ivgi iwl_mvm_send_temp_report_ths_cmd(mvm); 1440c221daf2SChaya Rachel Ivgi } else { 1441e705c121SKalle Valo /* Initialize tx backoffs to the minimal possible */ 1442e705c121SKalle Valo iwl_mvm_tt_tx_backoff(mvm, 0); 1443c221daf2SChaya Rachel Ivgi } 14445c89e7bcSChaya Rachel Ivgi 1445242d9c8bSJohannes Berg #ifdef CONFIG_THERMAL 14465c89e7bcSChaya Rachel Ivgi /* TODO: read the budget from BIOS / Platform NVM */ 1447944eafc2SChaya Rachel Ivgi 1448944eafc2SChaya Rachel Ivgi /* 1449944eafc2SChaya Rachel Ivgi * In case there is no budget from BIOS / Platform NVM the default 1450944eafc2SChaya Rachel Ivgi * budget should be 2000mW (cooling state 0). 1451944eafc2SChaya Rachel Ivgi */ 1452944eafc2SChaya Rachel Ivgi if (iwl_mvm_is_ctdp_supported(mvm)) { 14535c89e7bcSChaya Rachel Ivgi ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START, 14545c89e7bcSChaya Rachel Ivgi mvm->cooling_dev.cur_state); 145575cfe338SLuca Coelho if (ret) 145675cfe338SLuca Coelho goto error; 145775cfe338SLuca Coelho } 1458c221daf2SChaya Rachel Ivgi #endif 1459e705c121SKalle Valo 1460aa43ae12SAlex Malamud if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2)) 1461e705c121SKalle Valo WARN_ON(iwl_mvm_config_ltr(mvm)); 1462e705c121SKalle Valo 1463e705c121SKalle Valo ret = iwl_mvm_power_update_device(mvm); 1464e705c121SKalle Valo if (ret) 1465e705c121SKalle Valo goto error; 1466e705c121SKalle Valo 1467f5b1cb2eSGil Adam iwl_mvm_lari_cfg(mvm); 1468e705c121SKalle Valo /* 1469e705c121SKalle Valo * RTNL is not taken during Ct-kill, but we don't need to scan/Tx 1470e705c121SKalle Valo * anyway, so don't init MCC. 1471e705c121SKalle Valo */ 1472e705c121SKalle Valo if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { 1473e705c121SKalle Valo ret = iwl_mvm_init_mcc(mvm); 1474e705c121SKalle Valo if (ret) 1475e705c121SKalle Valo goto error; 1476e705c121SKalle Valo } 1477e705c121SKalle Valo 1478e705c121SKalle Valo if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { 14794ca87a5fSEmmanuel Grumbach mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; 1480b66b5817SSara Sharon mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET; 1481e705c121SKalle Valo ret = iwl_mvm_config_scan(mvm); 1482e705c121SKalle Valo if (ret) 1483e705c121SKalle Valo goto error; 1484e705c121SKalle Valo } 1485e705c121SKalle Valo 1486f130bb75SMordechay Goodstein if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) 1487f130bb75SMordechay Goodstein iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB); 1488f130bb75SMordechay Goodstein 148948e775e6SHaim Dreyfuss if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid)) 149048e775e6SHaim Dreyfuss IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n"); 149148e775e6SHaim Dreyfuss 14926ce1e5c0SGil Adam ret = iwl_mvm_ppag_init(mvm); 14936ce1e5c0SGil Adam if (ret) 14946ce1e5c0SGil Adam goto error; 14956ce1e5c0SGil Adam 1496da2830acSLuca Coelho ret = iwl_mvm_sar_init(mvm); 14975d041c46SLuca Coelho if (ret == 0) { 1498a6bff3cbSHaim Dreyfuss ret = iwl_mvm_sar_geo_init(mvm); 14991edd56e6SLuca Coelho } else if (ret == -ENOENT && !iwl_sar_get_wgds_table(&mvm->fwrt)) { 15005d041c46SLuca Coelho /* 15015d041c46SLuca Coelho * If basic SAR is not available, we check for WGDS, 15025d041c46SLuca Coelho * which should *not* be available either. If it is 15035d041c46SLuca Coelho * available, issue an error, because we can't use SAR 15045d041c46SLuca Coelho * Geo without basic SAR. 15055d041c46SLuca Coelho */ 15065d041c46SLuca Coelho IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n"); 15075d041c46SLuca Coelho } 15085d041c46SLuca Coelho 15095d041c46SLuca Coelho if (ret < 0) 1510a6bff3cbSHaim Dreyfuss goto error; 1511a6bff3cbSHaim Dreyfuss 151228dd7ccdSMordechay Goodstein iwl_mvm_tas_init(mvm); 15137089ae63SJohannes Berg iwl_mvm_leds_sync(mvm); 15147089ae63SJohannes Berg 1515e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); 1516e705c121SKalle Valo return 0; 1517e705c121SKalle Valo error: 1518f4744258SLiad Kaufman if (!iwlmvm_mod_params.init_dbg || !ret) 1519fcb6b92aSChaya Rachel Ivgi iwl_mvm_stop_device(mvm); 1520e705c121SKalle Valo return ret; 1521e705c121SKalle Valo } 1522e705c121SKalle Valo 1523e705c121SKalle Valo int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) 1524e705c121SKalle Valo { 1525e705c121SKalle Valo int ret, i; 1526e705c121SKalle Valo 1527e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 1528e705c121SKalle Valo 1529e705c121SKalle Valo ret = iwl_trans_start_hw(mvm->trans); 1530e705c121SKalle Valo if (ret) 1531e705c121SKalle Valo return ret; 1532e705c121SKalle Valo 1533e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); 1534e705c121SKalle Valo if (ret) { 1535e705c121SKalle Valo IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); 1536e705c121SKalle Valo goto error; 1537e705c121SKalle Valo } 1538e705c121SKalle Valo 1539e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 1540e705c121SKalle Valo if (ret) 1541e705c121SKalle Valo goto error; 1542e705c121SKalle Valo 1543e705c121SKalle Valo /* Send phy db control command and then phy db calibration*/ 1544e705c121SKalle Valo ret = iwl_send_phy_db_data(mvm->phy_db); 1545e705c121SKalle Valo if (ret) 1546e705c121SKalle Valo goto error; 1547e705c121SKalle Valo 1548e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 1549e705c121SKalle Valo if (ret) 1550e705c121SKalle Valo goto error; 1551e705c121SKalle Valo 1552e705c121SKalle Valo /* init the fw <-> mac80211 STA mapping */ 15530ae98812SSara Sharon for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++) 1554e705c121SKalle Valo RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); 1555e705c121SKalle Valo 1556e705c121SKalle Valo /* Add auxiliary station for scanning */ 1557e705c121SKalle Valo ret = iwl_mvm_add_aux_sta(mvm); 1558e705c121SKalle Valo if (ret) 1559e705c121SKalle Valo goto error; 1560e705c121SKalle Valo 1561e705c121SKalle Valo return 0; 1562e705c121SKalle Valo error: 1563fcb6b92aSChaya Rachel Ivgi iwl_mvm_stop_device(mvm); 1564e705c121SKalle Valo return ret; 1565e705c121SKalle Valo } 1566e705c121SKalle Valo 1567e705c121SKalle Valo void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, 1568e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1569e705c121SKalle Valo { 1570e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1571e705c121SKalle Valo struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; 1572e705c121SKalle Valo u32 flags = le32_to_cpu(card_state_notif->flags); 1573e705c121SKalle Valo 1574e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", 1575e705c121SKalle Valo (flags & HW_CARD_DISABLED) ? "Kill" : "On", 1576e705c121SKalle Valo (flags & SW_CARD_DISABLED) ? "Kill" : "On", 1577e705c121SKalle Valo (flags & CT_KILL_CARD_DISABLED) ? 1578e705c121SKalle Valo "Reached" : "Not reached"); 1579e705c121SKalle Valo } 1580e705c121SKalle Valo 1581e705c121SKalle Valo void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, 1582e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1583e705c121SKalle Valo { 1584e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1585e705c121SKalle Valo struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; 1586e705c121SKalle Valo 1587e705c121SKalle Valo IWL_DEBUG_INFO(mvm, 1588e705c121SKalle Valo "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", 1589e705c121SKalle Valo le32_to_cpu(mfuart_notif->installed_ver), 1590e705c121SKalle Valo le32_to_cpu(mfuart_notif->external_ver), 1591e705c121SKalle Valo le32_to_cpu(mfuart_notif->status), 1592e705c121SKalle Valo le32_to_cpu(mfuart_notif->duration)); 15930c8d0a47SGolan Ben-Ami 15940c8d0a47SGolan Ben-Ami if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif)) 15950c8d0a47SGolan Ben-Ami IWL_DEBUG_INFO(mvm, 15960c8d0a47SGolan Ben-Ami "MFUART: image size: 0x%08x\n", 15970c8d0a47SGolan Ben-Ami le32_to_cpu(mfuart_notif->image_size)); 1598e705c121SKalle Valo } 1599