1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 9bdccdb85SGolan Ben-Ami * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 10cceb4507SShahar S Matityahu * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation 11e705c121SKalle Valo * 12e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 13e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 14e705c121SKalle Valo * published by the Free Software Foundation. 15e705c121SKalle Valo * 16e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 17e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 18e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19e705c121SKalle Valo * General Public License for more details. 20e705c121SKalle Valo * 21e705c121SKalle Valo * The full GNU General Public License is included in this distribution 22e705c121SKalle Valo * in the file called COPYING. 23e705c121SKalle Valo * 24e705c121SKalle Valo * Contact Information: 25cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 26e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27e705c121SKalle Valo * 28e705c121SKalle Valo * BSD LICENSE 29e705c121SKalle Valo * 30e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 31bdccdb85SGolan Ben-Ami * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 32cceb4507SShahar S Matityahu * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation 33e705c121SKalle Valo * All rights reserved. 34e705c121SKalle Valo * 35e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 36e705c121SKalle Valo * modification, are permitted provided that the following conditions 37e705c121SKalle Valo * are met: 38e705c121SKalle Valo * 39e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 40e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 41e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 43e705c121SKalle Valo * the documentation and/or other materials provided with the 44e705c121SKalle Valo * distribution. 45e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 46e705c121SKalle Valo * contributors may be used to endorse or promote products derived 47e705c121SKalle Valo * from this software without specific prior written permission. 48e705c121SKalle Valo * 49e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 50e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 51e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 52e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 53e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 55e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 59e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60e705c121SKalle Valo * 61e705c121SKalle Valo *****************************************************************************/ 62e705c121SKalle Valo #include <net/mac80211.h> 63854d773eSSara Sharon #include <linux/netdevice.h> 64e705c121SKalle Valo 65e705c121SKalle Valo #include "iwl-trans.h" 66e705c121SKalle Valo #include "iwl-op-mode.h" 67d962f9b1SJohannes Berg #include "fw/img.h" 68e705c121SKalle Valo #include "iwl-debug.h" 69e705c121SKalle Valo #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ 70e705c121SKalle Valo #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ 71e705c121SKalle Valo #include "iwl-prph.h" 72813df5ceSLuca Coelho #include "fw/acpi.h" 73e705c121SKalle Valo 74e705c121SKalle Valo #include "mvm.h" 757174beb6SJohannes Berg #include "fw/dbg.h" 76e705c121SKalle Valo #include "iwl-phy-db.h" 779c4f7d51SShaul Triebitz #include "iwl-modparams.h" 789c4f7d51SShaul Triebitz #include "iwl-nvm-parse.h" 79e705c121SKalle Valo 80e705c121SKalle Valo #define MVM_UCODE_ALIVE_TIMEOUT HZ 81e705c121SKalle Valo #define MVM_UCODE_CALIB_TIMEOUT (2*HZ) 82e705c121SKalle Valo 83e705c121SKalle Valo #define UCODE_VALID_OK cpu_to_le32(0x1) 84e705c121SKalle Valo 85e705c121SKalle Valo struct iwl_mvm_alive_data { 86e705c121SKalle Valo bool valid; 87e705c121SKalle Valo u32 scd_base_addr; 88e705c121SKalle Valo }; 89e705c121SKalle Valo 90cceb4507SShahar S Matityahu /* set device type and latency */ 91cceb4507SShahar S Matityahu static int iwl_set_soc_latency(struct iwl_mvm *mvm) 92cceb4507SShahar S Matityahu { 93095650c0SLuca Coelho struct iwl_soc_configuration_cmd cmd = {}; 94cceb4507SShahar S Matityahu int ret; 95cceb4507SShahar S Matityahu 96095650c0SLuca Coelho /* 97095650c0SLuca Coelho * In VER_1 of this command, the discrete value is considered 98095650c0SLuca Coelho * an integer; In VER_2, it's a bitmask. Since we have only 2 99095650c0SLuca Coelho * values in VER_1, this is backwards-compatible with VER_2, 100095650c0SLuca Coelho * as long as we don't set any other bits. 101095650c0SLuca Coelho */ 102095650c0SLuca Coelho if (!mvm->trans->trans_cfg->integrated) 103095650c0SLuca Coelho cmd.flags = cpu_to_le32(SOC_CONFIG_CMD_FLAGS_DISCRETE); 104095650c0SLuca Coelho 1054af11950SMordechay Goodstein if (iwl_fw_lookup_cmd_ver(mvm->fw, IWL_ALWAYS_LONG_GROUP, 106095650c0SLuca Coelho SCAN_REQ_UMAC) >= 2 && 1074af11950SMordechay Goodstein mvm->trans->trans_cfg->low_latency_xtal) 108095650c0SLuca Coelho cmd.flags |= cpu_to_le32(SOC_CONFIG_CMD_FLAGS_LOW_LATENCY); 109095650c0SLuca Coelho 110095650c0SLuca Coelho cmd.latency = cpu_to_le32(mvm->trans->trans_cfg->xtal_latency); 111cceb4507SShahar S Matityahu 112cceb4507SShahar S Matityahu ret = iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(SOC_CONFIGURATION_CMD, 113cceb4507SShahar S Matityahu SYSTEM_GROUP, 0), 0, 114cceb4507SShahar S Matityahu sizeof(cmd), &cmd); 115cceb4507SShahar S Matityahu if (ret) 116cceb4507SShahar S Matityahu IWL_ERR(mvm, "Failed to set soc latency: %d\n", ret); 117cceb4507SShahar S Matityahu return ret; 118cceb4507SShahar S Matityahu } 119cceb4507SShahar S Matityahu 120e705c121SKalle Valo static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) 121e705c121SKalle Valo { 122e705c121SKalle Valo struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { 123e705c121SKalle Valo .valid = cpu_to_le32(valid_tx_ant), 124e705c121SKalle Valo }; 125e705c121SKalle Valo 126e705c121SKalle Valo IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); 127e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, 128e705c121SKalle Valo sizeof(tx_ant_cmd), &tx_ant_cmd); 129e705c121SKalle Valo } 130e705c121SKalle Valo 13143413a97SSara Sharon static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm) 13243413a97SSara Sharon { 13343413a97SSara Sharon int i; 13443413a97SSara Sharon struct iwl_rss_config_cmd cmd = { 13543413a97SSara Sharon .flags = cpu_to_le32(IWL_RSS_ENABLE), 136608dce95SSara Sharon .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) | 137608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) | 138608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) | 139608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) | 140608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) | 141608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD), 14243413a97SSara Sharon }; 14343413a97SSara Sharon 144f43495fdSSara Sharon if (mvm->trans->num_rx_queues == 1) 145f43495fdSSara Sharon return 0; 146f43495fdSSara Sharon 147854d773eSSara Sharon /* Do not direct RSS traffic to Q 0 which is our fallback queue */ 14843413a97SSara Sharon for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++) 149854d773eSSara Sharon cmd.indirection_table[i] = 150854d773eSSara Sharon 1 + (i % (mvm->trans->num_rx_queues - 1)); 151854d773eSSara Sharon netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key)); 15243413a97SSara Sharon 15343413a97SSara Sharon return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd); 15443413a97SSara Sharon } 15543413a97SSara Sharon 1568edbfaa1SSara Sharon static int iwl_configure_rxq(struct iwl_mvm *mvm) 1578edbfaa1SSara Sharon { 158dbf592f3SJohannes Berg int i, num_queues, size, ret; 1598edbfaa1SSara Sharon struct iwl_rfh_queue_config *cmd; 160dbf592f3SJohannes Berg struct iwl_host_cmd hcmd = { 161dbf592f3SJohannes Berg .id = WIDE_ID(DATA_PATH_GROUP, RFH_QUEUE_CONFIG_CMD), 162dbf592f3SJohannes Berg .dataflags[0] = IWL_HCMD_DFL_NOCOPY, 163dbf592f3SJohannes Berg }; 1648edbfaa1SSara Sharon 1658edbfaa1SSara Sharon /* Do not configure default queue, it is configured via context info */ 1668edbfaa1SSara Sharon num_queues = mvm->trans->num_rx_queues - 1; 1678edbfaa1SSara Sharon 168dbf592f3SJohannes Berg size = struct_size(cmd, data, num_queues); 1698edbfaa1SSara Sharon 1708edbfaa1SSara Sharon cmd = kzalloc(size, GFP_KERNEL); 1718edbfaa1SSara Sharon if (!cmd) 1728edbfaa1SSara Sharon return -ENOMEM; 1738edbfaa1SSara Sharon 1748edbfaa1SSara Sharon cmd->num_queues = num_queues; 1758edbfaa1SSara Sharon 1768edbfaa1SSara Sharon for (i = 0; i < num_queues; i++) { 1778edbfaa1SSara Sharon struct iwl_trans_rxq_dma_data data; 1788edbfaa1SSara Sharon 1798edbfaa1SSara Sharon cmd->data[i].q_num = i + 1; 1808edbfaa1SSara Sharon iwl_trans_get_rxq_dma_data(mvm->trans, i + 1, &data); 1818edbfaa1SSara Sharon 1828edbfaa1SSara Sharon cmd->data[i].fr_bd_cb = cpu_to_le64(data.fr_bd_cb); 1838edbfaa1SSara Sharon cmd->data[i].urbd_stts_wrptr = 1848edbfaa1SSara Sharon cpu_to_le64(data.urbd_stts_wrptr); 1858edbfaa1SSara Sharon cmd->data[i].ur_bd_cb = cpu_to_le64(data.ur_bd_cb); 1868edbfaa1SSara Sharon cmd->data[i].fr_bd_wid = cpu_to_le32(data.fr_bd_wid); 1878edbfaa1SSara Sharon } 1888edbfaa1SSara Sharon 189dbf592f3SJohannes Berg hcmd.data[0] = cmd; 190dbf592f3SJohannes Berg hcmd.len[0] = size; 191dbf592f3SJohannes Berg 192dbf592f3SJohannes Berg ret = iwl_mvm_send_cmd(mvm, &hcmd); 193dbf592f3SJohannes Berg 194dbf592f3SJohannes Berg kfree(cmd); 195dbf592f3SJohannes Berg 196dbf592f3SJohannes Berg return ret; 1978edbfaa1SSara Sharon } 1988edbfaa1SSara Sharon 19997d5be7eSLiad Kaufman static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm) 20097d5be7eSLiad Kaufman { 20197d5be7eSLiad Kaufman struct iwl_dqa_enable_cmd dqa_cmd = { 20297d5be7eSLiad Kaufman .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE), 20397d5be7eSLiad Kaufman }; 20497d5be7eSLiad Kaufman u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0); 20597d5be7eSLiad Kaufman int ret; 20697d5be7eSLiad Kaufman 20797d5be7eSLiad Kaufman ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); 20897d5be7eSLiad Kaufman if (ret) 20997d5be7eSLiad Kaufman IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret); 21097d5be7eSLiad Kaufman else 21197d5be7eSLiad Kaufman IWL_DEBUG_FW(mvm, "Working in DQA mode\n"); 21297d5be7eSLiad Kaufman 21397d5be7eSLiad Kaufman return ret; 21497d5be7eSLiad Kaufman } 21597d5be7eSLiad Kaufman 216bdccdb85SGolan Ben-Ami void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm, 217bdccdb85SGolan Ben-Ami struct iwl_rx_cmd_buffer *rxb) 218bdccdb85SGolan Ben-Ami { 219bdccdb85SGolan Ben-Ami struct iwl_rx_packet *pkt = rxb_addr(rxb); 220bdccdb85SGolan Ben-Ami struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data; 221bdccdb85SGolan Ben-Ami __le32 *dump_data = mfu_dump_notif->data; 222bdccdb85SGolan Ben-Ami int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32); 223bdccdb85SGolan Ben-Ami int i; 224bdccdb85SGolan Ben-Ami 225bdccdb85SGolan Ben-Ami if (mfu_dump_notif->index_num == 0) 226bdccdb85SGolan Ben-Ami IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n", 227bdccdb85SGolan Ben-Ami le32_to_cpu(mfu_dump_notif->assert_id)); 228bdccdb85SGolan Ben-Ami 229bdccdb85SGolan Ben-Ami for (i = 0; i < n_words; i++) 230bdccdb85SGolan Ben-Ami IWL_DEBUG_INFO(mvm, 231bdccdb85SGolan Ben-Ami "MFUART assert dump, dword %u: 0x%08x\n", 232bdccdb85SGolan Ben-Ami le16_to_cpu(mfu_dump_notif->index_num) * 233bdccdb85SGolan Ben-Ami n_words + i, 234bdccdb85SGolan Ben-Ami le32_to_cpu(dump_data[i])); 235bdccdb85SGolan Ben-Ami } 236bdccdb85SGolan Ben-Ami 237e705c121SKalle Valo static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, 238e705c121SKalle Valo struct iwl_rx_packet *pkt, void *data) 239e705c121SKalle Valo { 240e705c121SKalle Valo struct iwl_mvm *mvm = 241e705c121SKalle Valo container_of(notif_wait, struct iwl_mvm, notif_wait); 242e705c121SKalle Valo struct iwl_mvm_alive_data *alive_data = data; 2435c228d63SSara Sharon struct mvm_alive_resp_v3 *palive3; 244e705c121SKalle Valo struct mvm_alive_resp *palive; 2455c228d63SSara Sharon struct iwl_umac_alive *umac; 2465c228d63SSara Sharon struct iwl_lmac_alive *lmac1; 2475c228d63SSara Sharon struct iwl_lmac_alive *lmac2 = NULL; 2485c228d63SSara Sharon u16 status; 24922463857SShahar S Matityahu u32 lmac_error_event_table, umac_error_event_table; 250e705c121SKalle Valo 2515c228d63SSara Sharon if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) { 252e705c121SKalle Valo palive = (void *)pkt->data; 2535c228d63SSara Sharon umac = &palive->umac_data; 2545c228d63SSara Sharon lmac1 = &palive->lmac_data[0]; 2555c228d63SSara Sharon lmac2 = &palive->lmac_data[1]; 2565c228d63SSara Sharon status = le16_to_cpu(palive->status); 2575c228d63SSara Sharon } else { 2585c228d63SSara Sharon palive3 = (void *)pkt->data; 2595c228d63SSara Sharon umac = &palive3->umac_data; 2605c228d63SSara Sharon lmac1 = &palive3->lmac_data; 2615c228d63SSara Sharon status = le16_to_cpu(palive3->status); 2625c228d63SSara Sharon } 263e705c121SKalle Valo 26422463857SShahar S Matityahu lmac_error_event_table = 26522463857SShahar S Matityahu le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr); 26622463857SShahar S Matityahu iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table); 267e705c121SKalle Valo 26822463857SShahar S Matityahu if (lmac2) 26991c28b83SShahar S Matityahu mvm->trans->dbg.lmac_error_event_table[1] = 27022463857SShahar S Matityahu le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr); 27122463857SShahar S Matityahu 27222463857SShahar S Matityahu umac_error_event_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr); 2735c228d63SSara Sharon 2743485e76eSLuca Coelho if (!umac_error_event_table) { 2753485e76eSLuca Coelho mvm->support_umac_log = false; 2763485e76eSLuca Coelho } else if (umac_error_event_table >= 2773485e76eSLuca Coelho mvm->trans->cfg->min_umac_error_event_table) { 2783485e76eSLuca Coelho mvm->support_umac_log = true; 2793485e76eSLuca Coelho } else { 280fb5b2846SLuca Coelho IWL_ERR(mvm, 281fb5b2846SLuca Coelho "Not valid error log pointer 0x%08X for %s uCode\n", 28222463857SShahar S Matityahu umac_error_event_table, 283fb5b2846SLuca Coelho (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ? 284fb5b2846SLuca Coelho "Init" : "RT"); 2853485e76eSLuca Coelho mvm->support_umac_log = false; 2863485e76eSLuca Coelho } 287fb5b2846SLuca Coelho 28822463857SShahar S Matityahu if (mvm->support_umac_log) 28922463857SShahar S Matityahu iwl_fw_umac_set_alive_err_table(mvm->trans, 29022463857SShahar S Matityahu umac_error_event_table); 29122463857SShahar S Matityahu 29222463857SShahar S Matityahu alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr); 2935c228d63SSara Sharon alive_data->valid = status == IWL_ALIVE_STATUS_OK; 294e705c121SKalle Valo 295e705c121SKalle Valo IWL_DEBUG_FW(mvm, 2965c228d63SSara Sharon "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n", 2975c228d63SSara Sharon status, lmac1->ver_type, lmac1->ver_subtype); 2985c228d63SSara Sharon 2995c228d63SSara Sharon if (lmac2) 3005c228d63SSara Sharon IWL_DEBUG_FW(mvm, "Alive ucode CDB\n"); 301e705c121SKalle Valo 302e705c121SKalle Valo IWL_DEBUG_FW(mvm, 303e705c121SKalle Valo "UMAC version: Major - 0x%x, Minor - 0x%x\n", 3045c228d63SSara Sharon le32_to_cpu(umac->umac_major), 3055c228d63SSara Sharon le32_to_cpu(umac->umac_minor)); 306e705c121SKalle Valo 3070a3a3e9eSShahar S Matityahu iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac); 3080a3a3e9eSShahar S Matityahu 309e705c121SKalle Valo return true; 310e705c121SKalle Valo } 311e705c121SKalle Valo 3121f370650SSara Sharon static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait, 3131f370650SSara Sharon struct iwl_rx_packet *pkt, void *data) 3141f370650SSara Sharon { 3151f370650SSara Sharon WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); 3161f370650SSara Sharon 3171f370650SSara Sharon return true; 3181f370650SSara Sharon } 3191f370650SSara Sharon 320e705c121SKalle Valo static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, 321e705c121SKalle Valo struct iwl_rx_packet *pkt, void *data) 322e705c121SKalle Valo { 323e705c121SKalle Valo struct iwl_phy_db *phy_db = data; 324e705c121SKalle Valo 325e705c121SKalle Valo if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { 326e705c121SKalle Valo WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); 327e705c121SKalle Valo return true; 328e705c121SKalle Valo } 329e705c121SKalle Valo 330ce1f2778SSara Sharon WARN_ON(iwl_phy_db_set_section(phy_db, pkt)); 331e705c121SKalle Valo 332e705c121SKalle Valo return false; 333e705c121SKalle Valo } 334e705c121SKalle Valo 335e705c121SKalle Valo static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, 336e705c121SKalle Valo enum iwl_ucode_type ucode_type) 337e705c121SKalle Valo { 338e705c121SKalle Valo struct iwl_notification_wait alive_wait; 33994a8d87cSLuca Coelho struct iwl_mvm_alive_data alive_data = {}; 340e705c121SKalle Valo const struct fw_img *fw; 341cfbc6c4cSSara Sharon int ret; 342702e975dSJohannes Berg enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img; 343e705c121SKalle Valo static const u16 alive_cmd[] = { MVM_ALIVE }; 344b3500b47SEmmanuel Grumbach bool run_in_rfkill = 345b3500b47SEmmanuel Grumbach ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm); 346e705c121SKalle Valo 347e705c121SKalle Valo if (ucode_type == IWL_UCODE_REGULAR && 3483d2d4422SGolan Ben-Ami iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) && 3493d2d4422SGolan Ben-Ami !(fw_has_capa(&mvm->fw->ucode_capa, 3503d2d4422SGolan Ben-Ami IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED))) 351612da1efSSharon Dvir fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER); 352e705c121SKalle Valo else 353612da1efSSharon Dvir fw = iwl_get_ucode_image(mvm->fw, ucode_type); 354e705c121SKalle Valo if (WARN_ON(!fw)) 355e705c121SKalle Valo return -EINVAL; 356702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, ucode_type); 35765b280feSJohannes Berg clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); 358e705c121SKalle Valo 359e705c121SKalle Valo iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, 360e705c121SKalle Valo alive_cmd, ARRAY_SIZE(alive_cmd), 361e705c121SKalle Valo iwl_alive_fn, &alive_data); 362e705c121SKalle Valo 363b3500b47SEmmanuel Grumbach /* 364b3500b47SEmmanuel Grumbach * We want to load the INIT firmware even in RFKILL 365b3500b47SEmmanuel Grumbach * For the unified firmware case, the ucode_type is not 366b3500b47SEmmanuel Grumbach * INIT, but we still need to run it. 367b3500b47SEmmanuel Grumbach */ 368b3500b47SEmmanuel Grumbach ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill); 369e705c121SKalle Valo if (ret) { 370702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, old_type); 371e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &alive_wait); 372e705c121SKalle Valo return ret; 373e705c121SKalle Valo } 374e705c121SKalle Valo 375e705c121SKalle Valo /* 376e705c121SKalle Valo * Some things may run in the background now, but we 377e705c121SKalle Valo * just wait for the ALIVE notification here. 378e705c121SKalle Valo */ 379e705c121SKalle Valo ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, 380e705c121SKalle Valo MVM_UCODE_ALIVE_TIMEOUT); 381e705c121SKalle Valo if (ret) { 382d6be9c1dSSara Sharon struct iwl_trans *trans = mvm->trans; 383d6be9c1dSSara Sharon 38420f5aef5SJohannes Berg if (trans->trans_cfg->device_family >= 38520f5aef5SJohannes Berg IWL_DEVICE_FAMILY_22000) { 386e705c121SKalle Valo IWL_ERR(mvm, 387e705c121SKalle Valo "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", 388ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS), 389ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, 390ea695b7cSShaul Triebitz UMAG_SB_CPU_2_STATUS)); 39120f5aef5SJohannes Berg IWL_ERR(mvm, "UMAC PC: 0x%x\n", 39220f5aef5SJohannes Berg iwl_read_umac_prph(trans, 39320f5aef5SJohannes Berg UREG_UMAC_CURRENT_PC)); 39420f5aef5SJohannes Berg IWL_ERR(mvm, "LMAC PC: 0x%x\n", 39520f5aef5SJohannes Berg iwl_read_umac_prph(trans, 39620f5aef5SJohannes Berg UREG_LMAC1_CURRENT_PC)); 39720f5aef5SJohannes Berg if (iwl_mvm_is_cdb_supported(mvm)) 39820f5aef5SJohannes Berg IWL_ERR(mvm, "LMAC2 PC: 0x%x\n", 39920f5aef5SJohannes Berg iwl_read_umac_prph(trans, 40020f5aef5SJohannes Berg UREG_LMAC2_CURRENT_PC)); 40120f5aef5SJohannes Berg } else if (trans->trans_cfg->device_family >= 40220f5aef5SJohannes Berg IWL_DEVICE_FAMILY_8000) { 403d6be9c1dSSara Sharon IWL_ERR(mvm, 404d6be9c1dSSara Sharon "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", 405d6be9c1dSSara Sharon iwl_read_prph(trans, SB_CPU_1_STATUS), 406d6be9c1dSSara Sharon iwl_read_prph(trans, SB_CPU_2_STATUS)); 40720f5aef5SJohannes Berg } 40820f5aef5SJohannes Berg 40920f5aef5SJohannes Berg if (ret == -ETIMEDOUT) 41020f5aef5SJohannes Berg iwl_fw_dbg_error_collect(&mvm->fwrt, 41120f5aef5SJohannes Berg FW_DBG_TRIGGER_ALIVE_TIMEOUT); 41220f5aef5SJohannes Berg 413702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, old_type); 414e705c121SKalle Valo return ret; 415e705c121SKalle Valo } 416e705c121SKalle Valo 417e705c121SKalle Valo if (!alive_data.valid) { 418e705c121SKalle Valo IWL_ERR(mvm, "Loaded ucode is not valid!\n"); 419702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, old_type); 420e705c121SKalle Valo return -EIO; 421e705c121SKalle Valo } 422e705c121SKalle Valo 423e705c121SKalle Valo iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); 424e705c121SKalle Valo 425e705c121SKalle Valo /* 426e705c121SKalle Valo * Note: all the queues are enabled as part of the interface 427e705c121SKalle Valo * initialization, but in firmware restart scenarios they 428e705c121SKalle Valo * could be stopped, so wake them up. In firmware restart, 429e705c121SKalle Valo * mac80211 will have the queues stopped as well until the 430e705c121SKalle Valo * reconfiguration completes. During normal startup, they 431e705c121SKalle Valo * will be empty. 432e705c121SKalle Valo */ 433e705c121SKalle Valo 434e705c121SKalle Valo memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); 4351c14089eSJohannes Berg /* 4361c14089eSJohannes Berg * Set a 'fake' TID for the command queue, since we use the 4371c14089eSJohannes Berg * hweight() of the tid_bitmap as a refcount now. Not that 4381c14089eSJohannes Berg * we ever even consider the command queue as one we might 4391c14089eSJohannes Berg * want to reuse, but be safe nevertheless. 4401c14089eSJohannes Berg */ 4411c14089eSJohannes Berg mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap = 4421c14089eSJohannes Berg BIT(IWL_MAX_TID_COUNT + 2); 443e705c121SKalle Valo 44465b280feSJohannes Berg set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); 445f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 446f7805b33SLior Cohen iwl_fw_set_dbg_rec_on(&mvm->fwrt); 447f7805b33SLior Cohen #endif 448e705c121SKalle Valo 449e705c121SKalle Valo return 0; 450e705c121SKalle Valo } 451e705c121SKalle Valo 4528c5f47b1SJohannes Berg static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) 4538c5f47b1SJohannes Berg { 4548c5f47b1SJohannes Berg struct iwl_notification_wait init_wait; 4558c5f47b1SJohannes Berg struct iwl_nvm_access_complete_cmd nvm_complete = {}; 4568c5f47b1SJohannes Berg struct iwl_init_extended_cfg_cmd init_cfg = { 4578c5f47b1SJohannes Berg .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)), 4588c5f47b1SJohannes Berg }; 4598c5f47b1SJohannes Berg static const u16 init_complete[] = { 4608c5f47b1SJohannes Berg INIT_COMPLETE_NOTIF, 4618c5f47b1SJohannes Berg }; 4628c5f47b1SJohannes Berg int ret; 4638c5f47b1SJohannes Berg 464a4584729SHaim Dreyfuss if (mvm->trans->cfg->tx_with_siso_diversity) 465a4584729SHaim Dreyfuss init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY)); 466a4584729SHaim Dreyfuss 4678c5f47b1SJohannes Berg lockdep_assert_held(&mvm->mutex); 4688c5f47b1SJohannes Berg 46994022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 47094022562SEmmanuel Grumbach 4718c5f47b1SJohannes Berg iwl_init_notification_wait(&mvm->notif_wait, 4728c5f47b1SJohannes Berg &init_wait, 4738c5f47b1SJohannes Berg init_complete, 4748c5f47b1SJohannes Berg ARRAY_SIZE(init_complete), 4758c5f47b1SJohannes Berg iwl_wait_init_complete, 4768c5f47b1SJohannes Berg NULL); 4778c5f47b1SJohannes Berg 478b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); 47986ce5c74SShahar S Matityahu 4808c5f47b1SJohannes Berg /* Will also start the device */ 4818c5f47b1SJohannes Berg ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); 4828c5f47b1SJohannes Berg if (ret) { 4838c5f47b1SJohannes Berg IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); 4848c5f47b1SJohannes Berg goto error; 4858c5f47b1SJohannes Berg } 486b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, 487b108d8c7SShahar S Matityahu NULL); 4888c5f47b1SJohannes Berg 4898c5f47b1SJohannes Berg /* Send init config command to mark that we are sending NVM access 4908c5f47b1SJohannes Berg * commands 4918c5f47b1SJohannes Berg */ 4928c5f47b1SJohannes Berg ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP, 493b3500b47SEmmanuel Grumbach INIT_EXTENDED_CFG_CMD), 494b3500b47SEmmanuel Grumbach CMD_SEND_IN_RFKILL, 4958c5f47b1SJohannes Berg sizeof(init_cfg), &init_cfg); 4968c5f47b1SJohannes Berg if (ret) { 4978c5f47b1SJohannes Berg IWL_ERR(mvm, "Failed to run init config command: %d\n", 4988c5f47b1SJohannes Berg ret); 4998c5f47b1SJohannes Berg goto error; 5008c5f47b1SJohannes Berg } 5018c5f47b1SJohannes Berg 502e9e1ba3dSSara Sharon /* Load NVM to NIC if needed */ 503e9e1ba3dSSara Sharon if (mvm->nvm_file_name) { 5049c4f7d51SShaul Triebitz iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name, 5059c4f7d51SShaul Triebitz mvm->nvm_sections); 5068c5f47b1SJohannes Berg iwl_mvm_load_nvm_to_nic(mvm); 507e9e1ba3dSSara Sharon } 5088c5f47b1SJohannes Berg 509d4f3695eSSara Sharon if (IWL_MVM_PARSE_NVM && read_nvm) { 5105bd1d2c1SLuca Coelho ret = iwl_nvm_init(mvm); 511d4f3695eSSara Sharon if (ret) { 512d4f3695eSSara Sharon IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); 513d4f3695eSSara Sharon goto error; 514d4f3695eSSara Sharon } 515d4f3695eSSara Sharon } 516d4f3695eSSara Sharon 5178c5f47b1SJohannes Berg ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP, 518b3500b47SEmmanuel Grumbach NVM_ACCESS_COMPLETE), 519b3500b47SEmmanuel Grumbach CMD_SEND_IN_RFKILL, 5208c5f47b1SJohannes Berg sizeof(nvm_complete), &nvm_complete); 5218c5f47b1SJohannes Berg if (ret) { 5228c5f47b1SJohannes Berg IWL_ERR(mvm, "Failed to run complete NVM access: %d\n", 5238c5f47b1SJohannes Berg ret); 5248c5f47b1SJohannes Berg goto error; 5258c5f47b1SJohannes Berg } 5268c5f47b1SJohannes Berg 5278c5f47b1SJohannes Berg /* We wait for the INIT complete notification */ 528e9e1ba3dSSara Sharon ret = iwl_wait_notification(&mvm->notif_wait, &init_wait, 5298c5f47b1SJohannes Berg MVM_UCODE_ALIVE_TIMEOUT); 530e9e1ba3dSSara Sharon if (ret) 531e9e1ba3dSSara Sharon return ret; 532e9e1ba3dSSara Sharon 533e9e1ba3dSSara Sharon /* Read the NVM only at driver load time, no need to do this twice */ 534d4f3695eSSara Sharon if (!IWL_MVM_PARSE_NVM && read_nvm) { 5354c625c56SShaul Triebitz mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw); 536c135cb56SShaul Triebitz if (IS_ERR(mvm->nvm_data)) { 537c135cb56SShaul Triebitz ret = PTR_ERR(mvm->nvm_data); 538c135cb56SShaul Triebitz mvm->nvm_data = NULL; 539e9e1ba3dSSara Sharon IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); 540e9e1ba3dSSara Sharon return ret; 541e9e1ba3dSSara Sharon } 542e9e1ba3dSSara Sharon } 543e9e1ba3dSSara Sharon 544b3500b47SEmmanuel Grumbach mvm->rfkill_safe_init_done = true; 545b3500b47SEmmanuel Grumbach 546e9e1ba3dSSara Sharon return 0; 5478c5f47b1SJohannes Berg 5488c5f47b1SJohannes Berg error: 5498c5f47b1SJohannes Berg iwl_remove_notification(&mvm->notif_wait, &init_wait); 5508c5f47b1SJohannes Berg return ret; 5518c5f47b1SJohannes Berg } 5528c5f47b1SJohannes Berg 553c4ace426SGil Adam #ifdef CONFIG_ACPI 554c4ace426SGil Adam static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm, 555c4ace426SGil Adam struct iwl_phy_specific_cfg *phy_filters) 556c4ace426SGil Adam { 557c4ace426SGil Adam /* 558c4ace426SGil Adam * TODO: read specific phy config from BIOS 559c4ace426SGil Adam * ACPI table for this feature has not been defined yet, 560c4ace426SGil Adam * so for now we use hardcoded values. 561c4ace426SGil Adam */ 562c4ace426SGil Adam 563c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_A) { 564c4ace426SGil Adam phy_filters->filter_cfg_chain_a = 565c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A); 566c4ace426SGil Adam } 567c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_B) { 568c4ace426SGil Adam phy_filters->filter_cfg_chain_b = 569c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B); 570c4ace426SGil Adam } 571c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_C) { 572c4ace426SGil Adam phy_filters->filter_cfg_chain_c = 573c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C); 574c4ace426SGil Adam } 575c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_D) { 576c4ace426SGil Adam phy_filters->filter_cfg_chain_d = 577c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D); 578c4ace426SGil Adam } 579c4ace426SGil Adam } 580c4ace426SGil Adam 581c4ace426SGil Adam #else /* CONFIG_ACPI */ 582c4ace426SGil Adam 583c4ace426SGil Adam static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm, 584c4ace426SGil Adam struct iwl_phy_specific_cfg *phy_filters) 585c4ace426SGil Adam { 586c4ace426SGil Adam } 587c4ace426SGil Adam #endif /* CONFIG_ACPI */ 588c4ace426SGil Adam 589e705c121SKalle Valo static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) 590e705c121SKalle Valo { 591c4ace426SGil Adam struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd; 592702e975dSJohannes Berg enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img; 593c4ace426SGil Adam struct iwl_phy_specific_cfg phy_filters = {}; 594c4ace426SGil Adam u8 cmd_ver; 595c4ace426SGil Adam size_t cmd_size; 596e705c121SKalle Valo 597bb99ff9bSLuca Coelho if (iwl_mvm_has_unified_ucode(mvm) && 598d923b020SLuca Coelho !mvm->trans->cfg->tx_with_siso_diversity) 599bb99ff9bSLuca Coelho return 0; 600d923b020SLuca Coelho 601d923b020SLuca Coelho if (mvm->trans->cfg->tx_with_siso_diversity) { 602bb99ff9bSLuca Coelho /* 603bb99ff9bSLuca Coelho * TODO: currently we don't set the antenna but letting the NIC 604bb99ff9bSLuca Coelho * to decide which antenna to use. This should come from BIOS. 605bb99ff9bSLuca Coelho */ 606bb99ff9bSLuca Coelho phy_cfg_cmd.phy_cfg = 607bb99ff9bSLuca Coelho cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED); 608bb99ff9bSLuca Coelho } 609bb99ff9bSLuca Coelho 610e705c121SKalle Valo /* Set parameters */ 611e705c121SKalle Valo phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); 61286a2b204SLuca Coelho 61386a2b204SLuca Coelho /* set flags extra PHY configuration flags from the device's cfg */ 6147897dfa2SLuca Coelho phy_cfg_cmd.phy_cfg |= 6157897dfa2SLuca Coelho cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags); 61686a2b204SLuca Coelho 617e705c121SKalle Valo phy_cfg_cmd.calib_control.event_trigger = 618e705c121SKalle Valo mvm->fw->default_calib[ucode_type].event_trigger; 619e705c121SKalle Valo phy_cfg_cmd.calib_control.flow_trigger = 620e705c121SKalle Valo mvm->fw->default_calib[ucode_type].flow_trigger; 621e705c121SKalle Valo 622c4ace426SGil Adam cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, IWL_ALWAYS_LONG_GROUP, 623c4ace426SGil Adam PHY_CONFIGURATION_CMD); 624c4ace426SGil Adam if (cmd_ver == 3) { 625c4ace426SGil Adam iwl_mvm_phy_filter_init(mvm, &phy_filters); 626c4ace426SGil Adam memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters, 627c4ace426SGil Adam sizeof(struct iwl_phy_specific_cfg)); 628c4ace426SGil Adam } 629c4ace426SGil Adam 630e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", 631e705c121SKalle Valo phy_cfg_cmd.phy_cfg); 632c4ace426SGil Adam cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) : 633c4ace426SGil Adam sizeof(struct iwl_phy_cfg_cmd_v1); 634e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, 635c4ace426SGil Adam cmd_size, &phy_cfg_cmd); 636e705c121SKalle Valo } 637e705c121SKalle Valo 638e705c121SKalle Valo int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) 639e705c121SKalle Valo { 640e705c121SKalle Valo struct iwl_notification_wait calib_wait; 641e705c121SKalle Valo static const u16 init_complete[] = { 642e705c121SKalle Valo INIT_COMPLETE_NOTIF, 643e705c121SKalle Valo CALIB_RES_NOTIF_PHY_DB 644e705c121SKalle Valo }; 645e705c121SKalle Valo int ret; 646e705c121SKalle Valo 6477d6222e2SJohannes Berg if (iwl_mvm_has_unified_ucode(mvm)) 6488c5f47b1SJohannes Berg return iwl_run_unified_mvm_ucode(mvm, true); 6498c5f47b1SJohannes Berg 650e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 651e705c121SKalle Valo 65294022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 653e705c121SKalle Valo 654e705c121SKalle Valo iwl_init_notification_wait(&mvm->notif_wait, 655e705c121SKalle Valo &calib_wait, 656e705c121SKalle Valo init_complete, 657e705c121SKalle Valo ARRAY_SIZE(init_complete), 658e705c121SKalle Valo iwl_wait_phy_db_entry, 659e705c121SKalle Valo mvm->phy_db); 660e705c121SKalle Valo 661e705c121SKalle Valo /* Will also start the device */ 662e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); 663e705c121SKalle Valo if (ret) { 664e705c121SKalle Valo IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); 66500e0c6c8SLuca Coelho goto remove_notif; 666e705c121SKalle Valo } 667e705c121SKalle Valo 6687d34a7d7SLuca Coelho if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) { 669b3de3ef4SEmmanuel Grumbach ret = iwl_mvm_send_bt_init_conf(mvm); 670e705c121SKalle Valo if (ret) 67100e0c6c8SLuca Coelho goto remove_notif; 672b3de3ef4SEmmanuel Grumbach } 673e705c121SKalle Valo 674e705c121SKalle Valo /* Read the NVM only at driver load time, no need to do this twice */ 675e705c121SKalle Valo if (read_nvm) { 6765bd1d2c1SLuca Coelho ret = iwl_nvm_init(mvm); 677e705c121SKalle Valo if (ret) { 678e705c121SKalle Valo IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); 67900e0c6c8SLuca Coelho goto remove_notif; 680e705c121SKalle Valo } 681e705c121SKalle Valo } 682e705c121SKalle Valo 683e705c121SKalle Valo /* In case we read the NVM from external file, load it to the NIC */ 684e705c121SKalle Valo if (mvm->nvm_file_name) 685e705c121SKalle Valo iwl_mvm_load_nvm_to_nic(mvm); 686e705c121SKalle Valo 68764866e5dSLuca Coelho WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver, 68864866e5dSLuca Coelho "Too old NVM version (0x%0x, required = 0x%0x)", 68964866e5dSLuca Coelho mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver); 690e705c121SKalle Valo 691e705c121SKalle Valo /* 692e705c121SKalle Valo * abort after reading the nvm in case RF Kill is on, we will complete 693e705c121SKalle Valo * the init seq later when RF kill will switch to off 694e705c121SKalle Valo */ 695e705c121SKalle Valo if (iwl_mvm_is_radio_hw_killed(mvm)) { 696e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, 697e705c121SKalle Valo "jump over all phy activities due to RF kill\n"); 69800e0c6c8SLuca Coelho goto remove_notif; 699e705c121SKalle Valo } 700e705c121SKalle Valo 701b3500b47SEmmanuel Grumbach mvm->rfkill_safe_init_done = true; 702e705c121SKalle Valo 703e705c121SKalle Valo /* Send TX valid antennas before triggering calibrations */ 704e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 705e705c121SKalle Valo if (ret) 70600e0c6c8SLuca Coelho goto remove_notif; 707e705c121SKalle Valo 708e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 709e705c121SKalle Valo if (ret) { 710e705c121SKalle Valo IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", 711e705c121SKalle Valo ret); 71200e0c6c8SLuca Coelho goto remove_notif; 713e705c121SKalle Valo } 714e705c121SKalle Valo 715e705c121SKalle Valo /* 716e705c121SKalle Valo * Some things may run in the background now, but we 717e705c121SKalle Valo * just wait for the calibration complete notification. 718e705c121SKalle Valo */ 719e705c121SKalle Valo ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, 720e705c121SKalle Valo MVM_UCODE_CALIB_TIMEOUT); 72100e0c6c8SLuca Coelho if (!ret) 722e705c121SKalle Valo goto out; 723e705c121SKalle Valo 72400e0c6c8SLuca Coelho if (iwl_mvm_is_radio_hw_killed(mvm)) { 72500e0c6c8SLuca Coelho IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); 72600e0c6c8SLuca Coelho ret = 0; 72700e0c6c8SLuca Coelho } else { 72800e0c6c8SLuca Coelho IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", 72900e0c6c8SLuca Coelho ret); 73000e0c6c8SLuca Coelho } 73100e0c6c8SLuca Coelho 73200e0c6c8SLuca Coelho goto out; 73300e0c6c8SLuca Coelho 73400e0c6c8SLuca Coelho remove_notif: 735e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &calib_wait); 736e705c121SKalle Valo out: 737b3500b47SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 738e705c121SKalle Valo if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { 739e705c121SKalle Valo /* we want to debug INIT and we have no NVM - fake */ 740e705c121SKalle Valo mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + 741e705c121SKalle Valo sizeof(struct ieee80211_channel) + 742e705c121SKalle Valo sizeof(struct ieee80211_rate), 743e705c121SKalle Valo GFP_KERNEL); 744e705c121SKalle Valo if (!mvm->nvm_data) 745e705c121SKalle Valo return -ENOMEM; 746e705c121SKalle Valo mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; 747e705c121SKalle Valo mvm->nvm_data->bands[0].n_channels = 1; 748e705c121SKalle Valo mvm->nvm_data->bands[0].n_bitrates = 1; 749e705c121SKalle Valo mvm->nvm_data->bands[0].bitrates = 750e705c121SKalle Valo (void *)mvm->nvm_data->channels + 1; 751e705c121SKalle Valo mvm->nvm_data->bands[0].bitrates->hw_value = 10; 752e705c121SKalle Valo } 753e705c121SKalle Valo 754e705c121SKalle Valo return ret; 755e705c121SKalle Valo } 756e705c121SKalle Valo 757e705c121SKalle Valo static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) 758e705c121SKalle Valo { 759e705c121SKalle Valo struct iwl_ltr_config_cmd cmd = { 760e705c121SKalle Valo .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), 761e705c121SKalle Valo }; 762e705c121SKalle Valo 763e705c121SKalle Valo if (!mvm->trans->ltr_enabled) 764e705c121SKalle Valo return 0; 765e705c121SKalle Valo 766e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, 767e705c121SKalle Valo sizeof(cmd), &cmd); 768e705c121SKalle Valo } 769e705c121SKalle Valo 770c386dacbSHaim Dreyfuss #ifdef CONFIG_ACPI 77142ce76d6SLuca Coelho int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b) 772da2830acSLuca Coelho { 7730791c2fcSHaim Dreyfuss union { 7740791c2fcSHaim Dreyfuss struct iwl_dev_tx_power_cmd v5; 7750791c2fcSHaim Dreyfuss struct iwl_dev_tx_power_cmd_v4 v4; 7760791c2fcSHaim Dreyfuss } cmd; 777da2830acSLuca Coelho 77839c1a972SIhab Zhaika u16 len = 0; 77942ce76d6SLuca Coelho 7800791c2fcSHaim Dreyfuss cmd.v5.v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS); 7810791c2fcSHaim Dreyfuss 7820791c2fcSHaim Dreyfuss if (fw_has_api(&mvm->fw->ucode_capa, 7830791c2fcSHaim Dreyfuss IWL_UCODE_TLV_API_REDUCE_TX_POWER)) 7840791c2fcSHaim Dreyfuss len = sizeof(cmd.v5); 7850791c2fcSHaim Dreyfuss else if (fw_has_capa(&mvm->fw->ucode_capa, 7860791c2fcSHaim Dreyfuss IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) 78739c1a972SIhab Zhaika len = sizeof(struct iwl_dev_tx_power_cmd_v4); 7880791c2fcSHaim Dreyfuss else 7890791c2fcSHaim Dreyfuss len = sizeof(cmd.v4.v3); 79055bfa4b9SLuca Coelho 79142ce76d6SLuca Coelho 79239c1a972SIhab Zhaika if (iwl_sar_select_profile(&mvm->fwrt, cmd.v5.v3.per_chain_restriction, 79339c1a972SIhab Zhaika prof_a, prof_b)) 79442ce76d6SLuca Coelho return -ENOENT; 79542ce76d6SLuca Coelho IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n"); 79642ce76d6SLuca Coelho return iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd); 79742ce76d6SLuca Coelho } 79842ce76d6SLuca Coelho 7997fe90e0eSHaim Dreyfuss int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) 8007fe90e0eSHaim Dreyfuss { 80139c1a972SIhab Zhaika union geo_tx_power_profiles_cmd geo_tx_cmd; 8020c3d7282SHaim Dreyfuss u16 len; 80339c1a972SIhab Zhaika int ret; 8040c3d7282SHaim Dreyfuss struct iwl_host_cmd cmd; 8057fe90e0eSHaim Dreyfuss 80639c1a972SIhab Zhaika if (fw_has_api(&mvm->fwrt.fw->ucode_capa, 80739c1a972SIhab Zhaika IWL_UCODE_TLV_API_SAR_TABLE_VER)) { 80839c1a972SIhab Zhaika geo_tx_cmd.geo_cmd.ops = 8090c3d7282SHaim Dreyfuss cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE); 81039c1a972SIhab Zhaika len = sizeof(geo_tx_cmd.geo_cmd); 8110c3d7282SHaim Dreyfuss } else { 81239c1a972SIhab Zhaika geo_tx_cmd.geo_cmd_v1.ops = 8130c3d7282SHaim Dreyfuss cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE); 81439c1a972SIhab Zhaika len = sizeof(geo_tx_cmd.geo_cmd_v1); 8150c3d7282SHaim Dreyfuss } 8160c3d7282SHaim Dreyfuss 81739c1a972SIhab Zhaika if (!iwl_sar_geo_support(&mvm->fwrt)) 81839c1a972SIhab Zhaika return -EOPNOTSUPP; 81939c1a972SIhab Zhaika 8200c3d7282SHaim Dreyfuss cmd = (struct iwl_host_cmd){ 8217fe90e0eSHaim Dreyfuss .id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT), 8220c3d7282SHaim Dreyfuss .len = { len, }, 8237fe90e0eSHaim Dreyfuss .flags = CMD_WANT_SKB, 82439c1a972SIhab Zhaika .data = { &geo_tx_cmd }, 8257fe90e0eSHaim Dreyfuss }; 8267fe90e0eSHaim Dreyfuss 8277fe90e0eSHaim Dreyfuss ret = iwl_mvm_send_cmd(mvm, &cmd); 8287fe90e0eSHaim Dreyfuss if (ret) { 8297fe90e0eSHaim Dreyfuss IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret); 8307fe90e0eSHaim Dreyfuss return ret; 8317fe90e0eSHaim Dreyfuss } 83239c1a972SIhab Zhaika ret = iwl_validate_sar_geo_profile(&mvm->fwrt, &cmd); 8337fe90e0eSHaim Dreyfuss iwl_free_resp(&cmd); 8347fe90e0eSHaim Dreyfuss return ret; 8357fe90e0eSHaim Dreyfuss } 8367fe90e0eSHaim Dreyfuss 837a6bff3cbSHaim Dreyfuss static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) 838a6bff3cbSHaim Dreyfuss { 839a6bff3cbSHaim Dreyfuss u16 cmd_wide_id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT); 84039c1a972SIhab Zhaika union geo_tx_power_profiles_cmd cmd; 84139c1a972SIhab Zhaika u16 len; 8420433ae55SGolan Ben Ami int ret; 843a6bff3cbSHaim Dreyfuss 84439c1a972SIhab Zhaika cmd.geo_cmd.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES); 845eca1e56cSEmmanuel Grumbach 8460433ae55SGolan Ben Ami ret = iwl_sar_geo_init(&mvm->fwrt, cmd.geo_cmd.table); 8470433ae55SGolan Ben Ami /* 8480433ae55SGolan Ben Ami * It is a valid scenario to not support SAR, or miss wgds table, 8490433ae55SGolan Ben Ami * but in that case there is no need to send the command. 8500433ae55SGolan Ben Ami */ 8510433ae55SGolan Ben Ami if (ret) 8520433ae55SGolan Ben Ami return 0; 853a6bff3cbSHaim Dreyfuss 85439c1a972SIhab Zhaika cmd.geo_cmd.table_revision = cpu_to_le32(mvm->fwrt.geo_rev); 855a6bff3cbSHaim Dreyfuss 85639c1a972SIhab Zhaika if (!fw_has_api(&mvm->fwrt.fw->ucode_capa, 8570c3d7282SHaim Dreyfuss IWL_UCODE_TLV_API_SAR_TABLE_VER)) { 85839c1a972SIhab Zhaika len = sizeof(struct iwl_geo_tx_power_profiles_cmd_v1); 85939c1a972SIhab Zhaika } else { 86039c1a972SIhab Zhaika len = sizeof(cmd.geo_cmd); 8610c3d7282SHaim Dreyfuss } 8620c3d7282SHaim Dreyfuss 86339c1a972SIhab Zhaika return iwl_mvm_send_cmd_pdu(mvm, cmd_wide_id, 0, len, &cmd); 864a6bff3cbSHaim Dreyfuss } 865a6bff3cbSHaim Dreyfuss 8666ce1e5c0SGil Adam static int iwl_mvm_get_ppag_table(struct iwl_mvm *mvm) 8676ce1e5c0SGil Adam { 8686ce1e5c0SGil Adam union acpi_object *wifi_pkg, *data, *enabled; 8696ce1e5c0SGil Adam int i, j, ret, tbl_rev; 8706ce1e5c0SGil Adam int idx = 2; 8716ce1e5c0SGil Adam 87239c1a972SIhab Zhaika mvm->fwrt.ppag_table.enabled = cpu_to_le32(0); 8736ce1e5c0SGil Adam data = iwl_acpi_get_object(mvm->dev, ACPI_PPAG_METHOD); 8746ce1e5c0SGil Adam if (IS_ERR(data)) 8756ce1e5c0SGil Adam return PTR_ERR(data); 8766ce1e5c0SGil Adam 8776ce1e5c0SGil Adam wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data, 8786ce1e5c0SGil Adam ACPI_PPAG_WIFI_DATA_SIZE, &tbl_rev); 8796ce1e5c0SGil Adam 8803ed83da3SLuca Coelho if (IS_ERR(wifi_pkg)) { 8816ce1e5c0SGil Adam ret = PTR_ERR(wifi_pkg); 8826ce1e5c0SGil Adam goto out_free; 8836ce1e5c0SGil Adam } 8846ce1e5c0SGil Adam 8853ed83da3SLuca Coelho if (tbl_rev != 0) { 8863ed83da3SLuca Coelho ret = -EINVAL; 8873ed83da3SLuca Coelho goto out_free; 8883ed83da3SLuca Coelho } 8893ed83da3SLuca Coelho 8906ce1e5c0SGil Adam enabled = &wifi_pkg->package.elements[1]; 8916ce1e5c0SGil Adam if (enabled->type != ACPI_TYPE_INTEGER || 8926ce1e5c0SGil Adam (enabled->integer.value != 0 && enabled->integer.value != 1)) { 8936ce1e5c0SGil Adam ret = -EINVAL; 8946ce1e5c0SGil Adam goto out_free; 8956ce1e5c0SGil Adam } 8966ce1e5c0SGil Adam 89739c1a972SIhab Zhaika mvm->fwrt.ppag_table.enabled = cpu_to_le32(enabled->integer.value); 89839c1a972SIhab Zhaika if (!mvm->fwrt.ppag_table.enabled) { 8996ce1e5c0SGil Adam ret = 0; 9006ce1e5c0SGil Adam goto out_free; 9016ce1e5c0SGil Adam } 9026ce1e5c0SGil Adam 9036ce1e5c0SGil Adam /* 9046ce1e5c0SGil Adam * read, verify gain values and save them into the PPAG table. 9056ce1e5c0SGil Adam * first sub-band (j=0) corresponds to Low-Band (2.4GHz), and the 9066ce1e5c0SGil Adam * following sub-bands to High-Band (5GHz). 9076ce1e5c0SGil Adam */ 9086ce1e5c0SGil Adam for (i = 0; i < ACPI_PPAG_NUM_CHAINS; i++) { 9096ce1e5c0SGil Adam for (j = 0; j < ACPI_PPAG_NUM_SUB_BANDS; j++) { 9106ce1e5c0SGil Adam union acpi_object *ent; 9116ce1e5c0SGil Adam 9126ce1e5c0SGil Adam ent = &wifi_pkg->package.elements[idx++]; 9136ce1e5c0SGil Adam if (ent->type != ACPI_TYPE_INTEGER || 9146ce1e5c0SGil Adam (j == 0 && ent->integer.value > ACPI_PPAG_MAX_LB) || 9156ce1e5c0SGil Adam (j == 0 && ent->integer.value < ACPI_PPAG_MIN_LB) || 9166ce1e5c0SGil Adam (j != 0 && ent->integer.value > ACPI_PPAG_MAX_HB) || 9176ce1e5c0SGil Adam (j != 0 && ent->integer.value < ACPI_PPAG_MIN_HB)) { 91839c1a972SIhab Zhaika mvm->fwrt.ppag_table.enabled = cpu_to_le32(0); 9196ce1e5c0SGil Adam ret = -EINVAL; 9206ce1e5c0SGil Adam goto out_free; 9216ce1e5c0SGil Adam } 92239c1a972SIhab Zhaika mvm->fwrt.ppag_table.gain[i][j] = ent->integer.value; 9236ce1e5c0SGil Adam } 9246ce1e5c0SGil Adam } 9256ce1e5c0SGil Adam ret = 0; 9266ce1e5c0SGil Adam out_free: 9276ce1e5c0SGil Adam kfree(data); 9286ce1e5c0SGil Adam return ret; 9296ce1e5c0SGil Adam } 9306ce1e5c0SGil Adam 9316ce1e5c0SGil Adam int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) 9326ce1e5c0SGil Adam { 9336ce1e5c0SGil Adam int i, j, ret; 9346ce1e5c0SGil Adam 9356ce1e5c0SGil Adam if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) { 9366ce1e5c0SGil Adam IWL_DEBUG_RADIO(mvm, 9376ce1e5c0SGil Adam "PPAG capability not supported by FW, command not sent.\n"); 9386ce1e5c0SGil Adam return 0; 9396ce1e5c0SGil Adam } 9406ce1e5c0SGil Adam 941160bab43SGil Adam if (!mvm->fwrt.ppag_table.enabled) { 942160bab43SGil Adam IWL_DEBUG_RADIO(mvm, 943160bab43SGil Adam "PPAG not enabled, command not sent.\n"); 944160bab43SGil Adam return 0; 945160bab43SGil Adam } 946160bab43SGil Adam 9476ce1e5c0SGil Adam IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n"); 9486ce1e5c0SGil Adam 9496ce1e5c0SGil Adam for (i = 0; i < ACPI_PPAG_NUM_CHAINS; i++) { 9506ce1e5c0SGil Adam for (j = 0; j < ACPI_PPAG_NUM_SUB_BANDS; j++) { 9516ce1e5c0SGil Adam IWL_DEBUG_RADIO(mvm, 9526ce1e5c0SGil Adam "PPAG table: chain[%d] band[%d]: gain = %d\n", 95339c1a972SIhab Zhaika i, j, mvm->fwrt.ppag_table.gain[i][j]); 9546ce1e5c0SGil Adam } 9556ce1e5c0SGil Adam } 9566ce1e5c0SGil Adam 9576ce1e5c0SGil Adam ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP, 9586ce1e5c0SGil Adam PER_PLATFORM_ANT_GAIN_CMD), 95939c1a972SIhab Zhaika 0, sizeof(mvm->fwrt.ppag_table), 96039c1a972SIhab Zhaika &mvm->fwrt.ppag_table); 9616ce1e5c0SGil Adam if (ret < 0) 9626ce1e5c0SGil Adam IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n", 9636ce1e5c0SGil Adam ret); 9646ce1e5c0SGil Adam 9656ce1e5c0SGil Adam return ret; 9666ce1e5c0SGil Adam } 9676ce1e5c0SGil Adam 9686ce1e5c0SGil Adam static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) 9696ce1e5c0SGil Adam { 9706ce1e5c0SGil Adam int ret; 9716ce1e5c0SGil Adam 9726ce1e5c0SGil Adam ret = iwl_mvm_get_ppag_table(mvm); 9736ce1e5c0SGil Adam if (ret < 0) { 9746ce1e5c0SGil Adam IWL_DEBUG_RADIO(mvm, 9756ce1e5c0SGil Adam "PPAG BIOS table invalid or unavailable. (%d)\n", 9766ce1e5c0SGil Adam ret); 9776ce1e5c0SGil Adam return 0; 9786ce1e5c0SGil Adam } 9796ce1e5c0SGil Adam return iwl_mvm_ppag_send_cmd(mvm); 9806ce1e5c0SGil Adam } 9816ce1e5c0SGil Adam 98269964905SLuca Coelho #else /* CONFIG_ACPI */ 98339c1a972SIhab Zhaika 98439c1a972SIhab Zhaika inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, 98539c1a972SIhab Zhaika int prof_a, int prof_b) 98669964905SLuca Coelho { 98769964905SLuca Coelho return -ENOENT; 98869964905SLuca Coelho } 98969964905SLuca Coelho 99039c1a972SIhab Zhaika inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) 9915d041c46SLuca Coelho { 9925d041c46SLuca Coelho return -ENOENT; 9935d041c46SLuca Coelho } 9945d041c46SLuca Coelho 995a6bff3cbSHaim Dreyfuss static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) 996a6bff3cbSHaim Dreyfuss { 997a6bff3cbSHaim Dreyfuss return 0; 998a6bff3cbSHaim Dreyfuss } 99918f1755dSLuca Coelho 10006ce1e5c0SGil Adam int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) 10016ce1e5c0SGil Adam { 10026ce1e5c0SGil Adam return -ENOENT; 10036ce1e5c0SGil Adam } 10046ce1e5c0SGil Adam 10056ce1e5c0SGil Adam static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) 10066ce1e5c0SGil Adam { 10077937fd32SJohannes Berg return 0; 10086ce1e5c0SGil Adam } 100969964905SLuca Coelho #endif /* CONFIG_ACPI */ 101069964905SLuca Coelho 1011f130bb75SMordechay Goodstein void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags) 1012f130bb75SMordechay Goodstein { 1013f130bb75SMordechay Goodstein u32 error_log_size = mvm->fw->ucode_capa.error_log_size; 1014f130bb75SMordechay Goodstein int ret; 1015f130bb75SMordechay Goodstein u32 resp; 1016f130bb75SMordechay Goodstein 1017f130bb75SMordechay Goodstein struct iwl_fw_error_recovery_cmd recovery_cmd = { 1018f130bb75SMordechay Goodstein .flags = cpu_to_le32(flags), 1019f130bb75SMordechay Goodstein .buf_size = 0, 1020f130bb75SMordechay Goodstein }; 1021f130bb75SMordechay Goodstein struct iwl_host_cmd host_cmd = { 1022f130bb75SMordechay Goodstein .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD), 1023f130bb75SMordechay Goodstein .flags = CMD_WANT_SKB, 1024f130bb75SMordechay Goodstein .data = {&recovery_cmd, }, 1025f130bb75SMordechay Goodstein .len = {sizeof(recovery_cmd), }, 1026f130bb75SMordechay Goodstein }; 1027f130bb75SMordechay Goodstein 1028f130bb75SMordechay Goodstein /* no error log was defined in TLV */ 1029f130bb75SMordechay Goodstein if (!error_log_size) 1030f130bb75SMordechay Goodstein return; 1031f130bb75SMordechay Goodstein 1032f130bb75SMordechay Goodstein if (flags & ERROR_RECOVERY_UPDATE_DB) { 1033f130bb75SMordechay Goodstein /* no buf was allocated while HW reset */ 1034f130bb75SMordechay Goodstein if (!mvm->error_recovery_buf) 1035f130bb75SMordechay Goodstein return; 1036f130bb75SMordechay Goodstein 1037f130bb75SMordechay Goodstein host_cmd.data[1] = mvm->error_recovery_buf; 1038f130bb75SMordechay Goodstein host_cmd.len[1] = error_log_size; 1039f130bb75SMordechay Goodstein host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY; 1040f130bb75SMordechay Goodstein recovery_cmd.buf_size = cpu_to_le32(error_log_size); 1041f130bb75SMordechay Goodstein } 1042f130bb75SMordechay Goodstein 1043f130bb75SMordechay Goodstein ret = iwl_mvm_send_cmd(mvm, &host_cmd); 1044f130bb75SMordechay Goodstein kfree(mvm->error_recovery_buf); 1045f130bb75SMordechay Goodstein mvm->error_recovery_buf = NULL; 1046f130bb75SMordechay Goodstein 1047f130bb75SMordechay Goodstein if (ret) { 1048f130bb75SMordechay Goodstein IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret); 1049f130bb75SMordechay Goodstein return; 1050f130bb75SMordechay Goodstein } 1051f130bb75SMordechay Goodstein 1052f130bb75SMordechay Goodstein /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */ 1053f130bb75SMordechay Goodstein if (flags & ERROR_RECOVERY_UPDATE_DB) { 1054f130bb75SMordechay Goodstein resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data); 1055f130bb75SMordechay Goodstein if (resp) 1056f130bb75SMordechay Goodstein IWL_ERR(mvm, 1057f130bb75SMordechay Goodstein "Failed to send recovery cmd blob was invalid %d\n", 1058f130bb75SMordechay Goodstein resp); 1059f130bb75SMordechay Goodstein } 1060f130bb75SMordechay Goodstein } 1061f130bb75SMordechay Goodstein 106242ce76d6SLuca Coelho static int iwl_mvm_sar_init(struct iwl_mvm *mvm) 106342ce76d6SLuca Coelho { 106442ce76d6SLuca Coelho int ret; 106542ce76d6SLuca Coelho 106639c1a972SIhab Zhaika ret = iwl_sar_get_wrds_table(&mvm->fwrt); 1067da2830acSLuca Coelho if (ret < 0) { 1068da2830acSLuca Coelho IWL_DEBUG_RADIO(mvm, 106969964905SLuca Coelho "WRDS SAR BIOS table invalid or unavailable. (%d)\n", 1070da2830acSLuca Coelho ret); 10715d041c46SLuca Coelho /* 10725d041c46SLuca Coelho * If not available, don't fail and don't bother with EWRD. 10735d041c46SLuca Coelho * Return 1 to tell that we can't use WGDS either. 10745d041c46SLuca Coelho */ 10755d041c46SLuca Coelho return 1; 1076da2830acSLuca Coelho } 1077da2830acSLuca Coelho 107839c1a972SIhab Zhaika ret = iwl_sar_get_ewrd_table(&mvm->fwrt); 107969964905SLuca Coelho /* if EWRD is not available, we can still use WRDS, so don't fail */ 108069964905SLuca Coelho if (ret < 0) 108169964905SLuca Coelho IWL_DEBUG_RADIO(mvm, 108269964905SLuca Coelho "EWRD SAR BIOS table invalid or unavailable. (%d)\n", 108369964905SLuca Coelho ret); 108469964905SLuca Coelho 108542ce76d6SLuca Coelho ret = iwl_mvm_sar_select_profile(mvm, 1, 1); 10865d041c46SLuca Coelho /* 10875d041c46SLuca Coelho * If we don't have profile 0 from BIOS, just skip it. This 10885d041c46SLuca Coelho * means that SAR Geo will not be enabled either, even if we 10895d041c46SLuca Coelho * have other valid profiles. 10905d041c46SLuca Coelho */ 109142ce76d6SLuca Coelho if (ret == -ENOENT) 10925d041c46SLuca Coelho return 1; 1093da2830acSLuca Coelho 1094da2830acSLuca Coelho return ret; 1095da2830acSLuca Coelho } 1096da2830acSLuca Coelho 10971f370650SSara Sharon static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm) 10981f370650SSara Sharon { 10991f370650SSara Sharon int ret; 11001f370650SSara Sharon 11017d6222e2SJohannes Berg if (iwl_mvm_has_unified_ucode(mvm)) 11021f370650SSara Sharon return iwl_run_unified_mvm_ucode(mvm, false); 11031f370650SSara Sharon 11041f370650SSara Sharon ret = iwl_run_init_mvm_ucode(mvm, false); 11051f370650SSara Sharon 11061f370650SSara Sharon if (ret) { 11071f370650SSara Sharon IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); 1108f4744258SLiad Kaufman 1109f4744258SLiad Kaufman if (iwlmvm_mod_params.init_dbg) 1110f4744258SLiad Kaufman return 0; 11111f370650SSara Sharon return ret; 11121f370650SSara Sharon } 11131f370650SSara Sharon 1114203c83d3SShahar S Matityahu iwl_fw_dbg_stop_sync(&mvm->fwrt); 1115bab3cb92SEmmanuel Grumbach iwl_trans_stop_device(mvm->trans); 1116bab3cb92SEmmanuel Grumbach ret = iwl_trans_start_hw(mvm->trans); 11171f370650SSara Sharon if (ret) 11181f370650SSara Sharon return ret; 11191f370650SSara Sharon 1120b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); 1121da2eb669SSara Sharon 112294022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 11231f370650SSara Sharon ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); 11241f370650SSara Sharon if (ret) 11251f370650SSara Sharon return ret; 11261f370650SSara Sharon 112794022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = true; 112894022562SEmmanuel Grumbach 1129b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, 1130b108d8c7SShahar S Matityahu NULL); 1131da2eb669SSara Sharon 1132702e975dSJohannes Berg return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img); 11331f370650SSara Sharon } 11341f370650SSara Sharon 1135e705c121SKalle Valo int iwl_mvm_up(struct iwl_mvm *mvm) 1136e705c121SKalle Valo { 1137e705c121SKalle Valo int ret, i; 1138e705c121SKalle Valo struct ieee80211_channel *chan; 1139e705c121SKalle Valo struct cfg80211_chan_def chandef; 1140dd36a507STova Mussai struct ieee80211_supported_band *sband = NULL; 1141e705c121SKalle Valo 1142e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 1143e705c121SKalle Valo 1144e705c121SKalle Valo ret = iwl_trans_start_hw(mvm->trans); 1145e705c121SKalle Valo if (ret) 1146e705c121SKalle Valo return ret; 1147e705c121SKalle Valo 11481f370650SSara Sharon ret = iwl_mvm_load_rt_fw(mvm); 1149e705c121SKalle Valo if (ret) { 1150e705c121SKalle Valo IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); 115172d3c7bbSJohannes Berg if (ret != -ERFKILL) 115272d3c7bbSJohannes Berg iwl_fw_dbg_error_collect(&mvm->fwrt, 115372d3c7bbSJohannes Berg FW_DBG_TRIGGER_DRIVER); 1154e705c121SKalle Valo goto error; 1155e705c121SKalle Valo } 1156e705c121SKalle Valo 1157d0b813fcSJohannes Berg iwl_get_shared_mem_conf(&mvm->fwrt); 1158e705c121SKalle Valo 1159e705c121SKalle Valo ret = iwl_mvm_sf_update(mvm, NULL, false); 1160e705c121SKalle Valo if (ret) 1161e705c121SKalle Valo IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); 1162e705c121SKalle Valo 1163a1af4c48SShahar S Matityahu if (!iwl_trans_dbg_ini_valid(mvm->trans)) { 11647174beb6SJohannes Berg mvm->fwrt.dump.conf = FW_DBG_INVALID; 1165e705c121SKalle Valo /* if we have a destination, assume EARLY START */ 116617b809c9SSara Sharon if (mvm->fw->dbg.dest_tlv) 11677174beb6SJohannes Berg mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE; 11687174beb6SJohannes Berg iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE); 11697a14c23dSSara Sharon } 1170e705c121SKalle Valo 1171e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 1172e705c121SKalle Valo if (ret) 1173e705c121SKalle Valo goto error; 1174e705c121SKalle Valo 11757d6222e2SJohannes Berg if (!iwl_mvm_has_unified_ucode(mvm)) { 1176e705c121SKalle Valo /* Send phy db control command and then phy db calibration */ 1177e705c121SKalle Valo ret = iwl_send_phy_db_data(mvm->phy_db); 1178e705c121SKalle Valo if (ret) 1179e705c121SKalle Valo goto error; 1180bb99ff9bSLuca Coelho } 1181e705c121SKalle Valo 1182e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 1183e705c121SKalle Valo if (ret) 1184e705c121SKalle Valo goto error; 1185e705c121SKalle Valo 1186b3de3ef4SEmmanuel Grumbach ret = iwl_mvm_send_bt_init_conf(mvm); 1187b3de3ef4SEmmanuel Grumbach if (ret) 1188b3de3ef4SEmmanuel Grumbach goto error; 1189b3de3ef4SEmmanuel Grumbach 1190cceb4507SShahar S Matityahu if (fw_has_capa(&mvm->fw->ucode_capa, 1191cceb4507SShahar S Matityahu IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) { 1192cceb4507SShahar S Matityahu ret = iwl_set_soc_latency(mvm); 1193cceb4507SShahar S Matityahu if (ret) 1194cceb4507SShahar S Matityahu goto error; 1195cceb4507SShahar S Matityahu } 1196cceb4507SShahar S Matityahu 119743413a97SSara Sharon /* Init RSS configuration */ 1198286ca8ebSLuca Coelho if (mvm->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) { 11998edbfaa1SSara Sharon ret = iwl_configure_rxq(mvm); 12008edbfaa1SSara Sharon if (ret) { 12018edbfaa1SSara Sharon IWL_ERR(mvm, "Failed to configure RX queues: %d\n", 12028edbfaa1SSara Sharon ret); 12038edbfaa1SSara Sharon goto error; 12048edbfaa1SSara Sharon } 12058edbfaa1SSara Sharon } 12068edbfaa1SSara Sharon 12078edbfaa1SSara Sharon if (iwl_mvm_has_new_rx_api(mvm)) { 120843413a97SSara Sharon ret = iwl_send_rss_cfg_cmd(mvm); 120943413a97SSara Sharon if (ret) { 121043413a97SSara Sharon IWL_ERR(mvm, "Failed to configure RSS queues: %d\n", 121143413a97SSara Sharon ret); 121243413a97SSara Sharon goto error; 121343413a97SSara Sharon } 121443413a97SSara Sharon } 121543413a97SSara Sharon 1216e705c121SKalle Valo /* init the fw <-> mac80211 STA mapping */ 12170ae98812SSara Sharon for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++) 1218e705c121SKalle Valo RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); 1219e705c121SKalle Valo 12200ae98812SSara Sharon mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA; 1221e705c121SKalle Valo 1222e705c121SKalle Valo /* reset quota debouncing buffer - 0xff will yield invalid data */ 1223e705c121SKalle Valo memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); 1224e705c121SKalle Valo 122579660869SIlia Lin if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) { 122697d5be7eSLiad Kaufman ret = iwl_mvm_send_dqa_cmd(mvm); 122797d5be7eSLiad Kaufman if (ret) 122897d5be7eSLiad Kaufman goto error; 122979660869SIlia Lin } 123097d5be7eSLiad Kaufman 1231e705c121SKalle Valo /* Add auxiliary station for scanning */ 1232e705c121SKalle Valo ret = iwl_mvm_add_aux_sta(mvm); 1233e705c121SKalle Valo if (ret) 1234e705c121SKalle Valo goto error; 1235e705c121SKalle Valo 1236e705c121SKalle Valo /* Add all the PHY contexts */ 1237dd36a507STova Mussai i = 0; 1238dd36a507STova Mussai while (!sband && i < NUM_NL80211_BANDS) 1239dd36a507STova Mussai sband = mvm->hw->wiphy->bands[i++]; 1240dd36a507STova Mussai 1241dd36a507STova Mussai if (WARN_ON_ONCE(!sband)) 1242dd36a507STova Mussai goto error; 1243dd36a507STova Mussai 1244dd36a507STova Mussai chan = &sband->channels[0]; 1245dd36a507STova Mussai 1246e705c121SKalle Valo cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); 1247e705c121SKalle Valo for (i = 0; i < NUM_PHY_CTX; i++) { 1248e705c121SKalle Valo /* 1249e705c121SKalle Valo * The channel used here isn't relevant as it's 1250e705c121SKalle Valo * going to be overwritten in the other flows. 1251e705c121SKalle Valo * For now use the first channel we have. 1252e705c121SKalle Valo */ 1253e705c121SKalle Valo ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], 1254e705c121SKalle Valo &chandef, 1, 1); 1255e705c121SKalle Valo if (ret) 1256e705c121SKalle Valo goto error; 1257e705c121SKalle Valo } 1258e705c121SKalle Valo 1259c221daf2SChaya Rachel Ivgi if (iwl_mvm_is_tt_in_fw(mvm)) { 1260c221daf2SChaya Rachel Ivgi /* in order to give the responsibility of ct-kill and 1261c221daf2SChaya Rachel Ivgi * TX backoff to FW we need to send empty temperature reporting 1262c221daf2SChaya Rachel Ivgi * cmd during init time 1263c221daf2SChaya Rachel Ivgi */ 1264c221daf2SChaya Rachel Ivgi iwl_mvm_send_temp_report_ths_cmd(mvm); 1265c221daf2SChaya Rachel Ivgi } else { 1266e705c121SKalle Valo /* Initialize tx backoffs to the minimal possible */ 1267e705c121SKalle Valo iwl_mvm_tt_tx_backoff(mvm, 0); 1268c221daf2SChaya Rachel Ivgi } 12695c89e7bcSChaya Rachel Ivgi 1270242d9c8bSJohannes Berg #ifdef CONFIG_THERMAL 12715c89e7bcSChaya Rachel Ivgi /* TODO: read the budget from BIOS / Platform NVM */ 1272944eafc2SChaya Rachel Ivgi 1273944eafc2SChaya Rachel Ivgi /* 1274944eafc2SChaya Rachel Ivgi * In case there is no budget from BIOS / Platform NVM the default 1275944eafc2SChaya Rachel Ivgi * budget should be 2000mW (cooling state 0). 1276944eafc2SChaya Rachel Ivgi */ 1277944eafc2SChaya Rachel Ivgi if (iwl_mvm_is_ctdp_supported(mvm)) { 12785c89e7bcSChaya Rachel Ivgi ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START, 12795c89e7bcSChaya Rachel Ivgi mvm->cooling_dev.cur_state); 128075cfe338SLuca Coelho if (ret) 128175cfe338SLuca Coelho goto error; 128275cfe338SLuca Coelho } 1283c221daf2SChaya Rachel Ivgi #endif 1284e705c121SKalle Valo 1285aa43ae12SAlex Malamud if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2)) 1286e705c121SKalle Valo WARN_ON(iwl_mvm_config_ltr(mvm)); 1287e705c121SKalle Valo 1288e705c121SKalle Valo ret = iwl_mvm_power_update_device(mvm); 1289e705c121SKalle Valo if (ret) 1290e705c121SKalle Valo goto error; 1291e705c121SKalle Valo 1292e705c121SKalle Valo /* 1293e705c121SKalle Valo * RTNL is not taken during Ct-kill, but we don't need to scan/Tx 1294e705c121SKalle Valo * anyway, so don't init MCC. 1295e705c121SKalle Valo */ 1296e705c121SKalle Valo if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { 1297e705c121SKalle Valo ret = iwl_mvm_init_mcc(mvm); 1298e705c121SKalle Valo if (ret) 1299e705c121SKalle Valo goto error; 1300e705c121SKalle Valo } 1301e705c121SKalle Valo 1302e705c121SKalle Valo if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { 13034ca87a5fSEmmanuel Grumbach mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; 1304b66b5817SSara Sharon mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET; 1305e705c121SKalle Valo ret = iwl_mvm_config_scan(mvm); 1306e705c121SKalle Valo if (ret) 1307e705c121SKalle Valo goto error; 1308e705c121SKalle Valo } 1309e705c121SKalle Valo 1310f130bb75SMordechay Goodstein if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) 1311f130bb75SMordechay Goodstein iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB); 1312f130bb75SMordechay Goodstein 131348e775e6SHaim Dreyfuss if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid)) 131448e775e6SHaim Dreyfuss IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n"); 131548e775e6SHaim Dreyfuss 13166ce1e5c0SGil Adam ret = iwl_mvm_ppag_init(mvm); 13176ce1e5c0SGil Adam if (ret) 13186ce1e5c0SGil Adam goto error; 13196ce1e5c0SGil Adam 1320da2830acSLuca Coelho ret = iwl_mvm_sar_init(mvm); 13215d041c46SLuca Coelho if (ret == 0) { 1322a6bff3cbSHaim Dreyfuss ret = iwl_mvm_sar_geo_init(mvm); 132339c1a972SIhab Zhaika } else if (ret > 0 && !iwl_sar_get_wgds_table(&mvm->fwrt)) { 13245d041c46SLuca Coelho /* 13255d041c46SLuca Coelho * If basic SAR is not available, we check for WGDS, 13265d041c46SLuca Coelho * which should *not* be available either. If it is 13275d041c46SLuca Coelho * available, issue an error, because we can't use SAR 13285d041c46SLuca Coelho * Geo without basic SAR. 13295d041c46SLuca Coelho */ 13305d041c46SLuca Coelho IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n"); 13315d041c46SLuca Coelho } 13325d041c46SLuca Coelho 13335d041c46SLuca Coelho if (ret < 0) 1334a6bff3cbSHaim Dreyfuss goto error; 1335a6bff3cbSHaim Dreyfuss 13367089ae63SJohannes Berg iwl_mvm_leds_sync(mvm); 13377089ae63SJohannes Berg 1338e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); 1339e705c121SKalle Valo return 0; 1340e705c121SKalle Valo error: 1341f4744258SLiad Kaufman if (!iwlmvm_mod_params.init_dbg || !ret) 1342fcb6b92aSChaya Rachel Ivgi iwl_mvm_stop_device(mvm); 1343e705c121SKalle Valo return ret; 1344e705c121SKalle Valo } 1345e705c121SKalle Valo 1346e705c121SKalle Valo int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) 1347e705c121SKalle Valo { 1348e705c121SKalle Valo int ret, i; 1349e705c121SKalle Valo 1350e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 1351e705c121SKalle Valo 1352e705c121SKalle Valo ret = iwl_trans_start_hw(mvm->trans); 1353e705c121SKalle Valo if (ret) 1354e705c121SKalle Valo return ret; 1355e705c121SKalle Valo 1356e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); 1357e705c121SKalle Valo if (ret) { 1358e705c121SKalle Valo IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); 1359e705c121SKalle Valo goto error; 1360e705c121SKalle Valo } 1361e705c121SKalle Valo 1362e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 1363e705c121SKalle Valo if (ret) 1364e705c121SKalle Valo goto error; 1365e705c121SKalle Valo 1366e705c121SKalle Valo /* Send phy db control command and then phy db calibration*/ 1367e705c121SKalle Valo ret = iwl_send_phy_db_data(mvm->phy_db); 1368e705c121SKalle Valo if (ret) 1369e705c121SKalle Valo goto error; 1370e705c121SKalle Valo 1371e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 1372e705c121SKalle Valo if (ret) 1373e705c121SKalle Valo goto error; 1374e705c121SKalle Valo 1375e705c121SKalle Valo /* init the fw <-> mac80211 STA mapping */ 13760ae98812SSara Sharon for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++) 1377e705c121SKalle Valo RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); 1378e705c121SKalle Valo 1379e705c121SKalle Valo /* Add auxiliary station for scanning */ 1380e705c121SKalle Valo ret = iwl_mvm_add_aux_sta(mvm); 1381e705c121SKalle Valo if (ret) 1382e705c121SKalle Valo goto error; 1383e705c121SKalle Valo 1384e705c121SKalle Valo return 0; 1385e705c121SKalle Valo error: 1386fcb6b92aSChaya Rachel Ivgi iwl_mvm_stop_device(mvm); 1387e705c121SKalle Valo return ret; 1388e705c121SKalle Valo } 1389e705c121SKalle Valo 1390e705c121SKalle Valo void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, 1391e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1392e705c121SKalle Valo { 1393e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1394e705c121SKalle Valo struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; 1395e705c121SKalle Valo u32 flags = le32_to_cpu(card_state_notif->flags); 1396e705c121SKalle Valo 1397e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", 1398e705c121SKalle Valo (flags & HW_CARD_DISABLED) ? "Kill" : "On", 1399e705c121SKalle Valo (flags & SW_CARD_DISABLED) ? "Kill" : "On", 1400e705c121SKalle Valo (flags & CT_KILL_CARD_DISABLED) ? 1401e705c121SKalle Valo "Reached" : "Not reached"); 1402e705c121SKalle Valo } 1403e705c121SKalle Valo 1404e705c121SKalle Valo void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, 1405e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1406e705c121SKalle Valo { 1407e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1408e705c121SKalle Valo struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; 1409e705c121SKalle Valo 1410e705c121SKalle Valo IWL_DEBUG_INFO(mvm, 1411e705c121SKalle Valo "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", 1412e705c121SKalle Valo le32_to_cpu(mfuart_notif->installed_ver), 1413e705c121SKalle Valo le32_to_cpu(mfuart_notif->external_ver), 1414e705c121SKalle Valo le32_to_cpu(mfuart_notif->status), 1415e705c121SKalle Valo le32_to_cpu(mfuart_notif->duration)); 14160c8d0a47SGolan Ben-Ami 14170c8d0a47SGolan Ben-Ami if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif)) 14180c8d0a47SGolan Ben-Ami IWL_DEBUG_INFO(mvm, 14190c8d0a47SGolan Ben-Ami "MFUART: image size: 0x%08x\n", 14200c8d0a47SGolan Ben-Ami le32_to_cpu(mfuart_notif->image_size)); 1421e705c121SKalle Valo } 1422