1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 1043413a97SSara Sharon * Copyright(c) 2016 Intel Deutschland GmbH 11e705c121SKalle Valo * 12e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 13e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 14e705c121SKalle Valo * published by the Free Software Foundation. 15e705c121SKalle Valo * 16e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 17e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 18e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19e705c121SKalle Valo * General Public License for more details. 20e705c121SKalle Valo * 21e705c121SKalle Valo * You should have received a copy of the GNU General Public License 22e705c121SKalle Valo * along with this program; if not, write to the Free Software 23e705c121SKalle Valo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24e705c121SKalle Valo * USA 25e705c121SKalle Valo * 26e705c121SKalle Valo * The full GNU General Public License is included in this distribution 27e705c121SKalle Valo * in the file called COPYING. 28e705c121SKalle Valo * 29e705c121SKalle Valo * Contact Information: 30cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 31e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32e705c121SKalle Valo * 33e705c121SKalle Valo * BSD LICENSE 34e705c121SKalle Valo * 35e705c121SKalle Valo * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 36e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 37e705c121SKalle Valo * All rights reserved. 38e705c121SKalle Valo * 39e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 40e705c121SKalle Valo * modification, are permitted provided that the following conditions 41e705c121SKalle Valo * are met: 42e705c121SKalle Valo * 43e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 45e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 46e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 47e705c121SKalle Valo * the documentation and/or other materials provided with the 48e705c121SKalle Valo * distribution. 49e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 50e705c121SKalle Valo * contributors may be used to endorse or promote products derived 51e705c121SKalle Valo * from this software without specific prior written permission. 52e705c121SKalle Valo * 53e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64e705c121SKalle Valo * 65e705c121SKalle Valo *****************************************************************************/ 66e705c121SKalle Valo #include <net/mac80211.h> 67854d773eSSara Sharon #include <linux/netdevice.h> 68e705c121SKalle Valo 69e705c121SKalle Valo #include "iwl-trans.h" 70e705c121SKalle Valo #include "iwl-op-mode.h" 71e705c121SKalle Valo #include "iwl-fw.h" 72e705c121SKalle Valo #include "iwl-debug.h" 73e705c121SKalle Valo #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ 74e705c121SKalle Valo #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ 75e705c121SKalle Valo #include "iwl-prph.h" 76e705c121SKalle Valo #include "iwl-eeprom-parse.h" 77e705c121SKalle Valo 78e705c121SKalle Valo #include "mvm.h" 792f89a5d7SGolan Ben-Ami #include "fw-dbg.h" 80e705c121SKalle Valo #include "iwl-phy-db.h" 81e705c121SKalle Valo 82e705c121SKalle Valo #define MVM_UCODE_ALIVE_TIMEOUT HZ 83e705c121SKalle Valo #define MVM_UCODE_CALIB_TIMEOUT (2*HZ) 84e705c121SKalle Valo 85e705c121SKalle Valo #define UCODE_VALID_OK cpu_to_le32(0x1) 86e705c121SKalle Valo 87e705c121SKalle Valo struct iwl_mvm_alive_data { 88e705c121SKalle Valo bool valid; 89e705c121SKalle Valo u32 scd_base_addr; 90e705c121SKalle Valo }; 91e705c121SKalle Valo 92e705c121SKalle Valo static inline const struct fw_img * 93e705c121SKalle Valo iwl_get_ucode_image(struct iwl_mvm *mvm, enum iwl_ucode_type ucode_type) 94e705c121SKalle Valo { 95e705c121SKalle Valo if (ucode_type >= IWL_UCODE_TYPE_MAX) 96e705c121SKalle Valo return NULL; 97e705c121SKalle Valo 98e705c121SKalle Valo return &mvm->fw->img[ucode_type]; 99e705c121SKalle Valo } 100e705c121SKalle Valo 101e705c121SKalle Valo static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) 102e705c121SKalle Valo { 103e705c121SKalle Valo struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { 104e705c121SKalle Valo .valid = cpu_to_le32(valid_tx_ant), 105e705c121SKalle Valo }; 106e705c121SKalle Valo 107e705c121SKalle Valo IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); 108e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, 109e705c121SKalle Valo sizeof(tx_ant_cmd), &tx_ant_cmd); 110e705c121SKalle Valo } 111e705c121SKalle Valo 11243413a97SSara Sharon static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm) 11343413a97SSara Sharon { 11443413a97SSara Sharon int i; 11543413a97SSara Sharon struct iwl_rss_config_cmd cmd = { 11643413a97SSara Sharon .flags = cpu_to_le32(IWL_RSS_ENABLE), 11743413a97SSara Sharon .hash_mask = IWL_RSS_HASH_TYPE_IPV4_TCP | 118854d773eSSara Sharon IWL_RSS_HASH_TYPE_IPV4_UDP | 11943413a97SSara Sharon IWL_RSS_HASH_TYPE_IPV4_PAYLOAD | 12043413a97SSara Sharon IWL_RSS_HASH_TYPE_IPV6_TCP | 121854d773eSSara Sharon IWL_RSS_HASH_TYPE_IPV6_UDP | 12243413a97SSara Sharon IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 12343413a97SSara Sharon }; 12443413a97SSara Sharon 125f43495fdSSara Sharon if (mvm->trans->num_rx_queues == 1) 126f43495fdSSara Sharon return 0; 127f43495fdSSara Sharon 128854d773eSSara Sharon /* Do not direct RSS traffic to Q 0 which is our fallback queue */ 12943413a97SSara Sharon for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++) 130854d773eSSara Sharon cmd.indirection_table[i] = 131854d773eSSara Sharon 1 + (i % (mvm->trans->num_rx_queues - 1)); 132854d773eSSara Sharon netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key)); 13343413a97SSara Sharon 13443413a97SSara Sharon return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd); 13543413a97SSara Sharon } 13643413a97SSara Sharon 13797d5be7eSLiad Kaufman static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm) 13897d5be7eSLiad Kaufman { 13997d5be7eSLiad Kaufman struct iwl_dqa_enable_cmd dqa_cmd = { 14097d5be7eSLiad Kaufman .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE), 14197d5be7eSLiad Kaufman }; 14297d5be7eSLiad Kaufman u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0); 14397d5be7eSLiad Kaufman int ret; 14497d5be7eSLiad Kaufman 14597d5be7eSLiad Kaufman ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); 14697d5be7eSLiad Kaufman if (ret) 14797d5be7eSLiad Kaufman IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret); 14897d5be7eSLiad Kaufman else 14997d5be7eSLiad Kaufman IWL_DEBUG_FW(mvm, "Working in DQA mode\n"); 15097d5be7eSLiad Kaufman 15197d5be7eSLiad Kaufman return ret; 15297d5be7eSLiad Kaufman } 15397d5be7eSLiad Kaufman 154905e36aeSMatti Gottlieb void iwl_free_fw_paging(struct iwl_mvm *mvm) 155e705c121SKalle Valo { 156e705c121SKalle Valo int i; 157e705c121SKalle Valo 158e705c121SKalle Valo if (!mvm->fw_paging_db[0].fw_paging_block) 159e705c121SKalle Valo return; 160e705c121SKalle Valo 161e705c121SKalle Valo for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) { 162e705c121SKalle Valo if (!mvm->fw_paging_db[i].fw_paging_block) { 163e705c121SKalle Valo IWL_DEBUG_FW(mvm, 164e705c121SKalle Valo "Paging: block %d already freed, continue to next page\n", 165e705c121SKalle Valo i); 166e705c121SKalle Valo 167e705c121SKalle Valo continue; 168e705c121SKalle Valo } 169e705c121SKalle Valo 170e705c121SKalle Valo __free_pages(mvm->fw_paging_db[i].fw_paging_block, 171e705c121SKalle Valo get_order(mvm->fw_paging_db[i].fw_paging_size)); 172f742aaf3SMatti Gottlieb mvm->fw_paging_db[i].fw_paging_block = NULL; 173e705c121SKalle Valo } 174e705c121SKalle Valo kfree(mvm->trans->paging_download_buf); 175905e36aeSMatti Gottlieb mvm->trans->paging_download_buf = NULL; 176f742aaf3SMatti Gottlieb mvm->trans->paging_db = NULL; 177905e36aeSMatti Gottlieb 178e705c121SKalle Valo memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db)); 179e705c121SKalle Valo } 180e705c121SKalle Valo 181e705c121SKalle Valo static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image) 182e705c121SKalle Valo { 183e705c121SKalle Valo int sec_idx, idx; 184e705c121SKalle Valo u32 offset = 0; 185e705c121SKalle Valo 186e705c121SKalle Valo /* 187e705c121SKalle Valo * find where is the paging image start point: 188e705c121SKalle Valo * if CPU2 exist and it's in paging format, then the image looks like: 189e705c121SKalle Valo * CPU1 sections (2 or more) 190e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2 191e705c121SKalle Valo * CPU2 sections (not paged) 192e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2 193e705c121SKalle Valo * non paged to CPU2 paging sec 194e705c121SKalle Valo * CPU2 paging CSS 195e705c121SKalle Valo * CPU2 paging image (including instruction and data) 196e705c121SKalle Valo */ 197e705c121SKalle Valo for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) { 198e705c121SKalle Valo if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) { 199e705c121SKalle Valo sec_idx++; 200e705c121SKalle Valo break; 201e705c121SKalle Valo } 202e705c121SKalle Valo } 203e705c121SKalle Valo 204cd47a3d3SMatti Gottlieb /* 205cd47a3d3SMatti Gottlieb * If paging is enabled there should be at least 2 more sections left 206cd47a3d3SMatti Gottlieb * (one for CSS and one for Paging data) 207cd47a3d3SMatti Gottlieb */ 208cd47a3d3SMatti Gottlieb if (sec_idx >= ARRAY_SIZE(image->sec) - 1) { 209cd47a3d3SMatti Gottlieb IWL_ERR(mvm, "Paging: Missing CSS and/or paging sections\n"); 210e705c121SKalle Valo iwl_free_fw_paging(mvm); 211e705c121SKalle Valo return -EINVAL; 212e705c121SKalle Valo } 213e705c121SKalle Valo 214e705c121SKalle Valo /* copy the CSS block to the dram */ 215e705c121SKalle Valo IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n", 216e705c121SKalle Valo sec_idx); 217e705c121SKalle Valo 218e705c121SKalle Valo memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block), 219e705c121SKalle Valo image->sec[sec_idx].data, 220e705c121SKalle Valo mvm->fw_paging_db[0].fw_paging_size); 221e705c121SKalle Valo 222e705c121SKalle Valo IWL_DEBUG_FW(mvm, 223e705c121SKalle Valo "Paging: copied %d CSS bytes to first block\n", 224e705c121SKalle Valo mvm->fw_paging_db[0].fw_paging_size); 225e705c121SKalle Valo 226e705c121SKalle Valo sec_idx++; 227e705c121SKalle Valo 228e705c121SKalle Valo /* 229e705c121SKalle Valo * copy the paging blocks to the dram 230e705c121SKalle Valo * loop index start from 1 since that CSS block already copied to dram 231e705c121SKalle Valo * and CSS index is 0. 232e705c121SKalle Valo * loop stop at num_of_paging_blk since that last block is not full. 233e705c121SKalle Valo */ 234e705c121SKalle Valo for (idx = 1; idx < mvm->num_of_paging_blk; idx++) { 235e705c121SKalle Valo memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), 236e705c121SKalle Valo image->sec[sec_idx].data + offset, 237e705c121SKalle Valo mvm->fw_paging_db[idx].fw_paging_size); 238e705c121SKalle Valo 239e705c121SKalle Valo IWL_DEBUG_FW(mvm, 240e705c121SKalle Valo "Paging: copied %d paging bytes to block %d\n", 241e705c121SKalle Valo mvm->fw_paging_db[idx].fw_paging_size, 242e705c121SKalle Valo idx); 243e705c121SKalle Valo 244e705c121SKalle Valo offset += mvm->fw_paging_db[idx].fw_paging_size; 245e705c121SKalle Valo } 246e705c121SKalle Valo 247e705c121SKalle Valo /* copy the last paging block */ 248e705c121SKalle Valo if (mvm->num_of_pages_in_last_blk > 0) { 249e705c121SKalle Valo memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block), 250e705c121SKalle Valo image->sec[sec_idx].data + offset, 251e705c121SKalle Valo FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk); 252e705c121SKalle Valo 253e705c121SKalle Valo IWL_DEBUG_FW(mvm, 254e705c121SKalle Valo "Paging: copied %d pages in the last block %d\n", 255e705c121SKalle Valo mvm->num_of_pages_in_last_blk, idx); 256e705c121SKalle Valo } 257e705c121SKalle Valo 258e705c121SKalle Valo return 0; 259e705c121SKalle Valo } 260e705c121SKalle Valo 261e705c121SKalle Valo static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm, 262e705c121SKalle Valo const struct fw_img *image) 263e705c121SKalle Valo { 264e705c121SKalle Valo struct page *block; 265e705c121SKalle Valo dma_addr_t phys = 0; 266e705c121SKalle Valo int blk_idx = 0; 267e705c121SKalle Valo int order, num_of_pages; 268e705c121SKalle Valo int dma_enabled; 269e705c121SKalle Valo 270e705c121SKalle Valo if (mvm->fw_paging_db[0].fw_paging_block) 271e705c121SKalle Valo return 0; 272e705c121SKalle Valo 273e705c121SKalle Valo dma_enabled = is_device_dma_capable(mvm->trans->dev); 274e705c121SKalle Valo 275e705c121SKalle Valo /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */ 276e705c121SKalle Valo BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE); 277e705c121SKalle Valo 278e705c121SKalle Valo num_of_pages = image->paging_mem_size / FW_PAGING_SIZE; 279e705c121SKalle Valo mvm->num_of_paging_blk = ((num_of_pages - 1) / 280e705c121SKalle Valo NUM_OF_PAGE_PER_GROUP) + 1; 281e705c121SKalle Valo 282e705c121SKalle Valo mvm->num_of_pages_in_last_blk = 283e705c121SKalle Valo num_of_pages - 284e705c121SKalle Valo NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1); 285e705c121SKalle Valo 286e705c121SKalle Valo IWL_DEBUG_FW(mvm, 287e705c121SKalle Valo "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n", 288e705c121SKalle Valo mvm->num_of_paging_blk, 289e705c121SKalle Valo mvm->num_of_pages_in_last_blk); 290e705c121SKalle Valo 291e705c121SKalle Valo /* allocate block of 4Kbytes for paging CSS */ 292e705c121SKalle Valo order = get_order(FW_PAGING_SIZE); 293e705c121SKalle Valo block = alloc_pages(GFP_KERNEL, order); 294e705c121SKalle Valo if (!block) { 295e705c121SKalle Valo /* free all the previous pages since we failed */ 296e705c121SKalle Valo iwl_free_fw_paging(mvm); 297e705c121SKalle Valo return -ENOMEM; 298e705c121SKalle Valo } 299e705c121SKalle Valo 300e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_block = block; 301e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE; 302e705c121SKalle Valo 303e705c121SKalle Valo if (dma_enabled) { 304e705c121SKalle Valo phys = dma_map_page(mvm->trans->dev, block, 0, 305e705c121SKalle Valo PAGE_SIZE << order, DMA_BIDIRECTIONAL); 306e705c121SKalle Valo if (dma_mapping_error(mvm->trans->dev, phys)) { 307e705c121SKalle Valo /* 308e705c121SKalle Valo * free the previous pages and the current one since 309e705c121SKalle Valo * we failed to map_page. 310e705c121SKalle Valo */ 311e705c121SKalle Valo iwl_free_fw_paging(mvm); 312e705c121SKalle Valo return -ENOMEM; 313e705c121SKalle Valo } 314e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; 315e705c121SKalle Valo } else { 316e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG | 317e705c121SKalle Valo blk_idx << BLOCK_2_EXP_SIZE; 318e705c121SKalle Valo } 319e705c121SKalle Valo 320e705c121SKalle Valo IWL_DEBUG_FW(mvm, 321e705c121SKalle Valo "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n", 322e705c121SKalle Valo order); 323e705c121SKalle Valo 324e705c121SKalle Valo /* 325e705c121SKalle Valo * allocate blocks in dram. 326e705c121SKalle Valo * since that CSS allocated in fw_paging_db[0] loop start from index 1 327e705c121SKalle Valo */ 328e705c121SKalle Valo for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { 329e705c121SKalle Valo /* allocate block of PAGING_BLOCK_SIZE (32K) */ 330e705c121SKalle Valo order = get_order(PAGING_BLOCK_SIZE); 331e705c121SKalle Valo block = alloc_pages(GFP_KERNEL, order); 332e705c121SKalle Valo if (!block) { 333e705c121SKalle Valo /* free all the previous pages since we failed */ 334e705c121SKalle Valo iwl_free_fw_paging(mvm); 335e705c121SKalle Valo return -ENOMEM; 336e705c121SKalle Valo } 337e705c121SKalle Valo 338e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_block = block; 339e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE; 340e705c121SKalle Valo 341e705c121SKalle Valo if (dma_enabled) { 342e705c121SKalle Valo phys = dma_map_page(mvm->trans->dev, block, 0, 343e705c121SKalle Valo PAGE_SIZE << order, 344e705c121SKalle Valo DMA_BIDIRECTIONAL); 345e705c121SKalle Valo if (dma_mapping_error(mvm->trans->dev, phys)) { 346e705c121SKalle Valo /* 347e705c121SKalle Valo * free the previous pages and the current one 348e705c121SKalle Valo * since we failed to map_page. 349e705c121SKalle Valo */ 350e705c121SKalle Valo iwl_free_fw_paging(mvm); 351e705c121SKalle Valo return -ENOMEM; 352e705c121SKalle Valo } 353e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_phys = phys; 354e705c121SKalle Valo } else { 355e705c121SKalle Valo mvm->fw_paging_db[blk_idx].fw_paging_phys = 356e705c121SKalle Valo PAGING_ADDR_SIG | 357e705c121SKalle Valo blk_idx << BLOCK_2_EXP_SIZE; 358e705c121SKalle Valo } 359e705c121SKalle Valo 360e705c121SKalle Valo IWL_DEBUG_FW(mvm, 361e705c121SKalle Valo "Paging: allocated 32K bytes (order %d) for firmware paging.\n", 362e705c121SKalle Valo order); 363e705c121SKalle Valo } 364e705c121SKalle Valo 365e705c121SKalle Valo return 0; 366e705c121SKalle Valo } 367e705c121SKalle Valo 368e705c121SKalle Valo static int iwl_save_fw_paging(struct iwl_mvm *mvm, 369e705c121SKalle Valo const struct fw_img *fw) 370e705c121SKalle Valo { 371e705c121SKalle Valo int ret; 372e705c121SKalle Valo 373e705c121SKalle Valo ret = iwl_alloc_fw_paging_mem(mvm, fw); 374e705c121SKalle Valo if (ret) 375e705c121SKalle Valo return ret; 376e705c121SKalle Valo 377e705c121SKalle Valo return iwl_fill_paging_mem(mvm, fw); 378e705c121SKalle Valo } 379e705c121SKalle Valo 380e705c121SKalle Valo /* send paging cmd to FW in case CPU2 has paging image */ 381e705c121SKalle Valo static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw) 382e705c121SKalle Valo { 383e705c121SKalle Valo int blk_idx; 384e705c121SKalle Valo __le32 dev_phy_addr; 385e705c121SKalle Valo struct iwl_fw_paging_cmd fw_paging_cmd = { 386e705c121SKalle Valo .flags = 387e705c121SKalle Valo cpu_to_le32(PAGING_CMD_IS_SECURED | 388e705c121SKalle Valo PAGING_CMD_IS_ENABLED | 389e705c121SKalle Valo (mvm->num_of_pages_in_last_blk << 390e705c121SKalle Valo PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)), 391e705c121SKalle Valo .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE), 392e705c121SKalle Valo .block_num = cpu_to_le32(mvm->num_of_paging_blk), 393e705c121SKalle Valo }; 394e705c121SKalle Valo 395e705c121SKalle Valo /* loop for for all paging blocks + CSS block */ 396e705c121SKalle Valo for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) { 397e705c121SKalle Valo dev_phy_addr = 398e705c121SKalle Valo cpu_to_le32(mvm->fw_paging_db[blk_idx].fw_paging_phys >> 399e705c121SKalle Valo PAGE_2_EXP_SIZE); 400e705c121SKalle Valo fw_paging_cmd.device_phy_addr[blk_idx] = dev_phy_addr; 401e705c121SKalle Valo } 402e705c121SKalle Valo 403e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD, 404e705c121SKalle Valo IWL_ALWAYS_LONG_GROUP, 0), 405e705c121SKalle Valo 0, sizeof(fw_paging_cmd), &fw_paging_cmd); 406e705c121SKalle Valo } 407e705c121SKalle Valo 408e705c121SKalle Valo /* 409e705c121SKalle Valo * Send paging item cmd to FW in case CPU2 has paging image 410e705c121SKalle Valo */ 411e705c121SKalle Valo static int iwl_trans_get_paging_item(struct iwl_mvm *mvm) 412e705c121SKalle Valo { 413e705c121SKalle Valo int ret; 414e705c121SKalle Valo struct iwl_fw_get_item_cmd fw_get_item_cmd = { 415e705c121SKalle Valo .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING), 416e705c121SKalle Valo }; 417e705c121SKalle Valo 418e705c121SKalle Valo struct iwl_fw_get_item_resp *item_resp; 419e705c121SKalle Valo struct iwl_host_cmd cmd = { 420e705c121SKalle Valo .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0), 421e705c121SKalle Valo .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 422e705c121SKalle Valo .data = { &fw_get_item_cmd, }, 423e705c121SKalle Valo }; 424e705c121SKalle Valo 425e705c121SKalle Valo cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd); 426e705c121SKalle Valo 427e705c121SKalle Valo ret = iwl_mvm_send_cmd(mvm, &cmd); 428e705c121SKalle Valo if (ret) { 429e705c121SKalle Valo IWL_ERR(mvm, 430e705c121SKalle Valo "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n", 431e705c121SKalle Valo ret); 432e705c121SKalle Valo return ret; 433e705c121SKalle Valo } 434e705c121SKalle Valo 435e705c121SKalle Valo item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data; 436e705c121SKalle Valo if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) { 437e705c121SKalle Valo IWL_ERR(mvm, 438e705c121SKalle Valo "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n", 439e705c121SKalle Valo le32_to_cpu(item_resp->item_id)); 440e705c121SKalle Valo ret = -EIO; 441e705c121SKalle Valo goto exit; 442e705c121SKalle Valo } 443e705c121SKalle Valo 444c94d7996SMatti Gottlieb /* Add an extra page for headers */ 445c94d7996SMatti Gottlieb mvm->trans->paging_download_buf = kzalloc(PAGING_BLOCK_SIZE + 446c94d7996SMatti Gottlieb FW_PAGING_SIZE, 447e705c121SKalle Valo GFP_KERNEL); 448e705c121SKalle Valo if (!mvm->trans->paging_download_buf) { 449e705c121SKalle Valo ret = -ENOMEM; 450e705c121SKalle Valo goto exit; 451e705c121SKalle Valo } 452e705c121SKalle Valo mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val); 453e705c121SKalle Valo mvm->trans->paging_db = mvm->fw_paging_db; 454e705c121SKalle Valo IWL_DEBUG_FW(mvm, 455e705c121SKalle Valo "Paging: got paging request address (paging_req_addr 0x%08x)\n", 456e705c121SKalle Valo mvm->trans->paging_req_addr); 457e705c121SKalle Valo 458e705c121SKalle Valo exit: 459e705c121SKalle Valo iwl_free_resp(&cmd); 460e705c121SKalle Valo 461e705c121SKalle Valo return ret; 462e705c121SKalle Valo } 463e705c121SKalle Valo 464e705c121SKalle Valo static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, 465e705c121SKalle Valo struct iwl_rx_packet *pkt, void *data) 466e705c121SKalle Valo { 467e705c121SKalle Valo struct iwl_mvm *mvm = 468e705c121SKalle Valo container_of(notif_wait, struct iwl_mvm, notif_wait); 469e705c121SKalle Valo struct iwl_mvm_alive_data *alive_data = data; 470e705c121SKalle Valo struct mvm_alive_resp_ver1 *palive1; 471e705c121SKalle Valo struct mvm_alive_resp_ver2 *palive2; 472e705c121SKalle Valo struct mvm_alive_resp *palive; 473e705c121SKalle Valo 474e705c121SKalle Valo if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) { 475e705c121SKalle Valo palive1 = (void *)pkt->data; 476e705c121SKalle Valo 477e705c121SKalle Valo mvm->support_umac_log = false; 478e705c121SKalle Valo mvm->error_event_table = 479e705c121SKalle Valo le32_to_cpu(palive1->error_event_table_ptr); 480e705c121SKalle Valo mvm->log_event_table = 481e705c121SKalle Valo le32_to_cpu(palive1->log_event_table_ptr); 482e705c121SKalle Valo alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr); 483e705c121SKalle Valo 484e705c121SKalle Valo alive_data->valid = le16_to_cpu(palive1->status) == 485e705c121SKalle Valo IWL_ALIVE_STATUS_OK; 486e705c121SKalle Valo IWL_DEBUG_FW(mvm, 487e705c121SKalle Valo "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", 488e705c121SKalle Valo le16_to_cpu(palive1->status), palive1->ver_type, 489e705c121SKalle Valo palive1->ver_subtype, palive1->flags); 490e705c121SKalle Valo } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) { 491e705c121SKalle Valo palive2 = (void *)pkt->data; 492e705c121SKalle Valo 493e705c121SKalle Valo mvm->error_event_table = 494e705c121SKalle Valo le32_to_cpu(palive2->error_event_table_ptr); 495e705c121SKalle Valo mvm->log_event_table = 496e705c121SKalle Valo le32_to_cpu(palive2->log_event_table_ptr); 497e705c121SKalle Valo alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr); 498e705c121SKalle Valo mvm->umac_error_event_table = 499e705c121SKalle Valo le32_to_cpu(palive2->error_info_addr); 500e705c121SKalle Valo mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr); 501e705c121SKalle Valo mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size); 502e705c121SKalle Valo 503e705c121SKalle Valo alive_data->valid = le16_to_cpu(palive2->status) == 504e705c121SKalle Valo IWL_ALIVE_STATUS_OK; 505e705c121SKalle Valo if (mvm->umac_error_event_table) 506e705c121SKalle Valo mvm->support_umac_log = true; 507e705c121SKalle Valo 508e705c121SKalle Valo IWL_DEBUG_FW(mvm, 509e705c121SKalle Valo "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", 510e705c121SKalle Valo le16_to_cpu(palive2->status), palive2->ver_type, 511e705c121SKalle Valo palive2->ver_subtype, palive2->flags); 512e705c121SKalle Valo 513e705c121SKalle Valo IWL_DEBUG_FW(mvm, 514e705c121SKalle Valo "UMAC version: Major - 0x%x, Minor - 0x%x\n", 515e705c121SKalle Valo palive2->umac_major, palive2->umac_minor); 516e705c121SKalle Valo } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) { 517e705c121SKalle Valo palive = (void *)pkt->data; 518e705c121SKalle Valo 519e705c121SKalle Valo mvm->error_event_table = 520e705c121SKalle Valo le32_to_cpu(palive->error_event_table_ptr); 521e705c121SKalle Valo mvm->log_event_table = 522e705c121SKalle Valo le32_to_cpu(palive->log_event_table_ptr); 523e705c121SKalle Valo alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr); 524e705c121SKalle Valo mvm->umac_error_event_table = 525e705c121SKalle Valo le32_to_cpu(palive->error_info_addr); 526e705c121SKalle Valo mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr); 527e705c121SKalle Valo mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size); 528e705c121SKalle Valo 529e705c121SKalle Valo alive_data->valid = le16_to_cpu(palive->status) == 530e705c121SKalle Valo IWL_ALIVE_STATUS_OK; 531e705c121SKalle Valo if (mvm->umac_error_event_table) 532e705c121SKalle Valo mvm->support_umac_log = true; 533e705c121SKalle Valo 534e705c121SKalle Valo IWL_DEBUG_FW(mvm, 535e705c121SKalle Valo "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n", 536e705c121SKalle Valo le16_to_cpu(palive->status), palive->ver_type, 537e705c121SKalle Valo palive->ver_subtype, palive->flags); 538e705c121SKalle Valo 539e705c121SKalle Valo IWL_DEBUG_FW(mvm, 540e705c121SKalle Valo "UMAC version: Major - 0x%x, Minor - 0x%x\n", 541e705c121SKalle Valo le32_to_cpu(palive->umac_major), 542e705c121SKalle Valo le32_to_cpu(palive->umac_minor)); 543e705c121SKalle Valo } 544e705c121SKalle Valo 545e705c121SKalle Valo return true; 546e705c121SKalle Valo } 547e705c121SKalle Valo 548e705c121SKalle Valo static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, 549e705c121SKalle Valo struct iwl_rx_packet *pkt, void *data) 550e705c121SKalle Valo { 551e705c121SKalle Valo struct iwl_phy_db *phy_db = data; 552e705c121SKalle Valo 553e705c121SKalle Valo if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { 554e705c121SKalle Valo WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); 555e705c121SKalle Valo return true; 556e705c121SKalle Valo } 557e705c121SKalle Valo 558ce1f2778SSara Sharon WARN_ON(iwl_phy_db_set_section(phy_db, pkt)); 559e705c121SKalle Valo 560e705c121SKalle Valo return false; 561e705c121SKalle Valo } 562e705c121SKalle Valo 563e705c121SKalle Valo static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, 564e705c121SKalle Valo enum iwl_ucode_type ucode_type) 565e705c121SKalle Valo { 566e705c121SKalle Valo struct iwl_notification_wait alive_wait; 567e705c121SKalle Valo struct iwl_mvm_alive_data alive_data; 568e705c121SKalle Valo const struct fw_img *fw; 569e705c121SKalle Valo int ret, i; 570e705c121SKalle Valo enum iwl_ucode_type old_type = mvm->cur_ucode; 571e705c121SKalle Valo static const u16 alive_cmd[] = { MVM_ALIVE }; 572e705c121SKalle Valo struct iwl_sf_region st_fwrd_space; 573e705c121SKalle Valo 574e705c121SKalle Valo if (ucode_type == IWL_UCODE_REGULAR && 5753d2d4422SGolan Ben-Ami iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) && 5763d2d4422SGolan Ben-Ami !(fw_has_capa(&mvm->fw->ucode_capa, 5773d2d4422SGolan Ben-Ami IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED))) 578e705c121SKalle Valo fw = iwl_get_ucode_image(mvm, IWL_UCODE_REGULAR_USNIFFER); 579e705c121SKalle Valo else 580e705c121SKalle Valo fw = iwl_get_ucode_image(mvm, ucode_type); 581e705c121SKalle Valo if (WARN_ON(!fw)) 582e705c121SKalle Valo return -EINVAL; 583e705c121SKalle Valo mvm->cur_ucode = ucode_type; 584e705c121SKalle Valo mvm->ucode_loaded = false; 585e705c121SKalle Valo 586e705c121SKalle Valo iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, 587e705c121SKalle Valo alive_cmd, ARRAY_SIZE(alive_cmd), 588e705c121SKalle Valo iwl_alive_fn, &alive_data); 589e705c121SKalle Valo 590e705c121SKalle Valo ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT); 591e705c121SKalle Valo if (ret) { 592e705c121SKalle Valo mvm->cur_ucode = old_type; 593e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &alive_wait); 594e705c121SKalle Valo return ret; 595e705c121SKalle Valo } 596e705c121SKalle Valo 597e705c121SKalle Valo /* 598e705c121SKalle Valo * Some things may run in the background now, but we 599e705c121SKalle Valo * just wait for the ALIVE notification here. 600e705c121SKalle Valo */ 601e705c121SKalle Valo ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, 602e705c121SKalle Valo MVM_UCODE_ALIVE_TIMEOUT); 603e705c121SKalle Valo if (ret) { 604e705c121SKalle Valo if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 605e705c121SKalle Valo IWL_ERR(mvm, 606e705c121SKalle Valo "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", 607e705c121SKalle Valo iwl_read_prph(mvm->trans, SB_CPU_1_STATUS), 608e705c121SKalle Valo iwl_read_prph(mvm->trans, SB_CPU_2_STATUS)); 609e705c121SKalle Valo mvm->cur_ucode = old_type; 610e705c121SKalle Valo return ret; 611e705c121SKalle Valo } 612e705c121SKalle Valo 613e705c121SKalle Valo if (!alive_data.valid) { 614e705c121SKalle Valo IWL_ERR(mvm, "Loaded ucode is not valid!\n"); 615e705c121SKalle Valo mvm->cur_ucode = old_type; 616e705c121SKalle Valo return -EIO; 617e705c121SKalle Valo } 618e705c121SKalle Valo 619e705c121SKalle Valo /* 620e705c121SKalle Valo * update the sdio allocation according to the pointer we get in the 621e705c121SKalle Valo * alive notification. 622e705c121SKalle Valo */ 623e705c121SKalle Valo st_fwrd_space.addr = mvm->sf_space.addr; 624e705c121SKalle Valo st_fwrd_space.size = mvm->sf_space.size; 625e705c121SKalle Valo ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space); 626e705c121SKalle Valo if (ret) { 627e705c121SKalle Valo IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret); 628e705c121SKalle Valo return ret; 629e705c121SKalle Valo } 630e705c121SKalle Valo 631e705c121SKalle Valo iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); 632e705c121SKalle Valo 633e705c121SKalle Valo /* 634e705c121SKalle Valo * configure and operate fw paging mechanism. 635e705c121SKalle Valo * driver configures the paging flow only once, CPU2 paging image 636e705c121SKalle Valo * included in the IWL_UCODE_INIT image. 637e705c121SKalle Valo */ 638e705c121SKalle Valo if (fw->paging_mem_size) { 639e705c121SKalle Valo /* 640e705c121SKalle Valo * When dma is not enabled, the driver needs to copy / write 641e705c121SKalle Valo * the downloaded / uploaded page to / from the smem. 642e705c121SKalle Valo * This gets the location of the place were the pages are 643e705c121SKalle Valo * stored. 644e705c121SKalle Valo */ 645e705c121SKalle Valo if (!is_device_dma_capable(mvm->trans->dev)) { 646e705c121SKalle Valo ret = iwl_trans_get_paging_item(mvm); 647e705c121SKalle Valo if (ret) { 648e705c121SKalle Valo IWL_ERR(mvm, "failed to get FW paging item\n"); 649e705c121SKalle Valo return ret; 650e705c121SKalle Valo } 651e705c121SKalle Valo } 652e705c121SKalle Valo 653e705c121SKalle Valo ret = iwl_save_fw_paging(mvm, fw); 654e705c121SKalle Valo if (ret) { 655e705c121SKalle Valo IWL_ERR(mvm, "failed to save the FW paging image\n"); 656e705c121SKalle Valo return ret; 657e705c121SKalle Valo } 658e705c121SKalle Valo 659e705c121SKalle Valo ret = iwl_send_paging_cmd(mvm, fw); 660e705c121SKalle Valo if (ret) { 661e705c121SKalle Valo IWL_ERR(mvm, "failed to send the paging cmd\n"); 662e705c121SKalle Valo iwl_free_fw_paging(mvm); 663e705c121SKalle Valo return ret; 664e705c121SKalle Valo } 665e705c121SKalle Valo } 666e705c121SKalle Valo 667e705c121SKalle Valo /* 668e705c121SKalle Valo * Note: all the queues are enabled as part of the interface 669e705c121SKalle Valo * initialization, but in firmware restart scenarios they 670e705c121SKalle Valo * could be stopped, so wake them up. In firmware restart, 671e705c121SKalle Valo * mac80211 will have the queues stopped as well until the 672e705c121SKalle Valo * reconfiguration completes. During normal startup, they 673e705c121SKalle Valo * will be empty. 674e705c121SKalle Valo */ 675e705c121SKalle Valo 676e705c121SKalle Valo memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); 677097129c9SLiad Kaufman if (iwl_mvm_is_dqa_supported(mvm)) 678097129c9SLiad Kaufman mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].hw_queue_refcount = 1; 679097129c9SLiad Kaufman else 680e705c121SKalle Valo mvm->queue_info[IWL_MVM_CMD_QUEUE].hw_queue_refcount = 1; 681e705c121SKalle Valo 682e705c121SKalle Valo for (i = 0; i < IEEE80211_MAX_QUEUES; i++) 683e705c121SKalle Valo atomic_set(&mvm->mac80211_queue_stop_count[i], 0); 684e705c121SKalle Valo 685e705c121SKalle Valo mvm->ucode_loaded = true; 686e705c121SKalle Valo 687e705c121SKalle Valo return 0; 688e705c121SKalle Valo } 689e705c121SKalle Valo 690e705c121SKalle Valo static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) 691e705c121SKalle Valo { 692e705c121SKalle Valo struct iwl_phy_cfg_cmd phy_cfg_cmd; 693e705c121SKalle Valo enum iwl_ucode_type ucode_type = mvm->cur_ucode; 694e705c121SKalle Valo 695e705c121SKalle Valo /* Set parameters */ 696e705c121SKalle Valo phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); 697e705c121SKalle Valo phy_cfg_cmd.calib_control.event_trigger = 698e705c121SKalle Valo mvm->fw->default_calib[ucode_type].event_trigger; 699e705c121SKalle Valo phy_cfg_cmd.calib_control.flow_trigger = 700e705c121SKalle Valo mvm->fw->default_calib[ucode_type].flow_trigger; 701e705c121SKalle Valo 702e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", 703e705c121SKalle Valo phy_cfg_cmd.phy_cfg); 704e705c121SKalle Valo 705e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, 706e705c121SKalle Valo sizeof(phy_cfg_cmd), &phy_cfg_cmd); 707e705c121SKalle Valo } 708e705c121SKalle Valo 709e705c121SKalle Valo int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) 710e705c121SKalle Valo { 711e705c121SKalle Valo struct iwl_notification_wait calib_wait; 712e705c121SKalle Valo static const u16 init_complete[] = { 713e705c121SKalle Valo INIT_COMPLETE_NOTIF, 714e705c121SKalle Valo CALIB_RES_NOTIF_PHY_DB 715e705c121SKalle Valo }; 716e705c121SKalle Valo int ret; 717e705c121SKalle Valo 718e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 719e705c121SKalle Valo 720e705c121SKalle Valo if (WARN_ON_ONCE(mvm->calibrating)) 721e705c121SKalle Valo return 0; 722e705c121SKalle Valo 723e705c121SKalle Valo iwl_init_notification_wait(&mvm->notif_wait, 724e705c121SKalle Valo &calib_wait, 725e705c121SKalle Valo init_complete, 726e705c121SKalle Valo ARRAY_SIZE(init_complete), 727e705c121SKalle Valo iwl_wait_phy_db_entry, 728e705c121SKalle Valo mvm->phy_db); 729e705c121SKalle Valo 730e705c121SKalle Valo /* Will also start the device */ 731e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); 732e705c121SKalle Valo if (ret) { 733e705c121SKalle Valo IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); 734e705c121SKalle Valo goto error; 735e705c121SKalle Valo } 736e705c121SKalle Valo 737e705c121SKalle Valo ret = iwl_send_bt_init_conf(mvm); 738e705c121SKalle Valo if (ret) 739e705c121SKalle Valo goto error; 740e705c121SKalle Valo 741e705c121SKalle Valo /* Read the NVM only at driver load time, no need to do this twice */ 742e705c121SKalle Valo if (read_nvm) { 743e705c121SKalle Valo /* Read nvm */ 744e705c121SKalle Valo ret = iwl_nvm_init(mvm, true); 745e705c121SKalle Valo if (ret) { 746e705c121SKalle Valo IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); 747e705c121SKalle Valo goto error; 748e705c121SKalle Valo } 749e705c121SKalle Valo } 750e705c121SKalle Valo 751e705c121SKalle Valo /* In case we read the NVM from external file, load it to the NIC */ 752e705c121SKalle Valo if (mvm->nvm_file_name) 753e705c121SKalle Valo iwl_mvm_load_nvm_to_nic(mvm); 754e705c121SKalle Valo 755e705c121SKalle Valo ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans); 756e705c121SKalle Valo WARN_ON(ret); 757e705c121SKalle Valo 758e705c121SKalle Valo /* 759e705c121SKalle Valo * abort after reading the nvm in case RF Kill is on, we will complete 760e705c121SKalle Valo * the init seq later when RF kill will switch to off 761e705c121SKalle Valo */ 762e705c121SKalle Valo if (iwl_mvm_is_radio_hw_killed(mvm)) { 763e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, 764e705c121SKalle Valo "jump over all phy activities due to RF kill\n"); 765e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &calib_wait); 766e705c121SKalle Valo ret = 1; 767e705c121SKalle Valo goto out; 768e705c121SKalle Valo } 769e705c121SKalle Valo 770e705c121SKalle Valo mvm->calibrating = true; 771e705c121SKalle Valo 772e705c121SKalle Valo /* Send TX valid antennas before triggering calibrations */ 773e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 774e705c121SKalle Valo if (ret) 775e705c121SKalle Valo goto error; 776e705c121SKalle Valo 777e705c121SKalle Valo /* 778e705c121SKalle Valo * Send phy configurations command to init uCode 779e705c121SKalle Valo * to start the 16.0 uCode init image internal calibrations. 780e705c121SKalle Valo */ 781e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 782e705c121SKalle Valo if (ret) { 783e705c121SKalle Valo IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", 784e705c121SKalle Valo ret); 785e705c121SKalle Valo goto error; 786e705c121SKalle Valo } 787e705c121SKalle Valo 788e705c121SKalle Valo /* 789e705c121SKalle Valo * Some things may run in the background now, but we 790e705c121SKalle Valo * just wait for the calibration complete notification. 791e705c121SKalle Valo */ 792e705c121SKalle Valo ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, 793e705c121SKalle Valo MVM_UCODE_CALIB_TIMEOUT); 794e705c121SKalle Valo 795e705c121SKalle Valo if (ret && iwl_mvm_is_radio_hw_killed(mvm)) { 796e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); 797e705c121SKalle Valo ret = 1; 798e705c121SKalle Valo } 799e705c121SKalle Valo goto out; 800e705c121SKalle Valo 801e705c121SKalle Valo error: 802e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &calib_wait); 803e705c121SKalle Valo out: 804e705c121SKalle Valo mvm->calibrating = false; 805e705c121SKalle Valo if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { 806e705c121SKalle Valo /* we want to debug INIT and we have no NVM - fake */ 807e705c121SKalle Valo mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + 808e705c121SKalle Valo sizeof(struct ieee80211_channel) + 809e705c121SKalle Valo sizeof(struct ieee80211_rate), 810e705c121SKalle Valo GFP_KERNEL); 811e705c121SKalle Valo if (!mvm->nvm_data) 812e705c121SKalle Valo return -ENOMEM; 813e705c121SKalle Valo mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; 814e705c121SKalle Valo mvm->nvm_data->bands[0].n_channels = 1; 815e705c121SKalle Valo mvm->nvm_data->bands[0].n_bitrates = 1; 816e705c121SKalle Valo mvm->nvm_data->bands[0].bitrates = 817e705c121SKalle Valo (void *)mvm->nvm_data->channels + 1; 818e705c121SKalle Valo mvm->nvm_data->bands[0].bitrates->hw_value = 10; 819e705c121SKalle Valo } 820e705c121SKalle Valo 821e705c121SKalle Valo return ret; 822e705c121SKalle Valo } 823e705c121SKalle Valo 824e705c121SKalle Valo static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm) 825e705c121SKalle Valo { 826e705c121SKalle Valo struct iwl_host_cmd cmd = { 827e705c121SKalle Valo .flags = CMD_WANT_SKB, 828e705c121SKalle Valo .data = { NULL, }, 829e705c121SKalle Valo .len = { 0, }, 830e705c121SKalle Valo }; 831e705c121SKalle Valo struct iwl_shared_mem_cfg *mem_cfg; 8325b086414SGolan Ben-Ami struct iwl_rx_packet *pkt; 833e705c121SKalle Valo u32 i; 834e705c121SKalle Valo 835e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 836e705c121SKalle Valo 8375b086414SGolan Ben-Ami if (fw_has_capa(&mvm->fw->ucode_capa, 8385b086414SGolan Ben-Ami IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 8395b086414SGolan Ben-Ami cmd.id = iwl_cmd_id(SHARED_MEM_CFG_CMD, SYSTEM_GROUP, 0); 8405b086414SGolan Ben-Ami else 8415b086414SGolan Ben-Ami cmd.id = SHARED_MEM_CFG; 8425b086414SGolan Ben-Ami 843e705c121SKalle Valo if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd))) 844e705c121SKalle Valo return; 845e705c121SKalle Valo 846e705c121SKalle Valo pkt = cmd.resp_pkt; 847e705c121SKalle Valo mem_cfg = (void *)pkt->data; 848e705c121SKalle Valo 849e705c121SKalle Valo mvm->shared_mem_cfg.shared_mem_addr = 850e705c121SKalle Valo le32_to_cpu(mem_cfg->shared_mem_addr); 851e705c121SKalle Valo mvm->shared_mem_cfg.shared_mem_size = 852e705c121SKalle Valo le32_to_cpu(mem_cfg->shared_mem_size); 853e705c121SKalle Valo mvm->shared_mem_cfg.sample_buff_addr = 854e705c121SKalle Valo le32_to_cpu(mem_cfg->sample_buff_addr); 855e705c121SKalle Valo mvm->shared_mem_cfg.sample_buff_size = 856e705c121SKalle Valo le32_to_cpu(mem_cfg->sample_buff_size); 857e705c121SKalle Valo mvm->shared_mem_cfg.txfifo_addr = le32_to_cpu(mem_cfg->txfifo_addr); 858e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++) 859e705c121SKalle Valo mvm->shared_mem_cfg.txfifo_size[i] = 860e705c121SKalle Valo le32_to_cpu(mem_cfg->txfifo_size[i]); 861e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++) 862e705c121SKalle Valo mvm->shared_mem_cfg.rxfifo_size[i] = 863e705c121SKalle Valo le32_to_cpu(mem_cfg->rxfifo_size[i]); 864e705c121SKalle Valo mvm->shared_mem_cfg.page_buff_addr = 865e705c121SKalle Valo le32_to_cpu(mem_cfg->page_buff_addr); 866e705c121SKalle Valo mvm->shared_mem_cfg.page_buff_size = 867e705c121SKalle Valo le32_to_cpu(mem_cfg->page_buff_size); 8685b086414SGolan Ben-Ami 8695b086414SGolan Ben-Ami /* new API has more data */ 8705b086414SGolan Ben-Ami if (fw_has_capa(&mvm->fw->ucode_capa, 8715b086414SGolan Ben-Ami IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 8725b086414SGolan Ben-Ami mvm->shared_mem_cfg.rxfifo_addr = 8735b086414SGolan Ben-Ami le32_to_cpu(mem_cfg->rxfifo_addr); 8745b086414SGolan Ben-Ami mvm->shared_mem_cfg.internal_txfifo_addr = 8755b086414SGolan Ben-Ami le32_to_cpu(mem_cfg->internal_txfifo_addr); 8765b086414SGolan Ben-Ami 8775b086414SGolan Ben-Ami BUILD_BUG_ON(sizeof(mvm->shared_mem_cfg.internal_txfifo_size) != 8785b086414SGolan Ben-Ami sizeof(mem_cfg->internal_txfifo_size)); 8795b086414SGolan Ben-Ami 8805b086414SGolan Ben-Ami for (i = 0; 8815b086414SGolan Ben-Ami i < ARRAY_SIZE(mvm->shared_mem_cfg.internal_txfifo_size); 8825b086414SGolan Ben-Ami i++) 8835b086414SGolan Ben-Ami mvm->shared_mem_cfg.internal_txfifo_size[i] = 8845b086414SGolan Ben-Ami le32_to_cpu(mem_cfg->internal_txfifo_size[i]); 8855b086414SGolan Ben-Ami } 8865b086414SGolan Ben-Ami 887e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n"); 888e705c121SKalle Valo 889e705c121SKalle Valo iwl_free_resp(&cmd); 890e705c121SKalle Valo } 891e705c121SKalle Valo 892e705c121SKalle Valo static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) 893e705c121SKalle Valo { 894e705c121SKalle Valo struct iwl_ltr_config_cmd cmd = { 895e705c121SKalle Valo .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), 896e705c121SKalle Valo }; 897e705c121SKalle Valo 898e705c121SKalle Valo if (!mvm->trans->ltr_enabled) 899e705c121SKalle Valo return 0; 900e705c121SKalle Valo 901e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, 902e705c121SKalle Valo sizeof(cmd), &cmd); 903e705c121SKalle Valo } 904e705c121SKalle Valo 905e705c121SKalle Valo int iwl_mvm_up(struct iwl_mvm *mvm) 906e705c121SKalle Valo { 907e705c121SKalle Valo int ret, i; 908e705c121SKalle Valo struct ieee80211_channel *chan; 909e705c121SKalle Valo struct cfg80211_chan_def chandef; 910e705c121SKalle Valo 911e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 912e705c121SKalle Valo 913e705c121SKalle Valo ret = iwl_trans_start_hw(mvm->trans); 914e705c121SKalle Valo if (ret) 915e705c121SKalle Valo return ret; 916e705c121SKalle Valo 917e705c121SKalle Valo /* 918e705c121SKalle Valo * If we haven't completed the run of the init ucode during 919e705c121SKalle Valo * module loading, load init ucode now 920e705c121SKalle Valo * (for example, if we were in RFKILL) 921e705c121SKalle Valo */ 922e705c121SKalle Valo ret = iwl_run_init_mvm_ucode(mvm, false); 923e705c121SKalle Valo if (ret && !iwlmvm_mod_params.init_dbg) { 924e705c121SKalle Valo IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); 925e705c121SKalle Valo /* this can't happen */ 926e705c121SKalle Valo if (WARN_ON(ret > 0)) 927e705c121SKalle Valo ret = -ERFKILL; 928e705c121SKalle Valo goto error; 929e705c121SKalle Valo } 930e705c121SKalle Valo if (!iwlmvm_mod_params.init_dbg) { 931e705c121SKalle Valo /* 932e705c121SKalle Valo * Stop and start the transport without entering low power 933e705c121SKalle Valo * mode. This will save the state of other components on the 934e705c121SKalle Valo * device that are triggered by the INIT firwmare (MFUART). 935e705c121SKalle Valo */ 936e705c121SKalle Valo _iwl_trans_stop_device(mvm->trans, false); 937e705c121SKalle Valo ret = _iwl_trans_start_hw(mvm->trans, false); 938e705c121SKalle Valo if (ret) 939e705c121SKalle Valo goto error; 940e705c121SKalle Valo } 941e705c121SKalle Valo 942e705c121SKalle Valo if (iwlmvm_mod_params.init_dbg) 943e705c121SKalle Valo return 0; 944e705c121SKalle Valo 945e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); 946e705c121SKalle Valo if (ret) { 947e705c121SKalle Valo IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); 948e705c121SKalle Valo goto error; 949e705c121SKalle Valo } 950e705c121SKalle Valo 951e705c121SKalle Valo iwl_mvm_get_shared_mem_conf(mvm); 952e705c121SKalle Valo 953e705c121SKalle Valo ret = iwl_mvm_sf_update(mvm, NULL, false); 954e705c121SKalle Valo if (ret) 955e705c121SKalle Valo IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); 956e705c121SKalle Valo 957e705c121SKalle Valo mvm->fw_dbg_conf = FW_DBG_INVALID; 958e705c121SKalle Valo /* if we have a destination, assume EARLY START */ 959e705c121SKalle Valo if (mvm->fw->dbg_dest_tlv) 960e705c121SKalle Valo mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE; 961e705c121SKalle Valo iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE); 962e705c121SKalle Valo 963e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 964e705c121SKalle Valo if (ret) 965e705c121SKalle Valo goto error; 966e705c121SKalle Valo 967e705c121SKalle Valo ret = iwl_send_bt_init_conf(mvm); 968e705c121SKalle Valo if (ret) 969e705c121SKalle Valo goto error; 970e705c121SKalle Valo 971e705c121SKalle Valo /* Send phy db control command and then phy db calibration*/ 972e705c121SKalle Valo ret = iwl_send_phy_db_data(mvm->phy_db); 973e705c121SKalle Valo if (ret) 974e705c121SKalle Valo goto error; 975e705c121SKalle Valo 976e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 977e705c121SKalle Valo if (ret) 978e705c121SKalle Valo goto error; 979e705c121SKalle Valo 98043413a97SSara Sharon /* Init RSS configuration */ 98143413a97SSara Sharon if (iwl_mvm_has_new_rx_api(mvm)) { 98243413a97SSara Sharon ret = iwl_send_rss_cfg_cmd(mvm); 98343413a97SSara Sharon if (ret) { 98443413a97SSara Sharon IWL_ERR(mvm, "Failed to configure RSS queues: %d\n", 98543413a97SSara Sharon ret); 98643413a97SSara Sharon goto error; 98743413a97SSara Sharon } 98843413a97SSara Sharon } 98943413a97SSara Sharon 990e705c121SKalle Valo /* init the fw <-> mac80211 STA mapping */ 991e705c121SKalle Valo for (i = 0; i < IWL_MVM_STATION_COUNT; i++) 992e705c121SKalle Valo RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); 993e705c121SKalle Valo 994e705c121SKalle Valo mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT; 995e705c121SKalle Valo 996e705c121SKalle Valo /* reset quota debouncing buffer - 0xff will yield invalid data */ 997e705c121SKalle Valo memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); 998e705c121SKalle Valo 99997d5be7eSLiad Kaufman /* Enable DQA-mode if required */ 100097d5be7eSLiad Kaufman if (iwl_mvm_is_dqa_supported(mvm)) { 100197d5be7eSLiad Kaufman ret = iwl_mvm_send_dqa_cmd(mvm); 100297d5be7eSLiad Kaufman if (ret) 100397d5be7eSLiad Kaufman goto error; 100497d5be7eSLiad Kaufman } else { 100597d5be7eSLiad Kaufman IWL_DEBUG_FW(mvm, "Working in non-DQA mode\n"); 100697d5be7eSLiad Kaufman } 100797d5be7eSLiad Kaufman 1008e705c121SKalle Valo /* Add auxiliary station for scanning */ 1009e705c121SKalle Valo ret = iwl_mvm_add_aux_sta(mvm); 1010e705c121SKalle Valo if (ret) 1011e705c121SKalle Valo goto error; 1012e705c121SKalle Valo 1013e705c121SKalle Valo /* Add all the PHY contexts */ 101457fbcce3SJohannes Berg chan = &mvm->hw->wiphy->bands[NL80211_BAND_2GHZ]->channels[0]; 1015e705c121SKalle Valo cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); 1016e705c121SKalle Valo for (i = 0; i < NUM_PHY_CTX; i++) { 1017e705c121SKalle Valo /* 1018e705c121SKalle Valo * The channel used here isn't relevant as it's 1019e705c121SKalle Valo * going to be overwritten in the other flows. 1020e705c121SKalle Valo * For now use the first channel we have. 1021e705c121SKalle Valo */ 1022e705c121SKalle Valo ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], 1023e705c121SKalle Valo &chandef, 1, 1); 1024e705c121SKalle Valo if (ret) 1025e705c121SKalle Valo goto error; 1026e705c121SKalle Valo } 1027e705c121SKalle Valo 1028c221daf2SChaya Rachel Ivgi #ifdef CONFIG_THERMAL 1029c221daf2SChaya Rachel Ivgi if (iwl_mvm_is_tt_in_fw(mvm)) { 1030c221daf2SChaya Rachel Ivgi /* in order to give the responsibility of ct-kill and 1031c221daf2SChaya Rachel Ivgi * TX backoff to FW we need to send empty temperature reporting 1032c221daf2SChaya Rachel Ivgi * cmd during init time 1033c221daf2SChaya Rachel Ivgi */ 1034c221daf2SChaya Rachel Ivgi iwl_mvm_send_temp_report_ths_cmd(mvm); 1035c221daf2SChaya Rachel Ivgi } else { 1036e705c121SKalle Valo /* Initialize tx backoffs to the minimal possible */ 1037e705c121SKalle Valo iwl_mvm_tt_tx_backoff(mvm, 0); 1038c221daf2SChaya Rachel Ivgi } 10395c89e7bcSChaya Rachel Ivgi 10405c89e7bcSChaya Rachel Ivgi /* TODO: read the budget from BIOS / Platform NVM */ 10415c89e7bcSChaya Rachel Ivgi if (iwl_mvm_is_ctdp_supported(mvm) && mvm->cooling_dev.cur_state > 0) 10425c89e7bcSChaya Rachel Ivgi ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START, 10435c89e7bcSChaya Rachel Ivgi mvm->cooling_dev.cur_state); 1044c221daf2SChaya Rachel Ivgi #else 1045c221daf2SChaya Rachel Ivgi /* Initialize tx backoffs to the minimal possible */ 1046c221daf2SChaya Rachel Ivgi iwl_mvm_tt_tx_backoff(mvm, 0); 1047c221daf2SChaya Rachel Ivgi #endif 1048e705c121SKalle Valo 1049e705c121SKalle Valo WARN_ON(iwl_mvm_config_ltr(mvm)); 1050e705c121SKalle Valo 1051e705c121SKalle Valo ret = iwl_mvm_power_update_device(mvm); 1052e705c121SKalle Valo if (ret) 1053e705c121SKalle Valo goto error; 1054e705c121SKalle Valo 1055e705c121SKalle Valo /* 1056e705c121SKalle Valo * RTNL is not taken during Ct-kill, but we don't need to scan/Tx 1057e705c121SKalle Valo * anyway, so don't init MCC. 1058e705c121SKalle Valo */ 1059e705c121SKalle Valo if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { 1060e705c121SKalle Valo ret = iwl_mvm_init_mcc(mvm); 1061e705c121SKalle Valo if (ret) 1062e705c121SKalle Valo goto error; 1063e705c121SKalle Valo } 1064e705c121SKalle Valo 1065e705c121SKalle Valo if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { 10664ca87a5fSEmmanuel Grumbach mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; 1067e705c121SKalle Valo ret = iwl_mvm_config_scan(mvm); 1068e705c121SKalle Valo if (ret) 1069e705c121SKalle Valo goto error; 1070e705c121SKalle Valo } 1071e705c121SKalle Valo 1072e705c121SKalle Valo if (iwl_mvm_is_csum_supported(mvm) && 1073e705c121SKalle Valo mvm->cfg->features & NETIF_F_RXCSUM) 1074e705c121SKalle Valo iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3); 1075e705c121SKalle Valo 1076e705c121SKalle Valo /* allow FW/transport low power modes if not during restart */ 1077e705c121SKalle Valo if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) 1078e705c121SKalle Valo iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN); 1079e705c121SKalle Valo 1080e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); 1081e705c121SKalle Valo return 0; 1082e705c121SKalle Valo error: 1083fcb6b92aSChaya Rachel Ivgi iwl_mvm_stop_device(mvm); 1084e705c121SKalle Valo return ret; 1085e705c121SKalle Valo } 1086e705c121SKalle Valo 1087e705c121SKalle Valo int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) 1088e705c121SKalle Valo { 1089e705c121SKalle Valo int ret, i; 1090e705c121SKalle Valo 1091e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 1092e705c121SKalle Valo 1093e705c121SKalle Valo ret = iwl_trans_start_hw(mvm->trans); 1094e705c121SKalle Valo if (ret) 1095e705c121SKalle Valo return ret; 1096e705c121SKalle Valo 1097e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); 1098e705c121SKalle Valo if (ret) { 1099e705c121SKalle Valo IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); 1100e705c121SKalle Valo goto error; 1101e705c121SKalle Valo } 1102e705c121SKalle Valo 1103e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 1104e705c121SKalle Valo if (ret) 1105e705c121SKalle Valo goto error; 1106e705c121SKalle Valo 1107e705c121SKalle Valo /* Send phy db control command and then phy db calibration*/ 1108e705c121SKalle Valo ret = iwl_send_phy_db_data(mvm->phy_db); 1109e705c121SKalle Valo if (ret) 1110e705c121SKalle Valo goto error; 1111e705c121SKalle Valo 1112e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 1113e705c121SKalle Valo if (ret) 1114e705c121SKalle Valo goto error; 1115e705c121SKalle Valo 1116e705c121SKalle Valo /* init the fw <-> mac80211 STA mapping */ 1117e705c121SKalle Valo for (i = 0; i < IWL_MVM_STATION_COUNT; i++) 1118e705c121SKalle Valo RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); 1119e705c121SKalle Valo 1120e705c121SKalle Valo /* Add auxiliary station for scanning */ 1121e705c121SKalle Valo ret = iwl_mvm_add_aux_sta(mvm); 1122e705c121SKalle Valo if (ret) 1123e705c121SKalle Valo goto error; 1124e705c121SKalle Valo 1125e705c121SKalle Valo return 0; 1126e705c121SKalle Valo error: 1127fcb6b92aSChaya Rachel Ivgi iwl_mvm_stop_device(mvm); 1128e705c121SKalle Valo return ret; 1129e705c121SKalle Valo } 1130e705c121SKalle Valo 1131e705c121SKalle Valo void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, 1132e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1133e705c121SKalle Valo { 1134e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1135e705c121SKalle Valo struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; 1136e705c121SKalle Valo u32 flags = le32_to_cpu(card_state_notif->flags); 1137e705c121SKalle Valo 1138e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", 1139e705c121SKalle Valo (flags & HW_CARD_DISABLED) ? "Kill" : "On", 1140e705c121SKalle Valo (flags & SW_CARD_DISABLED) ? "Kill" : "On", 1141e705c121SKalle Valo (flags & CT_KILL_CARD_DISABLED) ? 1142e705c121SKalle Valo "Reached" : "Not reached"); 1143e705c121SKalle Valo } 1144e705c121SKalle Valo 1145e705c121SKalle Valo void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, 1146e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1147e705c121SKalle Valo { 1148e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1149e705c121SKalle Valo struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; 1150e705c121SKalle Valo 1151e705c121SKalle Valo IWL_DEBUG_INFO(mvm, 1152e705c121SKalle Valo "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", 1153e705c121SKalle Valo le32_to_cpu(mfuart_notif->installed_ver), 1154e705c121SKalle Valo le32_to_cpu(mfuart_notif->external_ver), 1155e705c121SKalle Valo le32_to_cpu(mfuart_notif->status), 1156e705c121SKalle Valo le32_to_cpu(mfuart_notif->duration)); 1157e705c121SKalle Valo } 1158