1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 9bdccdb85SGolan Ben-Ami * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 10cceb4507SShahar S Matityahu * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation 11e705c121SKalle Valo * 12e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 13e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 14e705c121SKalle Valo * published by the Free Software Foundation. 15e705c121SKalle Valo * 16e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 17e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 18e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19e705c121SKalle Valo * General Public License for more details. 20e705c121SKalle Valo * 21e705c121SKalle Valo * The full GNU General Public License is included in this distribution 22e705c121SKalle Valo * in the file called COPYING. 23e705c121SKalle Valo * 24e705c121SKalle Valo * Contact Information: 25cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 26e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27e705c121SKalle Valo * 28e705c121SKalle Valo * BSD LICENSE 29e705c121SKalle Valo * 30e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 31bdccdb85SGolan Ben-Ami * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 32cceb4507SShahar S Matityahu * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation 33e705c121SKalle Valo * All rights reserved. 34e705c121SKalle Valo * 35e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 36e705c121SKalle Valo * modification, are permitted provided that the following conditions 37e705c121SKalle Valo * are met: 38e705c121SKalle Valo * 39e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 40e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 41e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 43e705c121SKalle Valo * the documentation and/or other materials provided with the 44e705c121SKalle Valo * distribution. 45e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 46e705c121SKalle Valo * contributors may be used to endorse or promote products derived 47e705c121SKalle Valo * from this software without specific prior written permission. 48e705c121SKalle Valo * 49e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 50e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 51e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 52e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 53e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 55e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 59e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60e705c121SKalle Valo * 61e705c121SKalle Valo *****************************************************************************/ 62e705c121SKalle Valo #include <net/mac80211.h> 63854d773eSSara Sharon #include <linux/netdevice.h> 64e705c121SKalle Valo 65e705c121SKalle Valo #include "iwl-trans.h" 66e705c121SKalle Valo #include "iwl-op-mode.h" 67d962f9b1SJohannes Berg #include "fw/img.h" 68e705c121SKalle Valo #include "iwl-debug.h" 69e705c121SKalle Valo #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */ 70e705c121SKalle Valo #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */ 71e705c121SKalle Valo #include "iwl-prph.h" 72813df5ceSLuca Coelho #include "fw/acpi.h" 73e705c121SKalle Valo 74e705c121SKalle Valo #include "mvm.h" 757174beb6SJohannes Berg #include "fw/dbg.h" 76e705c121SKalle Valo #include "iwl-phy-db.h" 779c4f7d51SShaul Triebitz #include "iwl-modparams.h" 789c4f7d51SShaul Triebitz #include "iwl-nvm-parse.h" 79e705c121SKalle Valo 80e705c121SKalle Valo #define MVM_UCODE_ALIVE_TIMEOUT HZ 81e705c121SKalle Valo #define MVM_UCODE_CALIB_TIMEOUT (2*HZ) 8270d3ca86SLuca Coelho #define MVM_UCODE_PNVM_TIMEOUT (HZ / 10) 83e705c121SKalle Valo 84e705c121SKalle Valo #define UCODE_VALID_OK cpu_to_le32(0x1) 85e705c121SKalle Valo 86e705c121SKalle Valo struct iwl_mvm_alive_data { 87e705c121SKalle Valo bool valid; 88e705c121SKalle Valo u32 scd_base_addr; 89e705c121SKalle Valo }; 90e705c121SKalle Valo 91e705c121SKalle Valo static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant) 92e705c121SKalle Valo { 93e705c121SKalle Valo struct iwl_tx_ant_cfg_cmd tx_ant_cmd = { 94e705c121SKalle Valo .valid = cpu_to_le32(valid_tx_ant), 95e705c121SKalle Valo }; 96e705c121SKalle Valo 97e705c121SKalle Valo IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant); 98e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0, 99e705c121SKalle Valo sizeof(tx_ant_cmd), &tx_ant_cmd); 100e705c121SKalle Valo } 101e705c121SKalle Valo 10243413a97SSara Sharon static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm) 10343413a97SSara Sharon { 10443413a97SSara Sharon int i; 10543413a97SSara Sharon struct iwl_rss_config_cmd cmd = { 10643413a97SSara Sharon .flags = cpu_to_le32(IWL_RSS_ENABLE), 107608dce95SSara Sharon .hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) | 108608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) | 109608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) | 110608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) | 111608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) | 112608dce95SSara Sharon BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD), 11343413a97SSara Sharon }; 11443413a97SSara Sharon 115f43495fdSSara Sharon if (mvm->trans->num_rx_queues == 1) 116f43495fdSSara Sharon return 0; 117f43495fdSSara Sharon 118854d773eSSara Sharon /* Do not direct RSS traffic to Q 0 which is our fallback queue */ 11943413a97SSara Sharon for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++) 120854d773eSSara Sharon cmd.indirection_table[i] = 121854d773eSSara Sharon 1 + (i % (mvm->trans->num_rx_queues - 1)); 122854d773eSSara Sharon netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key)); 12343413a97SSara Sharon 12443413a97SSara Sharon return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd); 12543413a97SSara Sharon } 12643413a97SSara Sharon 1278edbfaa1SSara Sharon static int iwl_configure_rxq(struct iwl_mvm *mvm) 1288edbfaa1SSara Sharon { 129dbf592f3SJohannes Berg int i, num_queues, size, ret; 1308edbfaa1SSara Sharon struct iwl_rfh_queue_config *cmd; 131dbf592f3SJohannes Berg struct iwl_host_cmd hcmd = { 132dbf592f3SJohannes Berg .id = WIDE_ID(DATA_PATH_GROUP, RFH_QUEUE_CONFIG_CMD), 133dbf592f3SJohannes Berg .dataflags[0] = IWL_HCMD_DFL_NOCOPY, 134dbf592f3SJohannes Berg }; 1358edbfaa1SSara Sharon 13664f55156SLuca Coelho /* 13764f55156SLuca Coelho * The default queue is configured via context info, so if we 13864f55156SLuca Coelho * have a single queue, there's nothing to do here. 13964f55156SLuca Coelho */ 14064f55156SLuca Coelho if (mvm->trans->num_rx_queues == 1) 14164f55156SLuca Coelho return 0; 14264f55156SLuca Coelho 14364f55156SLuca Coelho /* skip the default queue */ 1448edbfaa1SSara Sharon num_queues = mvm->trans->num_rx_queues - 1; 1458edbfaa1SSara Sharon 146dbf592f3SJohannes Berg size = struct_size(cmd, data, num_queues); 1478edbfaa1SSara Sharon 1488edbfaa1SSara Sharon cmd = kzalloc(size, GFP_KERNEL); 1498edbfaa1SSara Sharon if (!cmd) 1508edbfaa1SSara Sharon return -ENOMEM; 1518edbfaa1SSara Sharon 1528edbfaa1SSara Sharon cmd->num_queues = num_queues; 1538edbfaa1SSara Sharon 1548edbfaa1SSara Sharon for (i = 0; i < num_queues; i++) { 1558edbfaa1SSara Sharon struct iwl_trans_rxq_dma_data data; 1568edbfaa1SSara Sharon 1578edbfaa1SSara Sharon cmd->data[i].q_num = i + 1; 1588edbfaa1SSara Sharon iwl_trans_get_rxq_dma_data(mvm->trans, i + 1, &data); 1598edbfaa1SSara Sharon 1608edbfaa1SSara Sharon cmd->data[i].fr_bd_cb = cpu_to_le64(data.fr_bd_cb); 1618edbfaa1SSara Sharon cmd->data[i].urbd_stts_wrptr = 1628edbfaa1SSara Sharon cpu_to_le64(data.urbd_stts_wrptr); 1638edbfaa1SSara Sharon cmd->data[i].ur_bd_cb = cpu_to_le64(data.ur_bd_cb); 1648edbfaa1SSara Sharon cmd->data[i].fr_bd_wid = cpu_to_le32(data.fr_bd_wid); 1658edbfaa1SSara Sharon } 1668edbfaa1SSara Sharon 167dbf592f3SJohannes Berg hcmd.data[0] = cmd; 168dbf592f3SJohannes Berg hcmd.len[0] = size; 169dbf592f3SJohannes Berg 170dbf592f3SJohannes Berg ret = iwl_mvm_send_cmd(mvm, &hcmd); 171dbf592f3SJohannes Berg 172dbf592f3SJohannes Berg kfree(cmd); 173dbf592f3SJohannes Berg 174dbf592f3SJohannes Berg return ret; 1758edbfaa1SSara Sharon } 1768edbfaa1SSara Sharon 17797d5be7eSLiad Kaufman static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm) 17897d5be7eSLiad Kaufman { 17997d5be7eSLiad Kaufman struct iwl_dqa_enable_cmd dqa_cmd = { 18097d5be7eSLiad Kaufman .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE), 18197d5be7eSLiad Kaufman }; 18297d5be7eSLiad Kaufman u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0); 18397d5be7eSLiad Kaufman int ret; 18497d5be7eSLiad Kaufman 18597d5be7eSLiad Kaufman ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); 18697d5be7eSLiad Kaufman if (ret) 18797d5be7eSLiad Kaufman IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret); 18897d5be7eSLiad Kaufman else 18997d5be7eSLiad Kaufman IWL_DEBUG_FW(mvm, "Working in DQA mode\n"); 19097d5be7eSLiad Kaufman 19197d5be7eSLiad Kaufman return ret; 19297d5be7eSLiad Kaufman } 19397d5be7eSLiad Kaufman 194bdccdb85SGolan Ben-Ami void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm, 195bdccdb85SGolan Ben-Ami struct iwl_rx_cmd_buffer *rxb) 196bdccdb85SGolan Ben-Ami { 197bdccdb85SGolan Ben-Ami struct iwl_rx_packet *pkt = rxb_addr(rxb); 198bdccdb85SGolan Ben-Ami struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data; 199bdccdb85SGolan Ben-Ami __le32 *dump_data = mfu_dump_notif->data; 200bdccdb85SGolan Ben-Ami int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32); 201bdccdb85SGolan Ben-Ami int i; 202bdccdb85SGolan Ben-Ami 203bdccdb85SGolan Ben-Ami if (mfu_dump_notif->index_num == 0) 204bdccdb85SGolan Ben-Ami IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n", 205bdccdb85SGolan Ben-Ami le32_to_cpu(mfu_dump_notif->assert_id)); 206bdccdb85SGolan Ben-Ami 207bdccdb85SGolan Ben-Ami for (i = 0; i < n_words; i++) 208bdccdb85SGolan Ben-Ami IWL_DEBUG_INFO(mvm, 209bdccdb85SGolan Ben-Ami "MFUART assert dump, dword %u: 0x%08x\n", 210bdccdb85SGolan Ben-Ami le16_to_cpu(mfu_dump_notif->index_num) * 211bdccdb85SGolan Ben-Ami n_words + i, 212bdccdb85SGolan Ben-Ami le32_to_cpu(dump_data[i])); 213bdccdb85SGolan Ben-Ami } 214bdccdb85SGolan Ben-Ami 215e705c121SKalle Valo static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, 216e705c121SKalle Valo struct iwl_rx_packet *pkt, void *data) 217e705c121SKalle Valo { 218e705c121SKalle Valo struct iwl_mvm *mvm = 219e705c121SKalle Valo container_of(notif_wait, struct iwl_mvm, notif_wait); 220e705c121SKalle Valo struct iwl_mvm_alive_data *alive_data = data; 2215c228d63SSara Sharon struct iwl_umac_alive *umac; 2225c228d63SSara Sharon struct iwl_lmac_alive *lmac1; 2235c228d63SSara Sharon struct iwl_lmac_alive *lmac2 = NULL; 2245c228d63SSara Sharon u16 status; 225cfa5d0caSMordechay Goodstein u32 lmac_error_event_table, umac_error_table; 226e705c121SKalle Valo 22790824f2fSLuca Coelho /* 22890824f2fSLuca Coelho * For v5 and above, we can check the version, for older 22990824f2fSLuca Coelho * versions we need to check the size. 23090824f2fSLuca Coelho */ 231b4248c08SAndrei Otcheretianski if (iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP, 23290824f2fSLuca Coelho UCODE_ALIVE_NTFY, 0) == 5) { 23390824f2fSLuca Coelho struct iwl_alive_ntf_v5 *palive; 23490824f2fSLuca Coelho 23590824f2fSLuca Coelho palive = (void *)pkt->data; 23690824f2fSLuca Coelho umac = &palive->umac_data; 23790824f2fSLuca Coelho lmac1 = &palive->lmac_data[0]; 23890824f2fSLuca Coelho lmac2 = &palive->lmac_data[1]; 23990824f2fSLuca Coelho status = le16_to_cpu(palive->status); 24090824f2fSLuca Coelho 24190824f2fSLuca Coelho mvm->trans->sku_id[0] = le32_to_cpu(palive->sku_id.data[0]); 24290824f2fSLuca Coelho mvm->trans->sku_id[1] = le32_to_cpu(palive->sku_id.data[1]); 24390824f2fSLuca Coelho mvm->trans->sku_id[2] = le32_to_cpu(palive->sku_id.data[2]); 24490824f2fSLuca Coelho 24590824f2fSLuca Coelho IWL_DEBUG_FW(mvm, "Got sku_id: 0x0%x 0x0%x 0x0%x\n", 24690824f2fSLuca Coelho mvm->trans->sku_id[0], 24790824f2fSLuca Coelho mvm->trans->sku_id[1], 24890824f2fSLuca Coelho mvm->trans->sku_id[2]); 24990824f2fSLuca Coelho } else if (iwl_rx_packet_payload_len(pkt) == sizeof(struct iwl_alive_ntf_v4)) { 2509422b978SLuca Coelho struct iwl_alive_ntf_v4 *palive; 2519422b978SLuca Coelho 252e705c121SKalle Valo palive = (void *)pkt->data; 2535c228d63SSara Sharon umac = &palive->umac_data; 2545c228d63SSara Sharon lmac1 = &palive->lmac_data[0]; 2555c228d63SSara Sharon lmac2 = &palive->lmac_data[1]; 2565c228d63SSara Sharon status = le16_to_cpu(palive->status); 2579422b978SLuca Coelho } else if (iwl_rx_packet_payload_len(pkt) == 2589422b978SLuca Coelho sizeof(struct iwl_alive_ntf_v3)) { 2599422b978SLuca Coelho struct iwl_alive_ntf_v3 *palive3; 2609422b978SLuca Coelho 2615c228d63SSara Sharon palive3 = (void *)pkt->data; 2625c228d63SSara Sharon umac = &palive3->umac_data; 2635c228d63SSara Sharon lmac1 = &palive3->lmac_data; 2645c228d63SSara Sharon status = le16_to_cpu(palive3->status); 2659422b978SLuca Coelho } else { 2669422b978SLuca Coelho WARN(1, "unsupported alive notification (size %d)\n", 2679422b978SLuca Coelho iwl_rx_packet_payload_len(pkt)); 2689422b978SLuca Coelho /* get timeout later */ 2699422b978SLuca Coelho return false; 2705c228d63SSara Sharon } 271e705c121SKalle Valo 27222463857SShahar S Matityahu lmac_error_event_table = 27322463857SShahar S Matityahu le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr); 27422463857SShahar S Matityahu iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table); 275e705c121SKalle Valo 27622463857SShahar S Matityahu if (lmac2) 27791c28b83SShahar S Matityahu mvm->trans->dbg.lmac_error_event_table[1] = 27822463857SShahar S Matityahu le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr); 27922463857SShahar S Matityahu 280cfa5d0caSMordechay Goodstein umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr); 2815c228d63SSara Sharon 282cfa5d0caSMordechay Goodstein if (umac_error_table) { 283cfa5d0caSMordechay Goodstein if (umac_error_table >= 2843485e76eSLuca Coelho mvm->trans->cfg->min_umac_error_event_table) { 285cfa5d0caSMordechay Goodstein iwl_fw_umac_set_alive_err_table(mvm->trans, 286cfa5d0caSMordechay Goodstein umac_error_table); 2873485e76eSLuca Coelho } else { 288fb5b2846SLuca Coelho IWL_ERR(mvm, 289fb5b2846SLuca Coelho "Not valid error log pointer 0x%08X for %s uCode\n", 290cfa5d0caSMordechay Goodstein umac_error_table, 291fb5b2846SLuca Coelho (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ? 292fb5b2846SLuca Coelho "Init" : "RT"); 2933485e76eSLuca Coelho } 294cfa5d0caSMordechay Goodstein } 29522463857SShahar S Matityahu 29622463857SShahar S Matityahu alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr); 2975c228d63SSara Sharon alive_data->valid = status == IWL_ALIVE_STATUS_OK; 298e705c121SKalle Valo 299e705c121SKalle Valo IWL_DEBUG_FW(mvm, 3005c228d63SSara Sharon "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n", 3015c228d63SSara Sharon status, lmac1->ver_type, lmac1->ver_subtype); 3025c228d63SSara Sharon 3035c228d63SSara Sharon if (lmac2) 3045c228d63SSara Sharon IWL_DEBUG_FW(mvm, "Alive ucode CDB\n"); 305e705c121SKalle Valo 306e705c121SKalle Valo IWL_DEBUG_FW(mvm, 307e705c121SKalle Valo "UMAC version: Major - 0x%x, Minor - 0x%x\n", 3085c228d63SSara Sharon le32_to_cpu(umac->umac_major), 3095c228d63SSara Sharon le32_to_cpu(umac->umac_minor)); 310e705c121SKalle Valo 3110a3a3e9eSShahar S Matityahu iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac); 3120a3a3e9eSShahar S Matityahu 313e705c121SKalle Valo return true; 314e705c121SKalle Valo } 315e705c121SKalle Valo 31670d3ca86SLuca Coelho static bool iwl_pnvm_complete_fn(struct iwl_notif_wait_data *notif_wait, 31770d3ca86SLuca Coelho struct iwl_rx_packet *pkt, void *data) 31870d3ca86SLuca Coelho { 31970d3ca86SLuca Coelho struct iwl_mvm *mvm = 32070d3ca86SLuca Coelho container_of(notif_wait, struct iwl_mvm, notif_wait); 32170d3ca86SLuca Coelho struct iwl_pnvm_init_complete_ntfy *pnvm_ntf = (void *)pkt->data; 32270d3ca86SLuca Coelho 32370d3ca86SLuca Coelho IWL_DEBUG_FW(mvm, 32470d3ca86SLuca Coelho "PNVM complete notification received with status %d\n", 32570d3ca86SLuca Coelho le32_to_cpu(pnvm_ntf->status)); 32670d3ca86SLuca Coelho 32770d3ca86SLuca Coelho return true; 32870d3ca86SLuca Coelho } 32970d3ca86SLuca Coelho 3301f370650SSara Sharon static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait, 3311f370650SSara Sharon struct iwl_rx_packet *pkt, void *data) 3321f370650SSara Sharon { 3331f370650SSara Sharon WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); 3341f370650SSara Sharon 3351f370650SSara Sharon return true; 3361f370650SSara Sharon } 3371f370650SSara Sharon 338e705c121SKalle Valo static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait, 339e705c121SKalle Valo struct iwl_rx_packet *pkt, void *data) 340e705c121SKalle Valo { 341e705c121SKalle Valo struct iwl_phy_db *phy_db = data; 342e705c121SKalle Valo 343e705c121SKalle Valo if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) { 344e705c121SKalle Valo WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF); 345e705c121SKalle Valo return true; 346e705c121SKalle Valo } 347e705c121SKalle Valo 348ce1f2778SSara Sharon WARN_ON(iwl_phy_db_set_section(phy_db, pkt)); 349e705c121SKalle Valo 350e705c121SKalle Valo return false; 351e705c121SKalle Valo } 352e705c121SKalle Valo 35370d3ca86SLuca Coelho static int iwl_mvm_load_pnvm(struct iwl_mvm *mvm) 35470d3ca86SLuca Coelho { 35570d3ca86SLuca Coelho struct iwl_notification_wait pnvm_wait; 35670d3ca86SLuca Coelho static const u16 ntf_cmds[] = { WIDE_ID(REGULATORY_AND_NVM_GROUP, 35770d3ca86SLuca Coelho PNVM_INIT_COMPLETE_NTFY) }; 35870d3ca86SLuca Coelho 35970d3ca86SLuca Coelho /* if the SKU_ID is empty, there's nothing to do */ 36070d3ca86SLuca Coelho if (!mvm->trans->sku_id[0] && 36170d3ca86SLuca Coelho !mvm->trans->sku_id[1] && 36270d3ca86SLuca Coelho !mvm->trans->sku_id[2]) 36370d3ca86SLuca Coelho return 0; 36470d3ca86SLuca Coelho 36570d3ca86SLuca Coelho /* 36670d3ca86SLuca Coelho * TODO: phase 2: load the pnvm file, find the right section, 36770d3ca86SLuca Coelho * load it and set the right DMA pointer. 36870d3ca86SLuca Coelho */ 36970d3ca86SLuca Coelho 37070d3ca86SLuca Coelho iwl_init_notification_wait(&mvm->notif_wait, &pnvm_wait, 37170d3ca86SLuca Coelho ntf_cmds, ARRAY_SIZE(ntf_cmds), 37270d3ca86SLuca Coelho iwl_pnvm_complete_fn, NULL); 37370d3ca86SLuca Coelho 37470d3ca86SLuca Coelho /* kick the doorbell */ 37570d3ca86SLuca Coelho iwl_write_umac_prph(mvm->trans, UREG_DOORBELL_TO_ISR6, 37670d3ca86SLuca Coelho UREG_DOORBELL_TO_ISR6_PNVM); 37770d3ca86SLuca Coelho 37870d3ca86SLuca Coelho return iwl_wait_notification(&mvm->notif_wait, &pnvm_wait, 37970d3ca86SLuca Coelho MVM_UCODE_PNVM_TIMEOUT); 38070d3ca86SLuca Coelho } 38170d3ca86SLuca Coelho 382e705c121SKalle Valo static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm, 383e705c121SKalle Valo enum iwl_ucode_type ucode_type) 384e705c121SKalle Valo { 385e705c121SKalle Valo struct iwl_notification_wait alive_wait; 38694a8d87cSLuca Coelho struct iwl_mvm_alive_data alive_data = {}; 387e705c121SKalle Valo const struct fw_img *fw; 388cfbc6c4cSSara Sharon int ret; 389702e975dSJohannes Berg enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img; 3909422b978SLuca Coelho static const u16 alive_cmd[] = { UCODE_ALIVE_NTFY }; 391b3500b47SEmmanuel Grumbach bool run_in_rfkill = 392b3500b47SEmmanuel Grumbach ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm); 393e705c121SKalle Valo 394e705c121SKalle Valo if (ucode_type == IWL_UCODE_REGULAR && 3953d2d4422SGolan Ben-Ami iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) && 3963d2d4422SGolan Ben-Ami !(fw_has_capa(&mvm->fw->ucode_capa, 3973d2d4422SGolan Ben-Ami IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED))) 398612da1efSSharon Dvir fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER); 399e705c121SKalle Valo else 400612da1efSSharon Dvir fw = iwl_get_ucode_image(mvm->fw, ucode_type); 401e705c121SKalle Valo if (WARN_ON(!fw)) 402e705c121SKalle Valo return -EINVAL; 403702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, ucode_type); 40465b280feSJohannes Berg clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); 405e705c121SKalle Valo 406e705c121SKalle Valo iwl_init_notification_wait(&mvm->notif_wait, &alive_wait, 407e705c121SKalle Valo alive_cmd, ARRAY_SIZE(alive_cmd), 408e705c121SKalle Valo iwl_alive_fn, &alive_data); 409e705c121SKalle Valo 410b3500b47SEmmanuel Grumbach /* 411b3500b47SEmmanuel Grumbach * We want to load the INIT firmware even in RFKILL 412b3500b47SEmmanuel Grumbach * For the unified firmware case, the ucode_type is not 413b3500b47SEmmanuel Grumbach * INIT, but we still need to run it. 414b3500b47SEmmanuel Grumbach */ 415b3500b47SEmmanuel Grumbach ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill); 416e705c121SKalle Valo if (ret) { 417702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, old_type); 418e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &alive_wait); 419e705c121SKalle Valo return ret; 420e705c121SKalle Valo } 421e705c121SKalle Valo 422e705c121SKalle Valo /* 423e705c121SKalle Valo * Some things may run in the background now, but we 424e705c121SKalle Valo * just wait for the ALIVE notification here. 425e705c121SKalle Valo */ 426e705c121SKalle Valo ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait, 427e705c121SKalle Valo MVM_UCODE_ALIVE_TIMEOUT); 428e705c121SKalle Valo if (ret) { 429d6be9c1dSSara Sharon struct iwl_trans *trans = mvm->trans; 430d6be9c1dSSara Sharon 43120f5aef5SJohannes Berg if (trans->trans_cfg->device_family >= 43220f5aef5SJohannes Berg IWL_DEVICE_FAMILY_22000) { 433e705c121SKalle Valo IWL_ERR(mvm, 434e705c121SKalle Valo "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", 435ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS), 436ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, 437ea695b7cSShaul Triebitz UMAG_SB_CPU_2_STATUS)); 43820f5aef5SJohannes Berg IWL_ERR(mvm, "UMAC PC: 0x%x\n", 43920f5aef5SJohannes Berg iwl_read_umac_prph(trans, 44020f5aef5SJohannes Berg UREG_UMAC_CURRENT_PC)); 44120f5aef5SJohannes Berg IWL_ERR(mvm, "LMAC PC: 0x%x\n", 44220f5aef5SJohannes Berg iwl_read_umac_prph(trans, 44320f5aef5SJohannes Berg UREG_LMAC1_CURRENT_PC)); 44420f5aef5SJohannes Berg if (iwl_mvm_is_cdb_supported(mvm)) 44520f5aef5SJohannes Berg IWL_ERR(mvm, "LMAC2 PC: 0x%x\n", 44620f5aef5SJohannes Berg iwl_read_umac_prph(trans, 44720f5aef5SJohannes Berg UREG_LMAC2_CURRENT_PC)); 44820f5aef5SJohannes Berg } else if (trans->trans_cfg->device_family >= 44920f5aef5SJohannes Berg IWL_DEVICE_FAMILY_8000) { 450d6be9c1dSSara Sharon IWL_ERR(mvm, 451d6be9c1dSSara Sharon "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", 452d6be9c1dSSara Sharon iwl_read_prph(trans, SB_CPU_1_STATUS), 453d6be9c1dSSara Sharon iwl_read_prph(trans, SB_CPU_2_STATUS)); 45420f5aef5SJohannes Berg } 45520f5aef5SJohannes Berg 45620f5aef5SJohannes Berg if (ret == -ETIMEDOUT) 45720f5aef5SJohannes Berg iwl_fw_dbg_error_collect(&mvm->fwrt, 45820f5aef5SJohannes Berg FW_DBG_TRIGGER_ALIVE_TIMEOUT); 45920f5aef5SJohannes Berg 460702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, old_type); 461e705c121SKalle Valo return ret; 462e705c121SKalle Valo } 463e705c121SKalle Valo 464e705c121SKalle Valo if (!alive_data.valid) { 465e705c121SKalle Valo IWL_ERR(mvm, "Loaded ucode is not valid!\n"); 466702e975dSJohannes Berg iwl_fw_set_current_image(&mvm->fwrt, old_type); 467e705c121SKalle Valo return -EIO; 468e705c121SKalle Valo } 469e705c121SKalle Valo 47070d3ca86SLuca Coelho ret = iwl_mvm_load_pnvm(mvm); 47170d3ca86SLuca Coelho if (ret) { 47270d3ca86SLuca Coelho IWL_ERR(mvm, "Timeout waiting for PNVM load!\n"); 47370d3ca86SLuca Coelho iwl_fw_set_current_image(&mvm->fwrt, old_type); 47470d3ca86SLuca Coelho return ret; 47570d3ca86SLuca Coelho } 47670d3ca86SLuca Coelho 477e705c121SKalle Valo iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr); 478e705c121SKalle Valo 479e705c121SKalle Valo /* 480e705c121SKalle Valo * Note: all the queues are enabled as part of the interface 481e705c121SKalle Valo * initialization, but in firmware restart scenarios they 482e705c121SKalle Valo * could be stopped, so wake them up. In firmware restart, 483e705c121SKalle Valo * mac80211 will have the queues stopped as well until the 484e705c121SKalle Valo * reconfiguration completes. During normal startup, they 485e705c121SKalle Valo * will be empty. 486e705c121SKalle Valo */ 487e705c121SKalle Valo 488e705c121SKalle Valo memset(&mvm->queue_info, 0, sizeof(mvm->queue_info)); 4891c14089eSJohannes Berg /* 4901c14089eSJohannes Berg * Set a 'fake' TID for the command queue, since we use the 4911c14089eSJohannes Berg * hweight() of the tid_bitmap as a refcount now. Not that 4921c14089eSJohannes Berg * we ever even consider the command queue as one we might 4931c14089eSJohannes Berg * want to reuse, but be safe nevertheless. 4941c14089eSJohannes Berg */ 4951c14089eSJohannes Berg mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap = 4961c14089eSJohannes Berg BIT(IWL_MAX_TID_COUNT + 2); 497e705c121SKalle Valo 49865b280feSJohannes Berg set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status); 499f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 500f7805b33SLior Cohen iwl_fw_set_dbg_rec_on(&mvm->fwrt); 501f7805b33SLior Cohen #endif 502e705c121SKalle Valo 503e705c121SKalle Valo return 0; 504e705c121SKalle Valo } 505e705c121SKalle Valo 5068c5f47b1SJohannes Berg static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) 5078c5f47b1SJohannes Berg { 5088c5f47b1SJohannes Berg struct iwl_notification_wait init_wait; 5098c5f47b1SJohannes Berg struct iwl_nvm_access_complete_cmd nvm_complete = {}; 5108c5f47b1SJohannes Berg struct iwl_init_extended_cfg_cmd init_cfg = { 5118c5f47b1SJohannes Berg .init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)), 5128c5f47b1SJohannes Berg }; 5138c5f47b1SJohannes Berg static const u16 init_complete[] = { 5148c5f47b1SJohannes Berg INIT_COMPLETE_NOTIF, 5158c5f47b1SJohannes Berg }; 5168c5f47b1SJohannes Berg int ret; 5178c5f47b1SJohannes Berg 518a4584729SHaim Dreyfuss if (mvm->trans->cfg->tx_with_siso_diversity) 519a4584729SHaim Dreyfuss init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY)); 520a4584729SHaim Dreyfuss 5218c5f47b1SJohannes Berg lockdep_assert_held(&mvm->mutex); 5228c5f47b1SJohannes Berg 52394022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 52494022562SEmmanuel Grumbach 5258c5f47b1SJohannes Berg iwl_init_notification_wait(&mvm->notif_wait, 5268c5f47b1SJohannes Berg &init_wait, 5278c5f47b1SJohannes Berg init_complete, 5288c5f47b1SJohannes Berg ARRAY_SIZE(init_complete), 5298c5f47b1SJohannes Berg iwl_wait_init_complete, 5308c5f47b1SJohannes Berg NULL); 5318c5f47b1SJohannes Berg 532b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); 53386ce5c74SShahar S Matityahu 5348c5f47b1SJohannes Berg /* Will also start the device */ 5358c5f47b1SJohannes Berg ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); 5368c5f47b1SJohannes Berg if (ret) { 5378c5f47b1SJohannes Berg IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); 5388c5f47b1SJohannes Berg goto error; 5398c5f47b1SJohannes Berg } 540b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, 541b108d8c7SShahar S Matityahu NULL); 5428c5f47b1SJohannes Berg 5438c5f47b1SJohannes Berg /* Send init config command to mark that we are sending NVM access 5448c5f47b1SJohannes Berg * commands 5458c5f47b1SJohannes Berg */ 5468c5f47b1SJohannes Berg ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP, 547b3500b47SEmmanuel Grumbach INIT_EXTENDED_CFG_CMD), 548b3500b47SEmmanuel Grumbach CMD_SEND_IN_RFKILL, 5498c5f47b1SJohannes Berg sizeof(init_cfg), &init_cfg); 5508c5f47b1SJohannes Berg if (ret) { 5518c5f47b1SJohannes Berg IWL_ERR(mvm, "Failed to run init config command: %d\n", 5528c5f47b1SJohannes Berg ret); 5538c5f47b1SJohannes Berg goto error; 5548c5f47b1SJohannes Berg } 5558c5f47b1SJohannes Berg 556e9e1ba3dSSara Sharon /* Load NVM to NIC if needed */ 557e9e1ba3dSSara Sharon if (mvm->nvm_file_name) { 5589c4f7d51SShaul Triebitz iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name, 5599c4f7d51SShaul Triebitz mvm->nvm_sections); 5608c5f47b1SJohannes Berg iwl_mvm_load_nvm_to_nic(mvm); 561e9e1ba3dSSara Sharon } 5628c5f47b1SJohannes Berg 563d4f3695eSSara Sharon if (IWL_MVM_PARSE_NVM && read_nvm) { 5645bd1d2c1SLuca Coelho ret = iwl_nvm_init(mvm); 565d4f3695eSSara Sharon if (ret) { 566d4f3695eSSara Sharon IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); 567d4f3695eSSara Sharon goto error; 568d4f3695eSSara Sharon } 569d4f3695eSSara Sharon } 570d4f3695eSSara Sharon 5718c5f47b1SJohannes Berg ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP, 572b3500b47SEmmanuel Grumbach NVM_ACCESS_COMPLETE), 573b3500b47SEmmanuel Grumbach CMD_SEND_IN_RFKILL, 5748c5f47b1SJohannes Berg sizeof(nvm_complete), &nvm_complete); 5758c5f47b1SJohannes Berg if (ret) { 5768c5f47b1SJohannes Berg IWL_ERR(mvm, "Failed to run complete NVM access: %d\n", 5778c5f47b1SJohannes Berg ret); 5788c5f47b1SJohannes Berg goto error; 5798c5f47b1SJohannes Berg } 5808c5f47b1SJohannes Berg 5818c5f47b1SJohannes Berg /* We wait for the INIT complete notification */ 582e9e1ba3dSSara Sharon ret = iwl_wait_notification(&mvm->notif_wait, &init_wait, 5838c5f47b1SJohannes Berg MVM_UCODE_ALIVE_TIMEOUT); 584e9e1ba3dSSara Sharon if (ret) 585e9e1ba3dSSara Sharon return ret; 586e9e1ba3dSSara Sharon 587e9e1ba3dSSara Sharon /* Read the NVM only at driver load time, no need to do this twice */ 588d4f3695eSSara Sharon if (!IWL_MVM_PARSE_NVM && read_nvm) { 5894c625c56SShaul Triebitz mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw); 590c135cb56SShaul Triebitz if (IS_ERR(mvm->nvm_data)) { 591c135cb56SShaul Triebitz ret = PTR_ERR(mvm->nvm_data); 592c135cb56SShaul Triebitz mvm->nvm_data = NULL; 593e9e1ba3dSSara Sharon IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); 594e9e1ba3dSSara Sharon return ret; 595e9e1ba3dSSara Sharon } 596e9e1ba3dSSara Sharon } 597e9e1ba3dSSara Sharon 598b3500b47SEmmanuel Grumbach mvm->rfkill_safe_init_done = true; 599b3500b47SEmmanuel Grumbach 600e9e1ba3dSSara Sharon return 0; 6018c5f47b1SJohannes Berg 6028c5f47b1SJohannes Berg error: 6038c5f47b1SJohannes Berg iwl_remove_notification(&mvm->notif_wait, &init_wait); 6048c5f47b1SJohannes Berg return ret; 6058c5f47b1SJohannes Berg } 6068c5f47b1SJohannes Berg 607c4ace426SGil Adam #ifdef CONFIG_ACPI 608c4ace426SGil Adam static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm, 609c4ace426SGil Adam struct iwl_phy_specific_cfg *phy_filters) 610c4ace426SGil Adam { 611c4ace426SGil Adam /* 612c4ace426SGil Adam * TODO: read specific phy config from BIOS 613c4ace426SGil Adam * ACPI table for this feature has not been defined yet, 614c4ace426SGil Adam * so for now we use hardcoded values. 615c4ace426SGil Adam */ 616c4ace426SGil Adam 617c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_A) { 618c4ace426SGil Adam phy_filters->filter_cfg_chain_a = 619c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A); 620c4ace426SGil Adam } 621c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_B) { 622c4ace426SGil Adam phy_filters->filter_cfg_chain_b = 623c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B); 624c4ace426SGil Adam } 625c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_C) { 626c4ace426SGil Adam phy_filters->filter_cfg_chain_c = 627c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C); 628c4ace426SGil Adam } 629c4ace426SGil Adam if (IWL_MVM_PHY_FILTER_CHAIN_D) { 630c4ace426SGil Adam phy_filters->filter_cfg_chain_d = 631c4ace426SGil Adam cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D); 632c4ace426SGil Adam } 633c4ace426SGil Adam } 634c4ace426SGil Adam 635c4ace426SGil Adam #else /* CONFIG_ACPI */ 636c4ace426SGil Adam 637c4ace426SGil Adam static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm, 638c4ace426SGil Adam struct iwl_phy_specific_cfg *phy_filters) 639c4ace426SGil Adam { 640c4ace426SGil Adam } 641c4ace426SGil Adam #endif /* CONFIG_ACPI */ 642c4ace426SGil Adam 643e705c121SKalle Valo static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm) 644e705c121SKalle Valo { 645c4ace426SGil Adam struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd; 646702e975dSJohannes Berg enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img; 647c4ace426SGil Adam struct iwl_phy_specific_cfg phy_filters = {}; 648c4ace426SGil Adam u8 cmd_ver; 649c4ace426SGil Adam size_t cmd_size; 650e705c121SKalle Valo 651bb99ff9bSLuca Coelho if (iwl_mvm_has_unified_ucode(mvm) && 652d923b020SLuca Coelho !mvm->trans->cfg->tx_with_siso_diversity) 653bb99ff9bSLuca Coelho return 0; 654d923b020SLuca Coelho 655d923b020SLuca Coelho if (mvm->trans->cfg->tx_with_siso_diversity) { 656bb99ff9bSLuca Coelho /* 657bb99ff9bSLuca Coelho * TODO: currently we don't set the antenna but letting the NIC 658bb99ff9bSLuca Coelho * to decide which antenna to use. This should come from BIOS. 659bb99ff9bSLuca Coelho */ 660bb99ff9bSLuca Coelho phy_cfg_cmd.phy_cfg = 661bb99ff9bSLuca Coelho cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED); 662bb99ff9bSLuca Coelho } 663bb99ff9bSLuca Coelho 664e705c121SKalle Valo /* Set parameters */ 665e705c121SKalle Valo phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm)); 66686a2b204SLuca Coelho 66786a2b204SLuca Coelho /* set flags extra PHY configuration flags from the device's cfg */ 6687897dfa2SLuca Coelho phy_cfg_cmd.phy_cfg |= 6697897dfa2SLuca Coelho cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags); 67086a2b204SLuca Coelho 671e705c121SKalle Valo phy_cfg_cmd.calib_control.event_trigger = 672e705c121SKalle Valo mvm->fw->default_calib[ucode_type].event_trigger; 673e705c121SKalle Valo phy_cfg_cmd.calib_control.flow_trigger = 674e705c121SKalle Valo mvm->fw->default_calib[ucode_type].flow_trigger; 675e705c121SKalle Valo 676c4ace426SGil Adam cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, IWL_ALWAYS_LONG_GROUP, 677e80bfd11SMordechay Goodstein PHY_CONFIGURATION_CMD, 678e80bfd11SMordechay Goodstein IWL_FW_CMD_VER_UNKNOWN); 679c4ace426SGil Adam if (cmd_ver == 3) { 680c4ace426SGil Adam iwl_mvm_phy_filter_init(mvm, &phy_filters); 681c4ace426SGil Adam memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters, 682c4ace426SGil Adam sizeof(struct iwl_phy_specific_cfg)); 683c4ace426SGil Adam } 684c4ace426SGil Adam 685e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", 686e705c121SKalle Valo phy_cfg_cmd.phy_cfg); 687c4ace426SGil Adam cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) : 688c4ace426SGil Adam sizeof(struct iwl_phy_cfg_cmd_v1); 689e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0, 690c4ace426SGil Adam cmd_size, &phy_cfg_cmd); 691e705c121SKalle Valo } 692e705c121SKalle Valo 693e705c121SKalle Valo int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm) 694e705c121SKalle Valo { 695e705c121SKalle Valo struct iwl_notification_wait calib_wait; 696e705c121SKalle Valo static const u16 init_complete[] = { 697e705c121SKalle Valo INIT_COMPLETE_NOTIF, 698e705c121SKalle Valo CALIB_RES_NOTIF_PHY_DB 699e705c121SKalle Valo }; 700e705c121SKalle Valo int ret; 701e705c121SKalle Valo 7027d6222e2SJohannes Berg if (iwl_mvm_has_unified_ucode(mvm)) 7038c5f47b1SJohannes Berg return iwl_run_unified_mvm_ucode(mvm, true); 7048c5f47b1SJohannes Berg 705e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 706e705c121SKalle Valo 70794022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 708e705c121SKalle Valo 709e705c121SKalle Valo iwl_init_notification_wait(&mvm->notif_wait, 710e705c121SKalle Valo &calib_wait, 711e705c121SKalle Valo init_complete, 712e705c121SKalle Valo ARRAY_SIZE(init_complete), 713e705c121SKalle Valo iwl_wait_phy_db_entry, 714e705c121SKalle Valo mvm->phy_db); 715e705c121SKalle Valo 716e705c121SKalle Valo /* Will also start the device */ 717e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT); 718e705c121SKalle Valo if (ret) { 719e705c121SKalle Valo IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret); 72000e0c6c8SLuca Coelho goto remove_notif; 721e705c121SKalle Valo } 722e705c121SKalle Valo 7237d34a7d7SLuca Coelho if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) { 724b3de3ef4SEmmanuel Grumbach ret = iwl_mvm_send_bt_init_conf(mvm); 725e705c121SKalle Valo if (ret) 72600e0c6c8SLuca Coelho goto remove_notif; 727b3de3ef4SEmmanuel Grumbach } 728e705c121SKalle Valo 729e705c121SKalle Valo /* Read the NVM only at driver load time, no need to do this twice */ 730e705c121SKalle Valo if (read_nvm) { 7315bd1d2c1SLuca Coelho ret = iwl_nvm_init(mvm); 732e705c121SKalle Valo if (ret) { 733e705c121SKalle Valo IWL_ERR(mvm, "Failed to read NVM: %d\n", ret); 73400e0c6c8SLuca Coelho goto remove_notif; 735e705c121SKalle Valo } 736e705c121SKalle Valo } 737e705c121SKalle Valo 738e705c121SKalle Valo /* In case we read the NVM from external file, load it to the NIC */ 739e705c121SKalle Valo if (mvm->nvm_file_name) 740e705c121SKalle Valo iwl_mvm_load_nvm_to_nic(mvm); 741e705c121SKalle Valo 74264866e5dSLuca Coelho WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver, 74364866e5dSLuca Coelho "Too old NVM version (0x%0x, required = 0x%0x)", 74464866e5dSLuca Coelho mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver); 745e705c121SKalle Valo 746e705c121SKalle Valo /* 747e705c121SKalle Valo * abort after reading the nvm in case RF Kill is on, we will complete 748e705c121SKalle Valo * the init seq later when RF kill will switch to off 749e705c121SKalle Valo */ 750e705c121SKalle Valo if (iwl_mvm_is_radio_hw_killed(mvm)) { 751e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, 752e705c121SKalle Valo "jump over all phy activities due to RF kill\n"); 75300e0c6c8SLuca Coelho goto remove_notif; 754e705c121SKalle Valo } 755e705c121SKalle Valo 756b3500b47SEmmanuel Grumbach mvm->rfkill_safe_init_done = true; 757e705c121SKalle Valo 758e705c121SKalle Valo /* Send TX valid antennas before triggering calibrations */ 759e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 760e705c121SKalle Valo if (ret) 76100e0c6c8SLuca Coelho goto remove_notif; 762e705c121SKalle Valo 763e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 764e705c121SKalle Valo if (ret) { 765e705c121SKalle Valo IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", 766e705c121SKalle Valo ret); 76700e0c6c8SLuca Coelho goto remove_notif; 768e705c121SKalle Valo } 769e705c121SKalle Valo 770e705c121SKalle Valo /* 771e705c121SKalle Valo * Some things may run in the background now, but we 772e705c121SKalle Valo * just wait for the calibration complete notification. 773e705c121SKalle Valo */ 774e705c121SKalle Valo ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait, 775e705c121SKalle Valo MVM_UCODE_CALIB_TIMEOUT); 77600e0c6c8SLuca Coelho if (!ret) 777e705c121SKalle Valo goto out; 778e705c121SKalle Valo 77900e0c6c8SLuca Coelho if (iwl_mvm_is_radio_hw_killed(mvm)) { 78000e0c6c8SLuca Coelho IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n"); 78100e0c6c8SLuca Coelho ret = 0; 78200e0c6c8SLuca Coelho } else { 78300e0c6c8SLuca Coelho IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n", 78400e0c6c8SLuca Coelho ret); 78500e0c6c8SLuca Coelho } 78600e0c6c8SLuca Coelho 78700e0c6c8SLuca Coelho goto out; 78800e0c6c8SLuca Coelho 78900e0c6c8SLuca Coelho remove_notif: 790e705c121SKalle Valo iwl_remove_notification(&mvm->notif_wait, &calib_wait); 791e705c121SKalle Valo out: 792b3500b47SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 793e705c121SKalle Valo if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) { 794e705c121SKalle Valo /* we want to debug INIT and we have no NVM - fake */ 795e705c121SKalle Valo mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) + 796e705c121SKalle Valo sizeof(struct ieee80211_channel) + 797e705c121SKalle Valo sizeof(struct ieee80211_rate), 798e705c121SKalle Valo GFP_KERNEL); 799e705c121SKalle Valo if (!mvm->nvm_data) 800e705c121SKalle Valo return -ENOMEM; 801e705c121SKalle Valo mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels; 802e705c121SKalle Valo mvm->nvm_data->bands[0].n_channels = 1; 803e705c121SKalle Valo mvm->nvm_data->bands[0].n_bitrates = 1; 804e705c121SKalle Valo mvm->nvm_data->bands[0].bitrates = 805e705c121SKalle Valo (void *)mvm->nvm_data->channels + 1; 806e705c121SKalle Valo mvm->nvm_data->bands[0].bitrates->hw_value = 10; 807e705c121SKalle Valo } 808e705c121SKalle Valo 809e705c121SKalle Valo return ret; 810e705c121SKalle Valo } 811e705c121SKalle Valo 812e705c121SKalle Valo static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) 813e705c121SKalle Valo { 814e705c121SKalle Valo struct iwl_ltr_config_cmd cmd = { 815e705c121SKalle Valo .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE), 816e705c121SKalle Valo }; 817e705c121SKalle Valo 818e705c121SKalle Valo if (!mvm->trans->ltr_enabled) 819e705c121SKalle Valo return 0; 820e705c121SKalle Valo 821e705c121SKalle Valo return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0, 822e705c121SKalle Valo sizeof(cmd), &cmd); 823e705c121SKalle Valo } 824e705c121SKalle Valo 825c386dacbSHaim Dreyfuss #ifdef CONFIG_ACPI 82642ce76d6SLuca Coelho int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b) 827da2830acSLuca Coelho { 828216cdfb5SLuca Coelho struct iwl_dev_tx_power_cmd cmd = { 829216cdfb5SLuca Coelho .common.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS), 83071e9378bSLuca Coelho }; 8319c08cef8SLuca Coelho __le16 *per_chain; 8321edd56e6SLuca Coelho int ret; 83339c1a972SIhab Zhaika u16 len = 0; 834fbb7957dSLuca Coelho u32 n_subbands; 835fbb7957dSLuca Coelho u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, LONG_GROUP, 836e80bfd11SMordechay Goodstein REDUCE_TX_POWER_CMD, 837e80bfd11SMordechay Goodstein IWL_FW_CMD_VER_UNKNOWN); 83842ce76d6SLuca Coelho 839fbb7957dSLuca Coelho if (cmd_ver == 6) { 840fbb7957dSLuca Coelho len = sizeof(cmd.v6); 841fbb7957dSLuca Coelho n_subbands = IWL_NUM_SUB_BANDS_V2; 842fbb7957dSLuca Coelho per_chain = cmd.v6.per_chain[0][0]; 843fbb7957dSLuca Coelho } else if (fw_has_api(&mvm->fw->ucode_capa, 8449c08cef8SLuca Coelho IWL_UCODE_TLV_API_REDUCE_TX_POWER)) { 8450791c2fcSHaim Dreyfuss len = sizeof(cmd.v5); 846fbb7957dSLuca Coelho n_subbands = IWL_NUM_SUB_BANDS; 8479c08cef8SLuca Coelho per_chain = cmd.v5.per_chain[0][0]; 8489c08cef8SLuca Coelho } else if (fw_has_capa(&mvm->fw->ucode_capa, 8499c08cef8SLuca Coelho IWL_UCODE_TLV_CAPA_TX_POWER_ACK)) { 850216cdfb5SLuca Coelho len = sizeof(cmd.v4); 851fbb7957dSLuca Coelho n_subbands = IWL_NUM_SUB_BANDS; 8529c08cef8SLuca Coelho per_chain = cmd.v4.per_chain[0][0]; 8539c08cef8SLuca Coelho } else { 854216cdfb5SLuca Coelho len = sizeof(cmd.v3); 855fbb7957dSLuca Coelho n_subbands = IWL_NUM_SUB_BANDS; 8569c08cef8SLuca Coelho per_chain = cmd.v3.per_chain[0][0]; 8579c08cef8SLuca Coelho } 85855bfa4b9SLuca Coelho 859216cdfb5SLuca Coelho /* all structs have the same common part, add it */ 860216cdfb5SLuca Coelho len += sizeof(cmd.common); 86142ce76d6SLuca Coelho 8629c08cef8SLuca Coelho ret = iwl_sar_select_profile(&mvm->fwrt, per_chain, ACPI_SAR_NUM_TABLES, 863fbb7957dSLuca Coelho n_subbands, prof_a, prof_b); 8641edd56e6SLuca Coelho 8651edd56e6SLuca Coelho /* return on error or if the profile is disabled (positive number) */ 8661edd56e6SLuca Coelho if (ret) 8671edd56e6SLuca Coelho return ret; 8681edd56e6SLuca Coelho 86942ce76d6SLuca Coelho IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n"); 87042ce76d6SLuca Coelho return iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd); 87142ce76d6SLuca Coelho } 87242ce76d6SLuca Coelho 8737fe90e0eSHaim Dreyfuss int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) 8747fe90e0eSHaim Dreyfuss { 875dd2a1256SLuca Coelho union iwl_geo_tx_power_profiles_cmd geo_tx_cmd; 876f604324eSLuca Coelho struct iwl_geo_tx_power_profiles_resp *resp; 8770c3d7282SHaim Dreyfuss u16 len; 87839c1a972SIhab Zhaika int ret; 8790c3d7282SHaim Dreyfuss struct iwl_host_cmd cmd; 880e80bfd11SMordechay Goodstein u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP, 881e80bfd11SMordechay Goodstein GEO_TX_POWER_LIMIT, 882e80bfd11SMordechay Goodstein IWL_FW_CMD_VER_UNKNOWN); 8837fe90e0eSHaim Dreyfuss 884dd2a1256SLuca Coelho /* the ops field is at the same spot for all versions, so set in v1 */ 885dd2a1256SLuca Coelho geo_tx_cmd.v1.ops = 886dd2a1256SLuca Coelho cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE); 887dd2a1256SLuca Coelho 8880ea788edSLuca Coelho if (cmd_ver == 3) 8890ea788edSLuca Coelho len = sizeof(geo_tx_cmd.v3); 8900ea788edSLuca Coelho else if (fw_has_api(&mvm->fwrt.fw->ucode_capa, 891dd2a1256SLuca Coelho IWL_UCODE_TLV_API_SAR_TABLE_VER)) 892dd2a1256SLuca Coelho len = sizeof(geo_tx_cmd.v2); 893dd2a1256SLuca Coelho else 894dd2a1256SLuca Coelho len = sizeof(geo_tx_cmd.v1); 8950c3d7282SHaim Dreyfuss 89639c1a972SIhab Zhaika if (!iwl_sar_geo_support(&mvm->fwrt)) 89739c1a972SIhab Zhaika return -EOPNOTSUPP; 89839c1a972SIhab Zhaika 8990c3d7282SHaim Dreyfuss cmd = (struct iwl_host_cmd){ 9007fe90e0eSHaim Dreyfuss .id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT), 9010c3d7282SHaim Dreyfuss .len = { len, }, 9027fe90e0eSHaim Dreyfuss .flags = CMD_WANT_SKB, 90339c1a972SIhab Zhaika .data = { &geo_tx_cmd }, 9047fe90e0eSHaim Dreyfuss }; 9057fe90e0eSHaim Dreyfuss 9067fe90e0eSHaim Dreyfuss ret = iwl_mvm_send_cmd(mvm, &cmd); 9077fe90e0eSHaim Dreyfuss if (ret) { 9087fe90e0eSHaim Dreyfuss IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret); 9097fe90e0eSHaim Dreyfuss return ret; 9107fe90e0eSHaim Dreyfuss } 911f604324eSLuca Coelho 912f604324eSLuca Coelho resp = (void *)cmd.resp_pkt->data; 913f604324eSLuca Coelho ret = le32_to_cpu(resp->profile_idx); 914f604324eSLuca Coelho 915f604324eSLuca Coelho if (WARN_ON(ret > ACPI_NUM_GEO_PROFILES)) 916f604324eSLuca Coelho ret = -EIO; 917f604324eSLuca Coelho 9187fe90e0eSHaim Dreyfuss iwl_free_resp(&cmd); 9197fe90e0eSHaim Dreyfuss return ret; 9207fe90e0eSHaim Dreyfuss } 9217fe90e0eSHaim Dreyfuss 922a6bff3cbSHaim Dreyfuss static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) 923a6bff3cbSHaim Dreyfuss { 924dd2a1256SLuca Coelho union iwl_geo_tx_power_profiles_cmd cmd; 92539c1a972SIhab Zhaika u16 len; 9260433ae55SGolan Ben Ami int ret; 927e80bfd11SMordechay Goodstein u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP, 928e80bfd11SMordechay Goodstein GEO_TX_POWER_LIMIT, 929e80bfd11SMordechay Goodstein IWL_FW_CMD_VER_UNKNOWN); 930a6bff3cbSHaim Dreyfuss 931dd2a1256SLuca Coelho /* the table is also at the same position both in v1 and v2 */ 9320ea788edSLuca Coelho ret = iwl_sar_geo_init(&mvm->fwrt, &cmd.v1.table[0][0], 9330ea788edSLuca Coelho ACPI_WGDS_NUM_BANDS); 934eca1e56cSEmmanuel Grumbach 9350433ae55SGolan Ben Ami /* 9360433ae55SGolan Ben Ami * It is a valid scenario to not support SAR, or miss wgds table, 9370433ae55SGolan Ben Ami * but in that case there is no need to send the command. 9380433ae55SGolan Ben Ami */ 9390433ae55SGolan Ben Ami if (ret) 9400433ae55SGolan Ben Ami return 0; 941a6bff3cbSHaim Dreyfuss 942dd2a1256SLuca Coelho /* the ops field is at the same spot for all versions, so set in v1 */ 943dd2a1256SLuca Coelho cmd.v1.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES); 944a6bff3cbSHaim Dreyfuss 9450ea788edSLuca Coelho if (cmd_ver == 3) { 9460ea788edSLuca Coelho len = sizeof(cmd.v3); 9470ea788edSLuca Coelho cmd.v3.table_revision = cpu_to_le32(mvm->fwrt.geo_rev); 9480ea788edSLuca Coelho } else if (fw_has_api(&mvm->fwrt.fw->ucode_capa, 9490c3d7282SHaim Dreyfuss IWL_UCODE_TLV_API_SAR_TABLE_VER)) { 950dd2a1256SLuca Coelho len = sizeof(cmd.v2); 951dd2a1256SLuca Coelho cmd.v2.table_revision = cpu_to_le32(mvm->fwrt.geo_rev); 95239c1a972SIhab Zhaika } else { 953dd2a1256SLuca Coelho len = sizeof(cmd.v1); 9540c3d7282SHaim Dreyfuss } 9550c3d7282SHaim Dreyfuss 956dd2a1256SLuca Coelho return iwl_mvm_send_cmd_pdu(mvm, 957dd2a1256SLuca Coelho WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT), 958dd2a1256SLuca Coelho 0, len, &cmd); 959a6bff3cbSHaim Dreyfuss } 960a6bff3cbSHaim Dreyfuss 9616ce1e5c0SGil Adam static int iwl_mvm_get_ppag_table(struct iwl_mvm *mvm) 9626ce1e5c0SGil Adam { 9636ce1e5c0SGil Adam union acpi_object *wifi_pkg, *data, *enabled; 964f2134f66SGil Adam union iwl_ppag_table_cmd ppag_table; 965f2134f66SGil Adam int i, j, ret, tbl_rev, num_sub_bands; 9666ce1e5c0SGil Adam int idx = 2; 967f2134f66SGil Adam s8 *gain; 9686ce1e5c0SGil Adam 969f2134f66SGil Adam /* 970f2134f66SGil Adam * The 'enabled' field is the same in v1 and v2 so we can just 971f2134f66SGil Adam * use v1 to access it. 972f2134f66SGil Adam */ 973f2134f66SGil Adam mvm->fwrt.ppag_table.v1.enabled = cpu_to_le32(0); 9746ce1e5c0SGil Adam data = iwl_acpi_get_object(mvm->dev, ACPI_PPAG_METHOD); 9756ce1e5c0SGil Adam if (IS_ERR(data)) 9766ce1e5c0SGil Adam return PTR_ERR(data); 9776ce1e5c0SGil Adam 978f2134f66SGil Adam /* try to read ppag table revision 1 */ 9796ce1e5c0SGil Adam wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data, 980f2134f66SGil Adam ACPI_PPAG_WIFI_DATA_SIZE_V2, &tbl_rev); 981f2134f66SGil Adam if (!IS_ERR(wifi_pkg)) { 982f2134f66SGil Adam if (tbl_rev != 1) { 983f2134f66SGil Adam ret = -EINVAL; 9846ce1e5c0SGil Adam goto out_free; 9856ce1e5c0SGil Adam } 986f2134f66SGil Adam num_sub_bands = IWL_NUM_SUB_BANDS_V2; 987f2134f66SGil Adam gain = mvm->fwrt.ppag_table.v2.gain[0]; 988f2134f66SGil Adam mvm->fwrt.ppag_ver = 2; 989f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, "Reading PPAG table v2 (tbl_rev=1)\n"); 990f2134f66SGil Adam goto read_table; 991f2134f66SGil Adam } 9926ce1e5c0SGil Adam 993f2134f66SGil Adam /* try to read ppag table revision 0 */ 994f2134f66SGil Adam wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data, 995f2134f66SGil Adam ACPI_PPAG_WIFI_DATA_SIZE, &tbl_rev); 996f2134f66SGil Adam if (!IS_ERR(wifi_pkg)) { 9973ed83da3SLuca Coelho if (tbl_rev != 0) { 9983ed83da3SLuca Coelho ret = -EINVAL; 9993ed83da3SLuca Coelho goto out_free; 10003ed83da3SLuca Coelho } 1001f2134f66SGil Adam num_sub_bands = IWL_NUM_SUB_BANDS; 1002f2134f66SGil Adam gain = mvm->fwrt.ppag_table.v1.gain[0]; 1003f2134f66SGil Adam mvm->fwrt.ppag_ver = 1; 1004f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, "Reading PPAG table v1 (tbl_rev=0)\n"); 1005f2134f66SGil Adam goto read_table; 1006f2134f66SGil Adam } 1007f2134f66SGil Adam ret = PTR_ERR(wifi_pkg); 1008f2134f66SGil Adam goto out_free; 10093ed83da3SLuca Coelho 1010f2134f66SGil Adam read_table: 10116ce1e5c0SGil Adam enabled = &wifi_pkg->package.elements[1]; 10126ce1e5c0SGil Adam if (enabled->type != ACPI_TYPE_INTEGER || 10136ce1e5c0SGil Adam (enabled->integer.value != 0 && enabled->integer.value != 1)) { 10146ce1e5c0SGil Adam ret = -EINVAL; 10156ce1e5c0SGil Adam goto out_free; 10166ce1e5c0SGil Adam } 10176ce1e5c0SGil Adam 1018f2134f66SGil Adam ppag_table.v1.enabled = cpu_to_le32(enabled->integer.value); 1019f2134f66SGil Adam if (!ppag_table.v1.enabled) { 10206ce1e5c0SGil Adam ret = 0; 10216ce1e5c0SGil Adam goto out_free; 10226ce1e5c0SGil Adam } 10236ce1e5c0SGil Adam 10246ce1e5c0SGil Adam /* 10256ce1e5c0SGil Adam * read, verify gain values and save them into the PPAG table. 10266ce1e5c0SGil Adam * first sub-band (j=0) corresponds to Low-Band (2.4GHz), and the 10276ce1e5c0SGil Adam * following sub-bands to High-Band (5GHz). 10286ce1e5c0SGil Adam */ 1029f2134f66SGil Adam for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) { 1030f2134f66SGil Adam for (j = 0; j < num_sub_bands; j++) { 10316ce1e5c0SGil Adam union acpi_object *ent; 10326ce1e5c0SGil Adam 10336ce1e5c0SGil Adam ent = &wifi_pkg->package.elements[idx++]; 10346ce1e5c0SGil Adam if (ent->type != ACPI_TYPE_INTEGER || 10356ce1e5c0SGil Adam (j == 0 && ent->integer.value > ACPI_PPAG_MAX_LB) || 10366ce1e5c0SGil Adam (j == 0 && ent->integer.value < ACPI_PPAG_MIN_LB) || 10376ce1e5c0SGil Adam (j != 0 && ent->integer.value > ACPI_PPAG_MAX_HB) || 10386ce1e5c0SGil Adam (j != 0 && ent->integer.value < ACPI_PPAG_MIN_HB)) { 1039f2134f66SGil Adam ppag_table.v1.enabled = cpu_to_le32(0); 10406ce1e5c0SGil Adam ret = -EINVAL; 10416ce1e5c0SGil Adam goto out_free; 10426ce1e5c0SGil Adam } 1043f2134f66SGil Adam gain[i * num_sub_bands + j] = ent->integer.value; 10446ce1e5c0SGil Adam } 10456ce1e5c0SGil Adam } 10466ce1e5c0SGil Adam ret = 0; 10476ce1e5c0SGil Adam out_free: 10486ce1e5c0SGil Adam kfree(data); 10496ce1e5c0SGil Adam return ret; 10506ce1e5c0SGil Adam } 10516ce1e5c0SGil Adam 10526ce1e5c0SGil Adam int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) 10536ce1e5c0SGil Adam { 1054f2134f66SGil Adam u8 cmd_ver; 1055f2134f66SGil Adam int i, j, ret, num_sub_bands, cmd_size; 1056f2134f66SGil Adam union iwl_ppag_table_cmd ppag_table; 1057f2134f66SGil Adam s8 *gain; 10586ce1e5c0SGil Adam 10596ce1e5c0SGil Adam if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) { 10606ce1e5c0SGil Adam IWL_DEBUG_RADIO(mvm, 10616ce1e5c0SGil Adam "PPAG capability not supported by FW, command not sent.\n"); 10626ce1e5c0SGil Adam return 0; 10636ce1e5c0SGil Adam } 1064f2134f66SGil Adam if (!mvm->fwrt.ppag_table.v1.enabled) { 1065f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, "PPAG not enabled, command not sent.\n"); 1066160bab43SGil Adam return 0; 1067160bab43SGil Adam } 1068160bab43SGil Adam 1069f2134f66SGil Adam cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, PHY_OPS_GROUP, 1070e80bfd11SMordechay Goodstein PER_PLATFORM_ANT_GAIN_CMD, 1071e80bfd11SMordechay Goodstein IWL_FW_CMD_VER_UNKNOWN); 1072f2134f66SGil Adam if (cmd_ver == 1) { 1073f2134f66SGil Adam num_sub_bands = IWL_NUM_SUB_BANDS; 1074f2134f66SGil Adam gain = mvm->fwrt.ppag_table.v1.gain[0]; 1075f2134f66SGil Adam cmd_size = sizeof(ppag_table.v1); 1076f2134f66SGil Adam if (mvm->fwrt.ppag_ver == 2) { 1077f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, 1078f2134f66SGil Adam "PPAG table is v2 but FW supports v1, sending truncated table\n"); 1079f2134f66SGil Adam } 1080f2134f66SGil Adam } else if (cmd_ver == 2) { 1081f2134f66SGil Adam num_sub_bands = IWL_NUM_SUB_BANDS_V2; 1082f2134f66SGil Adam gain = mvm->fwrt.ppag_table.v2.gain[0]; 1083f2134f66SGil Adam cmd_size = sizeof(ppag_table.v2); 1084f2134f66SGil Adam if (mvm->fwrt.ppag_ver == 1) { 1085f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, 1086f2134f66SGil Adam "PPAG table is v1 but FW supports v2, sending padded table\n"); 1087f2134f66SGil Adam } 1088f2134f66SGil Adam } else { 1089f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, "Unsupported PPAG command version\n"); 1090f2134f66SGil Adam return 0; 1091f2134f66SGil Adam } 10926ce1e5c0SGil Adam 1093f2134f66SGil Adam for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) { 1094f2134f66SGil Adam for (j = 0; j < num_sub_bands; j++) { 10956ce1e5c0SGil Adam IWL_DEBUG_RADIO(mvm, 10966ce1e5c0SGil Adam "PPAG table: chain[%d] band[%d]: gain = %d\n", 1097f2134f66SGil Adam i, j, gain[i * num_sub_bands + j]); 10986ce1e5c0SGil Adam } 10996ce1e5c0SGil Adam } 1100f2134f66SGil Adam IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n"); 11016ce1e5c0SGil Adam ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP, 11026ce1e5c0SGil Adam PER_PLATFORM_ANT_GAIN_CMD), 1103f2134f66SGil Adam 0, cmd_size, &ppag_table); 11046ce1e5c0SGil Adam if (ret < 0) 11056ce1e5c0SGil Adam IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n", 11066ce1e5c0SGil Adam ret); 11076ce1e5c0SGil Adam 11086ce1e5c0SGil Adam return ret; 11096ce1e5c0SGil Adam } 11106ce1e5c0SGil Adam 11116ce1e5c0SGil Adam static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) 11126ce1e5c0SGil Adam { 11136ce1e5c0SGil Adam int ret; 11146ce1e5c0SGil Adam 11156ce1e5c0SGil Adam ret = iwl_mvm_get_ppag_table(mvm); 11166ce1e5c0SGil Adam if (ret < 0) { 11176ce1e5c0SGil Adam IWL_DEBUG_RADIO(mvm, 11186ce1e5c0SGil Adam "PPAG BIOS table invalid or unavailable. (%d)\n", 11196ce1e5c0SGil Adam ret); 11206ce1e5c0SGil Adam return 0; 11216ce1e5c0SGil Adam } 11226ce1e5c0SGil Adam return iwl_mvm_ppag_send_cmd(mvm); 11236ce1e5c0SGil Adam } 11246ce1e5c0SGil Adam 112528dd7ccdSMordechay Goodstein static void iwl_mvm_tas_init(struct iwl_mvm *mvm) 112628dd7ccdSMordechay Goodstein { 112728dd7ccdSMordechay Goodstein int ret; 112828dd7ccdSMordechay Goodstein struct iwl_tas_config_cmd cmd = {}; 112928dd7ccdSMordechay Goodstein int list_size; 113028dd7ccdSMordechay Goodstein 113128dd7ccdSMordechay Goodstein BUILD_BUG_ON(ARRAY_SIZE(cmd.black_list_array) < 113228dd7ccdSMordechay Goodstein APCI_WTAS_BLACK_LIST_MAX); 113328dd7ccdSMordechay Goodstein 113428dd7ccdSMordechay Goodstein if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) { 113528dd7ccdSMordechay Goodstein IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n"); 113628dd7ccdSMordechay Goodstein return; 113728dd7ccdSMordechay Goodstein } 113828dd7ccdSMordechay Goodstein 113928dd7ccdSMordechay Goodstein ret = iwl_acpi_get_tas(&mvm->fwrt, cmd.black_list_array, &list_size); 114028dd7ccdSMordechay Goodstein if (ret < 0) { 114128dd7ccdSMordechay Goodstein IWL_DEBUG_RADIO(mvm, 114228dd7ccdSMordechay Goodstein "TAS table invalid or unavailable. (%d)\n", 114328dd7ccdSMordechay Goodstein ret); 114428dd7ccdSMordechay Goodstein return; 114528dd7ccdSMordechay Goodstein } 114628dd7ccdSMordechay Goodstein 114728dd7ccdSMordechay Goodstein if (list_size < 0) 114828dd7ccdSMordechay Goodstein return; 114928dd7ccdSMordechay Goodstein 115028dd7ccdSMordechay Goodstein /* list size if TAS enabled can only be non-negative */ 115128dd7ccdSMordechay Goodstein cmd.black_list_size = cpu_to_le32((u32)list_size); 115228dd7ccdSMordechay Goodstein 115328dd7ccdSMordechay Goodstein ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP, 115428dd7ccdSMordechay Goodstein TAS_CONFIG), 115528dd7ccdSMordechay Goodstein 0, sizeof(cmd), &cmd); 115628dd7ccdSMordechay Goodstein if (ret < 0) 115728dd7ccdSMordechay Goodstein IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret); 115828dd7ccdSMordechay Goodstein } 1159f5b1cb2eSGil Adam 116002d31e9bSGil Adam static u8 iwl_mvm_eval_dsm_indonesia_5g2(struct iwl_mvm *mvm) 1161f5b1cb2eSGil Adam { 1162f5b1cb2eSGil Adam int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0, 1163f5b1cb2eSGil Adam DSM_FUNC_ENABLE_INDONESIA_5G2); 1164f5b1cb2eSGil Adam 116502d31e9bSGil Adam if (ret < 0) 1166f5b1cb2eSGil Adam IWL_DEBUG_RADIO(mvm, 116702d31e9bSGil Adam "Failed to evaluate DSM function ENABLE_INDONESIA_5G2, ret=%d\n", 1168f5b1cb2eSGil Adam ret); 1169f5b1cb2eSGil Adam 117002d31e9bSGil Adam else if (ret >= DSM_VALUE_INDONESIA_MAX) 117102d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 117202d31e9bSGil Adam "DSM function ENABLE_INDONESIA_5G2 return invalid value, ret=%d\n", 117302d31e9bSGil Adam ret); 117402d31e9bSGil Adam 117502d31e9bSGil Adam else if (ret == DSM_VALUE_INDONESIA_ENABLE) { 117602d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 117702d31e9bSGil Adam "Evaluated DSM function ENABLE_INDONESIA_5G2: Enabling 5g2\n"); 117802d31e9bSGil Adam return DSM_VALUE_INDONESIA_ENABLE; 117902d31e9bSGil Adam } 118002d31e9bSGil Adam /* default behaviour is disabled */ 118102d31e9bSGil Adam return DSM_VALUE_INDONESIA_DISABLE; 118202d31e9bSGil Adam } 118302d31e9bSGil Adam 118402d31e9bSGil Adam static u8 iwl_mvm_eval_dsm_disable_srd(struct iwl_mvm *mvm) 118502d31e9bSGil Adam { 118602d31e9bSGil Adam int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0, 118702d31e9bSGil Adam DSM_FUNC_DISABLE_SRD); 118802d31e9bSGil Adam 118902d31e9bSGil Adam if (ret < 0) 119002d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 119102d31e9bSGil Adam "Failed to evaluate DSM function DISABLE_SRD, ret=%d\n", 119202d31e9bSGil Adam ret); 119302d31e9bSGil Adam 119402d31e9bSGil Adam else if (ret >= DSM_VALUE_SRD_MAX) 119502d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 119602d31e9bSGil Adam "DSM function DISABLE_SRD return invalid value, ret=%d\n", 119702d31e9bSGil Adam ret); 119802d31e9bSGil Adam 119902d31e9bSGil Adam else if (ret == DSM_VALUE_SRD_PASSIVE) { 120002d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 120102d31e9bSGil Adam "Evaluated DSM function DISABLE_SRD: setting SRD to passive\n"); 120202d31e9bSGil Adam return DSM_VALUE_SRD_PASSIVE; 120302d31e9bSGil Adam 120402d31e9bSGil Adam } else if (ret == DSM_VALUE_SRD_DISABLE) { 120502d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, 120602d31e9bSGil Adam "Evaluated DSM function DISABLE_SRD: disabling SRD\n"); 120702d31e9bSGil Adam return DSM_VALUE_SRD_DISABLE; 120802d31e9bSGil Adam } 120902d31e9bSGil Adam /* default behaviour is active */ 121002d31e9bSGil Adam return DSM_VALUE_SRD_ACTIVE; 1211f5b1cb2eSGil Adam } 1212f5b1cb2eSGil Adam 1213f5b1cb2eSGil Adam static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm) 1214f5b1cb2eSGil Adam { 121502d31e9bSGil Adam u8 ret; 121602d31e9bSGil Adam int cmd_ret; 1217f5b1cb2eSGil Adam struct iwl_lari_config_change_cmd cmd = {}; 1218f5b1cb2eSGil Adam 121902d31e9bSGil Adam if (iwl_mvm_eval_dsm_indonesia_5g2(mvm) == DSM_VALUE_INDONESIA_ENABLE) 1220f5b1cb2eSGil Adam cmd.config_bitmap |= 1221f5b1cb2eSGil Adam cpu_to_le32(LARI_CONFIG_ENABLE_5G2_IN_INDONESIA_MSK); 1222f5b1cb2eSGil Adam 122302d31e9bSGil Adam ret = iwl_mvm_eval_dsm_disable_srd(mvm); 122402d31e9bSGil Adam if (ret == DSM_VALUE_SRD_PASSIVE) 122502d31e9bSGil Adam cmd.config_bitmap |= 122602d31e9bSGil Adam cpu_to_le32(LARI_CONFIG_CHANGE_ETSI_TO_PASSIVE_MSK); 122702d31e9bSGil Adam 122802d31e9bSGil Adam else if (ret == DSM_VALUE_SRD_DISABLE) 122902d31e9bSGil Adam cmd.config_bitmap |= 123002d31e9bSGil Adam cpu_to_le32(LARI_CONFIG_CHANGE_ETSI_TO_DISABLED_MSK); 123102d31e9bSGil Adam 1232f5b1cb2eSGil Adam /* apply more config masks here */ 1233f5b1cb2eSGil Adam 1234f5b1cb2eSGil Adam if (cmd.config_bitmap) { 123502d31e9bSGil Adam IWL_DEBUG_RADIO(mvm, "sending LARI_CONFIG_CHANGE\n"); 123602d31e9bSGil Adam cmd_ret = iwl_mvm_send_cmd_pdu(mvm, 1237f5b1cb2eSGil Adam WIDE_ID(REGULATORY_AND_NVM_GROUP, 1238f5b1cb2eSGil Adam LARI_CONFIG_CHANGE), 1239f5b1cb2eSGil Adam 0, sizeof(cmd), &cmd); 124002d31e9bSGil Adam if (cmd_ret < 0) 1241f5b1cb2eSGil Adam IWL_DEBUG_RADIO(mvm, 1242f5b1cb2eSGil Adam "Failed to send LARI_CONFIG_CHANGE (%d)\n", 124302d31e9bSGil Adam cmd_ret); 1244f5b1cb2eSGil Adam } 1245f5b1cb2eSGil Adam } 124669964905SLuca Coelho #else /* CONFIG_ACPI */ 124739c1a972SIhab Zhaika 124839c1a972SIhab Zhaika inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, 124939c1a972SIhab Zhaika int prof_a, int prof_b) 125069964905SLuca Coelho { 125169964905SLuca Coelho return -ENOENT; 125269964905SLuca Coelho } 125369964905SLuca Coelho 125439c1a972SIhab Zhaika inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm) 12555d041c46SLuca Coelho { 12565d041c46SLuca Coelho return -ENOENT; 12575d041c46SLuca Coelho } 12585d041c46SLuca Coelho 1259a6bff3cbSHaim Dreyfuss static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) 1260a6bff3cbSHaim Dreyfuss { 1261a6bff3cbSHaim Dreyfuss return 0; 1262a6bff3cbSHaim Dreyfuss } 126318f1755dSLuca Coelho 12646ce1e5c0SGil Adam int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm) 12656ce1e5c0SGil Adam { 12666ce1e5c0SGil Adam return -ENOENT; 12676ce1e5c0SGil Adam } 12686ce1e5c0SGil Adam 12696ce1e5c0SGil Adam static int iwl_mvm_ppag_init(struct iwl_mvm *mvm) 12706ce1e5c0SGil Adam { 12717937fd32SJohannes Berg return 0; 12726ce1e5c0SGil Adam } 127328dd7ccdSMordechay Goodstein 127428dd7ccdSMordechay Goodstein static void iwl_mvm_tas_init(struct iwl_mvm *mvm) 127528dd7ccdSMordechay Goodstein { 127628dd7ccdSMordechay Goodstein } 1277f5b1cb2eSGil Adam 1278f5b1cb2eSGil Adam static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm) 1279f5b1cb2eSGil Adam { 1280f5b1cb2eSGil Adam } 128169964905SLuca Coelho #endif /* CONFIG_ACPI */ 128269964905SLuca Coelho 1283f130bb75SMordechay Goodstein void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags) 1284f130bb75SMordechay Goodstein { 1285f130bb75SMordechay Goodstein u32 error_log_size = mvm->fw->ucode_capa.error_log_size; 1286f130bb75SMordechay Goodstein int ret; 1287f130bb75SMordechay Goodstein u32 resp; 1288f130bb75SMordechay Goodstein 1289f130bb75SMordechay Goodstein struct iwl_fw_error_recovery_cmd recovery_cmd = { 1290f130bb75SMordechay Goodstein .flags = cpu_to_le32(flags), 1291f130bb75SMordechay Goodstein .buf_size = 0, 1292f130bb75SMordechay Goodstein }; 1293f130bb75SMordechay Goodstein struct iwl_host_cmd host_cmd = { 1294f130bb75SMordechay Goodstein .id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD), 1295f130bb75SMordechay Goodstein .flags = CMD_WANT_SKB, 1296f130bb75SMordechay Goodstein .data = {&recovery_cmd, }, 1297f130bb75SMordechay Goodstein .len = {sizeof(recovery_cmd), }, 1298f130bb75SMordechay Goodstein }; 1299f130bb75SMordechay Goodstein 1300f130bb75SMordechay Goodstein /* no error log was defined in TLV */ 1301f130bb75SMordechay Goodstein if (!error_log_size) 1302f130bb75SMordechay Goodstein return; 1303f130bb75SMordechay Goodstein 1304f130bb75SMordechay Goodstein if (flags & ERROR_RECOVERY_UPDATE_DB) { 1305f130bb75SMordechay Goodstein /* no buf was allocated while HW reset */ 1306f130bb75SMordechay Goodstein if (!mvm->error_recovery_buf) 1307f130bb75SMordechay Goodstein return; 1308f130bb75SMordechay Goodstein 1309f130bb75SMordechay Goodstein host_cmd.data[1] = mvm->error_recovery_buf; 1310f130bb75SMordechay Goodstein host_cmd.len[1] = error_log_size; 1311f130bb75SMordechay Goodstein host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY; 1312f130bb75SMordechay Goodstein recovery_cmd.buf_size = cpu_to_le32(error_log_size); 1313f130bb75SMordechay Goodstein } 1314f130bb75SMordechay Goodstein 1315f130bb75SMordechay Goodstein ret = iwl_mvm_send_cmd(mvm, &host_cmd); 1316f130bb75SMordechay Goodstein kfree(mvm->error_recovery_buf); 1317f130bb75SMordechay Goodstein mvm->error_recovery_buf = NULL; 1318f130bb75SMordechay Goodstein 1319f130bb75SMordechay Goodstein if (ret) { 1320f130bb75SMordechay Goodstein IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret); 1321f130bb75SMordechay Goodstein return; 1322f130bb75SMordechay Goodstein } 1323f130bb75SMordechay Goodstein 1324f130bb75SMordechay Goodstein /* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */ 1325f130bb75SMordechay Goodstein if (flags & ERROR_RECOVERY_UPDATE_DB) { 1326f130bb75SMordechay Goodstein resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data); 1327f130bb75SMordechay Goodstein if (resp) 1328f130bb75SMordechay Goodstein IWL_ERR(mvm, 1329f130bb75SMordechay Goodstein "Failed to send recovery cmd blob was invalid %d\n", 1330f130bb75SMordechay Goodstein resp); 1331f130bb75SMordechay Goodstein } 1332f130bb75SMordechay Goodstein } 1333f130bb75SMordechay Goodstein 133442ce76d6SLuca Coelho static int iwl_mvm_sar_init(struct iwl_mvm *mvm) 133542ce76d6SLuca Coelho { 133642ce76d6SLuca Coelho int ret; 133742ce76d6SLuca Coelho 133839c1a972SIhab Zhaika ret = iwl_sar_get_wrds_table(&mvm->fwrt); 1339da2830acSLuca Coelho if (ret < 0) { 1340da2830acSLuca Coelho IWL_DEBUG_RADIO(mvm, 134169964905SLuca Coelho "WRDS SAR BIOS table invalid or unavailable. (%d)\n", 1342da2830acSLuca Coelho ret); 13435d041c46SLuca Coelho /* 13445d041c46SLuca Coelho * If not available, don't fail and don't bother with EWRD. 13455d041c46SLuca Coelho * Return 1 to tell that we can't use WGDS either. 13465d041c46SLuca Coelho */ 13475d041c46SLuca Coelho return 1; 1348da2830acSLuca Coelho } 1349da2830acSLuca Coelho 135039c1a972SIhab Zhaika ret = iwl_sar_get_ewrd_table(&mvm->fwrt); 135169964905SLuca Coelho /* if EWRD is not available, we can still use WRDS, so don't fail */ 135269964905SLuca Coelho if (ret < 0) 135369964905SLuca Coelho IWL_DEBUG_RADIO(mvm, 135469964905SLuca Coelho "EWRD SAR BIOS table invalid or unavailable. (%d)\n", 135569964905SLuca Coelho ret); 135669964905SLuca Coelho 13571edd56e6SLuca Coelho return iwl_mvm_sar_select_profile(mvm, 1, 1); 1358da2830acSLuca Coelho } 1359da2830acSLuca Coelho 13601f370650SSara Sharon static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm) 13611f370650SSara Sharon { 13621f370650SSara Sharon int ret; 13631f370650SSara Sharon 13647d6222e2SJohannes Berg if (iwl_mvm_has_unified_ucode(mvm)) 13651f370650SSara Sharon return iwl_run_unified_mvm_ucode(mvm, false); 13661f370650SSara Sharon 13671f370650SSara Sharon ret = iwl_run_init_mvm_ucode(mvm, false); 13681f370650SSara Sharon 13691f370650SSara Sharon if (ret) { 13701f370650SSara Sharon IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret); 1371f4744258SLiad Kaufman 1372f4744258SLiad Kaufman if (iwlmvm_mod_params.init_dbg) 1373f4744258SLiad Kaufman return 0; 13741f370650SSara Sharon return ret; 13751f370650SSara Sharon } 13761f370650SSara Sharon 1377203c83d3SShahar S Matityahu iwl_fw_dbg_stop_sync(&mvm->fwrt); 1378bab3cb92SEmmanuel Grumbach iwl_trans_stop_device(mvm->trans); 1379bab3cb92SEmmanuel Grumbach ret = iwl_trans_start_hw(mvm->trans); 13801f370650SSara Sharon if (ret) 13811f370650SSara Sharon return ret; 13821f370650SSara Sharon 1383b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL); 1384da2eb669SSara Sharon 138594022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = false; 13861f370650SSara Sharon ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR); 13871f370650SSara Sharon if (ret) 13881f370650SSara Sharon return ret; 13891f370650SSara Sharon 139094022562SEmmanuel Grumbach mvm->rfkill_safe_init_done = true; 139194022562SEmmanuel Grumbach 1392b108d8c7SShahar S Matityahu iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE, 1393b108d8c7SShahar S Matityahu NULL); 1394da2eb669SSara Sharon 1395702e975dSJohannes Berg return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img); 13961f370650SSara Sharon } 13971f370650SSara Sharon 1398e705c121SKalle Valo int iwl_mvm_up(struct iwl_mvm *mvm) 1399e705c121SKalle Valo { 1400e705c121SKalle Valo int ret, i; 1401e705c121SKalle Valo struct ieee80211_channel *chan; 1402e705c121SKalle Valo struct cfg80211_chan_def chandef; 1403dd36a507STova Mussai struct ieee80211_supported_band *sband = NULL; 1404e705c121SKalle Valo 1405e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 1406e705c121SKalle Valo 1407e705c121SKalle Valo ret = iwl_trans_start_hw(mvm->trans); 1408e705c121SKalle Valo if (ret) 1409e705c121SKalle Valo return ret; 1410e705c121SKalle Valo 14111f370650SSara Sharon ret = iwl_mvm_load_rt_fw(mvm); 1412e705c121SKalle Valo if (ret) { 1413e705c121SKalle Valo IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); 141472d3c7bbSJohannes Berg if (ret != -ERFKILL) 141572d3c7bbSJohannes Berg iwl_fw_dbg_error_collect(&mvm->fwrt, 141672d3c7bbSJohannes Berg FW_DBG_TRIGGER_DRIVER); 1417e705c121SKalle Valo goto error; 1418e705c121SKalle Valo } 1419e705c121SKalle Valo 1420d0b813fcSJohannes Berg iwl_get_shared_mem_conf(&mvm->fwrt); 1421e705c121SKalle Valo 1422e705c121SKalle Valo ret = iwl_mvm_sf_update(mvm, NULL, false); 1423e705c121SKalle Valo if (ret) 1424e705c121SKalle Valo IWL_ERR(mvm, "Failed to initialize Smart Fifo\n"); 1425e705c121SKalle Valo 1426a1af4c48SShahar S Matityahu if (!iwl_trans_dbg_ini_valid(mvm->trans)) { 14277174beb6SJohannes Berg mvm->fwrt.dump.conf = FW_DBG_INVALID; 1428e705c121SKalle Valo /* if we have a destination, assume EARLY START */ 142917b809c9SSara Sharon if (mvm->fw->dbg.dest_tlv) 14307174beb6SJohannes Berg mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE; 14317174beb6SJohannes Berg iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE); 14327a14c23dSSara Sharon } 1433e705c121SKalle Valo 1434e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 1435e705c121SKalle Valo if (ret) 1436e705c121SKalle Valo goto error; 1437e705c121SKalle Valo 14387d6222e2SJohannes Berg if (!iwl_mvm_has_unified_ucode(mvm)) { 1439e705c121SKalle Valo /* Send phy db control command and then phy db calibration */ 1440e705c121SKalle Valo ret = iwl_send_phy_db_data(mvm->phy_db); 1441e705c121SKalle Valo if (ret) 1442e705c121SKalle Valo goto error; 1443bb99ff9bSLuca Coelho } 1444e705c121SKalle Valo 1445e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 1446e705c121SKalle Valo if (ret) 1447e705c121SKalle Valo goto error; 1448e705c121SKalle Valo 1449b3de3ef4SEmmanuel Grumbach ret = iwl_mvm_send_bt_init_conf(mvm); 1450b3de3ef4SEmmanuel Grumbach if (ret) 1451b3de3ef4SEmmanuel Grumbach goto error; 1452b3de3ef4SEmmanuel Grumbach 1453cceb4507SShahar S Matityahu if (fw_has_capa(&mvm->fw->ucode_capa, 1454cceb4507SShahar S Matityahu IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) { 1455a8eb340fSEmmanuel Grumbach ret = iwl_set_soc_latency(&mvm->fwrt); 1456cceb4507SShahar S Matityahu if (ret) 1457cceb4507SShahar S Matityahu goto error; 1458cceb4507SShahar S Matityahu } 1459cceb4507SShahar S Matityahu 146043413a97SSara Sharon /* Init RSS configuration */ 1461286ca8ebSLuca Coelho if (mvm->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) { 14628edbfaa1SSara Sharon ret = iwl_configure_rxq(mvm); 14638edbfaa1SSara Sharon if (ret) { 14648edbfaa1SSara Sharon IWL_ERR(mvm, "Failed to configure RX queues: %d\n", 14658edbfaa1SSara Sharon ret); 14668edbfaa1SSara Sharon goto error; 14678edbfaa1SSara Sharon } 14688edbfaa1SSara Sharon } 14698edbfaa1SSara Sharon 14708edbfaa1SSara Sharon if (iwl_mvm_has_new_rx_api(mvm)) { 147143413a97SSara Sharon ret = iwl_send_rss_cfg_cmd(mvm); 147243413a97SSara Sharon if (ret) { 147343413a97SSara Sharon IWL_ERR(mvm, "Failed to configure RSS queues: %d\n", 147443413a97SSara Sharon ret); 147543413a97SSara Sharon goto error; 147643413a97SSara Sharon } 147743413a97SSara Sharon } 147843413a97SSara Sharon 1479e705c121SKalle Valo /* init the fw <-> mac80211 STA mapping */ 1480be9ae34eSNathan Errera for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) 1481e705c121SKalle Valo RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); 1482e705c121SKalle Valo 14830ae98812SSara Sharon mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA; 1484e705c121SKalle Valo 1485e705c121SKalle Valo /* reset quota debouncing buffer - 0xff will yield invalid data */ 1486e705c121SKalle Valo memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd)); 1487e705c121SKalle Valo 148879660869SIlia Lin if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) { 148997d5be7eSLiad Kaufman ret = iwl_mvm_send_dqa_cmd(mvm); 149097d5be7eSLiad Kaufman if (ret) 149197d5be7eSLiad Kaufman goto error; 149279660869SIlia Lin } 149397d5be7eSLiad Kaufman 1494e705c121SKalle Valo /* Add auxiliary station for scanning */ 1495e705c121SKalle Valo ret = iwl_mvm_add_aux_sta(mvm); 1496e705c121SKalle Valo if (ret) 1497e705c121SKalle Valo goto error; 1498e705c121SKalle Valo 1499e705c121SKalle Valo /* Add all the PHY contexts */ 1500dd36a507STova Mussai i = 0; 1501dd36a507STova Mussai while (!sband && i < NUM_NL80211_BANDS) 1502dd36a507STova Mussai sband = mvm->hw->wiphy->bands[i++]; 1503dd36a507STova Mussai 1504dd36a507STova Mussai if (WARN_ON_ONCE(!sband)) 1505dd36a507STova Mussai goto error; 1506dd36a507STova Mussai 1507dd36a507STova Mussai chan = &sband->channels[0]; 1508dd36a507STova Mussai 1509e705c121SKalle Valo cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT); 1510e705c121SKalle Valo for (i = 0; i < NUM_PHY_CTX; i++) { 1511e705c121SKalle Valo /* 1512e705c121SKalle Valo * The channel used here isn't relevant as it's 1513e705c121SKalle Valo * going to be overwritten in the other flows. 1514e705c121SKalle Valo * For now use the first channel we have. 1515e705c121SKalle Valo */ 1516e705c121SKalle Valo ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i], 1517e705c121SKalle Valo &chandef, 1, 1); 1518e705c121SKalle Valo if (ret) 1519e705c121SKalle Valo goto error; 1520e705c121SKalle Valo } 1521e705c121SKalle Valo 1522c221daf2SChaya Rachel Ivgi if (iwl_mvm_is_tt_in_fw(mvm)) { 1523c221daf2SChaya Rachel Ivgi /* in order to give the responsibility of ct-kill and 1524c221daf2SChaya Rachel Ivgi * TX backoff to FW we need to send empty temperature reporting 1525c221daf2SChaya Rachel Ivgi * cmd during init time 1526c221daf2SChaya Rachel Ivgi */ 1527c221daf2SChaya Rachel Ivgi iwl_mvm_send_temp_report_ths_cmd(mvm); 1528c221daf2SChaya Rachel Ivgi } else { 1529e705c121SKalle Valo /* Initialize tx backoffs to the minimal possible */ 1530e705c121SKalle Valo iwl_mvm_tt_tx_backoff(mvm, 0); 1531c221daf2SChaya Rachel Ivgi } 15325c89e7bcSChaya Rachel Ivgi 1533242d9c8bSJohannes Berg #ifdef CONFIG_THERMAL 15345c89e7bcSChaya Rachel Ivgi /* TODO: read the budget from BIOS / Platform NVM */ 1535944eafc2SChaya Rachel Ivgi 1536944eafc2SChaya Rachel Ivgi /* 1537944eafc2SChaya Rachel Ivgi * In case there is no budget from BIOS / Platform NVM the default 1538944eafc2SChaya Rachel Ivgi * budget should be 2000mW (cooling state 0). 1539944eafc2SChaya Rachel Ivgi */ 1540944eafc2SChaya Rachel Ivgi if (iwl_mvm_is_ctdp_supported(mvm)) { 15415c89e7bcSChaya Rachel Ivgi ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START, 15425c89e7bcSChaya Rachel Ivgi mvm->cooling_dev.cur_state); 154375cfe338SLuca Coelho if (ret) 154475cfe338SLuca Coelho goto error; 154575cfe338SLuca Coelho } 1546c221daf2SChaya Rachel Ivgi #endif 1547e705c121SKalle Valo 1548aa43ae12SAlex Malamud if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2)) 1549e705c121SKalle Valo WARN_ON(iwl_mvm_config_ltr(mvm)); 1550e705c121SKalle Valo 1551e705c121SKalle Valo ret = iwl_mvm_power_update_device(mvm); 1552e705c121SKalle Valo if (ret) 1553e705c121SKalle Valo goto error; 1554e705c121SKalle Valo 1555f5b1cb2eSGil Adam iwl_mvm_lari_cfg(mvm); 1556e705c121SKalle Valo /* 1557e705c121SKalle Valo * RTNL is not taken during Ct-kill, but we don't need to scan/Tx 1558e705c121SKalle Valo * anyway, so don't init MCC. 1559e705c121SKalle Valo */ 1560e705c121SKalle Valo if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) { 1561e705c121SKalle Valo ret = iwl_mvm_init_mcc(mvm); 1562e705c121SKalle Valo if (ret) 1563e705c121SKalle Valo goto error; 1564e705c121SKalle Valo } 1565e705c121SKalle Valo 1566e705c121SKalle Valo if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) { 15674ca87a5fSEmmanuel Grumbach mvm->scan_type = IWL_SCAN_TYPE_NOT_SET; 1568b66b5817SSara Sharon mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET; 1569e705c121SKalle Valo ret = iwl_mvm_config_scan(mvm); 1570e705c121SKalle Valo if (ret) 1571e705c121SKalle Valo goto error; 1572e705c121SKalle Valo } 1573e705c121SKalle Valo 1574f130bb75SMordechay Goodstein if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) 1575f130bb75SMordechay Goodstein iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB); 1576f130bb75SMordechay Goodstein 157748e775e6SHaim Dreyfuss if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid)) 157848e775e6SHaim Dreyfuss IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n"); 157948e775e6SHaim Dreyfuss 15806ce1e5c0SGil Adam ret = iwl_mvm_ppag_init(mvm); 15816ce1e5c0SGil Adam if (ret) 15826ce1e5c0SGil Adam goto error; 15836ce1e5c0SGil Adam 1584da2830acSLuca Coelho ret = iwl_mvm_sar_init(mvm); 15855d041c46SLuca Coelho if (ret == 0) { 1586a6bff3cbSHaim Dreyfuss ret = iwl_mvm_sar_geo_init(mvm); 15871edd56e6SLuca Coelho } else if (ret == -ENOENT && !iwl_sar_get_wgds_table(&mvm->fwrt)) { 15885d041c46SLuca Coelho /* 15895d041c46SLuca Coelho * If basic SAR is not available, we check for WGDS, 15905d041c46SLuca Coelho * which should *not* be available either. If it is 15915d041c46SLuca Coelho * available, issue an error, because we can't use SAR 15925d041c46SLuca Coelho * Geo without basic SAR. 15935d041c46SLuca Coelho */ 15945d041c46SLuca Coelho IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n"); 15955d041c46SLuca Coelho } 15965d041c46SLuca Coelho 15975d041c46SLuca Coelho if (ret < 0) 1598a6bff3cbSHaim Dreyfuss goto error; 1599a6bff3cbSHaim Dreyfuss 160028dd7ccdSMordechay Goodstein iwl_mvm_tas_init(mvm); 16017089ae63SJohannes Berg iwl_mvm_leds_sync(mvm); 16027089ae63SJohannes Berg 1603b68bd2e3SIlan Peer iwl_mvm_ftm_initiator_smooth_config(mvm); 1604b68bd2e3SIlan Peer 1605e705c121SKalle Valo IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); 1606e705c121SKalle Valo return 0; 1607e705c121SKalle Valo error: 1608f4744258SLiad Kaufman if (!iwlmvm_mod_params.init_dbg || !ret) 1609fcb6b92aSChaya Rachel Ivgi iwl_mvm_stop_device(mvm); 1610e705c121SKalle Valo return ret; 1611e705c121SKalle Valo } 1612e705c121SKalle Valo 1613e705c121SKalle Valo int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm) 1614e705c121SKalle Valo { 1615e705c121SKalle Valo int ret, i; 1616e705c121SKalle Valo 1617e705c121SKalle Valo lockdep_assert_held(&mvm->mutex); 1618e705c121SKalle Valo 1619e705c121SKalle Valo ret = iwl_trans_start_hw(mvm->trans); 1620e705c121SKalle Valo if (ret) 1621e705c121SKalle Valo return ret; 1622e705c121SKalle Valo 1623e705c121SKalle Valo ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN); 1624e705c121SKalle Valo if (ret) { 1625e705c121SKalle Valo IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret); 1626e705c121SKalle Valo goto error; 1627e705c121SKalle Valo } 1628e705c121SKalle Valo 1629e705c121SKalle Valo ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm)); 1630e705c121SKalle Valo if (ret) 1631e705c121SKalle Valo goto error; 1632e705c121SKalle Valo 1633e705c121SKalle Valo /* Send phy db control command and then phy db calibration*/ 1634e705c121SKalle Valo ret = iwl_send_phy_db_data(mvm->phy_db); 1635e705c121SKalle Valo if (ret) 1636e705c121SKalle Valo goto error; 1637e705c121SKalle Valo 1638e705c121SKalle Valo ret = iwl_send_phy_cfg_cmd(mvm); 1639e705c121SKalle Valo if (ret) 1640e705c121SKalle Valo goto error; 1641e705c121SKalle Valo 1642e705c121SKalle Valo /* init the fw <-> mac80211 STA mapping */ 1643be9ae34eSNathan Errera for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) 1644e705c121SKalle Valo RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL); 1645e705c121SKalle Valo 1646e705c121SKalle Valo /* Add auxiliary station for scanning */ 1647e705c121SKalle Valo ret = iwl_mvm_add_aux_sta(mvm); 1648e705c121SKalle Valo if (ret) 1649e705c121SKalle Valo goto error; 1650e705c121SKalle Valo 1651e705c121SKalle Valo return 0; 1652e705c121SKalle Valo error: 1653fcb6b92aSChaya Rachel Ivgi iwl_mvm_stop_device(mvm); 1654e705c121SKalle Valo return ret; 1655e705c121SKalle Valo } 1656e705c121SKalle Valo 1657e705c121SKalle Valo void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm, 1658e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1659e705c121SKalle Valo { 1660e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1661e705c121SKalle Valo struct iwl_card_state_notif *card_state_notif = (void *)pkt->data; 1662e705c121SKalle Valo u32 flags = le32_to_cpu(card_state_notif->flags); 1663e705c121SKalle Valo 1664e705c121SKalle Valo IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n", 1665e705c121SKalle Valo (flags & HW_CARD_DISABLED) ? "Kill" : "On", 1666e705c121SKalle Valo (flags & SW_CARD_DISABLED) ? "Kill" : "On", 1667e705c121SKalle Valo (flags & CT_KILL_CARD_DISABLED) ? 1668e705c121SKalle Valo "Reached" : "Not reached"); 1669e705c121SKalle Valo } 1670e705c121SKalle Valo 1671e705c121SKalle Valo void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm, 1672e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1673e705c121SKalle Valo { 1674e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1675e705c121SKalle Valo struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data; 1676e705c121SKalle Valo 1677e705c121SKalle Valo IWL_DEBUG_INFO(mvm, 1678e705c121SKalle Valo "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n", 1679e705c121SKalle Valo le32_to_cpu(mfuart_notif->installed_ver), 1680e705c121SKalle Valo le32_to_cpu(mfuart_notif->external_ver), 1681e705c121SKalle Valo le32_to_cpu(mfuart_notif->status), 1682e705c121SKalle Valo le32_to_cpu(mfuart_notif->duration)); 16830c8d0a47SGolan Ben-Ami 16840c8d0a47SGolan Ben-Ami if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif)) 16850c8d0a47SGolan Ben-Ami IWL_DEBUG_INFO(mvm, 16860c8d0a47SGolan Ben-Ami "MFUART: image size: 0x%08x\n", 16870c8d0a47SGolan Ben-Ami le32_to_cpu(mfuart_notif->image_size)); 1688e705c121SKalle Valo } 1689