1e705c121SKalle Valo /******************************************************************************
2e705c121SKalle Valo  *
3e705c121SKalle Valo  * This file is provided under a dual BSD/GPLv2 license.  When using or
4e705c121SKalle Valo  * redistributing this file, you may do so under either license.
5e705c121SKalle Valo  *
6e705c121SKalle Valo  * GPL LICENSE SUMMARY
7e705c121SKalle Valo  *
8e705c121SKalle Valo  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
9bdccdb85SGolan Ben-Ami  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
10cceb4507SShahar S Matityahu  * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation
11e705c121SKalle Valo  *
12e705c121SKalle Valo  * This program is free software; you can redistribute it and/or modify
13e705c121SKalle Valo  * it under the terms of version 2 of the GNU General Public License as
14e705c121SKalle Valo  * published by the Free Software Foundation.
15e705c121SKalle Valo  *
16e705c121SKalle Valo  * This program is distributed in the hope that it will be useful, but
17e705c121SKalle Valo  * WITHOUT ANY WARRANTY; without even the implied warranty of
18e705c121SKalle Valo  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19e705c121SKalle Valo  * General Public License for more details.
20e705c121SKalle Valo  *
21e705c121SKalle Valo  * The full GNU General Public License is included in this distribution
22e705c121SKalle Valo  * in the file called COPYING.
23e705c121SKalle Valo  *
24e705c121SKalle Valo  * Contact Information:
25cb2f8277SEmmanuel Grumbach  *  Intel Linux Wireless <linuxwifi@intel.com>
26e705c121SKalle Valo  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27e705c121SKalle Valo  *
28e705c121SKalle Valo  * BSD LICENSE
29e705c121SKalle Valo  *
30e705c121SKalle Valo  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
31bdccdb85SGolan Ben-Ami  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
32cceb4507SShahar S Matityahu  * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation
33e705c121SKalle Valo  * All rights reserved.
34e705c121SKalle Valo  *
35e705c121SKalle Valo  * Redistribution and use in source and binary forms, with or without
36e705c121SKalle Valo  * modification, are permitted provided that the following conditions
37e705c121SKalle Valo  * are met:
38e705c121SKalle Valo  *
39e705c121SKalle Valo  *  * Redistributions of source code must retain the above copyright
40e705c121SKalle Valo  *    notice, this list of conditions and the following disclaimer.
41e705c121SKalle Valo  *  * Redistributions in binary form must reproduce the above copyright
42e705c121SKalle Valo  *    notice, this list of conditions and the following disclaimer in
43e705c121SKalle Valo  *    the documentation and/or other materials provided with the
44e705c121SKalle Valo  *    distribution.
45e705c121SKalle Valo  *  * Neither the name Intel Corporation nor the names of its
46e705c121SKalle Valo  *    contributors may be used to endorse or promote products derived
47e705c121SKalle Valo  *    from this software without specific prior written permission.
48e705c121SKalle Valo  *
49e705c121SKalle Valo  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50e705c121SKalle Valo  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51e705c121SKalle Valo  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52e705c121SKalle Valo  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53e705c121SKalle Valo  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54e705c121SKalle Valo  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55e705c121SKalle Valo  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56e705c121SKalle Valo  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57e705c121SKalle Valo  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58e705c121SKalle Valo  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59e705c121SKalle Valo  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60e705c121SKalle Valo  *
61e705c121SKalle Valo  *****************************************************************************/
62e705c121SKalle Valo #include <net/mac80211.h>
63854d773eSSara Sharon #include <linux/netdevice.h>
64e705c121SKalle Valo 
65e705c121SKalle Valo #include "iwl-trans.h"
66e705c121SKalle Valo #include "iwl-op-mode.h"
67d962f9b1SJohannes Berg #include "fw/img.h"
68e705c121SKalle Valo #include "iwl-debug.h"
69e705c121SKalle Valo #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */
70e705c121SKalle Valo #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */
71e705c121SKalle Valo #include "iwl-prph.h"
72813df5ceSLuca Coelho #include "fw/acpi.h"
73e705c121SKalle Valo 
74e705c121SKalle Valo #include "mvm.h"
757174beb6SJohannes Berg #include "fw/dbg.h"
76e705c121SKalle Valo #include "iwl-phy-db.h"
779c4f7d51SShaul Triebitz #include "iwl-modparams.h"
789c4f7d51SShaul Triebitz #include "iwl-nvm-parse.h"
79e705c121SKalle Valo 
80e705c121SKalle Valo #define MVM_UCODE_ALIVE_TIMEOUT	HZ
81e705c121SKalle Valo #define MVM_UCODE_CALIB_TIMEOUT	(2*HZ)
82e705c121SKalle Valo 
83e705c121SKalle Valo #define UCODE_VALID_OK	cpu_to_le32(0x1)
84e705c121SKalle Valo 
85e705c121SKalle Valo struct iwl_mvm_alive_data {
86e705c121SKalle Valo 	bool valid;
87e705c121SKalle Valo 	u32 scd_base_addr;
88e705c121SKalle Valo };
89e705c121SKalle Valo 
90e705c121SKalle Valo static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
91e705c121SKalle Valo {
92e705c121SKalle Valo 	struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
93e705c121SKalle Valo 		.valid = cpu_to_le32(valid_tx_ant),
94e705c121SKalle Valo 	};
95e705c121SKalle Valo 
96e705c121SKalle Valo 	IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
97e705c121SKalle Valo 	return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
98e705c121SKalle Valo 				    sizeof(tx_ant_cmd), &tx_ant_cmd);
99e705c121SKalle Valo }
100e705c121SKalle Valo 
10143413a97SSara Sharon static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
10243413a97SSara Sharon {
10343413a97SSara Sharon 	int i;
10443413a97SSara Sharon 	struct iwl_rss_config_cmd cmd = {
10543413a97SSara Sharon 		.flags = cpu_to_le32(IWL_RSS_ENABLE),
106608dce95SSara Sharon 		.hash_mask = BIT(IWL_RSS_HASH_TYPE_IPV4_TCP) |
107608dce95SSara Sharon 			     BIT(IWL_RSS_HASH_TYPE_IPV4_UDP) |
108608dce95SSara Sharon 			     BIT(IWL_RSS_HASH_TYPE_IPV4_PAYLOAD) |
109608dce95SSara Sharon 			     BIT(IWL_RSS_HASH_TYPE_IPV6_TCP) |
110608dce95SSara Sharon 			     BIT(IWL_RSS_HASH_TYPE_IPV6_UDP) |
111608dce95SSara Sharon 			     BIT(IWL_RSS_HASH_TYPE_IPV6_PAYLOAD),
11243413a97SSara Sharon 	};
11343413a97SSara Sharon 
114f43495fdSSara Sharon 	if (mvm->trans->num_rx_queues == 1)
115f43495fdSSara Sharon 		return 0;
116f43495fdSSara Sharon 
117854d773eSSara Sharon 	/* Do not direct RSS traffic to Q 0 which is our fallback queue */
11843413a97SSara Sharon 	for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
119854d773eSSara Sharon 		cmd.indirection_table[i] =
120854d773eSSara Sharon 			1 + (i % (mvm->trans->num_rx_queues - 1));
121854d773eSSara Sharon 	netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
12243413a97SSara Sharon 
12343413a97SSara Sharon 	return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
12443413a97SSara Sharon }
12543413a97SSara Sharon 
1268edbfaa1SSara Sharon static int iwl_configure_rxq(struct iwl_mvm *mvm)
1278edbfaa1SSara Sharon {
128dbf592f3SJohannes Berg 	int i, num_queues, size, ret;
1298edbfaa1SSara Sharon 	struct iwl_rfh_queue_config *cmd;
130dbf592f3SJohannes Berg 	struct iwl_host_cmd hcmd = {
131dbf592f3SJohannes Berg 		.id = WIDE_ID(DATA_PATH_GROUP, RFH_QUEUE_CONFIG_CMD),
132dbf592f3SJohannes Berg 		.dataflags[0] = IWL_HCMD_DFL_NOCOPY,
133dbf592f3SJohannes Berg 	};
1348edbfaa1SSara Sharon 
1358edbfaa1SSara Sharon 	/* Do not configure default queue, it is configured via context info */
1368edbfaa1SSara Sharon 	num_queues = mvm->trans->num_rx_queues - 1;
1378edbfaa1SSara Sharon 
138dbf592f3SJohannes Berg 	size = struct_size(cmd, data, num_queues);
1398edbfaa1SSara Sharon 
1408edbfaa1SSara Sharon 	cmd = kzalloc(size, GFP_KERNEL);
1418edbfaa1SSara Sharon 	if (!cmd)
1428edbfaa1SSara Sharon 		return -ENOMEM;
1438edbfaa1SSara Sharon 
1448edbfaa1SSara Sharon 	cmd->num_queues = num_queues;
1458edbfaa1SSara Sharon 
1468edbfaa1SSara Sharon 	for (i = 0; i < num_queues; i++) {
1478edbfaa1SSara Sharon 		struct iwl_trans_rxq_dma_data data;
1488edbfaa1SSara Sharon 
1498edbfaa1SSara Sharon 		cmd->data[i].q_num = i + 1;
1508edbfaa1SSara Sharon 		iwl_trans_get_rxq_dma_data(mvm->trans, i + 1, &data);
1518edbfaa1SSara Sharon 
1528edbfaa1SSara Sharon 		cmd->data[i].fr_bd_cb = cpu_to_le64(data.fr_bd_cb);
1538edbfaa1SSara Sharon 		cmd->data[i].urbd_stts_wrptr =
1548edbfaa1SSara Sharon 			cpu_to_le64(data.urbd_stts_wrptr);
1558edbfaa1SSara Sharon 		cmd->data[i].ur_bd_cb = cpu_to_le64(data.ur_bd_cb);
1568edbfaa1SSara Sharon 		cmd->data[i].fr_bd_wid = cpu_to_le32(data.fr_bd_wid);
1578edbfaa1SSara Sharon 	}
1588edbfaa1SSara Sharon 
159dbf592f3SJohannes Berg 	hcmd.data[0] = cmd;
160dbf592f3SJohannes Berg 	hcmd.len[0] = size;
161dbf592f3SJohannes Berg 
162dbf592f3SJohannes Berg 	ret = iwl_mvm_send_cmd(mvm, &hcmd);
163dbf592f3SJohannes Berg 
164dbf592f3SJohannes Berg 	kfree(cmd);
165dbf592f3SJohannes Berg 
166dbf592f3SJohannes Berg 	return ret;
1678edbfaa1SSara Sharon }
1688edbfaa1SSara Sharon 
16997d5be7eSLiad Kaufman static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
17097d5be7eSLiad Kaufman {
17197d5be7eSLiad Kaufman 	struct iwl_dqa_enable_cmd dqa_cmd = {
17297d5be7eSLiad Kaufman 		.cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
17397d5be7eSLiad Kaufman 	};
17497d5be7eSLiad Kaufman 	u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0);
17597d5be7eSLiad Kaufman 	int ret;
17697d5be7eSLiad Kaufman 
17797d5be7eSLiad Kaufman 	ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
17897d5be7eSLiad Kaufman 	if (ret)
17997d5be7eSLiad Kaufman 		IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
18097d5be7eSLiad Kaufman 	else
18197d5be7eSLiad Kaufman 		IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
18297d5be7eSLiad Kaufman 
18397d5be7eSLiad Kaufman 	return ret;
18497d5be7eSLiad Kaufman }
18597d5be7eSLiad Kaufman 
186bdccdb85SGolan Ben-Ami void iwl_mvm_mfu_assert_dump_notif(struct iwl_mvm *mvm,
187bdccdb85SGolan Ben-Ami 				   struct iwl_rx_cmd_buffer *rxb)
188bdccdb85SGolan Ben-Ami {
189bdccdb85SGolan Ben-Ami 	struct iwl_rx_packet *pkt = rxb_addr(rxb);
190bdccdb85SGolan Ben-Ami 	struct iwl_mfu_assert_dump_notif *mfu_dump_notif = (void *)pkt->data;
191bdccdb85SGolan Ben-Ami 	__le32 *dump_data = mfu_dump_notif->data;
192bdccdb85SGolan Ben-Ami 	int n_words = le32_to_cpu(mfu_dump_notif->data_size) / sizeof(__le32);
193bdccdb85SGolan Ben-Ami 	int i;
194bdccdb85SGolan Ben-Ami 
195bdccdb85SGolan Ben-Ami 	if (mfu_dump_notif->index_num == 0)
196bdccdb85SGolan Ben-Ami 		IWL_INFO(mvm, "MFUART assert id 0x%x occurred\n",
197bdccdb85SGolan Ben-Ami 			 le32_to_cpu(mfu_dump_notif->assert_id));
198bdccdb85SGolan Ben-Ami 
199bdccdb85SGolan Ben-Ami 	for (i = 0; i < n_words; i++)
200bdccdb85SGolan Ben-Ami 		IWL_DEBUG_INFO(mvm,
201bdccdb85SGolan Ben-Ami 			       "MFUART assert dump, dword %u: 0x%08x\n",
202bdccdb85SGolan Ben-Ami 			       le16_to_cpu(mfu_dump_notif->index_num) *
203bdccdb85SGolan Ben-Ami 			       n_words + i,
204bdccdb85SGolan Ben-Ami 			       le32_to_cpu(dump_data[i]));
205bdccdb85SGolan Ben-Ami }
206bdccdb85SGolan Ben-Ami 
207e705c121SKalle Valo static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
208e705c121SKalle Valo 			 struct iwl_rx_packet *pkt, void *data)
209e705c121SKalle Valo {
210e705c121SKalle Valo 	struct iwl_mvm *mvm =
211e705c121SKalle Valo 		container_of(notif_wait, struct iwl_mvm, notif_wait);
212e705c121SKalle Valo 	struct iwl_mvm_alive_data *alive_data = data;
2135c228d63SSara Sharon 	struct mvm_alive_resp_v3 *palive3;
214e705c121SKalle Valo 	struct mvm_alive_resp *palive;
2155c228d63SSara Sharon 	struct iwl_umac_alive *umac;
2165c228d63SSara Sharon 	struct iwl_lmac_alive *lmac1;
2175c228d63SSara Sharon 	struct iwl_lmac_alive *lmac2 = NULL;
2185c228d63SSara Sharon 	u16 status;
21922463857SShahar S Matityahu 	u32 lmac_error_event_table, umac_error_event_table;
220e705c121SKalle Valo 
2215c228d63SSara Sharon 	if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) {
222e705c121SKalle Valo 		palive = (void *)pkt->data;
2235c228d63SSara Sharon 		umac = &palive->umac_data;
2245c228d63SSara Sharon 		lmac1 = &palive->lmac_data[0];
2255c228d63SSara Sharon 		lmac2 = &palive->lmac_data[1];
2265c228d63SSara Sharon 		status = le16_to_cpu(palive->status);
2275c228d63SSara Sharon 	} else {
2285c228d63SSara Sharon 		palive3 = (void *)pkt->data;
2295c228d63SSara Sharon 		umac = &palive3->umac_data;
2305c228d63SSara Sharon 		lmac1 = &palive3->lmac_data;
2315c228d63SSara Sharon 		status = le16_to_cpu(palive3->status);
2325c228d63SSara Sharon 	}
233e705c121SKalle Valo 
23422463857SShahar S Matityahu 	lmac_error_event_table =
23522463857SShahar S Matityahu 		le32_to_cpu(lmac1->dbg_ptrs.error_event_table_ptr);
23622463857SShahar S Matityahu 	iwl_fw_lmac1_set_alive_err_table(mvm->trans, lmac_error_event_table);
237e705c121SKalle Valo 
23822463857SShahar S Matityahu 	if (lmac2)
23991c28b83SShahar S Matityahu 		mvm->trans->dbg.lmac_error_event_table[1] =
24022463857SShahar S Matityahu 			le32_to_cpu(lmac2->dbg_ptrs.error_event_table_ptr);
24122463857SShahar S Matityahu 
24222463857SShahar S Matityahu 	umac_error_event_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr);
2435c228d63SSara Sharon 
2443485e76eSLuca Coelho 	if (!umac_error_event_table) {
2453485e76eSLuca Coelho 		mvm->support_umac_log = false;
2463485e76eSLuca Coelho 	} else if (umac_error_event_table >=
2473485e76eSLuca Coelho 		   mvm->trans->cfg->min_umac_error_event_table) {
2483485e76eSLuca Coelho 		mvm->support_umac_log = true;
2493485e76eSLuca Coelho 	} else {
250fb5b2846SLuca Coelho 		IWL_ERR(mvm,
251fb5b2846SLuca Coelho 			"Not valid error log pointer 0x%08X for %s uCode\n",
25222463857SShahar S Matityahu 			umac_error_event_table,
253fb5b2846SLuca Coelho 			(mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ?
254fb5b2846SLuca Coelho 			"Init" : "RT");
2553485e76eSLuca Coelho 		mvm->support_umac_log = false;
2563485e76eSLuca Coelho 	}
257fb5b2846SLuca Coelho 
25822463857SShahar S Matityahu 	if (mvm->support_umac_log)
25922463857SShahar S Matityahu 		iwl_fw_umac_set_alive_err_table(mvm->trans,
26022463857SShahar S Matityahu 						umac_error_event_table);
26122463857SShahar S Matityahu 
26222463857SShahar S Matityahu 	alive_data->scd_base_addr = le32_to_cpu(lmac1->dbg_ptrs.scd_base_ptr);
2635c228d63SSara Sharon 	alive_data->valid = status == IWL_ALIVE_STATUS_OK;
264e705c121SKalle Valo 
265e705c121SKalle Valo 	IWL_DEBUG_FW(mvm,
2665c228d63SSara Sharon 		     "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n",
2675c228d63SSara Sharon 		     status, lmac1->ver_type, lmac1->ver_subtype);
2685c228d63SSara Sharon 
2695c228d63SSara Sharon 	if (lmac2)
2705c228d63SSara Sharon 		IWL_DEBUG_FW(mvm, "Alive ucode CDB\n");
271e705c121SKalle Valo 
272e705c121SKalle Valo 	IWL_DEBUG_FW(mvm,
273e705c121SKalle Valo 		     "UMAC version: Major - 0x%x, Minor - 0x%x\n",
2745c228d63SSara Sharon 		     le32_to_cpu(umac->umac_major),
2755c228d63SSara Sharon 		     le32_to_cpu(umac->umac_minor));
276e705c121SKalle Valo 
2770a3a3e9eSShahar S Matityahu 	iwl_fwrt_update_fw_versions(&mvm->fwrt, lmac1, umac);
2780a3a3e9eSShahar S Matityahu 
279e705c121SKalle Valo 	return true;
280e705c121SKalle Valo }
281e705c121SKalle Valo 
2821f370650SSara Sharon static bool iwl_wait_init_complete(struct iwl_notif_wait_data *notif_wait,
2831f370650SSara Sharon 				   struct iwl_rx_packet *pkt, void *data)
2841f370650SSara Sharon {
2851f370650SSara Sharon 	WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
2861f370650SSara Sharon 
2871f370650SSara Sharon 	return true;
2881f370650SSara Sharon }
2891f370650SSara Sharon 
290e705c121SKalle Valo static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
291e705c121SKalle Valo 				  struct iwl_rx_packet *pkt, void *data)
292e705c121SKalle Valo {
293e705c121SKalle Valo 	struct iwl_phy_db *phy_db = data;
294e705c121SKalle Valo 
295e705c121SKalle Valo 	if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
296e705c121SKalle Valo 		WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
297e705c121SKalle Valo 		return true;
298e705c121SKalle Valo 	}
299e705c121SKalle Valo 
300ce1f2778SSara Sharon 	WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
301e705c121SKalle Valo 
302e705c121SKalle Valo 	return false;
303e705c121SKalle Valo }
304e705c121SKalle Valo 
305e705c121SKalle Valo static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
306e705c121SKalle Valo 					 enum iwl_ucode_type ucode_type)
307e705c121SKalle Valo {
308e705c121SKalle Valo 	struct iwl_notification_wait alive_wait;
30994a8d87cSLuca Coelho 	struct iwl_mvm_alive_data alive_data = {};
310e705c121SKalle Valo 	const struct fw_img *fw;
311cfbc6c4cSSara Sharon 	int ret;
312702e975dSJohannes Berg 	enum iwl_ucode_type old_type = mvm->fwrt.cur_fw_img;
313e705c121SKalle Valo 	static const u16 alive_cmd[] = { MVM_ALIVE };
314b3500b47SEmmanuel Grumbach 	bool run_in_rfkill =
315b3500b47SEmmanuel Grumbach 		ucode_type == IWL_UCODE_INIT || iwl_mvm_has_unified_ucode(mvm);
316e705c121SKalle Valo 
317e705c121SKalle Valo 	if (ucode_type == IWL_UCODE_REGULAR &&
3183d2d4422SGolan Ben-Ami 	    iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
3193d2d4422SGolan Ben-Ami 	    !(fw_has_capa(&mvm->fw->ucode_capa,
3203d2d4422SGolan Ben-Ami 			  IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
321612da1efSSharon Dvir 		fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
322e705c121SKalle Valo 	else
323612da1efSSharon Dvir 		fw = iwl_get_ucode_image(mvm->fw, ucode_type);
324e705c121SKalle Valo 	if (WARN_ON(!fw))
325e705c121SKalle Valo 		return -EINVAL;
326702e975dSJohannes Berg 	iwl_fw_set_current_image(&mvm->fwrt, ucode_type);
32765b280feSJohannes Berg 	clear_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
328e705c121SKalle Valo 
329e705c121SKalle Valo 	iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
330e705c121SKalle Valo 				   alive_cmd, ARRAY_SIZE(alive_cmd),
331e705c121SKalle Valo 				   iwl_alive_fn, &alive_data);
332e705c121SKalle Valo 
333b3500b47SEmmanuel Grumbach 	/*
334b3500b47SEmmanuel Grumbach 	 * We want to load the INIT firmware even in RFKILL
335b3500b47SEmmanuel Grumbach 	 * For the unified firmware case, the ucode_type is not
336b3500b47SEmmanuel Grumbach 	 * INIT, but we still need to run it.
337b3500b47SEmmanuel Grumbach 	 */
338b3500b47SEmmanuel Grumbach 	ret = iwl_trans_start_fw(mvm->trans, fw, run_in_rfkill);
339e705c121SKalle Valo 	if (ret) {
340702e975dSJohannes Berg 		iwl_fw_set_current_image(&mvm->fwrt, old_type);
341e705c121SKalle Valo 		iwl_remove_notification(&mvm->notif_wait, &alive_wait);
342e705c121SKalle Valo 		return ret;
343e705c121SKalle Valo 	}
344e705c121SKalle Valo 
345e705c121SKalle Valo 	/*
346e705c121SKalle Valo 	 * Some things may run in the background now, but we
347e705c121SKalle Valo 	 * just wait for the ALIVE notification here.
348e705c121SKalle Valo 	 */
349e705c121SKalle Valo 	ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
350e705c121SKalle Valo 				    MVM_UCODE_ALIVE_TIMEOUT);
351e705c121SKalle Valo 	if (ret) {
352d6be9c1dSSara Sharon 		struct iwl_trans *trans = mvm->trans;
353d6be9c1dSSara Sharon 
35420f5aef5SJohannes Berg 		if (trans->trans_cfg->device_family >=
35520f5aef5SJohannes Berg 					IWL_DEVICE_FAMILY_22000) {
356e705c121SKalle Valo 			IWL_ERR(mvm,
357e705c121SKalle Valo 				"SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
358ea695b7cSShaul Triebitz 				iwl_read_umac_prph(trans, UMAG_SB_CPU_1_STATUS),
359ea695b7cSShaul Triebitz 				iwl_read_umac_prph(trans,
360ea695b7cSShaul Triebitz 						   UMAG_SB_CPU_2_STATUS));
36120f5aef5SJohannes Berg 			IWL_ERR(mvm, "UMAC PC: 0x%x\n",
36220f5aef5SJohannes Berg 				iwl_read_umac_prph(trans,
36320f5aef5SJohannes Berg 						   UREG_UMAC_CURRENT_PC));
36420f5aef5SJohannes Berg 			IWL_ERR(mvm, "LMAC PC: 0x%x\n",
36520f5aef5SJohannes Berg 				iwl_read_umac_prph(trans,
36620f5aef5SJohannes Berg 						   UREG_LMAC1_CURRENT_PC));
36720f5aef5SJohannes Berg 			if (iwl_mvm_is_cdb_supported(mvm))
36820f5aef5SJohannes Berg 				IWL_ERR(mvm, "LMAC2 PC: 0x%x\n",
36920f5aef5SJohannes Berg 					iwl_read_umac_prph(trans,
37020f5aef5SJohannes Berg 						UREG_LMAC2_CURRENT_PC));
37120f5aef5SJohannes Berg 		} else if (trans->trans_cfg->device_family >=
37220f5aef5SJohannes Berg 			   IWL_DEVICE_FAMILY_8000) {
373d6be9c1dSSara Sharon 			IWL_ERR(mvm,
374d6be9c1dSSara Sharon 				"SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
375d6be9c1dSSara Sharon 				iwl_read_prph(trans, SB_CPU_1_STATUS),
376d6be9c1dSSara Sharon 				iwl_read_prph(trans, SB_CPU_2_STATUS));
37720f5aef5SJohannes Berg 		}
37820f5aef5SJohannes Berg 
37920f5aef5SJohannes Berg 		if (ret == -ETIMEDOUT)
38020f5aef5SJohannes Berg 			iwl_fw_dbg_error_collect(&mvm->fwrt,
38120f5aef5SJohannes Berg 						 FW_DBG_TRIGGER_ALIVE_TIMEOUT);
38220f5aef5SJohannes Berg 
383702e975dSJohannes Berg 		iwl_fw_set_current_image(&mvm->fwrt, old_type);
384e705c121SKalle Valo 		return ret;
385e705c121SKalle Valo 	}
386e705c121SKalle Valo 
387e705c121SKalle Valo 	if (!alive_data.valid) {
388e705c121SKalle Valo 		IWL_ERR(mvm, "Loaded ucode is not valid!\n");
389702e975dSJohannes Berg 		iwl_fw_set_current_image(&mvm->fwrt, old_type);
390e705c121SKalle Valo 		return -EIO;
391e705c121SKalle Valo 	}
392e705c121SKalle Valo 
393e705c121SKalle Valo 	iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
394e705c121SKalle Valo 
395e705c121SKalle Valo 	/*
396e705c121SKalle Valo 	 * Note: all the queues are enabled as part of the interface
397e705c121SKalle Valo 	 * initialization, but in firmware restart scenarios they
398e705c121SKalle Valo 	 * could be stopped, so wake them up. In firmware restart,
399e705c121SKalle Valo 	 * mac80211 will have the queues stopped as well until the
400e705c121SKalle Valo 	 * reconfiguration completes. During normal startup, they
401e705c121SKalle Valo 	 * will be empty.
402e705c121SKalle Valo 	 */
403e705c121SKalle Valo 
404e705c121SKalle Valo 	memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
4051c14089eSJohannes Berg 	/*
4061c14089eSJohannes Berg 	 * Set a 'fake' TID for the command queue, since we use the
4071c14089eSJohannes Berg 	 * hweight() of the tid_bitmap as a refcount now. Not that
4081c14089eSJohannes Berg 	 * we ever even consider the command queue as one we might
4091c14089eSJohannes Berg 	 * want to reuse, but be safe nevertheless.
4101c14089eSJohannes Berg 	 */
4111c14089eSJohannes Berg 	mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].tid_bitmap =
4121c14089eSJohannes Berg 		BIT(IWL_MAX_TID_COUNT + 2);
413e705c121SKalle Valo 
41465b280feSJohannes Berg 	set_bit(IWL_MVM_STATUS_FIRMWARE_RUNNING, &mvm->status);
415f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS
416f7805b33SLior Cohen 	iwl_fw_set_dbg_rec_on(&mvm->fwrt);
417f7805b33SLior Cohen #endif
418e705c121SKalle Valo 
419e705c121SKalle Valo 	return 0;
420e705c121SKalle Valo }
421e705c121SKalle Valo 
4228c5f47b1SJohannes Berg static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
4238c5f47b1SJohannes Berg {
4248c5f47b1SJohannes Berg 	struct iwl_notification_wait init_wait;
4258c5f47b1SJohannes Berg 	struct iwl_nvm_access_complete_cmd nvm_complete = {};
4268c5f47b1SJohannes Berg 	struct iwl_init_extended_cfg_cmd init_cfg = {
4278c5f47b1SJohannes Berg 		.init_flags = cpu_to_le32(BIT(IWL_INIT_NVM)),
4288c5f47b1SJohannes Berg 	};
4298c5f47b1SJohannes Berg 	static const u16 init_complete[] = {
4308c5f47b1SJohannes Berg 		INIT_COMPLETE_NOTIF,
4318c5f47b1SJohannes Berg 	};
4328c5f47b1SJohannes Berg 	int ret;
4338c5f47b1SJohannes Berg 
434a4584729SHaim Dreyfuss 	if (mvm->trans->cfg->tx_with_siso_diversity)
435a4584729SHaim Dreyfuss 		init_cfg.init_flags |= cpu_to_le32(BIT(IWL_INIT_PHY));
436a4584729SHaim Dreyfuss 
4378c5f47b1SJohannes Berg 	lockdep_assert_held(&mvm->mutex);
4388c5f47b1SJohannes Berg 
43994022562SEmmanuel Grumbach 	mvm->rfkill_safe_init_done = false;
44094022562SEmmanuel Grumbach 
4418c5f47b1SJohannes Berg 	iwl_init_notification_wait(&mvm->notif_wait,
4428c5f47b1SJohannes Berg 				   &init_wait,
4438c5f47b1SJohannes Berg 				   init_complete,
4448c5f47b1SJohannes Berg 				   ARRAY_SIZE(init_complete),
4458c5f47b1SJohannes Berg 				   iwl_wait_init_complete,
4468c5f47b1SJohannes Berg 				   NULL);
4478c5f47b1SJohannes Berg 
448b108d8c7SShahar S Matityahu 	iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
44986ce5c74SShahar S Matityahu 
4508c5f47b1SJohannes Berg 	/* Will also start the device */
4518c5f47b1SJohannes Berg 	ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
4528c5f47b1SJohannes Berg 	if (ret) {
4538c5f47b1SJohannes Berg 		IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
4548c5f47b1SJohannes Berg 		goto error;
4558c5f47b1SJohannes Berg 	}
456b108d8c7SShahar S Matityahu 	iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
457b108d8c7SShahar S Matityahu 			       NULL);
4588c5f47b1SJohannes Berg 
4598c5f47b1SJohannes Berg 	/* Send init config command to mark that we are sending NVM access
4608c5f47b1SJohannes Berg 	 * commands
4618c5f47b1SJohannes Berg 	 */
4628c5f47b1SJohannes Berg 	ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(SYSTEM_GROUP,
463b3500b47SEmmanuel Grumbach 						INIT_EXTENDED_CFG_CMD),
464b3500b47SEmmanuel Grumbach 				   CMD_SEND_IN_RFKILL,
4658c5f47b1SJohannes Berg 				   sizeof(init_cfg), &init_cfg);
4668c5f47b1SJohannes Berg 	if (ret) {
4678c5f47b1SJohannes Berg 		IWL_ERR(mvm, "Failed to run init config command: %d\n",
4688c5f47b1SJohannes Berg 			ret);
4698c5f47b1SJohannes Berg 		goto error;
4708c5f47b1SJohannes Berg 	}
4718c5f47b1SJohannes Berg 
472e9e1ba3dSSara Sharon 	/* Load NVM to NIC if needed */
473e9e1ba3dSSara Sharon 	if (mvm->nvm_file_name) {
4749c4f7d51SShaul Triebitz 		iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
4759c4f7d51SShaul Triebitz 				      mvm->nvm_sections);
4768c5f47b1SJohannes Berg 		iwl_mvm_load_nvm_to_nic(mvm);
477e9e1ba3dSSara Sharon 	}
4788c5f47b1SJohannes Berg 
479d4f3695eSSara Sharon 	if (IWL_MVM_PARSE_NVM && read_nvm) {
4805bd1d2c1SLuca Coelho 		ret = iwl_nvm_init(mvm);
481d4f3695eSSara Sharon 		if (ret) {
482d4f3695eSSara Sharon 			IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
483d4f3695eSSara Sharon 			goto error;
484d4f3695eSSara Sharon 		}
485d4f3695eSSara Sharon 	}
486d4f3695eSSara Sharon 
4878c5f47b1SJohannes Berg 	ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
488b3500b47SEmmanuel Grumbach 						NVM_ACCESS_COMPLETE),
489b3500b47SEmmanuel Grumbach 				   CMD_SEND_IN_RFKILL,
4908c5f47b1SJohannes Berg 				   sizeof(nvm_complete), &nvm_complete);
4918c5f47b1SJohannes Berg 	if (ret) {
4928c5f47b1SJohannes Berg 		IWL_ERR(mvm, "Failed to run complete NVM access: %d\n",
4938c5f47b1SJohannes Berg 			ret);
4948c5f47b1SJohannes Berg 		goto error;
4958c5f47b1SJohannes Berg 	}
4968c5f47b1SJohannes Berg 
4978c5f47b1SJohannes Berg 	/* We wait for the INIT complete notification */
498e9e1ba3dSSara Sharon 	ret = iwl_wait_notification(&mvm->notif_wait, &init_wait,
4998c5f47b1SJohannes Berg 				    MVM_UCODE_ALIVE_TIMEOUT);
500e9e1ba3dSSara Sharon 	if (ret)
501e9e1ba3dSSara Sharon 		return ret;
502e9e1ba3dSSara Sharon 
503e9e1ba3dSSara Sharon 	/* Read the NVM only at driver load time, no need to do this twice */
504d4f3695eSSara Sharon 	if (!IWL_MVM_PARSE_NVM && read_nvm) {
5054c625c56SShaul Triebitz 		mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw);
506c135cb56SShaul Triebitz 		if (IS_ERR(mvm->nvm_data)) {
507c135cb56SShaul Triebitz 			ret = PTR_ERR(mvm->nvm_data);
508c135cb56SShaul Triebitz 			mvm->nvm_data = NULL;
509e9e1ba3dSSara Sharon 			IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
510e9e1ba3dSSara Sharon 			return ret;
511e9e1ba3dSSara Sharon 		}
512e9e1ba3dSSara Sharon 	}
513e9e1ba3dSSara Sharon 
514b3500b47SEmmanuel Grumbach 	mvm->rfkill_safe_init_done = true;
515b3500b47SEmmanuel Grumbach 
516e9e1ba3dSSara Sharon 	return 0;
5178c5f47b1SJohannes Berg 
5188c5f47b1SJohannes Berg error:
5198c5f47b1SJohannes Berg 	iwl_remove_notification(&mvm->notif_wait, &init_wait);
5208c5f47b1SJohannes Berg 	return ret;
5218c5f47b1SJohannes Berg }
5228c5f47b1SJohannes Berg 
523c4ace426SGil Adam #ifdef CONFIG_ACPI
524c4ace426SGil Adam static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
525c4ace426SGil Adam 				    struct iwl_phy_specific_cfg *phy_filters)
526c4ace426SGil Adam {
527c4ace426SGil Adam 	/*
528c4ace426SGil Adam 	 * TODO: read specific phy config from BIOS
529c4ace426SGil Adam 	 * ACPI table for this feature has not been defined yet,
530c4ace426SGil Adam 	 * so for now we use hardcoded values.
531c4ace426SGil Adam 	 */
532c4ace426SGil Adam 
533c4ace426SGil Adam 	if (IWL_MVM_PHY_FILTER_CHAIN_A) {
534c4ace426SGil Adam 		phy_filters->filter_cfg_chain_a =
535c4ace426SGil Adam 			cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A);
536c4ace426SGil Adam 	}
537c4ace426SGil Adam 	if (IWL_MVM_PHY_FILTER_CHAIN_B) {
538c4ace426SGil Adam 		phy_filters->filter_cfg_chain_b =
539c4ace426SGil Adam 			cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B);
540c4ace426SGil Adam 	}
541c4ace426SGil Adam 	if (IWL_MVM_PHY_FILTER_CHAIN_C) {
542c4ace426SGil Adam 		phy_filters->filter_cfg_chain_c =
543c4ace426SGil Adam 			cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C);
544c4ace426SGil Adam 	}
545c4ace426SGil Adam 	if (IWL_MVM_PHY_FILTER_CHAIN_D) {
546c4ace426SGil Adam 		phy_filters->filter_cfg_chain_d =
547c4ace426SGil Adam 			cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D);
548c4ace426SGil Adam 	}
549c4ace426SGil Adam }
550c4ace426SGil Adam 
551c4ace426SGil Adam #else /* CONFIG_ACPI */
552c4ace426SGil Adam 
553c4ace426SGil Adam static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
554c4ace426SGil Adam 				    struct iwl_phy_specific_cfg *phy_filters)
555c4ace426SGil Adam {
556c4ace426SGil Adam }
557c4ace426SGil Adam #endif /* CONFIG_ACPI */
558c4ace426SGil Adam 
559e705c121SKalle Valo static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
560e705c121SKalle Valo {
561c4ace426SGil Adam 	struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd;
562702e975dSJohannes Berg 	enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
563c4ace426SGil Adam 	struct iwl_phy_specific_cfg phy_filters = {};
564c4ace426SGil Adam 	u8 cmd_ver;
565c4ace426SGil Adam 	size_t cmd_size;
566e705c121SKalle Valo 
567bb99ff9bSLuca Coelho 	if (iwl_mvm_has_unified_ucode(mvm) &&
568d923b020SLuca Coelho 	    !mvm->trans->cfg->tx_with_siso_diversity)
569bb99ff9bSLuca Coelho 		return 0;
570d923b020SLuca Coelho 
571d923b020SLuca Coelho 	if (mvm->trans->cfg->tx_with_siso_diversity) {
572bb99ff9bSLuca Coelho 		/*
573bb99ff9bSLuca Coelho 		 * TODO: currently we don't set the antenna but letting the NIC
574bb99ff9bSLuca Coelho 		 * to decide which antenna to use. This should come from BIOS.
575bb99ff9bSLuca Coelho 		 */
576bb99ff9bSLuca Coelho 		phy_cfg_cmd.phy_cfg =
577bb99ff9bSLuca Coelho 			cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED);
578bb99ff9bSLuca Coelho 	}
579bb99ff9bSLuca Coelho 
580e705c121SKalle Valo 	/* Set parameters */
581e705c121SKalle Valo 	phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
58286a2b204SLuca Coelho 
58386a2b204SLuca Coelho 	/* set flags extra PHY configuration flags from the device's cfg */
5847897dfa2SLuca Coelho 	phy_cfg_cmd.phy_cfg |=
5857897dfa2SLuca Coelho 		cpu_to_le32(mvm->trans->trans_cfg->extra_phy_cfg_flags);
58686a2b204SLuca Coelho 
587e705c121SKalle Valo 	phy_cfg_cmd.calib_control.event_trigger =
588e705c121SKalle Valo 		mvm->fw->default_calib[ucode_type].event_trigger;
589e705c121SKalle Valo 	phy_cfg_cmd.calib_control.flow_trigger =
590e705c121SKalle Valo 		mvm->fw->default_calib[ucode_type].flow_trigger;
591e705c121SKalle Valo 
592c4ace426SGil Adam 	cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, IWL_ALWAYS_LONG_GROUP,
593c4ace426SGil Adam 					PHY_CONFIGURATION_CMD);
594c4ace426SGil Adam 	if (cmd_ver == 3) {
595c4ace426SGil Adam 		iwl_mvm_phy_filter_init(mvm, &phy_filters);
596c4ace426SGil Adam 		memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters,
597c4ace426SGil Adam 		       sizeof(struct iwl_phy_specific_cfg));
598c4ace426SGil Adam 	}
599c4ace426SGil Adam 
600e705c121SKalle Valo 	IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
601e705c121SKalle Valo 		       phy_cfg_cmd.phy_cfg);
602c4ace426SGil Adam 	cmd_size = (cmd_ver == 3) ? sizeof(struct iwl_phy_cfg_cmd_v3) :
603c4ace426SGil Adam 				    sizeof(struct iwl_phy_cfg_cmd_v1);
604e705c121SKalle Valo 	return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0,
605c4ace426SGil Adam 				    cmd_size, &phy_cfg_cmd);
606e705c121SKalle Valo }
607e705c121SKalle Valo 
608e705c121SKalle Valo int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
609e705c121SKalle Valo {
610e705c121SKalle Valo 	struct iwl_notification_wait calib_wait;
611e705c121SKalle Valo 	static const u16 init_complete[] = {
612e705c121SKalle Valo 		INIT_COMPLETE_NOTIF,
613e705c121SKalle Valo 		CALIB_RES_NOTIF_PHY_DB
614e705c121SKalle Valo 	};
615e705c121SKalle Valo 	int ret;
616e705c121SKalle Valo 
6177d6222e2SJohannes Berg 	if (iwl_mvm_has_unified_ucode(mvm))
6188c5f47b1SJohannes Berg 		return iwl_run_unified_mvm_ucode(mvm, true);
6198c5f47b1SJohannes Berg 
620e705c121SKalle Valo 	lockdep_assert_held(&mvm->mutex);
621e705c121SKalle Valo 
62294022562SEmmanuel Grumbach 	mvm->rfkill_safe_init_done = false;
623e705c121SKalle Valo 
624e705c121SKalle Valo 	iwl_init_notification_wait(&mvm->notif_wait,
625e705c121SKalle Valo 				   &calib_wait,
626e705c121SKalle Valo 				   init_complete,
627e705c121SKalle Valo 				   ARRAY_SIZE(init_complete),
628e705c121SKalle Valo 				   iwl_wait_phy_db_entry,
629e705c121SKalle Valo 				   mvm->phy_db);
630e705c121SKalle Valo 
631e705c121SKalle Valo 	/* Will also start the device */
632e705c121SKalle Valo 	ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
633e705c121SKalle Valo 	if (ret) {
634e705c121SKalle Valo 		IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
63500e0c6c8SLuca Coelho 		goto remove_notif;
636e705c121SKalle Valo 	}
637e705c121SKalle Valo 
6387d34a7d7SLuca Coelho 	if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) {
639b3de3ef4SEmmanuel Grumbach 		ret = iwl_mvm_send_bt_init_conf(mvm);
640e705c121SKalle Valo 		if (ret)
64100e0c6c8SLuca Coelho 			goto remove_notif;
642b3de3ef4SEmmanuel Grumbach 	}
643e705c121SKalle Valo 
644e705c121SKalle Valo 	/* Read the NVM only at driver load time, no need to do this twice */
645e705c121SKalle Valo 	if (read_nvm) {
6465bd1d2c1SLuca Coelho 		ret = iwl_nvm_init(mvm);
647e705c121SKalle Valo 		if (ret) {
648e705c121SKalle Valo 			IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
64900e0c6c8SLuca Coelho 			goto remove_notif;
650e705c121SKalle Valo 		}
651e705c121SKalle Valo 	}
652e705c121SKalle Valo 
653e705c121SKalle Valo 	/* In case we read the NVM from external file, load it to the NIC */
654e705c121SKalle Valo 	if (mvm->nvm_file_name)
655e705c121SKalle Valo 		iwl_mvm_load_nvm_to_nic(mvm);
656e705c121SKalle Valo 
65764866e5dSLuca Coelho 	WARN_ONCE(mvm->nvm_data->nvm_version < mvm->trans->cfg->nvm_ver,
65864866e5dSLuca Coelho 		  "Too old NVM version (0x%0x, required = 0x%0x)",
65964866e5dSLuca Coelho 		  mvm->nvm_data->nvm_version, mvm->trans->cfg->nvm_ver);
660e705c121SKalle Valo 
661e705c121SKalle Valo 	/*
662e705c121SKalle Valo 	 * abort after reading the nvm in case RF Kill is on, we will complete
663e705c121SKalle Valo 	 * the init seq later when RF kill will switch to off
664e705c121SKalle Valo 	 */
665e705c121SKalle Valo 	if (iwl_mvm_is_radio_hw_killed(mvm)) {
666e705c121SKalle Valo 		IWL_DEBUG_RF_KILL(mvm,
667e705c121SKalle Valo 				  "jump over all phy activities due to RF kill\n");
66800e0c6c8SLuca Coelho 		goto remove_notif;
669e705c121SKalle Valo 	}
670e705c121SKalle Valo 
671b3500b47SEmmanuel Grumbach 	mvm->rfkill_safe_init_done = true;
672e705c121SKalle Valo 
673e705c121SKalle Valo 	/* Send TX valid antennas before triggering calibrations */
674e705c121SKalle Valo 	ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
675e705c121SKalle Valo 	if (ret)
67600e0c6c8SLuca Coelho 		goto remove_notif;
677e705c121SKalle Valo 
678e705c121SKalle Valo 	ret = iwl_send_phy_cfg_cmd(mvm);
679e705c121SKalle Valo 	if (ret) {
680e705c121SKalle Valo 		IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
681e705c121SKalle Valo 			ret);
68200e0c6c8SLuca Coelho 		goto remove_notif;
683e705c121SKalle Valo 	}
684e705c121SKalle Valo 
685e705c121SKalle Valo 	/*
686e705c121SKalle Valo 	 * Some things may run in the background now, but we
687e705c121SKalle Valo 	 * just wait for the calibration complete notification.
688e705c121SKalle Valo 	 */
689e705c121SKalle Valo 	ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
690e705c121SKalle Valo 				    MVM_UCODE_CALIB_TIMEOUT);
69100e0c6c8SLuca Coelho 	if (!ret)
692e705c121SKalle Valo 		goto out;
693e705c121SKalle Valo 
69400e0c6c8SLuca Coelho 	if (iwl_mvm_is_radio_hw_killed(mvm)) {
69500e0c6c8SLuca Coelho 		IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
69600e0c6c8SLuca Coelho 		ret = 0;
69700e0c6c8SLuca Coelho 	} else {
69800e0c6c8SLuca Coelho 		IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
69900e0c6c8SLuca Coelho 			ret);
70000e0c6c8SLuca Coelho 	}
70100e0c6c8SLuca Coelho 
70200e0c6c8SLuca Coelho 	goto out;
70300e0c6c8SLuca Coelho 
70400e0c6c8SLuca Coelho remove_notif:
705e705c121SKalle Valo 	iwl_remove_notification(&mvm->notif_wait, &calib_wait);
706e705c121SKalle Valo out:
707b3500b47SEmmanuel Grumbach 	mvm->rfkill_safe_init_done = false;
708e705c121SKalle Valo 	if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
709e705c121SKalle Valo 		/* we want to debug INIT and we have no NVM - fake */
710e705c121SKalle Valo 		mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
711e705c121SKalle Valo 					sizeof(struct ieee80211_channel) +
712e705c121SKalle Valo 					sizeof(struct ieee80211_rate),
713e705c121SKalle Valo 					GFP_KERNEL);
714e705c121SKalle Valo 		if (!mvm->nvm_data)
715e705c121SKalle Valo 			return -ENOMEM;
716e705c121SKalle Valo 		mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
717e705c121SKalle Valo 		mvm->nvm_data->bands[0].n_channels = 1;
718e705c121SKalle Valo 		mvm->nvm_data->bands[0].n_bitrates = 1;
719e705c121SKalle Valo 		mvm->nvm_data->bands[0].bitrates =
720e705c121SKalle Valo 			(void *)mvm->nvm_data->channels + 1;
721e705c121SKalle Valo 		mvm->nvm_data->bands[0].bitrates->hw_value = 10;
722e705c121SKalle Valo 	}
723e705c121SKalle Valo 
724e705c121SKalle Valo 	return ret;
725e705c121SKalle Valo }
726e705c121SKalle Valo 
727e705c121SKalle Valo static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
728e705c121SKalle Valo {
729e705c121SKalle Valo 	struct iwl_ltr_config_cmd cmd = {
730e705c121SKalle Valo 		.flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
731e705c121SKalle Valo 	};
732e705c121SKalle Valo 
733e705c121SKalle Valo 	if (!mvm->trans->ltr_enabled)
734e705c121SKalle Valo 		return 0;
735e705c121SKalle Valo 
736e705c121SKalle Valo 	return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
737e705c121SKalle Valo 				    sizeof(cmd), &cmd);
738e705c121SKalle Valo }
739e705c121SKalle Valo 
740c386dacbSHaim Dreyfuss #ifdef CONFIG_ACPI
74142ce76d6SLuca Coelho int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm, int prof_a, int prof_b)
742da2830acSLuca Coelho {
7430791c2fcSHaim Dreyfuss 	union {
7440791c2fcSHaim Dreyfuss 		struct iwl_dev_tx_power_cmd v5;
7450791c2fcSHaim Dreyfuss 		struct iwl_dev_tx_power_cmd_v4 v4;
74671e9378bSLuca Coelho 	} cmd = {
74771e9378bSLuca Coelho 		.v5.v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
74871e9378bSLuca Coelho 	};
7491edd56e6SLuca Coelho 	int ret;
75039c1a972SIhab Zhaika 	u16 len = 0;
75142ce76d6SLuca Coelho 
7520791c2fcSHaim Dreyfuss 	if (fw_has_api(&mvm->fw->ucode_capa,
7530791c2fcSHaim Dreyfuss 		       IWL_UCODE_TLV_API_REDUCE_TX_POWER))
7540791c2fcSHaim Dreyfuss 		len = sizeof(cmd.v5);
7550791c2fcSHaim Dreyfuss 	else if (fw_has_capa(&mvm->fw->ucode_capa,
7560791c2fcSHaim Dreyfuss 			     IWL_UCODE_TLV_CAPA_TX_POWER_ACK))
75739c1a972SIhab Zhaika 		len = sizeof(struct iwl_dev_tx_power_cmd_v4);
7580791c2fcSHaim Dreyfuss 	else
7590791c2fcSHaim Dreyfuss 		len = sizeof(cmd.v4.v3);
76055bfa4b9SLuca Coelho 
76142ce76d6SLuca Coelho 
7621edd56e6SLuca Coelho 	ret = iwl_sar_select_profile(&mvm->fwrt,
7631edd56e6SLuca Coelho 				     cmd.v5.v3.per_chain_restriction,
7641edd56e6SLuca Coelho 				     prof_a, prof_b);
7651edd56e6SLuca Coelho 
7661edd56e6SLuca Coelho 	/* return on error or if the profile is disabled (positive number) */
7671edd56e6SLuca Coelho 	if (ret)
7681edd56e6SLuca Coelho 		return ret;
7691edd56e6SLuca Coelho 
77042ce76d6SLuca Coelho 	IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
77142ce76d6SLuca Coelho 	return iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd);
77242ce76d6SLuca Coelho }
77342ce76d6SLuca Coelho 
7747fe90e0eSHaim Dreyfuss int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
7757fe90e0eSHaim Dreyfuss {
77639c1a972SIhab Zhaika 	union geo_tx_power_profiles_cmd geo_tx_cmd;
7770c3d7282SHaim Dreyfuss 	u16 len;
77839c1a972SIhab Zhaika 	int ret;
7790c3d7282SHaim Dreyfuss 	struct iwl_host_cmd cmd;
7807fe90e0eSHaim Dreyfuss 
78139c1a972SIhab Zhaika 	if (fw_has_api(&mvm->fwrt.fw->ucode_capa,
78239c1a972SIhab Zhaika 		       IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
78339c1a972SIhab Zhaika 		geo_tx_cmd.geo_cmd.ops =
7840c3d7282SHaim Dreyfuss 			cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
78539c1a972SIhab Zhaika 		len = sizeof(geo_tx_cmd.geo_cmd);
7860c3d7282SHaim Dreyfuss 	} else {
78739c1a972SIhab Zhaika 		geo_tx_cmd.geo_cmd_v1.ops =
7880c3d7282SHaim Dreyfuss 			cpu_to_le32(IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE);
78939c1a972SIhab Zhaika 		len = sizeof(geo_tx_cmd.geo_cmd_v1);
7900c3d7282SHaim Dreyfuss 	}
7910c3d7282SHaim Dreyfuss 
79239c1a972SIhab Zhaika 	if (!iwl_sar_geo_support(&mvm->fwrt))
79339c1a972SIhab Zhaika 		return -EOPNOTSUPP;
79439c1a972SIhab Zhaika 
7950c3d7282SHaim Dreyfuss 	cmd = (struct iwl_host_cmd){
7967fe90e0eSHaim Dreyfuss 		.id =  WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT),
7970c3d7282SHaim Dreyfuss 		.len = { len, },
7987fe90e0eSHaim Dreyfuss 		.flags = CMD_WANT_SKB,
79939c1a972SIhab Zhaika 		.data = { &geo_tx_cmd },
8007fe90e0eSHaim Dreyfuss 	};
8017fe90e0eSHaim Dreyfuss 
8027fe90e0eSHaim Dreyfuss 	ret = iwl_mvm_send_cmd(mvm, &cmd);
8037fe90e0eSHaim Dreyfuss 	if (ret) {
8047fe90e0eSHaim Dreyfuss 		IWL_ERR(mvm, "Failed to get geographic profile info %d\n", ret);
8057fe90e0eSHaim Dreyfuss 		return ret;
8067fe90e0eSHaim Dreyfuss 	}
80739c1a972SIhab Zhaika 	ret = iwl_validate_sar_geo_profile(&mvm->fwrt, &cmd);
8087fe90e0eSHaim Dreyfuss 	iwl_free_resp(&cmd);
8097fe90e0eSHaim Dreyfuss 	return ret;
8107fe90e0eSHaim Dreyfuss }
8117fe90e0eSHaim Dreyfuss 
812a6bff3cbSHaim Dreyfuss static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
813a6bff3cbSHaim Dreyfuss {
814a6bff3cbSHaim Dreyfuss 	u16 cmd_wide_id =  WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT);
81539c1a972SIhab Zhaika 	union geo_tx_power_profiles_cmd cmd;
81639c1a972SIhab Zhaika 	u16 len;
8170433ae55SGolan Ben Ami 	int ret;
818a6bff3cbSHaim Dreyfuss 
81939c1a972SIhab Zhaika 	cmd.geo_cmd.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES);
820eca1e56cSEmmanuel Grumbach 
8210433ae55SGolan Ben Ami 	ret = iwl_sar_geo_init(&mvm->fwrt, cmd.geo_cmd.table);
8220433ae55SGolan Ben Ami 	/*
8230433ae55SGolan Ben Ami 	 * It is a valid scenario to not support SAR, or miss wgds table,
8240433ae55SGolan Ben Ami 	 * but in that case there is no need to send the command.
8250433ae55SGolan Ben Ami 	 */
8260433ae55SGolan Ben Ami 	if (ret)
8270433ae55SGolan Ben Ami 		return 0;
828a6bff3cbSHaim Dreyfuss 
82939c1a972SIhab Zhaika 	cmd.geo_cmd.table_revision = cpu_to_le32(mvm->fwrt.geo_rev);
830a6bff3cbSHaim Dreyfuss 
83139c1a972SIhab Zhaika 	if (!fw_has_api(&mvm->fwrt.fw->ucode_capa,
8320c3d7282SHaim Dreyfuss 			IWL_UCODE_TLV_API_SAR_TABLE_VER)) {
83339c1a972SIhab Zhaika 		len = sizeof(struct iwl_geo_tx_power_profiles_cmd_v1);
83439c1a972SIhab Zhaika 	} else {
83539c1a972SIhab Zhaika 		len =  sizeof(cmd.geo_cmd);
8360c3d7282SHaim Dreyfuss 	}
8370c3d7282SHaim Dreyfuss 
83839c1a972SIhab Zhaika 	return iwl_mvm_send_cmd_pdu(mvm, cmd_wide_id, 0, len, &cmd);
839a6bff3cbSHaim Dreyfuss }
840a6bff3cbSHaim Dreyfuss 
8416ce1e5c0SGil Adam static int iwl_mvm_get_ppag_table(struct iwl_mvm *mvm)
8426ce1e5c0SGil Adam {
8436ce1e5c0SGil Adam 	union acpi_object *wifi_pkg, *data, *enabled;
8446ce1e5c0SGil Adam 	int i, j, ret, tbl_rev;
8456ce1e5c0SGil Adam 	int idx = 2;
8466ce1e5c0SGil Adam 
84739c1a972SIhab Zhaika 	mvm->fwrt.ppag_table.enabled = cpu_to_le32(0);
8486ce1e5c0SGil Adam 	data = iwl_acpi_get_object(mvm->dev, ACPI_PPAG_METHOD);
8496ce1e5c0SGil Adam 	if (IS_ERR(data))
8506ce1e5c0SGil Adam 		return PTR_ERR(data);
8516ce1e5c0SGil Adam 
8526ce1e5c0SGil Adam 	wifi_pkg = iwl_acpi_get_wifi_pkg(mvm->dev, data,
8536ce1e5c0SGil Adam 					 ACPI_PPAG_WIFI_DATA_SIZE, &tbl_rev);
8546ce1e5c0SGil Adam 
8553ed83da3SLuca Coelho 	if (IS_ERR(wifi_pkg)) {
8566ce1e5c0SGil Adam 		ret = PTR_ERR(wifi_pkg);
8576ce1e5c0SGil Adam 		goto out_free;
8586ce1e5c0SGil Adam 	}
8596ce1e5c0SGil Adam 
8603ed83da3SLuca Coelho 	if (tbl_rev != 0) {
8613ed83da3SLuca Coelho 		ret = -EINVAL;
8623ed83da3SLuca Coelho 		goto out_free;
8633ed83da3SLuca Coelho 	}
8643ed83da3SLuca Coelho 
8656ce1e5c0SGil Adam 	enabled = &wifi_pkg->package.elements[1];
8666ce1e5c0SGil Adam 	if (enabled->type != ACPI_TYPE_INTEGER ||
8676ce1e5c0SGil Adam 	    (enabled->integer.value != 0 && enabled->integer.value != 1)) {
8686ce1e5c0SGil Adam 		ret = -EINVAL;
8696ce1e5c0SGil Adam 		goto out_free;
8706ce1e5c0SGil Adam 	}
8716ce1e5c0SGil Adam 
87239c1a972SIhab Zhaika 	mvm->fwrt.ppag_table.enabled = cpu_to_le32(enabled->integer.value);
87339c1a972SIhab Zhaika 	if (!mvm->fwrt.ppag_table.enabled) {
8746ce1e5c0SGil Adam 		ret = 0;
8756ce1e5c0SGil Adam 		goto out_free;
8766ce1e5c0SGil Adam 	}
8776ce1e5c0SGil Adam 
8786ce1e5c0SGil Adam 	/*
8796ce1e5c0SGil Adam 	 * read, verify gain values and save them into the PPAG table.
8806ce1e5c0SGil Adam 	 * first sub-band (j=0) corresponds to Low-Band (2.4GHz), and the
8816ce1e5c0SGil Adam 	 * following sub-bands to High-Band (5GHz).
8826ce1e5c0SGil Adam 	 */
8836ce1e5c0SGil Adam 	for (i = 0; i < ACPI_PPAG_NUM_CHAINS; i++) {
8846ce1e5c0SGil Adam 		for (j = 0; j < ACPI_PPAG_NUM_SUB_BANDS; j++) {
8856ce1e5c0SGil Adam 			union acpi_object *ent;
8866ce1e5c0SGil Adam 
8876ce1e5c0SGil Adam 			ent = &wifi_pkg->package.elements[idx++];
8886ce1e5c0SGil Adam 			if (ent->type != ACPI_TYPE_INTEGER ||
8896ce1e5c0SGil Adam 			    (j == 0 && ent->integer.value > ACPI_PPAG_MAX_LB) ||
8906ce1e5c0SGil Adam 			    (j == 0 && ent->integer.value < ACPI_PPAG_MIN_LB) ||
8916ce1e5c0SGil Adam 			    (j != 0 && ent->integer.value > ACPI_PPAG_MAX_HB) ||
8926ce1e5c0SGil Adam 			    (j != 0 && ent->integer.value < ACPI_PPAG_MIN_HB)) {
89339c1a972SIhab Zhaika 				mvm->fwrt.ppag_table.enabled = cpu_to_le32(0);
8946ce1e5c0SGil Adam 				ret = -EINVAL;
8956ce1e5c0SGil Adam 				goto out_free;
8966ce1e5c0SGil Adam 			}
89739c1a972SIhab Zhaika 			mvm->fwrt.ppag_table.gain[i][j] = ent->integer.value;
8986ce1e5c0SGil Adam 		}
8996ce1e5c0SGil Adam 	}
9006ce1e5c0SGil Adam 	ret = 0;
9016ce1e5c0SGil Adam out_free:
9026ce1e5c0SGil Adam 	kfree(data);
9036ce1e5c0SGil Adam 	return ret;
9046ce1e5c0SGil Adam }
9056ce1e5c0SGil Adam 
9066ce1e5c0SGil Adam int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
9076ce1e5c0SGil Adam {
9086ce1e5c0SGil Adam 	int i, j, ret;
9096ce1e5c0SGil Adam 
9106ce1e5c0SGil Adam 	if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) {
9116ce1e5c0SGil Adam 		IWL_DEBUG_RADIO(mvm,
9126ce1e5c0SGil Adam 				"PPAG capability not supported by FW, command not sent.\n");
9136ce1e5c0SGil Adam 		return 0;
9146ce1e5c0SGil Adam 	}
9156ce1e5c0SGil Adam 
916160bab43SGil Adam 	if (!mvm->fwrt.ppag_table.enabled) {
917160bab43SGil Adam 		IWL_DEBUG_RADIO(mvm,
918160bab43SGil Adam 				"PPAG not enabled, command not sent.\n");
919160bab43SGil Adam 		return 0;
920160bab43SGil Adam 	}
921160bab43SGil Adam 
9226ce1e5c0SGil Adam 	IWL_DEBUG_RADIO(mvm, "Sending PER_PLATFORM_ANT_GAIN_CMD\n");
9236ce1e5c0SGil Adam 
9246ce1e5c0SGil Adam 	for (i = 0; i < ACPI_PPAG_NUM_CHAINS; i++) {
9256ce1e5c0SGil Adam 		for (j = 0; j < ACPI_PPAG_NUM_SUB_BANDS; j++) {
9266ce1e5c0SGil Adam 			IWL_DEBUG_RADIO(mvm,
9276ce1e5c0SGil Adam 					"PPAG table: chain[%d] band[%d]: gain = %d\n",
92839c1a972SIhab Zhaika 					i, j, mvm->fwrt.ppag_table.gain[i][j]);
9296ce1e5c0SGil Adam 		}
9306ce1e5c0SGil Adam 	}
9316ce1e5c0SGil Adam 
9326ce1e5c0SGil Adam 	ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(PHY_OPS_GROUP,
9336ce1e5c0SGil Adam 						PER_PLATFORM_ANT_GAIN_CMD),
93439c1a972SIhab Zhaika 				   0, sizeof(mvm->fwrt.ppag_table),
93539c1a972SIhab Zhaika 				   &mvm->fwrt.ppag_table);
9366ce1e5c0SGil Adam 	if (ret < 0)
9376ce1e5c0SGil Adam 		IWL_ERR(mvm, "failed to send PER_PLATFORM_ANT_GAIN_CMD (%d)\n",
9386ce1e5c0SGil Adam 			ret);
9396ce1e5c0SGil Adam 
9406ce1e5c0SGil Adam 	return ret;
9416ce1e5c0SGil Adam }
9426ce1e5c0SGil Adam 
9436ce1e5c0SGil Adam static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
9446ce1e5c0SGil Adam {
9456ce1e5c0SGil Adam 	int ret;
9466ce1e5c0SGil Adam 
9476ce1e5c0SGil Adam 	ret = iwl_mvm_get_ppag_table(mvm);
9486ce1e5c0SGil Adam 	if (ret < 0) {
9496ce1e5c0SGil Adam 		IWL_DEBUG_RADIO(mvm,
9506ce1e5c0SGil Adam 				"PPAG BIOS table invalid or unavailable. (%d)\n",
9516ce1e5c0SGil Adam 				ret);
9526ce1e5c0SGil Adam 		return 0;
9536ce1e5c0SGil Adam 	}
9546ce1e5c0SGil Adam 	return iwl_mvm_ppag_send_cmd(mvm);
9556ce1e5c0SGil Adam }
9566ce1e5c0SGil Adam 
95728dd7ccdSMordechay Goodstein static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
95828dd7ccdSMordechay Goodstein {
95928dd7ccdSMordechay Goodstein 	int ret;
96028dd7ccdSMordechay Goodstein 	struct iwl_tas_config_cmd cmd = {};
96128dd7ccdSMordechay Goodstein 	int list_size;
96228dd7ccdSMordechay Goodstein 
96328dd7ccdSMordechay Goodstein 	BUILD_BUG_ON(ARRAY_SIZE(cmd.black_list_array) <
96428dd7ccdSMordechay Goodstein 		     APCI_WTAS_BLACK_LIST_MAX);
96528dd7ccdSMordechay Goodstein 
96628dd7ccdSMordechay Goodstein 	if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TAS_CFG)) {
96728dd7ccdSMordechay Goodstein 		IWL_DEBUG_RADIO(mvm, "TAS not enabled in FW\n");
96828dd7ccdSMordechay Goodstein 		return;
96928dd7ccdSMordechay Goodstein 	}
97028dd7ccdSMordechay Goodstein 
97128dd7ccdSMordechay Goodstein 	ret = iwl_acpi_get_tas(&mvm->fwrt, cmd.black_list_array, &list_size);
97228dd7ccdSMordechay Goodstein 	if (ret < 0) {
97328dd7ccdSMordechay Goodstein 		IWL_DEBUG_RADIO(mvm,
97428dd7ccdSMordechay Goodstein 				"TAS table invalid or unavailable. (%d)\n",
97528dd7ccdSMordechay Goodstein 				ret);
97628dd7ccdSMordechay Goodstein 		return;
97728dd7ccdSMordechay Goodstein 	}
97828dd7ccdSMordechay Goodstein 
97928dd7ccdSMordechay Goodstein 	if (list_size < 0)
98028dd7ccdSMordechay Goodstein 		return;
98128dd7ccdSMordechay Goodstein 
98228dd7ccdSMordechay Goodstein 	/* list size if TAS enabled can only be non-negative */
98328dd7ccdSMordechay Goodstein 	cmd.black_list_size = cpu_to_le32((u32)list_size);
98428dd7ccdSMordechay Goodstein 
98528dd7ccdSMordechay Goodstein 	ret = iwl_mvm_send_cmd_pdu(mvm, WIDE_ID(REGULATORY_AND_NVM_GROUP,
98628dd7ccdSMordechay Goodstein 						TAS_CONFIG),
98728dd7ccdSMordechay Goodstein 				   0, sizeof(cmd), &cmd);
98828dd7ccdSMordechay Goodstein 	if (ret < 0)
98928dd7ccdSMordechay Goodstein 		IWL_DEBUG_RADIO(mvm, "failed to send TAS_CONFIG (%d)\n", ret);
99028dd7ccdSMordechay Goodstein }
991f5b1cb2eSGil Adam 
99202d31e9bSGil Adam static u8 iwl_mvm_eval_dsm_indonesia_5g2(struct iwl_mvm *mvm)
993f5b1cb2eSGil Adam {
994f5b1cb2eSGil Adam 	int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0,
995f5b1cb2eSGil Adam 				      DSM_FUNC_ENABLE_INDONESIA_5G2);
996f5b1cb2eSGil Adam 
99702d31e9bSGil Adam 	if (ret < 0)
998f5b1cb2eSGil Adam 		IWL_DEBUG_RADIO(mvm,
99902d31e9bSGil Adam 				"Failed to evaluate DSM function ENABLE_INDONESIA_5G2, ret=%d\n",
1000f5b1cb2eSGil Adam 				ret);
1001f5b1cb2eSGil Adam 
100202d31e9bSGil Adam 	else if (ret >= DSM_VALUE_INDONESIA_MAX)
100302d31e9bSGil Adam 		IWL_DEBUG_RADIO(mvm,
100402d31e9bSGil Adam 				"DSM function ENABLE_INDONESIA_5G2 return invalid value, ret=%d\n",
100502d31e9bSGil Adam 				ret);
100602d31e9bSGil Adam 
100702d31e9bSGil Adam 	else if (ret == DSM_VALUE_INDONESIA_ENABLE) {
100802d31e9bSGil Adam 		IWL_DEBUG_RADIO(mvm,
100902d31e9bSGil Adam 				"Evaluated DSM function ENABLE_INDONESIA_5G2: Enabling 5g2\n");
101002d31e9bSGil Adam 		return DSM_VALUE_INDONESIA_ENABLE;
101102d31e9bSGil Adam 	}
101202d31e9bSGil Adam 	/* default behaviour is disabled */
101302d31e9bSGil Adam 	return DSM_VALUE_INDONESIA_DISABLE;
101402d31e9bSGil Adam }
101502d31e9bSGil Adam 
101602d31e9bSGil Adam static u8 iwl_mvm_eval_dsm_disable_srd(struct iwl_mvm *mvm)
101702d31e9bSGil Adam {
101802d31e9bSGil Adam 	int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0,
101902d31e9bSGil Adam 				      DSM_FUNC_DISABLE_SRD);
102002d31e9bSGil Adam 
102102d31e9bSGil Adam 	if (ret < 0)
102202d31e9bSGil Adam 		IWL_DEBUG_RADIO(mvm,
102302d31e9bSGil Adam 				"Failed to evaluate DSM function DISABLE_SRD, ret=%d\n",
102402d31e9bSGil Adam 				ret);
102502d31e9bSGil Adam 
102602d31e9bSGil Adam 	else if (ret >= DSM_VALUE_SRD_MAX)
102702d31e9bSGil Adam 		IWL_DEBUG_RADIO(mvm,
102802d31e9bSGil Adam 				"DSM function DISABLE_SRD return invalid value, ret=%d\n",
102902d31e9bSGil Adam 				ret);
103002d31e9bSGil Adam 
103102d31e9bSGil Adam 	else if (ret == DSM_VALUE_SRD_PASSIVE) {
103202d31e9bSGil Adam 		IWL_DEBUG_RADIO(mvm,
103302d31e9bSGil Adam 				"Evaluated DSM function DISABLE_SRD: setting SRD to passive\n");
103402d31e9bSGil Adam 		return DSM_VALUE_SRD_PASSIVE;
103502d31e9bSGil Adam 
103602d31e9bSGil Adam 	} else if (ret == DSM_VALUE_SRD_DISABLE) {
103702d31e9bSGil Adam 		IWL_DEBUG_RADIO(mvm,
103802d31e9bSGil Adam 				"Evaluated DSM function DISABLE_SRD: disabling SRD\n");
103902d31e9bSGil Adam 		return DSM_VALUE_SRD_DISABLE;
104002d31e9bSGil Adam 	}
104102d31e9bSGil Adam 	/* default behaviour is active */
104202d31e9bSGil Adam 	return DSM_VALUE_SRD_ACTIVE;
1043f5b1cb2eSGil Adam }
1044f5b1cb2eSGil Adam 
1045f5b1cb2eSGil Adam static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1046f5b1cb2eSGil Adam {
104702d31e9bSGil Adam 	u8 ret;
104802d31e9bSGil Adam 	int cmd_ret;
1049f5b1cb2eSGil Adam 	struct iwl_lari_config_change_cmd cmd = {};
1050f5b1cb2eSGil Adam 
105102d31e9bSGil Adam 	if (iwl_mvm_eval_dsm_indonesia_5g2(mvm) == DSM_VALUE_INDONESIA_ENABLE)
1052f5b1cb2eSGil Adam 		cmd.config_bitmap |=
1053f5b1cb2eSGil Adam 			cpu_to_le32(LARI_CONFIG_ENABLE_5G2_IN_INDONESIA_MSK);
1054f5b1cb2eSGil Adam 
105502d31e9bSGil Adam 	ret = iwl_mvm_eval_dsm_disable_srd(mvm);
105602d31e9bSGil Adam 	if (ret == DSM_VALUE_SRD_PASSIVE)
105702d31e9bSGil Adam 		cmd.config_bitmap |=
105802d31e9bSGil Adam 			cpu_to_le32(LARI_CONFIG_CHANGE_ETSI_TO_PASSIVE_MSK);
105902d31e9bSGil Adam 
106002d31e9bSGil Adam 	else if (ret == DSM_VALUE_SRD_DISABLE)
106102d31e9bSGil Adam 		cmd.config_bitmap |=
106202d31e9bSGil Adam 			cpu_to_le32(LARI_CONFIG_CHANGE_ETSI_TO_DISABLED_MSK);
106302d31e9bSGil Adam 
1064f5b1cb2eSGil Adam 	/* apply more config masks here */
1065f5b1cb2eSGil Adam 
1066f5b1cb2eSGil Adam 	if (cmd.config_bitmap) {
106702d31e9bSGil Adam 		IWL_DEBUG_RADIO(mvm, "sending LARI_CONFIG_CHANGE\n");
106802d31e9bSGil Adam 		cmd_ret = iwl_mvm_send_cmd_pdu(mvm,
1069f5b1cb2eSGil Adam 					       WIDE_ID(REGULATORY_AND_NVM_GROUP,
1070f5b1cb2eSGil Adam 						       LARI_CONFIG_CHANGE),
1071f5b1cb2eSGil Adam 					       0, sizeof(cmd), &cmd);
107202d31e9bSGil Adam 		if (cmd_ret < 0)
1073f5b1cb2eSGil Adam 			IWL_DEBUG_RADIO(mvm,
1074f5b1cb2eSGil Adam 					"Failed to send LARI_CONFIG_CHANGE (%d)\n",
107502d31e9bSGil Adam 					cmd_ret);
1076f5b1cb2eSGil Adam 	}
1077f5b1cb2eSGil Adam }
107869964905SLuca Coelho #else /* CONFIG_ACPI */
107939c1a972SIhab Zhaika 
108039c1a972SIhab Zhaika inline int iwl_mvm_sar_select_profile(struct iwl_mvm *mvm,
108139c1a972SIhab Zhaika 				      int prof_a, int prof_b)
108269964905SLuca Coelho {
108369964905SLuca Coelho 	return -ENOENT;
108469964905SLuca Coelho }
108569964905SLuca Coelho 
108639c1a972SIhab Zhaika inline int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm)
10875d041c46SLuca Coelho {
10885d041c46SLuca Coelho 	return -ENOENT;
10895d041c46SLuca Coelho }
10905d041c46SLuca Coelho 
1091a6bff3cbSHaim Dreyfuss static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm)
1092a6bff3cbSHaim Dreyfuss {
1093a6bff3cbSHaim Dreyfuss 	return 0;
1094a6bff3cbSHaim Dreyfuss }
109518f1755dSLuca Coelho 
10966ce1e5c0SGil Adam int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm)
10976ce1e5c0SGil Adam {
10986ce1e5c0SGil Adam 	return -ENOENT;
10996ce1e5c0SGil Adam }
11006ce1e5c0SGil Adam 
11016ce1e5c0SGil Adam static int iwl_mvm_ppag_init(struct iwl_mvm *mvm)
11026ce1e5c0SGil Adam {
11037937fd32SJohannes Berg 	return 0;
11046ce1e5c0SGil Adam }
110528dd7ccdSMordechay Goodstein 
110628dd7ccdSMordechay Goodstein static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
110728dd7ccdSMordechay Goodstein {
110828dd7ccdSMordechay Goodstein }
1109f5b1cb2eSGil Adam 
1110f5b1cb2eSGil Adam static void iwl_mvm_lari_cfg(struct iwl_mvm *mvm)
1111f5b1cb2eSGil Adam {
1112f5b1cb2eSGil Adam }
111369964905SLuca Coelho #endif /* CONFIG_ACPI */
111469964905SLuca Coelho 
1115f130bb75SMordechay Goodstein void iwl_mvm_send_recovery_cmd(struct iwl_mvm *mvm, u32 flags)
1116f130bb75SMordechay Goodstein {
1117f130bb75SMordechay Goodstein 	u32 error_log_size = mvm->fw->ucode_capa.error_log_size;
1118f130bb75SMordechay Goodstein 	int ret;
1119f130bb75SMordechay Goodstein 	u32 resp;
1120f130bb75SMordechay Goodstein 
1121f130bb75SMordechay Goodstein 	struct iwl_fw_error_recovery_cmd recovery_cmd = {
1122f130bb75SMordechay Goodstein 		.flags = cpu_to_le32(flags),
1123f130bb75SMordechay Goodstein 		.buf_size = 0,
1124f130bb75SMordechay Goodstein 	};
1125f130bb75SMordechay Goodstein 	struct iwl_host_cmd host_cmd = {
1126f130bb75SMordechay Goodstein 		.id = WIDE_ID(SYSTEM_GROUP, FW_ERROR_RECOVERY_CMD),
1127f130bb75SMordechay Goodstein 		.flags = CMD_WANT_SKB,
1128f130bb75SMordechay Goodstein 		.data = {&recovery_cmd, },
1129f130bb75SMordechay Goodstein 		.len = {sizeof(recovery_cmd), },
1130f130bb75SMordechay Goodstein 	};
1131f130bb75SMordechay Goodstein 
1132f130bb75SMordechay Goodstein 	/* no error log was defined in TLV */
1133f130bb75SMordechay Goodstein 	if (!error_log_size)
1134f130bb75SMordechay Goodstein 		return;
1135f130bb75SMordechay Goodstein 
1136f130bb75SMordechay Goodstein 	if (flags & ERROR_RECOVERY_UPDATE_DB) {
1137f130bb75SMordechay Goodstein 		/* no buf was allocated while HW reset */
1138f130bb75SMordechay Goodstein 		if (!mvm->error_recovery_buf)
1139f130bb75SMordechay Goodstein 			return;
1140f130bb75SMordechay Goodstein 
1141f130bb75SMordechay Goodstein 		host_cmd.data[1] = mvm->error_recovery_buf;
1142f130bb75SMordechay Goodstein 		host_cmd.len[1] =  error_log_size;
1143f130bb75SMordechay Goodstein 		host_cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
1144f130bb75SMordechay Goodstein 		recovery_cmd.buf_size = cpu_to_le32(error_log_size);
1145f130bb75SMordechay Goodstein 	}
1146f130bb75SMordechay Goodstein 
1147f130bb75SMordechay Goodstein 	ret = iwl_mvm_send_cmd(mvm, &host_cmd);
1148f130bb75SMordechay Goodstein 	kfree(mvm->error_recovery_buf);
1149f130bb75SMordechay Goodstein 	mvm->error_recovery_buf = NULL;
1150f130bb75SMordechay Goodstein 
1151f130bb75SMordechay Goodstein 	if (ret) {
1152f130bb75SMordechay Goodstein 		IWL_ERR(mvm, "Failed to send recovery cmd %d\n", ret);
1153f130bb75SMordechay Goodstein 		return;
1154f130bb75SMordechay Goodstein 	}
1155f130bb75SMordechay Goodstein 
1156f130bb75SMordechay Goodstein 	/* skb respond is only relevant in ERROR_RECOVERY_UPDATE_DB */
1157f130bb75SMordechay Goodstein 	if (flags & ERROR_RECOVERY_UPDATE_DB) {
1158f130bb75SMordechay Goodstein 		resp = le32_to_cpu(*(__le32 *)host_cmd.resp_pkt->data);
1159f130bb75SMordechay Goodstein 		if (resp)
1160f130bb75SMordechay Goodstein 			IWL_ERR(mvm,
1161f130bb75SMordechay Goodstein 				"Failed to send recovery cmd blob was invalid %d\n",
1162f130bb75SMordechay Goodstein 				resp);
1163f130bb75SMordechay Goodstein 	}
1164f130bb75SMordechay Goodstein }
1165f130bb75SMordechay Goodstein 
116642ce76d6SLuca Coelho static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
116742ce76d6SLuca Coelho {
116842ce76d6SLuca Coelho 	int ret;
116942ce76d6SLuca Coelho 
117039c1a972SIhab Zhaika 	ret = iwl_sar_get_wrds_table(&mvm->fwrt);
1171da2830acSLuca Coelho 	if (ret < 0) {
1172da2830acSLuca Coelho 		IWL_DEBUG_RADIO(mvm,
117369964905SLuca Coelho 				"WRDS SAR BIOS table invalid or unavailable. (%d)\n",
1174da2830acSLuca Coelho 				ret);
11755d041c46SLuca Coelho 		/*
11765d041c46SLuca Coelho 		 * If not available, don't fail and don't bother with EWRD.
11775d041c46SLuca Coelho 		 * Return 1 to tell that we can't use WGDS either.
11785d041c46SLuca Coelho 		 */
11795d041c46SLuca Coelho 		return 1;
1180da2830acSLuca Coelho 	}
1181da2830acSLuca Coelho 
118239c1a972SIhab Zhaika 	ret = iwl_sar_get_ewrd_table(&mvm->fwrt);
118369964905SLuca Coelho 	/* if EWRD is not available, we can still use WRDS, so don't fail */
118469964905SLuca Coelho 	if (ret < 0)
118569964905SLuca Coelho 		IWL_DEBUG_RADIO(mvm,
118669964905SLuca Coelho 				"EWRD SAR BIOS table invalid or unavailable. (%d)\n",
118769964905SLuca Coelho 				ret);
118869964905SLuca Coelho 
11891edd56e6SLuca Coelho 	return iwl_mvm_sar_select_profile(mvm, 1, 1);
1190da2830acSLuca Coelho }
1191da2830acSLuca Coelho 
11921f370650SSara Sharon static int iwl_mvm_load_rt_fw(struct iwl_mvm *mvm)
11931f370650SSara Sharon {
11941f370650SSara Sharon 	int ret;
11951f370650SSara Sharon 
11967d6222e2SJohannes Berg 	if (iwl_mvm_has_unified_ucode(mvm))
11971f370650SSara Sharon 		return iwl_run_unified_mvm_ucode(mvm, false);
11981f370650SSara Sharon 
11991f370650SSara Sharon 	ret = iwl_run_init_mvm_ucode(mvm, false);
12001f370650SSara Sharon 
12011f370650SSara Sharon 	if (ret) {
12021f370650SSara Sharon 		IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
1203f4744258SLiad Kaufman 
1204f4744258SLiad Kaufman 		if (iwlmvm_mod_params.init_dbg)
1205f4744258SLiad Kaufman 			return 0;
12061f370650SSara Sharon 		return ret;
12071f370650SSara Sharon 	}
12081f370650SSara Sharon 
1209203c83d3SShahar S Matityahu 	iwl_fw_dbg_stop_sync(&mvm->fwrt);
1210bab3cb92SEmmanuel Grumbach 	iwl_trans_stop_device(mvm->trans);
1211bab3cb92SEmmanuel Grumbach 	ret = iwl_trans_start_hw(mvm->trans);
12121f370650SSara Sharon 	if (ret)
12131f370650SSara Sharon 		return ret;
12141f370650SSara Sharon 
1215b108d8c7SShahar S Matityahu 	iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_EARLY, NULL);
1216da2eb669SSara Sharon 
121794022562SEmmanuel Grumbach 	mvm->rfkill_safe_init_done = false;
12181f370650SSara Sharon 	ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
12191f370650SSara Sharon 	if (ret)
12201f370650SSara Sharon 		return ret;
12211f370650SSara Sharon 
122294022562SEmmanuel Grumbach 	mvm->rfkill_safe_init_done = true;
122394022562SEmmanuel Grumbach 
1224b108d8c7SShahar S Matityahu 	iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
1225b108d8c7SShahar S Matityahu 			       NULL);
1226da2eb669SSara Sharon 
1227702e975dSJohannes Berg 	return iwl_init_paging(&mvm->fwrt, mvm->fwrt.cur_fw_img);
12281f370650SSara Sharon }
12291f370650SSara Sharon 
1230e705c121SKalle Valo int iwl_mvm_up(struct iwl_mvm *mvm)
1231e705c121SKalle Valo {
1232e705c121SKalle Valo 	int ret, i;
1233e705c121SKalle Valo 	struct ieee80211_channel *chan;
1234e705c121SKalle Valo 	struct cfg80211_chan_def chandef;
1235dd36a507STova Mussai 	struct ieee80211_supported_band *sband = NULL;
1236e705c121SKalle Valo 
1237e705c121SKalle Valo 	lockdep_assert_held(&mvm->mutex);
1238e705c121SKalle Valo 
1239e705c121SKalle Valo 	ret = iwl_trans_start_hw(mvm->trans);
1240e705c121SKalle Valo 	if (ret)
1241e705c121SKalle Valo 		return ret;
1242e705c121SKalle Valo 
12431f370650SSara Sharon 	ret = iwl_mvm_load_rt_fw(mvm);
1244e705c121SKalle Valo 	if (ret) {
1245e705c121SKalle Valo 		IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
124672d3c7bbSJohannes Berg 		if (ret != -ERFKILL)
124772d3c7bbSJohannes Berg 			iwl_fw_dbg_error_collect(&mvm->fwrt,
124872d3c7bbSJohannes Berg 						 FW_DBG_TRIGGER_DRIVER);
1249e705c121SKalle Valo 		goto error;
1250e705c121SKalle Valo 	}
1251e705c121SKalle Valo 
1252d0b813fcSJohannes Berg 	iwl_get_shared_mem_conf(&mvm->fwrt);
1253e705c121SKalle Valo 
1254e705c121SKalle Valo 	ret = iwl_mvm_sf_update(mvm, NULL, false);
1255e705c121SKalle Valo 	if (ret)
1256e705c121SKalle Valo 		IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
1257e705c121SKalle Valo 
1258a1af4c48SShahar S Matityahu 	if (!iwl_trans_dbg_ini_valid(mvm->trans)) {
12597174beb6SJohannes Berg 		mvm->fwrt.dump.conf = FW_DBG_INVALID;
1260e705c121SKalle Valo 		/* if we have a destination, assume EARLY START */
126117b809c9SSara Sharon 		if (mvm->fw->dbg.dest_tlv)
12627174beb6SJohannes Berg 			mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
12637174beb6SJohannes Berg 		iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
12647a14c23dSSara Sharon 	}
1265e705c121SKalle Valo 
1266e705c121SKalle Valo 	ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
1267e705c121SKalle Valo 	if (ret)
1268e705c121SKalle Valo 		goto error;
1269e705c121SKalle Valo 
12707d6222e2SJohannes Berg 	if (!iwl_mvm_has_unified_ucode(mvm)) {
1271e705c121SKalle Valo 		/* Send phy db control command and then phy db calibration */
1272e705c121SKalle Valo 		ret = iwl_send_phy_db_data(mvm->phy_db);
1273e705c121SKalle Valo 		if (ret)
1274e705c121SKalle Valo 			goto error;
1275bb99ff9bSLuca Coelho 	}
1276e705c121SKalle Valo 
1277e705c121SKalle Valo 	ret = iwl_send_phy_cfg_cmd(mvm);
1278e705c121SKalle Valo 	if (ret)
1279e705c121SKalle Valo 		goto error;
1280e705c121SKalle Valo 
1281b3de3ef4SEmmanuel Grumbach 	ret = iwl_mvm_send_bt_init_conf(mvm);
1282b3de3ef4SEmmanuel Grumbach 	if (ret)
1283b3de3ef4SEmmanuel Grumbach 		goto error;
1284b3de3ef4SEmmanuel Grumbach 
1285cceb4507SShahar S Matityahu 	if (fw_has_capa(&mvm->fw->ucode_capa,
1286cceb4507SShahar S Matityahu 			IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) {
1287a8eb340fSEmmanuel Grumbach 		ret = iwl_set_soc_latency(&mvm->fwrt);
1288cceb4507SShahar S Matityahu 		if (ret)
1289cceb4507SShahar S Matityahu 			goto error;
1290cceb4507SShahar S Matityahu 	}
1291cceb4507SShahar S Matityahu 
129243413a97SSara Sharon 	/* Init RSS configuration */
1293286ca8ebSLuca Coelho 	if (mvm->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) {
12948edbfaa1SSara Sharon 		ret = iwl_configure_rxq(mvm);
12958edbfaa1SSara Sharon 		if (ret) {
12968edbfaa1SSara Sharon 			IWL_ERR(mvm, "Failed to configure RX queues: %d\n",
12978edbfaa1SSara Sharon 				ret);
12988edbfaa1SSara Sharon 			goto error;
12998edbfaa1SSara Sharon 		}
13008edbfaa1SSara Sharon 	}
13018edbfaa1SSara Sharon 
13028edbfaa1SSara Sharon 	if (iwl_mvm_has_new_rx_api(mvm)) {
130343413a97SSara Sharon 		ret = iwl_send_rss_cfg_cmd(mvm);
130443413a97SSara Sharon 		if (ret) {
130543413a97SSara Sharon 			IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
130643413a97SSara Sharon 				ret);
130743413a97SSara Sharon 			goto error;
130843413a97SSara Sharon 		}
130943413a97SSara Sharon 	}
131043413a97SSara Sharon 
1311e705c121SKalle Valo 	/* init the fw <-> mac80211 STA mapping */
13120ae98812SSara Sharon 	for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++)
1313e705c121SKalle Valo 		RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1314e705c121SKalle Valo 
13150ae98812SSara Sharon 	mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA;
1316e705c121SKalle Valo 
1317e705c121SKalle Valo 	/* reset quota debouncing buffer - 0xff will yield invalid data */
1318e705c121SKalle Valo 	memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
1319e705c121SKalle Valo 
132079660869SIlia Lin 	if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_DQA_SUPPORT)) {
132197d5be7eSLiad Kaufman 		ret = iwl_mvm_send_dqa_cmd(mvm);
132297d5be7eSLiad Kaufman 		if (ret)
132397d5be7eSLiad Kaufman 			goto error;
132479660869SIlia Lin 	}
132597d5be7eSLiad Kaufman 
1326e705c121SKalle Valo 	/* Add auxiliary station for scanning */
1327e705c121SKalle Valo 	ret = iwl_mvm_add_aux_sta(mvm);
1328e705c121SKalle Valo 	if (ret)
1329e705c121SKalle Valo 		goto error;
1330e705c121SKalle Valo 
1331e705c121SKalle Valo 	/* Add all the PHY contexts */
1332dd36a507STova Mussai 	i = 0;
1333dd36a507STova Mussai 	while (!sband && i < NUM_NL80211_BANDS)
1334dd36a507STova Mussai 		sband = mvm->hw->wiphy->bands[i++];
1335dd36a507STova Mussai 
1336dd36a507STova Mussai 	if (WARN_ON_ONCE(!sband))
1337dd36a507STova Mussai 		goto error;
1338dd36a507STova Mussai 
1339dd36a507STova Mussai 	chan = &sband->channels[0];
1340dd36a507STova Mussai 
1341e705c121SKalle Valo 	cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
1342e705c121SKalle Valo 	for (i = 0; i < NUM_PHY_CTX; i++) {
1343e705c121SKalle Valo 		/*
1344e705c121SKalle Valo 		 * The channel used here isn't relevant as it's
1345e705c121SKalle Valo 		 * going to be overwritten in the other flows.
1346e705c121SKalle Valo 		 * For now use the first channel we have.
1347e705c121SKalle Valo 		 */
1348e705c121SKalle Valo 		ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
1349e705c121SKalle Valo 					   &chandef, 1, 1);
1350e705c121SKalle Valo 		if (ret)
1351e705c121SKalle Valo 			goto error;
1352e705c121SKalle Valo 	}
1353e705c121SKalle Valo 
1354c221daf2SChaya Rachel Ivgi 	if (iwl_mvm_is_tt_in_fw(mvm)) {
1355c221daf2SChaya Rachel Ivgi 		/* in order to give the responsibility of ct-kill and
1356c221daf2SChaya Rachel Ivgi 		 * TX backoff to FW we need to send empty temperature reporting
1357c221daf2SChaya Rachel Ivgi 		 * cmd during init time
1358c221daf2SChaya Rachel Ivgi 		 */
1359c221daf2SChaya Rachel Ivgi 		iwl_mvm_send_temp_report_ths_cmd(mvm);
1360c221daf2SChaya Rachel Ivgi 	} else {
1361e705c121SKalle Valo 		/* Initialize tx backoffs to the minimal possible */
1362e705c121SKalle Valo 		iwl_mvm_tt_tx_backoff(mvm, 0);
1363c221daf2SChaya Rachel Ivgi 	}
13645c89e7bcSChaya Rachel Ivgi 
1365242d9c8bSJohannes Berg #ifdef CONFIG_THERMAL
13665c89e7bcSChaya Rachel Ivgi 	/* TODO: read the budget from BIOS / Platform NVM */
1367944eafc2SChaya Rachel Ivgi 
1368944eafc2SChaya Rachel Ivgi 	/*
1369944eafc2SChaya Rachel Ivgi 	 * In case there is no budget from BIOS / Platform NVM the default
1370944eafc2SChaya Rachel Ivgi 	 * budget should be 2000mW (cooling state 0).
1371944eafc2SChaya Rachel Ivgi 	 */
1372944eafc2SChaya Rachel Ivgi 	if (iwl_mvm_is_ctdp_supported(mvm)) {
13735c89e7bcSChaya Rachel Ivgi 		ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
13745c89e7bcSChaya Rachel Ivgi 					   mvm->cooling_dev.cur_state);
137575cfe338SLuca Coelho 		if (ret)
137675cfe338SLuca Coelho 			goto error;
137775cfe338SLuca Coelho 	}
1378c221daf2SChaya Rachel Ivgi #endif
1379e705c121SKalle Valo 
1380aa43ae12SAlex Malamud 	if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_LTR_GEN2))
1381e705c121SKalle Valo 		WARN_ON(iwl_mvm_config_ltr(mvm));
1382e705c121SKalle Valo 
1383e705c121SKalle Valo 	ret = iwl_mvm_power_update_device(mvm);
1384e705c121SKalle Valo 	if (ret)
1385e705c121SKalle Valo 		goto error;
1386e705c121SKalle Valo 
1387f5b1cb2eSGil Adam 	iwl_mvm_lari_cfg(mvm);
1388e705c121SKalle Valo 	/*
1389e705c121SKalle Valo 	 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1390e705c121SKalle Valo 	 * anyway, so don't init MCC.
1391e705c121SKalle Valo 	 */
1392e705c121SKalle Valo 	if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1393e705c121SKalle Valo 		ret = iwl_mvm_init_mcc(mvm);
1394e705c121SKalle Valo 		if (ret)
1395e705c121SKalle Valo 			goto error;
1396e705c121SKalle Valo 	}
1397e705c121SKalle Valo 
1398e705c121SKalle Valo 	if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
13994ca87a5fSEmmanuel Grumbach 		mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
1400b66b5817SSara Sharon 		mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET;
1401e705c121SKalle Valo 		ret = iwl_mvm_config_scan(mvm);
1402e705c121SKalle Valo 		if (ret)
1403e705c121SKalle Valo 			goto error;
1404e705c121SKalle Valo 	}
1405e705c121SKalle Valo 
1406f130bb75SMordechay Goodstein 	if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
1407f130bb75SMordechay Goodstein 		iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB);
1408f130bb75SMordechay Goodstein 
140948e775e6SHaim Dreyfuss 	if (iwl_acpi_get_eckv(mvm->dev, &mvm->ext_clock_valid))
141048e775e6SHaim Dreyfuss 		IWL_DEBUG_INFO(mvm, "ECKV table doesn't exist in BIOS\n");
141148e775e6SHaim Dreyfuss 
14126ce1e5c0SGil Adam 	ret = iwl_mvm_ppag_init(mvm);
14136ce1e5c0SGil Adam 	if (ret)
14146ce1e5c0SGil Adam 		goto error;
14156ce1e5c0SGil Adam 
1416da2830acSLuca Coelho 	ret = iwl_mvm_sar_init(mvm);
14175d041c46SLuca Coelho 	if (ret == 0) {
1418a6bff3cbSHaim Dreyfuss 		ret = iwl_mvm_sar_geo_init(mvm);
14191edd56e6SLuca Coelho 	} else if (ret == -ENOENT && !iwl_sar_get_wgds_table(&mvm->fwrt)) {
14205d041c46SLuca Coelho 		/*
14215d041c46SLuca Coelho 		 * If basic SAR is not available, we check for WGDS,
14225d041c46SLuca Coelho 		 * which should *not* be available either.  If it is
14235d041c46SLuca Coelho 		 * available, issue an error, because we can't use SAR
14245d041c46SLuca Coelho 		 * Geo without basic SAR.
14255d041c46SLuca Coelho 		 */
14265d041c46SLuca Coelho 		IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n");
14275d041c46SLuca Coelho 	}
14285d041c46SLuca Coelho 
14295d041c46SLuca Coelho 	if (ret < 0)
1430a6bff3cbSHaim Dreyfuss 		goto error;
1431a6bff3cbSHaim Dreyfuss 
143228dd7ccdSMordechay Goodstein 	iwl_mvm_tas_init(mvm);
14337089ae63SJohannes Berg 	iwl_mvm_leds_sync(mvm);
14347089ae63SJohannes Berg 
1435e705c121SKalle Valo 	IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
1436e705c121SKalle Valo 	return 0;
1437e705c121SKalle Valo  error:
1438f4744258SLiad Kaufman 	if (!iwlmvm_mod_params.init_dbg || !ret)
1439fcb6b92aSChaya Rachel Ivgi 		iwl_mvm_stop_device(mvm);
1440e705c121SKalle Valo 	return ret;
1441e705c121SKalle Valo }
1442e705c121SKalle Valo 
1443e705c121SKalle Valo int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1444e705c121SKalle Valo {
1445e705c121SKalle Valo 	int ret, i;
1446e705c121SKalle Valo 
1447e705c121SKalle Valo 	lockdep_assert_held(&mvm->mutex);
1448e705c121SKalle Valo 
1449e705c121SKalle Valo 	ret = iwl_trans_start_hw(mvm->trans);
1450e705c121SKalle Valo 	if (ret)
1451e705c121SKalle Valo 		return ret;
1452e705c121SKalle Valo 
1453e705c121SKalle Valo 	ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1454e705c121SKalle Valo 	if (ret) {
1455e705c121SKalle Valo 		IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1456e705c121SKalle Valo 		goto error;
1457e705c121SKalle Valo 	}
1458e705c121SKalle Valo 
1459e705c121SKalle Valo 	ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
1460e705c121SKalle Valo 	if (ret)
1461e705c121SKalle Valo 		goto error;
1462e705c121SKalle Valo 
1463e705c121SKalle Valo 	/* Send phy db control command and then phy db calibration*/
1464e705c121SKalle Valo 	ret = iwl_send_phy_db_data(mvm->phy_db);
1465e705c121SKalle Valo 	if (ret)
1466e705c121SKalle Valo 		goto error;
1467e705c121SKalle Valo 
1468e705c121SKalle Valo 	ret = iwl_send_phy_cfg_cmd(mvm);
1469e705c121SKalle Valo 	if (ret)
1470e705c121SKalle Valo 		goto error;
1471e705c121SKalle Valo 
1472e705c121SKalle Valo 	/* init the fw <-> mac80211 STA mapping */
14730ae98812SSara Sharon 	for (i = 0; i < ARRAY_SIZE(mvm->fw_id_to_mac_id); i++)
1474e705c121SKalle Valo 		RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1475e705c121SKalle Valo 
1476e705c121SKalle Valo 	/* Add auxiliary station for scanning */
1477e705c121SKalle Valo 	ret = iwl_mvm_add_aux_sta(mvm);
1478e705c121SKalle Valo 	if (ret)
1479e705c121SKalle Valo 		goto error;
1480e705c121SKalle Valo 
1481e705c121SKalle Valo 	return 0;
1482e705c121SKalle Valo  error:
1483fcb6b92aSChaya Rachel Ivgi 	iwl_mvm_stop_device(mvm);
1484e705c121SKalle Valo 	return ret;
1485e705c121SKalle Valo }
1486e705c121SKalle Valo 
1487e705c121SKalle Valo void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm,
1488e705c121SKalle Valo 				 struct iwl_rx_cmd_buffer *rxb)
1489e705c121SKalle Valo {
1490e705c121SKalle Valo 	struct iwl_rx_packet *pkt = rxb_addr(rxb);
1491e705c121SKalle Valo 	struct iwl_card_state_notif *card_state_notif = (void *)pkt->data;
1492e705c121SKalle Valo 	u32 flags = le32_to_cpu(card_state_notif->flags);
1493e705c121SKalle Valo 
1494e705c121SKalle Valo 	IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n",
1495e705c121SKalle Valo 			  (flags & HW_CARD_DISABLED) ? "Kill" : "On",
1496e705c121SKalle Valo 			  (flags & SW_CARD_DISABLED) ? "Kill" : "On",
1497e705c121SKalle Valo 			  (flags & CT_KILL_CARD_DISABLED) ?
1498e705c121SKalle Valo 			  "Reached" : "Not reached");
1499e705c121SKalle Valo }
1500e705c121SKalle Valo 
1501e705c121SKalle Valo void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1502e705c121SKalle Valo 			     struct iwl_rx_cmd_buffer *rxb)
1503e705c121SKalle Valo {
1504e705c121SKalle Valo 	struct iwl_rx_packet *pkt = rxb_addr(rxb);
1505e705c121SKalle Valo 	struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1506e705c121SKalle Valo 
1507e705c121SKalle Valo 	IWL_DEBUG_INFO(mvm,
1508e705c121SKalle Valo 		       "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1509e705c121SKalle Valo 		       le32_to_cpu(mfuart_notif->installed_ver),
1510e705c121SKalle Valo 		       le32_to_cpu(mfuart_notif->external_ver),
1511e705c121SKalle Valo 		       le32_to_cpu(mfuart_notif->status),
1512e705c121SKalle Valo 		       le32_to_cpu(mfuart_notif->duration));
15130c8d0a47SGolan Ben-Ami 
15140c8d0a47SGolan Ben-Ami 	if (iwl_rx_packet_payload_len(pkt) == sizeof(*mfuart_notif))
15150c8d0a47SGolan Ben-Ami 		IWL_DEBUG_INFO(mvm,
15160c8d0a47SGolan Ben-Ami 			       "MFUART: image size: 0x%08x\n",
15170c8d0a47SGolan Ben-Ami 			       le32_to_cpu(mfuart_notif->image_size));
1518e705c121SKalle Valo }
1519