1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #ifndef __iwl_trans_h__ 65 #define __iwl_trans_h__ 66 67 #include <linux/ieee80211.h> 68 #include <linux/mm.h> /* for page_address */ 69 #include <linux/lockdep.h> 70 #include <linux/kernel.h> 71 72 #include "iwl-debug.h" 73 #include "iwl-config.h" 74 #include "fw/img.h" 75 #include "iwl-op-mode.h" 76 #include "fw/api/cmdhdr.h" 77 #include "fw/api/txq.h" 78 #include "fw/api/dbg-tlv.h" 79 #include "iwl-dbg-tlv.h" 80 81 /** 82 * DOC: Transport layer - what is it ? 83 * 84 * The transport layer is the layer that deals with the HW directly. It provides 85 * an abstraction of the underlying HW to the upper layer. The transport layer 86 * doesn't provide any policy, algorithm or anything of this kind, but only 87 * mechanisms to make the HW do something. It is not completely stateless but 88 * close to it. 89 * We will have an implementation for each different supported bus. 90 */ 91 92 /** 93 * DOC: Life cycle of the transport layer 94 * 95 * The transport layer has a very precise life cycle. 96 * 97 * 1) A helper function is called during the module initialization and 98 * registers the bus driver's ops with the transport's alloc function. 99 * 2) Bus's probe calls to the transport layer's allocation functions. 100 * Of course this function is bus specific. 101 * 3) This allocation functions will spawn the upper layer which will 102 * register mac80211. 103 * 104 * 4) At some point (i.e. mac80211's start call), the op_mode will call 105 * the following sequence: 106 * start_hw 107 * start_fw 108 * 109 * 5) Then when finished (or reset): 110 * stop_device 111 * 112 * 6) Eventually, the free function will be called. 113 */ 114 115 #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 116 117 #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 118 #define FH_RSCSR_FRAME_INVALID 0x55550000 119 #define FH_RSCSR_FRAME_ALIGN 0x40 120 #define FH_RSCSR_RPA_EN BIT(25) 121 #define FH_RSCSR_RADA_EN BIT(26) 122 #define FH_RSCSR_RXQ_POS 16 123 #define FH_RSCSR_RXQ_MASK 0x3F0000 124 125 struct iwl_rx_packet { 126 /* 127 * The first 4 bytes of the RX frame header contain both the RX frame 128 * size and some flags. 129 * Bit fields: 130 * 31: flag flush RB request 131 * 30: flag ignore TC (terminal counter) request 132 * 29: flag fast IRQ request 133 * 28-27: Reserved 134 * 26: RADA enabled 135 * 25: Offload enabled 136 * 24: RPF enabled 137 * 23: RSS enabled 138 * 22: Checksum enabled 139 * 21-16: RX queue 140 * 15-14: Reserved 141 * 13-00: RX frame size 142 */ 143 __le32 len_n_flags; 144 struct iwl_cmd_header hdr; 145 u8 data[]; 146 } __packed; 147 148 static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 149 { 150 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 151 } 152 153 static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 154 { 155 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 156 } 157 158 /** 159 * enum CMD_MODE - how to send the host commands ? 160 * 161 * @CMD_ASYNC: Return right away and don't wait for the response 162 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 163 * the response. The caller needs to call iwl_free_resp when done. 164 * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be 165 * called after this command completes. Valid only with CMD_ASYNC. 166 */ 167 enum CMD_MODE { 168 CMD_ASYNC = BIT(0), 169 CMD_WANT_SKB = BIT(1), 170 CMD_SEND_IN_RFKILL = BIT(2), 171 CMD_WANT_ASYNC_CALLBACK = BIT(3), 172 }; 173 174 #define DEF_CMD_PAYLOAD_SIZE 320 175 176 /** 177 * struct iwl_device_cmd 178 * 179 * For allocation of the command and tx queues, this establishes the overall 180 * size of the largest command we send to uCode, except for commands that 181 * aren't fully copied and use other TFD space. 182 */ 183 struct iwl_device_cmd { 184 union { 185 struct { 186 struct iwl_cmd_header hdr; /* uCode API */ 187 u8 payload[DEF_CMD_PAYLOAD_SIZE]; 188 }; 189 struct { 190 struct iwl_cmd_header_wide hdr_wide; 191 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 192 sizeof(struct iwl_cmd_header_wide) + 193 sizeof(struct iwl_cmd_header)]; 194 }; 195 }; 196 } __packed; 197 198 /** 199 * struct iwl_device_tx_cmd - buffer for TX command 200 * @hdr: the header 201 * @payload: the payload placeholder 202 * 203 * The actual structure is sized dynamically according to need. 204 */ 205 struct iwl_device_tx_cmd { 206 struct iwl_cmd_header hdr; 207 u8 payload[]; 208 } __packed; 209 210 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 211 212 /* 213 * number of transfer buffers (fragments) per transmit frame descriptor; 214 * this is just the driver's idea, the hardware supports 20 215 */ 216 #define IWL_MAX_CMD_TBS_PER_TFD 2 217 218 /* We need 2 entries for the TX command and header, and another one might 219 * be needed for potential data in the SKB's head. The remaining ones can 220 * be used for frags. 221 */ 222 #define IWL_TRANS_MAX_FRAGS(trans) ((trans)->txqs.tfd.max_tbs - 3) 223 224 /** 225 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 226 * 227 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 228 * ring. The transport layer doesn't map the command's buffer to DMA, but 229 * rather copies it to a previously allocated DMA buffer. This flag tells 230 * the transport layer not to copy the command, but to map the existing 231 * buffer (that is passed in) instead. This saves the memcpy and allows 232 * commands that are bigger than the fixed buffer to be submitted. 233 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 234 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 235 * chunk internally and free it again after the command completes. This 236 * can (currently) be used only once per command. 237 * Note that a TFD entry after a DUP one cannot be a normal copied one. 238 */ 239 enum iwl_hcmd_dataflag { 240 IWL_HCMD_DFL_NOCOPY = BIT(0), 241 IWL_HCMD_DFL_DUP = BIT(1), 242 }; 243 244 enum iwl_error_event_table_status { 245 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 246 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 247 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 248 }; 249 250 /** 251 * struct iwl_host_cmd - Host command to the uCode 252 * 253 * @data: array of chunks that composes the data of the host command 254 * @resp_pkt: response packet, if %CMD_WANT_SKB was set 255 * @_rx_page_order: (internally used to free response packet) 256 * @_rx_page_addr: (internally used to free response packet) 257 * @flags: can be CMD_* 258 * @len: array of the lengths of the chunks in data 259 * @dataflags: IWL_HCMD_DFL_* 260 * @id: command id of the host command, for wide commands encoding the 261 * version and group as well 262 */ 263 struct iwl_host_cmd { 264 const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 265 struct iwl_rx_packet *resp_pkt; 266 unsigned long _rx_page_addr; 267 u32 _rx_page_order; 268 269 u32 flags; 270 u32 id; 271 u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 272 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 273 }; 274 275 static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 276 { 277 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 278 } 279 280 struct iwl_rx_cmd_buffer { 281 struct page *_page; 282 int _offset; 283 bool _page_stolen; 284 u32 _rx_page_order; 285 unsigned int truesize; 286 }; 287 288 static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 289 { 290 return (void *)((unsigned long)page_address(r->_page) + r->_offset); 291 } 292 293 static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 294 { 295 return r->_offset; 296 } 297 298 static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 299 { 300 r->_page_stolen = true; 301 get_page(r->_page); 302 return r->_page; 303 } 304 305 static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 306 { 307 __free_pages(r->_page, r->_rx_page_order); 308 } 309 310 #define MAX_NO_RECLAIM_CMDS 6 311 312 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 313 314 /* 315 * Maximum number of HW queues the transport layer 316 * currently supports 317 */ 318 #define IWL_MAX_HW_QUEUES 32 319 #define IWL_MAX_TVQM_QUEUES 512 320 321 #define IWL_MAX_TID_COUNT 8 322 #define IWL_MGMT_TID 15 323 #define IWL_FRAME_LIMIT 64 324 #define IWL_MAX_RX_HW_QUEUES 16 325 #define IWL_9000_MAX_RX_HW_QUEUES 6 326 327 /** 328 * enum iwl_wowlan_status - WoWLAN image/device status 329 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 330 * @IWL_D3_STATUS_RESET: device was reset while suspended 331 */ 332 enum iwl_d3_status { 333 IWL_D3_STATUS_ALIVE, 334 IWL_D3_STATUS_RESET, 335 }; 336 337 /** 338 * enum iwl_trans_status: transport status flags 339 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 340 * @STATUS_DEVICE_ENABLED: APM is enabled 341 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 342 * @STATUS_INT_ENABLED: interrupts are enabled 343 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 344 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 345 * @STATUS_FW_ERROR: the fw is in error state 346 * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands 347 * are sent 348 * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent 349 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 350 */ 351 enum iwl_trans_status { 352 STATUS_SYNC_HCMD_ACTIVE, 353 STATUS_DEVICE_ENABLED, 354 STATUS_TPOWER_PMI, 355 STATUS_INT_ENABLED, 356 STATUS_RFKILL_HW, 357 STATUS_RFKILL_OPMODE, 358 STATUS_FW_ERROR, 359 STATUS_TRANS_GOING_IDLE, 360 STATUS_TRANS_IDLE, 361 STATUS_TRANS_DEAD, 362 }; 363 364 static inline int 365 iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 366 { 367 switch (rb_size) { 368 case IWL_AMSDU_2K: 369 return get_order(2 * 1024); 370 case IWL_AMSDU_4K: 371 return get_order(4 * 1024); 372 case IWL_AMSDU_8K: 373 return get_order(8 * 1024); 374 case IWL_AMSDU_12K: 375 return get_order(12 * 1024); 376 default: 377 WARN_ON(1); 378 return -1; 379 } 380 } 381 382 static inline int 383 iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 384 { 385 switch (rb_size) { 386 case IWL_AMSDU_2K: 387 return 2 * 1024; 388 case IWL_AMSDU_4K: 389 return 4 * 1024; 390 case IWL_AMSDU_8K: 391 return 8 * 1024; 392 case IWL_AMSDU_12K: 393 return 12 * 1024; 394 default: 395 WARN_ON(1); 396 return 0; 397 } 398 } 399 400 struct iwl_hcmd_names { 401 u8 cmd_id; 402 const char *const cmd_name; 403 }; 404 405 #define HCMD_NAME(x) \ 406 { .cmd_id = x, .cmd_name = #x } 407 408 struct iwl_hcmd_arr { 409 const struct iwl_hcmd_names *arr; 410 int size; 411 }; 412 413 #define HCMD_ARR(x) \ 414 { .arr = x, .size = ARRAY_SIZE(x) } 415 416 /** 417 * struct iwl_trans_config - transport configuration 418 * 419 * @op_mode: pointer to the upper layer. 420 * @cmd_queue: the index of the command queue. 421 * Must be set before start_fw. 422 * @cmd_fifo: the fifo for host commands 423 * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 424 * @no_reclaim_cmds: Some devices erroneously don't set the 425 * SEQ_RX_FRAME bit on some notifications, this is the 426 * list of such notifications to filter. Max length is 427 * %MAX_NO_RECLAIM_CMDS. 428 * @n_no_reclaim_cmds: # of commands in list 429 * @rx_buf_size: RX buffer size needed for A-MSDUs 430 * if unset 4k will be the RX buffer size 431 * @bc_table_dword: set to true if the BC table expects the byte count to be 432 * in DWORD (as opposed to bytes) 433 * @scd_set_active: should the transport configure the SCD for HCMD queue 434 * @sw_csum_tx: transport should compute the TCP checksum 435 * @command_groups: array of command groups, each member is an array of the 436 * commands in the group; for debugging only 437 * @command_groups_size: number of command groups, to avoid illegal access 438 * @cb_data_offs: offset inside skb->cb to store transport data at, must have 439 * space for at least two pointers 440 */ 441 struct iwl_trans_config { 442 struct iwl_op_mode *op_mode; 443 444 u8 cmd_queue; 445 u8 cmd_fifo; 446 unsigned int cmd_q_wdg_timeout; 447 const u8 *no_reclaim_cmds; 448 unsigned int n_no_reclaim_cmds; 449 450 enum iwl_amsdu_size rx_buf_size; 451 bool bc_table_dword; 452 bool scd_set_active; 453 bool sw_csum_tx; 454 const struct iwl_hcmd_arr *command_groups; 455 int command_groups_size; 456 457 u8 cb_data_offs; 458 }; 459 460 struct iwl_trans_dump_data { 461 u32 len; 462 u8 data[]; 463 }; 464 465 struct iwl_trans; 466 467 struct iwl_trans_txq_scd_cfg { 468 u8 fifo; 469 u8 sta_id; 470 u8 tid; 471 bool aggregate; 472 int frame_limit; 473 }; 474 475 /** 476 * struct iwl_trans_rxq_dma_data - RX queue DMA data 477 * @fr_bd_cb: DMA address of free BD cyclic buffer 478 * @fr_bd_wid: Initial write index of the free BD cyclic buffer 479 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 480 * @ur_bd_cb: DMA address of used BD cyclic buffer 481 */ 482 struct iwl_trans_rxq_dma_data { 483 u64 fr_bd_cb; 484 u32 fr_bd_wid; 485 u64 urbd_stts_wrptr; 486 u64 ur_bd_cb; 487 }; 488 489 /** 490 * struct iwl_trans_ops - transport specific operations 491 * 492 * All the handlers MUST be implemented 493 * 494 * @start_hw: starts the HW. From that point on, the HW can send interrupts. 495 * May sleep. 496 * @op_mode_leave: Turn off the HW RF kill indication if on 497 * May sleep 498 * @start_fw: allocates and inits all the resources for the transport 499 * layer. Also kick a fw image. 500 * May sleep 501 * @fw_alive: called when the fw sends alive notification. If the fw provides 502 * the SCD base address in SRAM, then provide it here, or 0 otherwise. 503 * May sleep 504 * @stop_device: stops the whole device (embedded CPU put to reset) and stops 505 * the HW. From that point on, the HW will be stopped but will still issue 506 * an interrupt if the HW RF kill switch is triggered. 507 * This callback must do the right thing and not crash even if %start_hw() 508 * was called but not &start_fw(). May sleep. 509 * @d3_suspend: put the device into the correct mode for WoWLAN during 510 * suspend. This is optional, if not implemented WoWLAN will not be 511 * supported. This callback may sleep. 512 * @d3_resume: resume the device after WoWLAN, enabling the opmode to 513 * talk to the WoWLAN image to get its status. This is optional, if not 514 * implemented WoWLAN will not be supported. This callback may sleep. 515 * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. 516 * If RFkill is asserted in the middle of a SYNC host command, it must 517 * return -ERFKILL straight away. 518 * May sleep only if CMD_ASYNC is not set 519 * @tx: send an skb. The transport relies on the op_mode to zero the 520 * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all 521 * the CSUM will be taken care of (TCP CSUM and IP header in case of 522 * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP 523 * header if it is IPv4. 524 * Must be atomic 525 * @reclaim: free packet until ssn. Returns a list of freed packets. 526 * Must be atomic 527 * @txq_enable: setup a queue. To setup an AC queue, use the 528 * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before 529 * this one. The op_mode must not configure the HCMD queue. The scheduler 530 * configuration may be %NULL, in which case the hardware will not be 531 * configured. If true is returned, the operation mode needs to increment 532 * the sequence number of the packets routed to this queue because of a 533 * hardware scheduler bug. May sleep. 534 * @txq_disable: de-configure a Tx queue to send AMPDUs 535 * Must be atomic 536 * @txq_set_shared_mode: change Tx queue shared/unshared marking 537 * @wait_tx_queues_empty: wait until tx queues are empty. May sleep. 538 * @wait_txq_empty: wait until specific tx queue is empty. May sleep. 539 * @freeze_txq_timer: prevents the timer of the queue from firing until the 540 * queue is set to awake. Must be atomic. 541 * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note 542 * that the transport needs to refcount the calls since this function 543 * will be called several times with block = true, and then the queues 544 * need to be unblocked only after the same number of calls with 545 * block = false. 546 * @write8: write a u8 to a register at offset ofs from the BAR 547 * @write32: write a u32 to a register at offset ofs from the BAR 548 * @read32: read a u32 register at offset ofs from the BAR 549 * @read_prph: read a DWORD from a periphery register 550 * @write_prph: write a DWORD to a periphery register 551 * @read_mem: read device's SRAM in DWORD 552 * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory 553 * will be zeroed. 554 * @read_config32: read a u32 value from the device's config space at 555 * the given offset. 556 * @configure: configure parameters required by the transport layer from 557 * the op_mode. May be called several times before start_fw, can't be 558 * called after that. 559 * @set_pmi: set the power pmi state 560 * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. 561 * Sleeping is not allowed between grab_nic_access and 562 * release_nic_access. 563 * @release_nic_access: let the NIC go to sleep. The "flags" parameter 564 * must be the same one that was sent before to the grab_nic_access. 565 * @set_bits_mask - set SRAM register according to value and mask. 566 * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last 567 * TX'ed commands and similar. The buffer will be vfree'd by the caller. 568 * Note that the transport must fill in the proper file headers. 569 * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup 570 * of the trans debugfs 571 */ 572 struct iwl_trans_ops { 573 574 int (*start_hw)(struct iwl_trans *iwl_trans); 575 void (*op_mode_leave)(struct iwl_trans *iwl_trans); 576 int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, 577 bool run_in_rfkill); 578 void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); 579 void (*stop_device)(struct iwl_trans *trans); 580 581 int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset); 582 int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, 583 bool test, bool reset); 584 585 int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 586 587 int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, 588 struct iwl_device_tx_cmd *dev_cmd, int queue); 589 void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, 590 struct sk_buff_head *skbs); 591 592 void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr); 593 594 bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, 595 const struct iwl_trans_txq_scd_cfg *cfg, 596 unsigned int queue_wdg_timeout); 597 void (*txq_disable)(struct iwl_trans *trans, int queue, 598 bool configure_scd); 599 /* 22000 functions */ 600 int (*txq_alloc)(struct iwl_trans *trans, 601 __le16 flags, u8 sta_id, u8 tid, 602 int cmd_id, int size, 603 unsigned int queue_wdg_timeout); 604 void (*txq_free)(struct iwl_trans *trans, int queue); 605 int (*rxq_dma_data)(struct iwl_trans *trans, int queue, 606 struct iwl_trans_rxq_dma_data *data); 607 608 void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id, 609 bool shared); 610 611 int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm); 612 int (*wait_txq_empty)(struct iwl_trans *trans, int queue); 613 void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, 614 bool freeze); 615 void (*block_txq_ptrs)(struct iwl_trans *trans, bool block); 616 617 void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); 618 void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); 619 u32 (*read32)(struct iwl_trans *trans, u32 ofs); 620 u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); 621 void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); 622 int (*read_mem)(struct iwl_trans *trans, u32 addr, 623 void *buf, int dwords); 624 int (*write_mem)(struct iwl_trans *trans, u32 addr, 625 const void *buf, int dwords); 626 int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val); 627 void (*configure)(struct iwl_trans *trans, 628 const struct iwl_trans_config *trans_cfg); 629 void (*set_pmi)(struct iwl_trans *trans, bool state); 630 void (*sw_reset)(struct iwl_trans *trans); 631 bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags); 632 void (*release_nic_access)(struct iwl_trans *trans, 633 unsigned long *flags); 634 void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, 635 u32 value); 636 int (*suspend)(struct iwl_trans *trans); 637 void (*resume)(struct iwl_trans *trans); 638 639 struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, 640 u32 dump_mask); 641 void (*debugfs_cleanup)(struct iwl_trans *trans); 642 void (*sync_nmi)(struct iwl_trans *trans); 643 }; 644 645 /** 646 * enum iwl_trans_state - state of the transport layer 647 * 648 * @IWL_TRANS_NO_FW: no fw has sent an alive response 649 * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response 650 */ 651 enum iwl_trans_state { 652 IWL_TRANS_NO_FW = 0, 653 IWL_TRANS_FW_ALIVE = 1, 654 }; 655 656 /** 657 * DOC: Platform power management 658 * 659 * In system-wide power management the entire platform goes into a low 660 * power state (e.g. idle or suspend to RAM) at the same time and the 661 * device is configured as a wakeup source for the entire platform. 662 * This is usually triggered by userspace activity (e.g. the user 663 * presses the suspend button or a power management daemon decides to 664 * put the platform in low power mode). The device's behavior in this 665 * mode is dictated by the wake-on-WLAN configuration. 666 * 667 * The terms used for the device's behavior are as follows: 668 * 669 * - D0: the device is fully powered and the host is awake; 670 * - D3: the device is in low power mode and only reacts to 671 * specific events (e.g. magic-packet received or scan 672 * results found); 673 * 674 * These terms reflect the power modes in the firmware and are not to 675 * be confused with the physical device power state. 676 */ 677 678 /** 679 * enum iwl_plat_pm_mode - platform power management mode 680 * 681 * This enumeration describes the device's platform power management 682 * behavior when in system-wide suspend (i.e WoWLAN). 683 * 684 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 685 * device. In system-wide suspend mode, it means that the all 686 * connections will be closed automatically by mac80211 before 687 * the platform is suspended. 688 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 689 */ 690 enum iwl_plat_pm_mode { 691 IWL_PLAT_PM_MODE_DISABLED, 692 IWL_PLAT_PM_MODE_D3, 693 }; 694 695 /** 696 * enum iwl_ini_cfg_state 697 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 698 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 699 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 700 * are corrupted. The rest of the debug TLVs will still be used 701 */ 702 enum iwl_ini_cfg_state { 703 IWL_INI_CFG_STATE_NOT_LOADED, 704 IWL_INI_CFG_STATE_LOADED, 705 IWL_INI_CFG_STATE_CORRUPTED, 706 }; 707 708 /* Max time to wait for nmi interrupt */ 709 #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 710 711 /** 712 * struct iwl_dram_data 713 * @physical: page phy pointer 714 * @block: pointer to the allocated block/page 715 * @size: size of the block/page 716 */ 717 struct iwl_dram_data { 718 dma_addr_t physical; 719 void *block; 720 int size; 721 }; 722 723 /** 724 * struct iwl_fw_mon - fw monitor per allocation id 725 * @num_frags: number of fragments 726 * @frags: an array of DRAM buffer fragments 727 */ 728 struct iwl_fw_mon { 729 u32 num_frags; 730 struct iwl_dram_data *frags; 731 }; 732 733 /** 734 * struct iwl_self_init_dram - dram data used by self init process 735 * @fw: lmac and umac dram data 736 * @fw_cnt: total number of items in array 737 * @paging: paging dram data 738 * @paging_cnt: total number of items in array 739 */ 740 struct iwl_self_init_dram { 741 struct iwl_dram_data *fw; 742 int fw_cnt; 743 struct iwl_dram_data *paging; 744 int paging_cnt; 745 }; 746 747 /** 748 * struct iwl_trans_debug - transport debug related data 749 * 750 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 751 * @rec_on: true iff there is a fw debug recording currently active 752 * @dest_tlv: points to the destination TLV for debug 753 * @conf_tlv: array of pointers to configuration TLVs for debug 754 * @trigger_tlv: array of pointers to triggers TLVs for debug 755 * @lmac_error_event_table: addrs of lmacs error tables 756 * @umac_error_event_table: addr of umac error table 757 * @error_event_table_tlv_status: bitmap that indicates what error table 758 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 759 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 760 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 761 * @fw_mon_cfg: debug buffer allocation configuration 762 * @fw_mon_ini: DRAM buffer fragments per allocation id 763 * @fw_mon: DRAM buffer for firmware monitor 764 * @hw_error: equals true if hw error interrupt was received from the FW 765 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 766 * @active_regions: active regions 767 * @debug_info_tlv_list: list of debug info TLVs 768 * @time_point: array of debug time points 769 * @periodic_trig_list: periodic triggers list 770 * @domains_bitmap: bitmap of active domains other than 771 * &IWL_FW_INI_DOMAIN_ALWAYS_ON 772 */ 773 struct iwl_trans_debug { 774 u8 n_dest_reg; 775 bool rec_on; 776 777 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 778 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX]; 779 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv; 780 781 u32 lmac_error_event_table[2]; 782 u32 umac_error_event_table; 783 unsigned int error_event_table_tlv_status; 784 785 enum iwl_ini_cfg_state internal_ini_cfg; 786 enum iwl_ini_cfg_state external_ini_cfg; 787 788 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 789 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 790 791 struct iwl_dram_data fw_mon; 792 793 bool hw_error; 794 enum iwl_fw_ini_buffer_location ini_dest; 795 796 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 797 struct list_head debug_info_tlv_list; 798 struct iwl_dbg_tlv_time_point_data 799 time_point[IWL_FW_INI_TIME_POINT_NUM]; 800 struct list_head periodic_trig_list; 801 802 u32 domains_bitmap; 803 }; 804 805 struct iwl_dma_ptr { 806 dma_addr_t dma; 807 void *addr; 808 size_t size; 809 }; 810 811 struct iwl_cmd_meta { 812 /* only for SYNC commands, iff the reply skb is wanted */ 813 struct iwl_host_cmd *source; 814 u32 flags; 815 u32 tbs; 816 }; 817 818 /* 819 * The FH will write back to the first TB only, so we need to copy some data 820 * into the buffer regardless of whether it should be mapped or not. 821 * This indicates how big the first TB must be to include the scratch buffer 822 * and the assigned PN. 823 * Since PN location is 8 bytes at offset 12, it's 20 now. 824 * If we make it bigger then allocations will be bigger and copy slower, so 825 * that's probably not useful. 826 */ 827 #define IWL_FIRST_TB_SIZE 20 828 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 829 830 struct iwl_pcie_txq_entry { 831 void *cmd; 832 struct sk_buff *skb; 833 /* buffer to free after command completes */ 834 const void *free_buf; 835 struct iwl_cmd_meta meta; 836 }; 837 838 struct iwl_pcie_first_tb_buf { 839 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 840 }; 841 842 /** 843 * struct iwl_txq - Tx Queue for DMA 844 * @q: generic Rx/Tx queue descriptor 845 * @tfds: transmit frame descriptors (DMA memory) 846 * @first_tb_bufs: start of command headers, including scratch buffers, for 847 * the writeback -- this is DMA memory and an array holding one buffer 848 * for each command on the queue 849 * @first_tb_dma: DMA address for the first_tb_bufs start 850 * @entries: transmit entries (driver state) 851 * @lock: queue lock 852 * @stuck_timer: timer that fires if queue gets stuck 853 * @trans: pointer back to transport (for timer) 854 * @need_update: indicates need to update read/write index 855 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 856 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 857 * @frozen: tx stuck queue timer is frozen 858 * @frozen_expiry_remainder: remember how long until the timer fires 859 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 860 * @write_ptr: 1-st empty entry (index) host_w 861 * @read_ptr: last used entry (index) host_r 862 * @dma_addr: physical addr for BD's 863 * @n_window: safe queue window 864 * @id: queue id 865 * @low_mark: low watermark, resume queue if free space more than this 866 * @high_mark: high watermark, stop queue if free space less than this 867 * 868 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 869 * descriptors) and required locking structures. 870 * 871 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 872 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 873 * there might be HW changes in the future). For the normal TX 874 * queues, n_window, which is the size of the software queue data 875 * is also 256; however, for the command queue, n_window is only 876 * 32 since we don't need so many commands pending. Since the HW 877 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 878 * This means that we end up with the following: 879 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 880 * SW entries: | 0 | ... | 31 | 881 * where N is a number between 0 and 7. This means that the SW 882 * data is a window overlayed over the HW queue. 883 */ 884 struct iwl_txq { 885 void *tfds; 886 struct iwl_pcie_first_tb_buf *first_tb_bufs; 887 dma_addr_t first_tb_dma; 888 struct iwl_pcie_txq_entry *entries; 889 /* lock for syncing changes on the queue */ 890 spinlock_t lock; 891 unsigned long frozen_expiry_remainder; 892 struct timer_list stuck_timer; 893 struct iwl_trans *trans; 894 bool need_update; 895 bool frozen; 896 bool ampdu; 897 int block; 898 unsigned long wd_timeout; 899 struct sk_buff_head overflow_q; 900 struct iwl_dma_ptr bc_tbl; 901 902 int write_ptr; 903 int read_ptr; 904 dma_addr_t dma_addr; 905 int n_window; 906 u32 id; 907 int low_mark; 908 int high_mark; 909 910 bool overflow_tx; 911 }; 912 913 /** 914 * struct iwl_trans_txqs - transport tx queues data 915 * 916 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 917 * @queue_used - bit mask of used queues 918 * @queue_stopped - bit mask of stopped queues 919 */ 920 struct iwl_trans_txqs { 921 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 922 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 923 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 924 struct dma_pool *bc_pool; 925 size_t bc_tbl_size; 926 bool bc_table_dword; 927 928 struct { 929 u8 fifo; 930 u8 q_id; 931 unsigned int wdg_timeout; 932 } cmd; 933 934 struct { 935 u8 max_tbs; 936 u16 size; 937 u8 addr_size; 938 } tfd; 939 }; 940 941 /** 942 * struct iwl_trans - transport common data 943 * 944 * @ops - pointer to iwl_trans_ops 945 * @op_mode - pointer to the op_mode 946 * @trans_cfg: the trans-specific configuration part 947 * @cfg - pointer to the configuration 948 * @drv - pointer to iwl_drv 949 * @status: a bit-mask of transport status flags 950 * @dev - pointer to struct device * that represents the device 951 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 952 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 953 * @hw_rf_id a u32 with the device RF ID 954 * @hw_id: a u32 with the ID of the device / sub-device. 955 * Set during transport allocation. 956 * @hw_id_str: a string with info about HW ID. Set during transport allocation. 957 * @pm_support: set to true in start_hw if link pm is supported 958 * @ltr_enabled: set to true if the LTR is enabled 959 * @wide_cmd_header: true when ucode supports wide command header format 960 * @num_rx_queues: number of RX queues allocated by the transport; 961 * the transport must set this before calling iwl_drv_start() 962 * @iml_len: the length of the image loader 963 * @iml: a pointer to the image loader itself 964 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 965 * The user should use iwl_trans_{alloc,free}_tx_cmd. 966 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 967 * starting the firmware, used for tracing 968 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 969 * start of the 802.11 header in the @rx_mpdu_cmd 970 * @dflt_pwr_limit: default power limit fetched from the platform (ACPI) 971 * @system_pm_mode: the system-wide power management mode in use. 972 * This mode is set dynamically, depending on the WoWLAN values 973 * configured from the userspace at runtime. 974 * @iwl_trans_txqs: transport tx queues data. 975 */ 976 struct iwl_trans { 977 const struct iwl_trans_ops *ops; 978 struct iwl_op_mode *op_mode; 979 const struct iwl_cfg_trans_params *trans_cfg; 980 const struct iwl_cfg *cfg; 981 struct iwl_drv *drv; 982 enum iwl_trans_state state; 983 unsigned long status; 984 985 struct device *dev; 986 u32 max_skb_frags; 987 u32 hw_rev; 988 u32 hw_rf_id; 989 u32 hw_id; 990 char hw_id_str[52]; 991 992 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 993 994 bool pm_support; 995 bool ltr_enabled; 996 997 const struct iwl_hcmd_arr *command_groups; 998 int command_groups_size; 999 bool wide_cmd_header; 1000 1001 u8 num_rx_queues; 1002 1003 size_t iml_len; 1004 u8 *iml; 1005 1006 /* The following fields are internal only */ 1007 struct kmem_cache *dev_cmd_pool; 1008 char dev_cmd_pool_name[50]; 1009 1010 struct dentry *dbgfs_dir; 1011 1012 #ifdef CONFIG_LOCKDEP 1013 struct lockdep_map sync_cmd_lockdep_map; 1014 #endif 1015 1016 struct iwl_trans_debug dbg; 1017 struct iwl_self_init_dram init_dram; 1018 1019 enum iwl_plat_pm_mode system_pm_mode; 1020 1021 const char *name; 1022 struct iwl_trans_txqs txqs; 1023 1024 /* pointer to trans specific struct */ 1025 /*Ensure that this pointer will always be aligned to sizeof pointer */ 1026 char trans_specific[] __aligned(sizeof(void *)); 1027 }; 1028 1029 const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 1030 int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 1031 1032 static inline void iwl_trans_configure(struct iwl_trans *trans, 1033 const struct iwl_trans_config *trans_cfg) 1034 { 1035 trans->op_mode = trans_cfg->op_mode; 1036 1037 trans->ops->configure(trans, trans_cfg); 1038 WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)); 1039 } 1040 1041 static inline int iwl_trans_start_hw(struct iwl_trans *trans) 1042 { 1043 might_sleep(); 1044 1045 return trans->ops->start_hw(trans); 1046 } 1047 1048 static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) 1049 { 1050 might_sleep(); 1051 1052 if (trans->ops->op_mode_leave) 1053 trans->ops->op_mode_leave(trans); 1054 1055 trans->op_mode = NULL; 1056 1057 trans->state = IWL_TRANS_NO_FW; 1058 } 1059 1060 static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1061 { 1062 might_sleep(); 1063 1064 trans->state = IWL_TRANS_FW_ALIVE; 1065 1066 trans->ops->fw_alive(trans, scd_addr); 1067 } 1068 1069 static inline int iwl_trans_start_fw(struct iwl_trans *trans, 1070 const struct fw_img *fw, 1071 bool run_in_rfkill) 1072 { 1073 might_sleep(); 1074 1075 WARN_ON_ONCE(!trans->rx_mpdu_cmd); 1076 1077 clear_bit(STATUS_FW_ERROR, &trans->status); 1078 return trans->ops->start_fw(trans, fw, run_in_rfkill); 1079 } 1080 1081 static inline void iwl_trans_stop_device(struct iwl_trans *trans) 1082 { 1083 might_sleep(); 1084 1085 trans->ops->stop_device(trans); 1086 1087 trans->state = IWL_TRANS_NO_FW; 1088 } 1089 1090 static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, 1091 bool reset) 1092 { 1093 might_sleep(); 1094 if (!trans->ops->d3_suspend) 1095 return 0; 1096 1097 return trans->ops->d3_suspend(trans, test, reset); 1098 } 1099 1100 static inline int iwl_trans_d3_resume(struct iwl_trans *trans, 1101 enum iwl_d3_status *status, 1102 bool test, bool reset) 1103 { 1104 might_sleep(); 1105 if (!trans->ops->d3_resume) 1106 return 0; 1107 1108 return trans->ops->d3_resume(trans, status, test, reset); 1109 } 1110 1111 static inline int iwl_trans_suspend(struct iwl_trans *trans) 1112 { 1113 if (!trans->ops->suspend) 1114 return 0; 1115 1116 return trans->ops->suspend(trans); 1117 } 1118 1119 static inline void iwl_trans_resume(struct iwl_trans *trans) 1120 { 1121 if (trans->ops->resume) 1122 trans->ops->resume(trans); 1123 } 1124 1125 static inline struct iwl_trans_dump_data * 1126 iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask) 1127 { 1128 if (!trans->ops->dump_data) 1129 return NULL; 1130 return trans->ops->dump_data(trans, dump_mask); 1131 } 1132 1133 static inline struct iwl_device_tx_cmd * 1134 iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 1135 { 1136 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC); 1137 } 1138 1139 int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 1140 1141 static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 1142 struct iwl_device_tx_cmd *dev_cmd) 1143 { 1144 kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 1145 } 1146 1147 static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 1148 struct iwl_device_tx_cmd *dev_cmd, int queue) 1149 { 1150 if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) 1151 return -EIO; 1152 1153 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1154 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1155 return -EIO; 1156 } 1157 1158 return trans->ops->tx(trans, skb, dev_cmd, queue); 1159 } 1160 1161 static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, 1162 int ssn, struct sk_buff_head *skbs) 1163 { 1164 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1165 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1166 return; 1167 } 1168 1169 trans->ops->reclaim(trans, queue, ssn, skbs); 1170 } 1171 1172 static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, 1173 int ptr) 1174 { 1175 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1176 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1177 return; 1178 } 1179 1180 trans->ops->set_q_ptrs(trans, queue, ptr); 1181 } 1182 1183 static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 1184 bool configure_scd) 1185 { 1186 trans->ops->txq_disable(trans, queue, configure_scd); 1187 } 1188 1189 static inline bool 1190 iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 1191 const struct iwl_trans_txq_scd_cfg *cfg, 1192 unsigned int queue_wdg_timeout) 1193 { 1194 might_sleep(); 1195 1196 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1197 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1198 return false; 1199 } 1200 1201 return trans->ops->txq_enable(trans, queue, ssn, 1202 cfg, queue_wdg_timeout); 1203 } 1204 1205 static inline int 1206 iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 1207 struct iwl_trans_rxq_dma_data *data) 1208 { 1209 if (WARN_ON_ONCE(!trans->ops->rxq_dma_data)) 1210 return -ENOTSUPP; 1211 1212 return trans->ops->rxq_dma_data(trans, queue, data); 1213 } 1214 1215 static inline void 1216 iwl_trans_txq_free(struct iwl_trans *trans, int queue) 1217 { 1218 if (WARN_ON_ONCE(!trans->ops->txq_free)) 1219 return; 1220 1221 trans->ops->txq_free(trans, queue); 1222 } 1223 1224 static inline int 1225 iwl_trans_txq_alloc(struct iwl_trans *trans, 1226 __le16 flags, u8 sta_id, u8 tid, 1227 int cmd_id, int size, 1228 unsigned int wdg_timeout) 1229 { 1230 might_sleep(); 1231 1232 if (WARN_ON_ONCE(!trans->ops->txq_alloc)) 1233 return -ENOTSUPP; 1234 1235 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1236 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1237 return -EIO; 1238 } 1239 1240 return trans->ops->txq_alloc(trans, flags, sta_id, tid, 1241 cmd_id, size, wdg_timeout); 1242 } 1243 1244 static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 1245 int queue, bool shared_mode) 1246 { 1247 if (trans->ops->txq_set_shared_mode) 1248 trans->ops->txq_set_shared_mode(trans, queue, shared_mode); 1249 } 1250 1251 static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1252 int fifo, int sta_id, int tid, 1253 int frame_limit, u16 ssn, 1254 unsigned int queue_wdg_timeout) 1255 { 1256 struct iwl_trans_txq_scd_cfg cfg = { 1257 .fifo = fifo, 1258 .sta_id = sta_id, 1259 .tid = tid, 1260 .frame_limit = frame_limit, 1261 .aggregate = sta_id >= 0, 1262 }; 1263 1264 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1265 } 1266 1267 static inline 1268 void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1269 unsigned int queue_wdg_timeout) 1270 { 1271 struct iwl_trans_txq_scd_cfg cfg = { 1272 .fifo = fifo, 1273 .sta_id = -1, 1274 .tid = IWL_MAX_TID_COUNT, 1275 .frame_limit = IWL_FRAME_LIMIT, 1276 .aggregate = false, 1277 }; 1278 1279 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1280 } 1281 1282 static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1283 unsigned long txqs, 1284 bool freeze) 1285 { 1286 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1287 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1288 return; 1289 } 1290 1291 if (trans->ops->freeze_txq_timer) 1292 trans->ops->freeze_txq_timer(trans, txqs, freeze); 1293 } 1294 1295 static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans, 1296 bool block) 1297 { 1298 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1299 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1300 return; 1301 } 1302 1303 if (trans->ops->block_txq_ptrs) 1304 trans->ops->block_txq_ptrs(trans, block); 1305 } 1306 1307 static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, 1308 u32 txqs) 1309 { 1310 if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty)) 1311 return -ENOTSUPP; 1312 1313 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1314 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1315 return -EIO; 1316 } 1317 1318 return trans->ops->wait_tx_queues_empty(trans, txqs); 1319 } 1320 1321 static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue) 1322 { 1323 if (WARN_ON_ONCE(!trans->ops->wait_txq_empty)) 1324 return -ENOTSUPP; 1325 1326 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1327 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1328 return -EIO; 1329 } 1330 1331 return trans->ops->wait_txq_empty(trans, queue); 1332 } 1333 1334 static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1335 { 1336 trans->ops->write8(trans, ofs, val); 1337 } 1338 1339 static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1340 { 1341 trans->ops->write32(trans, ofs, val); 1342 } 1343 1344 static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) 1345 { 1346 return trans->ops->read32(trans, ofs); 1347 } 1348 1349 static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) 1350 { 1351 return trans->ops->read_prph(trans, ofs); 1352 } 1353 1354 static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, 1355 u32 val) 1356 { 1357 return trans->ops->write_prph(trans, ofs, val); 1358 } 1359 1360 static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1361 void *buf, int dwords) 1362 { 1363 return trans->ops->read_mem(trans, addr, buf, dwords); 1364 } 1365 1366 #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1367 do { \ 1368 if (__builtin_constant_p(bufsize)) \ 1369 BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1370 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1371 } while (0) 1372 1373 static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1374 { 1375 u32 value; 1376 1377 if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) 1378 return 0xa5a5a5a5; 1379 1380 return value; 1381 } 1382 1383 static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1384 const void *buf, int dwords) 1385 { 1386 return trans->ops->write_mem(trans, addr, buf, dwords); 1387 } 1388 1389 static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1390 u32 val) 1391 { 1392 return iwl_trans_write_mem(trans, addr, &val, 1); 1393 } 1394 1395 static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) 1396 { 1397 if (trans->ops->set_pmi) 1398 trans->ops->set_pmi(trans, state); 1399 } 1400 1401 static inline void iwl_trans_sw_reset(struct iwl_trans *trans) 1402 { 1403 if (trans->ops->sw_reset) 1404 trans->ops->sw_reset(trans); 1405 } 1406 1407 static inline void 1408 iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) 1409 { 1410 trans->ops->set_bits_mask(trans, reg, mask, value); 1411 } 1412 1413 #define iwl_trans_grab_nic_access(trans, flags) \ 1414 __cond_lock(nic_access, \ 1415 likely((trans)->ops->grab_nic_access(trans, flags))) 1416 1417 static inline void __releases(nic_access) 1418 iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags) 1419 { 1420 trans->ops->release_nic_access(trans, flags); 1421 __release(nic_access); 1422 } 1423 1424 static inline void iwl_trans_fw_error(struct iwl_trans *trans) 1425 { 1426 if (WARN_ON_ONCE(!trans->op_mode)) 1427 return; 1428 1429 /* prevent double restarts due to the same erroneous FW */ 1430 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) 1431 iwl_op_mode_nic_error(trans->op_mode); 1432 } 1433 1434 static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1435 { 1436 return trans->state == IWL_TRANS_FW_ALIVE; 1437 } 1438 1439 static inline void iwl_trans_sync_nmi(struct iwl_trans *trans) 1440 { 1441 if (trans->ops->sync_nmi) 1442 trans->ops->sync_nmi(trans); 1443 } 1444 1445 static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1446 { 1447 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1448 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1449 } 1450 1451 /***************************************************** 1452 * transport helper functions 1453 *****************************************************/ 1454 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1455 struct device *dev, 1456 const struct iwl_trans_ops *ops, 1457 const struct iwl_cfg_trans_params *cfg_trans); 1458 void iwl_trans_free(struct iwl_trans *trans); 1459 1460 /***************************************************** 1461 * driver (transport) register/unregister functions 1462 ******************************************************/ 1463 int __must_check iwl_pci_register_driver(void); 1464 void iwl_pci_unregister_driver(void); 1465 1466 #endif /* __iwl_trans_h__ */ 1467