1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2018-2022 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_trans_h__ 8 #define __iwl_trans_h__ 9 10 #include <linux/ieee80211.h> 11 #include <linux/mm.h> /* for page_address */ 12 #include <linux/lockdep.h> 13 #include <linux/kernel.h> 14 15 #include "iwl-debug.h" 16 #include "iwl-config.h" 17 #include "fw/img.h" 18 #include "iwl-op-mode.h" 19 #include <linux/firmware.h> 20 #include "fw/api/cmdhdr.h" 21 #include "fw/api/txq.h" 22 #include "fw/api/dbg-tlv.h" 23 #include "iwl-dbg-tlv.h" 24 25 /** 26 * DOC: Transport layer - what is it ? 27 * 28 * The transport layer is the layer that deals with the HW directly. It provides 29 * an abstraction of the underlying HW to the upper layer. The transport layer 30 * doesn't provide any policy, algorithm or anything of this kind, but only 31 * mechanisms to make the HW do something. It is not completely stateless but 32 * close to it. 33 * We will have an implementation for each different supported bus. 34 */ 35 36 /** 37 * DOC: Life cycle of the transport layer 38 * 39 * The transport layer has a very precise life cycle. 40 * 41 * 1) A helper function is called during the module initialization and 42 * registers the bus driver's ops with the transport's alloc function. 43 * 2) Bus's probe calls to the transport layer's allocation functions. 44 * Of course this function is bus specific. 45 * 3) This allocation functions will spawn the upper layer which will 46 * register mac80211. 47 * 48 * 4) At some point (i.e. mac80211's start call), the op_mode will call 49 * the following sequence: 50 * start_hw 51 * start_fw 52 * 53 * 5) Then when finished (or reset): 54 * stop_device 55 * 56 * 6) Eventually, the free function will be called. 57 */ 58 59 #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 60 61 #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 62 #define FH_RSCSR_FRAME_INVALID 0x55550000 63 #define FH_RSCSR_FRAME_ALIGN 0x40 64 #define FH_RSCSR_RPA_EN BIT(25) 65 #define FH_RSCSR_RADA_EN BIT(26) 66 #define FH_RSCSR_RXQ_POS 16 67 #define FH_RSCSR_RXQ_MASK 0x3F0000 68 69 struct iwl_rx_packet { 70 /* 71 * The first 4 bytes of the RX frame header contain both the RX frame 72 * size and some flags. 73 * Bit fields: 74 * 31: flag flush RB request 75 * 30: flag ignore TC (terminal counter) request 76 * 29: flag fast IRQ request 77 * 28-27: Reserved 78 * 26: RADA enabled 79 * 25: Offload enabled 80 * 24: RPF enabled 81 * 23: RSS enabled 82 * 22: Checksum enabled 83 * 21-16: RX queue 84 * 15-14: Reserved 85 * 13-00: RX frame size 86 */ 87 __le32 len_n_flags; 88 struct iwl_cmd_header hdr; 89 u8 data[]; 90 } __packed; 91 92 static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 93 { 94 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 95 } 96 97 static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 98 { 99 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 100 } 101 102 /** 103 * enum CMD_MODE - how to send the host commands ? 104 * 105 * @CMD_ASYNC: Return right away and don't wait for the response 106 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 107 * the response. The caller needs to call iwl_free_resp when done. 108 * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be 109 * called after this command completes. Valid only with CMD_ASYNC. 110 * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to 111 * SUSPEND and RESUME commands. We are in D3 mode when we set 112 * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3. 113 */ 114 enum CMD_MODE { 115 CMD_ASYNC = BIT(0), 116 CMD_WANT_SKB = BIT(1), 117 CMD_SEND_IN_RFKILL = BIT(2), 118 CMD_WANT_ASYNC_CALLBACK = BIT(3), 119 CMD_SEND_IN_D3 = BIT(4), 120 }; 121 122 #define DEF_CMD_PAYLOAD_SIZE 320 123 124 /** 125 * struct iwl_device_cmd 126 * 127 * For allocation of the command and tx queues, this establishes the overall 128 * size of the largest command we send to uCode, except for commands that 129 * aren't fully copied and use other TFD space. 130 */ 131 struct iwl_device_cmd { 132 union { 133 struct { 134 struct iwl_cmd_header hdr; /* uCode API */ 135 u8 payload[DEF_CMD_PAYLOAD_SIZE]; 136 }; 137 struct { 138 struct iwl_cmd_header_wide hdr_wide; 139 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 140 sizeof(struct iwl_cmd_header_wide) + 141 sizeof(struct iwl_cmd_header)]; 142 }; 143 }; 144 } __packed; 145 146 /** 147 * struct iwl_device_tx_cmd - buffer for TX command 148 * @hdr: the header 149 * @payload: the payload placeholder 150 * 151 * The actual structure is sized dynamically according to need. 152 */ 153 struct iwl_device_tx_cmd { 154 struct iwl_cmd_header hdr; 155 u8 payload[]; 156 } __packed; 157 158 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 159 160 /* 161 * number of transfer buffers (fragments) per transmit frame descriptor; 162 * this is just the driver's idea, the hardware supports 20 163 */ 164 #define IWL_MAX_CMD_TBS_PER_TFD 2 165 166 /* We need 2 entries for the TX command and header, and another one might 167 * be needed for potential data in the SKB's head. The remaining ones can 168 * be used for frags. 169 */ 170 #define IWL_TRANS_MAX_FRAGS(trans) ((trans)->txqs.tfd.max_tbs - 3) 171 172 /** 173 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 174 * 175 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 176 * ring. The transport layer doesn't map the command's buffer to DMA, but 177 * rather copies it to a previously allocated DMA buffer. This flag tells 178 * the transport layer not to copy the command, but to map the existing 179 * buffer (that is passed in) instead. This saves the memcpy and allows 180 * commands that are bigger than the fixed buffer to be submitted. 181 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 182 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 183 * chunk internally and free it again after the command completes. This 184 * can (currently) be used only once per command. 185 * Note that a TFD entry after a DUP one cannot be a normal copied one. 186 */ 187 enum iwl_hcmd_dataflag { 188 IWL_HCMD_DFL_NOCOPY = BIT(0), 189 IWL_HCMD_DFL_DUP = BIT(1), 190 }; 191 192 enum iwl_error_event_table_status { 193 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 194 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 195 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 196 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3), 197 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4), 198 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5), 199 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6), 200 }; 201 202 /** 203 * struct iwl_host_cmd - Host command to the uCode 204 * 205 * @data: array of chunks that composes the data of the host command 206 * @resp_pkt: response packet, if %CMD_WANT_SKB was set 207 * @_rx_page_order: (internally used to free response packet) 208 * @_rx_page_addr: (internally used to free response packet) 209 * @flags: can be CMD_* 210 * @len: array of the lengths of the chunks in data 211 * @dataflags: IWL_HCMD_DFL_* 212 * @id: command id of the host command, for wide commands encoding the 213 * version and group as well 214 */ 215 struct iwl_host_cmd { 216 const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 217 struct iwl_rx_packet *resp_pkt; 218 unsigned long _rx_page_addr; 219 u32 _rx_page_order; 220 221 u32 flags; 222 u32 id; 223 u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 224 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 225 }; 226 227 static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 228 { 229 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 230 } 231 232 struct iwl_rx_cmd_buffer { 233 struct page *_page; 234 int _offset; 235 bool _page_stolen; 236 u32 _rx_page_order; 237 unsigned int truesize; 238 }; 239 240 static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 241 { 242 return (void *)((unsigned long)page_address(r->_page) + r->_offset); 243 } 244 245 static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 246 { 247 return r->_offset; 248 } 249 250 static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 251 { 252 r->_page_stolen = true; 253 get_page(r->_page); 254 return r->_page; 255 } 256 257 static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 258 { 259 __free_pages(r->_page, r->_rx_page_order); 260 } 261 262 #define MAX_NO_RECLAIM_CMDS 6 263 264 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 265 266 /* 267 * Maximum number of HW queues the transport layer 268 * currently supports 269 */ 270 #define IWL_MAX_HW_QUEUES 32 271 #define IWL_MAX_TVQM_QUEUES 512 272 273 #define IWL_MAX_TID_COUNT 8 274 #define IWL_MGMT_TID 15 275 #define IWL_FRAME_LIMIT 64 276 #define IWL_MAX_RX_HW_QUEUES 16 277 #define IWL_9000_MAX_RX_HW_QUEUES 6 278 279 /** 280 * enum iwl_wowlan_status - WoWLAN image/device status 281 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 282 * @IWL_D3_STATUS_RESET: device was reset while suspended 283 */ 284 enum iwl_d3_status { 285 IWL_D3_STATUS_ALIVE, 286 IWL_D3_STATUS_RESET, 287 }; 288 289 /** 290 * enum iwl_trans_status: transport status flags 291 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 292 * @STATUS_DEVICE_ENABLED: APM is enabled 293 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 294 * @STATUS_INT_ENABLED: interrupts are enabled 295 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 296 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 297 * @STATUS_FW_ERROR: the fw is in error state 298 * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands 299 * are sent 300 * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent 301 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 302 * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once, 303 * e.g. for testing 304 */ 305 enum iwl_trans_status { 306 STATUS_SYNC_HCMD_ACTIVE, 307 STATUS_DEVICE_ENABLED, 308 STATUS_TPOWER_PMI, 309 STATUS_INT_ENABLED, 310 STATUS_RFKILL_HW, 311 STATUS_RFKILL_OPMODE, 312 STATUS_FW_ERROR, 313 STATUS_TRANS_GOING_IDLE, 314 STATUS_TRANS_IDLE, 315 STATUS_TRANS_DEAD, 316 STATUS_SUPPRESS_CMD_ERROR_ONCE, 317 }; 318 319 static inline int 320 iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 321 { 322 switch (rb_size) { 323 case IWL_AMSDU_2K: 324 return get_order(2 * 1024); 325 case IWL_AMSDU_4K: 326 return get_order(4 * 1024); 327 case IWL_AMSDU_8K: 328 return get_order(8 * 1024); 329 case IWL_AMSDU_12K: 330 return get_order(16 * 1024); 331 default: 332 WARN_ON(1); 333 return -1; 334 } 335 } 336 337 static inline int 338 iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 339 { 340 switch (rb_size) { 341 case IWL_AMSDU_2K: 342 return 2 * 1024; 343 case IWL_AMSDU_4K: 344 return 4 * 1024; 345 case IWL_AMSDU_8K: 346 return 8 * 1024; 347 case IWL_AMSDU_12K: 348 return 16 * 1024; 349 default: 350 WARN_ON(1); 351 return 0; 352 } 353 } 354 355 struct iwl_hcmd_names { 356 u8 cmd_id; 357 const char *const cmd_name; 358 }; 359 360 #define HCMD_NAME(x) \ 361 { .cmd_id = x, .cmd_name = #x } 362 363 struct iwl_hcmd_arr { 364 const struct iwl_hcmd_names *arr; 365 int size; 366 }; 367 368 #define HCMD_ARR(x) \ 369 { .arr = x, .size = ARRAY_SIZE(x) } 370 371 /** 372 * struct iwl_dump_sanitize_ops - dump sanitization operations 373 * @frob_txf: Scrub the TX FIFO data 374 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header 375 * but that might be short or long (&struct iwl_cmd_header or 376 * &struct iwl_cmd_header_wide) 377 * @frob_mem: Scrub memory data 378 */ 379 struct iwl_dump_sanitize_ops { 380 void (*frob_txf)(void *ctx, void *buf, size_t buflen); 381 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen); 382 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen); 383 }; 384 385 /** 386 * struct iwl_trans_config - transport configuration 387 * 388 * @op_mode: pointer to the upper layer. 389 * @cmd_queue: the index of the command queue. 390 * Must be set before start_fw. 391 * @cmd_fifo: the fifo for host commands 392 * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 393 * @no_reclaim_cmds: Some devices erroneously don't set the 394 * SEQ_RX_FRAME bit on some notifications, this is the 395 * list of such notifications to filter. Max length is 396 * %MAX_NO_RECLAIM_CMDS. 397 * @n_no_reclaim_cmds: # of commands in list 398 * @rx_buf_size: RX buffer size needed for A-MSDUs 399 * if unset 4k will be the RX buffer size 400 * @bc_table_dword: set to true if the BC table expects the byte count to be 401 * in DWORD (as opposed to bytes) 402 * @scd_set_active: should the transport configure the SCD for HCMD queue 403 * @command_groups: array of command groups, each member is an array of the 404 * commands in the group; for debugging only 405 * @command_groups_size: number of command groups, to avoid illegal access 406 * @cb_data_offs: offset inside skb->cb to store transport data at, must have 407 * space for at least two pointers 408 * @fw_reset_handshake: firmware supports reset flow handshake 409 * @queue_alloc_cmd_ver: queue allocation command version, set to 0 410 * for using the older SCD_QUEUE_CFG, set to the version of 411 * SCD_QUEUE_CONFIG_CMD otherwise. 412 */ 413 struct iwl_trans_config { 414 struct iwl_op_mode *op_mode; 415 416 u8 cmd_queue; 417 u8 cmd_fifo; 418 unsigned int cmd_q_wdg_timeout; 419 const u8 *no_reclaim_cmds; 420 unsigned int n_no_reclaim_cmds; 421 422 enum iwl_amsdu_size rx_buf_size; 423 bool bc_table_dword; 424 bool scd_set_active; 425 const struct iwl_hcmd_arr *command_groups; 426 int command_groups_size; 427 428 u8 cb_data_offs; 429 bool fw_reset_handshake; 430 u8 queue_alloc_cmd_ver; 431 }; 432 433 struct iwl_trans_dump_data { 434 u32 len; 435 u8 data[]; 436 }; 437 438 struct iwl_trans; 439 440 struct iwl_trans_txq_scd_cfg { 441 u8 fifo; 442 u8 sta_id; 443 u8 tid; 444 bool aggregate; 445 int frame_limit; 446 }; 447 448 /** 449 * struct iwl_trans_rxq_dma_data - RX queue DMA data 450 * @fr_bd_cb: DMA address of free BD cyclic buffer 451 * @fr_bd_wid: Initial write index of the free BD cyclic buffer 452 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 453 * @ur_bd_cb: DMA address of used BD cyclic buffer 454 */ 455 struct iwl_trans_rxq_dma_data { 456 u64 fr_bd_cb; 457 u32 fr_bd_wid; 458 u64 urbd_stts_wrptr; 459 u64 ur_bd_cb; 460 }; 461 462 /** 463 * struct iwl_trans_ops - transport specific operations 464 * 465 * All the handlers MUST be implemented 466 * 467 * @start_hw: starts the HW. From that point on, the HW can send interrupts. 468 * May sleep. 469 * @op_mode_leave: Turn off the HW RF kill indication if on 470 * May sleep 471 * @start_fw: allocates and inits all the resources for the transport 472 * layer. Also kick a fw image. 473 * May sleep 474 * @fw_alive: called when the fw sends alive notification. If the fw provides 475 * the SCD base address in SRAM, then provide it here, or 0 otherwise. 476 * May sleep 477 * @stop_device: stops the whole device (embedded CPU put to reset) and stops 478 * the HW. From that point on, the HW will be stopped but will still issue 479 * an interrupt if the HW RF kill switch is triggered. 480 * This callback must do the right thing and not crash even if %start_hw() 481 * was called but not &start_fw(). May sleep. 482 * @d3_suspend: put the device into the correct mode for WoWLAN during 483 * suspend. This is optional, if not implemented WoWLAN will not be 484 * supported. This callback may sleep. 485 * @d3_resume: resume the device after WoWLAN, enabling the opmode to 486 * talk to the WoWLAN image to get its status. This is optional, if not 487 * implemented WoWLAN will not be supported. This callback may sleep. 488 * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. 489 * If RFkill is asserted in the middle of a SYNC host command, it must 490 * return -ERFKILL straight away. 491 * May sleep only if CMD_ASYNC is not set 492 * @tx: send an skb. The transport relies on the op_mode to zero the 493 * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all 494 * the CSUM will be taken care of (TCP CSUM and IP header in case of 495 * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP 496 * header if it is IPv4. 497 * Must be atomic 498 * @reclaim: free packet until ssn. Returns a list of freed packets. 499 * Must be atomic 500 * @txq_enable: setup a queue. To setup an AC queue, use the 501 * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before 502 * this one. The op_mode must not configure the HCMD queue. The scheduler 503 * configuration may be %NULL, in which case the hardware will not be 504 * configured. If true is returned, the operation mode needs to increment 505 * the sequence number of the packets routed to this queue because of a 506 * hardware scheduler bug. May sleep. 507 * @txq_disable: de-configure a Tx queue to send AMPDUs 508 * Must be atomic 509 * @txq_set_shared_mode: change Tx queue shared/unshared marking 510 * @wait_tx_queues_empty: wait until tx queues are empty. May sleep. 511 * @wait_txq_empty: wait until specific tx queue is empty. May sleep. 512 * @freeze_txq_timer: prevents the timer of the queue from firing until the 513 * queue is set to awake. Must be atomic. 514 * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note 515 * that the transport needs to refcount the calls since this function 516 * will be called several times with block = true, and then the queues 517 * need to be unblocked only after the same number of calls with 518 * block = false. 519 * @write8: write a u8 to a register at offset ofs from the BAR 520 * @write32: write a u32 to a register at offset ofs from the BAR 521 * @read32: read a u32 register at offset ofs from the BAR 522 * @read_prph: read a DWORD from a periphery register 523 * @write_prph: write a DWORD to a periphery register 524 * @read_mem: read device's SRAM in DWORD 525 * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory 526 * will be zeroed. 527 * @read_config32: read a u32 value from the device's config space at 528 * the given offset. 529 * @configure: configure parameters required by the transport layer from 530 * the op_mode. May be called several times before start_fw, can't be 531 * called after that. 532 * @set_pmi: set the power pmi state 533 * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. 534 * Sleeping is not allowed between grab_nic_access and 535 * release_nic_access. 536 * @release_nic_access: let the NIC go to sleep. The "flags" parameter 537 * must be the same one that was sent before to the grab_nic_access. 538 * @set_bits_mask - set SRAM register according to value and mask. 539 * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last 540 * TX'ed commands and similar. The buffer will be vfree'd by the caller. 541 * Note that the transport must fill in the proper file headers. 542 * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup 543 * of the trans debugfs 544 * @set_pnvm: set the pnvm data in the prph scratch buffer, inside the 545 * context info. 546 * @interrupts: disable/enable interrupts to transport 547 */ 548 struct iwl_trans_ops { 549 550 int (*start_hw)(struct iwl_trans *iwl_trans); 551 void (*op_mode_leave)(struct iwl_trans *iwl_trans); 552 int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, 553 bool run_in_rfkill); 554 void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); 555 void (*stop_device)(struct iwl_trans *trans); 556 557 int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset); 558 int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, 559 bool test, bool reset); 560 561 int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 562 563 int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, 564 struct iwl_device_tx_cmd *dev_cmd, int queue); 565 void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, 566 struct sk_buff_head *skbs); 567 568 void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr); 569 570 bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, 571 const struct iwl_trans_txq_scd_cfg *cfg, 572 unsigned int queue_wdg_timeout); 573 void (*txq_disable)(struct iwl_trans *trans, int queue, 574 bool configure_scd); 575 /* 22000 functions */ 576 int (*txq_alloc)(struct iwl_trans *trans, u32 flags, 577 u32 sta_mask, u8 tid, 578 int size, unsigned int queue_wdg_timeout); 579 void (*txq_free)(struct iwl_trans *trans, int queue); 580 int (*rxq_dma_data)(struct iwl_trans *trans, int queue, 581 struct iwl_trans_rxq_dma_data *data); 582 583 void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id, 584 bool shared); 585 586 int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm); 587 int (*wait_txq_empty)(struct iwl_trans *trans, int queue); 588 void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, 589 bool freeze); 590 void (*block_txq_ptrs)(struct iwl_trans *trans, bool block); 591 592 void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); 593 void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); 594 u32 (*read32)(struct iwl_trans *trans, u32 ofs); 595 u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); 596 void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); 597 int (*read_mem)(struct iwl_trans *trans, u32 addr, 598 void *buf, int dwords); 599 int (*write_mem)(struct iwl_trans *trans, u32 addr, 600 const void *buf, int dwords); 601 int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val); 602 void (*configure)(struct iwl_trans *trans, 603 const struct iwl_trans_config *trans_cfg); 604 void (*set_pmi)(struct iwl_trans *trans, bool state); 605 int (*sw_reset)(struct iwl_trans *trans, bool retake_ownership); 606 bool (*grab_nic_access)(struct iwl_trans *trans); 607 void (*release_nic_access)(struct iwl_trans *trans); 608 void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, 609 u32 value); 610 611 struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, 612 u32 dump_mask, 613 const struct iwl_dump_sanitize_ops *sanitize_ops, 614 void *sanitize_ctx); 615 void (*debugfs_cleanup)(struct iwl_trans *trans); 616 void (*sync_nmi)(struct iwl_trans *trans); 617 int (*set_pnvm)(struct iwl_trans *trans, const void *data, u32 len); 618 int (*set_reduce_power)(struct iwl_trans *trans, 619 const void *data, u32 len); 620 void (*interrupts)(struct iwl_trans *trans, bool enable); 621 int (*imr_dma_data)(struct iwl_trans *trans, 622 u32 dst_addr, u64 src_addr, 623 u32 byte_cnt); 624 625 }; 626 627 /** 628 * enum iwl_trans_state - state of the transport layer 629 * 630 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed 631 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet 632 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response 633 */ 634 enum iwl_trans_state { 635 IWL_TRANS_NO_FW, 636 IWL_TRANS_FW_STARTED, 637 IWL_TRANS_FW_ALIVE, 638 }; 639 640 /** 641 * DOC: Platform power management 642 * 643 * In system-wide power management the entire platform goes into a low 644 * power state (e.g. idle or suspend to RAM) at the same time and the 645 * device is configured as a wakeup source for the entire platform. 646 * This is usually triggered by userspace activity (e.g. the user 647 * presses the suspend button or a power management daemon decides to 648 * put the platform in low power mode). The device's behavior in this 649 * mode is dictated by the wake-on-WLAN configuration. 650 * 651 * The terms used for the device's behavior are as follows: 652 * 653 * - D0: the device is fully powered and the host is awake; 654 * - D3: the device is in low power mode and only reacts to 655 * specific events (e.g. magic-packet received or scan 656 * results found); 657 * 658 * These terms reflect the power modes in the firmware and are not to 659 * be confused with the physical device power state. 660 */ 661 662 /** 663 * enum iwl_plat_pm_mode - platform power management mode 664 * 665 * This enumeration describes the device's platform power management 666 * behavior when in system-wide suspend (i.e WoWLAN). 667 * 668 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 669 * device. In system-wide suspend mode, it means that the all 670 * connections will be closed automatically by mac80211 before 671 * the platform is suspended. 672 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 673 */ 674 enum iwl_plat_pm_mode { 675 IWL_PLAT_PM_MODE_DISABLED, 676 IWL_PLAT_PM_MODE_D3, 677 }; 678 679 /** 680 * enum iwl_ini_cfg_state 681 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 682 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 683 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 684 * are corrupted. The rest of the debug TLVs will still be used 685 */ 686 enum iwl_ini_cfg_state { 687 IWL_INI_CFG_STATE_NOT_LOADED, 688 IWL_INI_CFG_STATE_LOADED, 689 IWL_INI_CFG_STATE_CORRUPTED, 690 }; 691 692 /* Max time to wait for nmi interrupt */ 693 #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 694 695 /** 696 * struct iwl_dram_data 697 * @physical: page phy pointer 698 * @block: pointer to the allocated block/page 699 * @size: size of the block/page 700 */ 701 struct iwl_dram_data { 702 dma_addr_t physical; 703 void *block; 704 int size; 705 }; 706 707 /** 708 * struct iwl_fw_mon - fw monitor per allocation id 709 * @num_frags: number of fragments 710 * @frags: an array of DRAM buffer fragments 711 */ 712 struct iwl_fw_mon { 713 u32 num_frags; 714 struct iwl_dram_data *frags; 715 }; 716 717 /** 718 * struct iwl_self_init_dram - dram data used by self init process 719 * @fw: lmac and umac dram data 720 * @fw_cnt: total number of items in array 721 * @paging: paging dram data 722 * @paging_cnt: total number of items in array 723 */ 724 struct iwl_self_init_dram { 725 struct iwl_dram_data *fw; 726 int fw_cnt; 727 struct iwl_dram_data *paging; 728 int paging_cnt; 729 }; 730 731 /** 732 * struct iwl_imr_data - imr dram data used during debug process 733 * @imr_enable: imr enable status received from fw 734 * @imr_size: imr dram size received from fw 735 * @sram_addr: sram address from debug tlv 736 * @sram_size: sram size from debug tlv 737 * @imr2sram_remainbyte`: size remained after each dma transfer 738 * @imr_curr_addr: current dst address used during dma transfer 739 * @imr_base_addr: imr address received from fw 740 */ 741 struct iwl_imr_data { 742 u32 imr_enable; 743 u32 imr_size; 744 u32 sram_addr; 745 u32 sram_size; 746 u32 imr2sram_remainbyte; 747 u64 imr_curr_addr; 748 __le64 imr_base_addr; 749 }; 750 751 /** 752 * struct iwl_trans_debug - transport debug related data 753 * 754 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 755 * @rec_on: true iff there is a fw debug recording currently active 756 * @dest_tlv: points to the destination TLV for debug 757 * @conf_tlv: array of pointers to configuration TLVs for debug 758 * @trigger_tlv: array of pointers to triggers TLVs for debug 759 * @lmac_error_event_table: addrs of lmacs error tables 760 * @umac_error_event_table: addr of umac error table 761 * @tcm_error_event_table: address(es) of TCM error table(s) 762 * @rcm_error_event_table: address(es) of RCM error table(s) 763 * @error_event_table_tlv_status: bitmap that indicates what error table 764 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 765 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 766 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 767 * @fw_mon_cfg: debug buffer allocation configuration 768 * @fw_mon_ini: DRAM buffer fragments per allocation id 769 * @fw_mon: DRAM buffer for firmware monitor 770 * @hw_error: equals true if hw error interrupt was received from the FW 771 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 772 * @active_regions: active regions 773 * @debug_info_tlv_list: list of debug info TLVs 774 * @time_point: array of debug time points 775 * @periodic_trig_list: periodic triggers list 776 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON 777 * @ucode_preset: preset based on ucode 778 * @dump_file_name_ext: dump file name extension 779 * @dump_file_name_ext_valid: dump file name extension if valid or not 780 */ 781 struct iwl_trans_debug { 782 u8 n_dest_reg; 783 bool rec_on; 784 785 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 786 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX]; 787 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv; 788 789 u32 lmac_error_event_table[2]; 790 u32 umac_error_event_table; 791 u32 tcm_error_event_table[2]; 792 u32 rcm_error_event_table[2]; 793 unsigned int error_event_table_tlv_status; 794 795 enum iwl_ini_cfg_state internal_ini_cfg; 796 enum iwl_ini_cfg_state external_ini_cfg; 797 798 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 799 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 800 801 struct iwl_dram_data fw_mon; 802 803 bool hw_error; 804 enum iwl_fw_ini_buffer_location ini_dest; 805 806 u64 unsupported_region_msk; 807 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 808 struct list_head debug_info_tlv_list; 809 struct iwl_dbg_tlv_time_point_data 810 time_point[IWL_FW_INI_TIME_POINT_NUM]; 811 struct list_head periodic_trig_list; 812 813 u32 domains_bitmap; 814 u32 ucode_preset; 815 bool restart_required; 816 u32 last_tp_resetfw; 817 struct iwl_imr_data imr_data; 818 u8 dump_file_name_ext[IWL_FW_INI_MAX_NAME]; 819 bool dump_file_name_ext_valid; 820 }; 821 822 struct iwl_dma_ptr { 823 dma_addr_t dma; 824 void *addr; 825 size_t size; 826 }; 827 828 struct iwl_cmd_meta { 829 /* only for SYNC commands, iff the reply skb is wanted */ 830 struct iwl_host_cmd *source; 831 u32 flags; 832 u32 tbs; 833 }; 834 835 /* 836 * The FH will write back to the first TB only, so we need to copy some data 837 * into the buffer regardless of whether it should be mapped or not. 838 * This indicates how big the first TB must be to include the scratch buffer 839 * and the assigned PN. 840 * Since PN location is 8 bytes at offset 12, it's 20 now. 841 * If we make it bigger then allocations will be bigger and copy slower, so 842 * that's probably not useful. 843 */ 844 #define IWL_FIRST_TB_SIZE 20 845 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 846 847 struct iwl_pcie_txq_entry { 848 void *cmd; 849 struct sk_buff *skb; 850 /* buffer to free after command completes */ 851 const void *free_buf; 852 struct iwl_cmd_meta meta; 853 }; 854 855 struct iwl_pcie_first_tb_buf { 856 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 857 }; 858 859 /** 860 * struct iwl_txq - Tx Queue for DMA 861 * @q: generic Rx/Tx queue descriptor 862 * @tfds: transmit frame descriptors (DMA memory) 863 * @first_tb_bufs: start of command headers, including scratch buffers, for 864 * the writeback -- this is DMA memory and an array holding one buffer 865 * for each command on the queue 866 * @first_tb_dma: DMA address for the first_tb_bufs start 867 * @entries: transmit entries (driver state) 868 * @lock: queue lock 869 * @stuck_timer: timer that fires if queue gets stuck 870 * @trans: pointer back to transport (for timer) 871 * @need_update: indicates need to update read/write index 872 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 873 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 874 * @frozen: tx stuck queue timer is frozen 875 * @frozen_expiry_remainder: remember how long until the timer fires 876 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 877 * @write_ptr: 1-st empty entry (index) host_w 878 * @read_ptr: last used entry (index) host_r 879 * @dma_addr: physical addr for BD's 880 * @n_window: safe queue window 881 * @id: queue id 882 * @low_mark: low watermark, resume queue if free space more than this 883 * @high_mark: high watermark, stop queue if free space less than this 884 * 885 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 886 * descriptors) and required locking structures. 887 * 888 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 889 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 890 * there might be HW changes in the future). For the normal TX 891 * queues, n_window, which is the size of the software queue data 892 * is also 256; however, for the command queue, n_window is only 893 * 32 since we don't need so many commands pending. Since the HW 894 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 895 * This means that we end up with the following: 896 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 897 * SW entries: | 0 | ... | 31 | 898 * where N is a number between 0 and 7. This means that the SW 899 * data is a window overlayed over the HW queue. 900 */ 901 struct iwl_txq { 902 void *tfds; 903 struct iwl_pcie_first_tb_buf *first_tb_bufs; 904 dma_addr_t first_tb_dma; 905 struct iwl_pcie_txq_entry *entries; 906 /* lock for syncing changes on the queue */ 907 spinlock_t lock; 908 unsigned long frozen_expiry_remainder; 909 struct timer_list stuck_timer; 910 struct iwl_trans *trans; 911 bool need_update; 912 bool frozen; 913 bool ampdu; 914 int block; 915 unsigned long wd_timeout; 916 struct sk_buff_head overflow_q; 917 struct iwl_dma_ptr bc_tbl; 918 919 int write_ptr; 920 int read_ptr; 921 dma_addr_t dma_addr; 922 int n_window; 923 u32 id; 924 int low_mark; 925 int high_mark; 926 927 bool overflow_tx; 928 }; 929 930 /** 931 * struct iwl_trans_txqs - transport tx queues data 932 * 933 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 934 * @page_offs: offset from skb->cb to mac header page pointer 935 * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer 936 * @queue_used - bit mask of used queues 937 * @queue_stopped - bit mask of stopped queues 938 * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler 939 * @queue_alloc_cmd_ver: queue allocation command version 940 */ 941 struct iwl_trans_txqs { 942 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 943 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 944 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 945 struct dma_pool *bc_pool; 946 size_t bc_tbl_size; 947 bool bc_table_dword; 948 u8 page_offs; 949 u8 dev_cmd_offs; 950 struct iwl_tso_hdr_page __percpu *tso_hdr_page; 951 952 struct { 953 u8 fifo; 954 u8 q_id; 955 unsigned int wdg_timeout; 956 } cmd; 957 958 struct { 959 u8 max_tbs; 960 u16 size; 961 u8 addr_size; 962 } tfd; 963 964 struct iwl_dma_ptr scd_bc_tbls; 965 966 u8 queue_alloc_cmd_ver; 967 }; 968 969 /** 970 * struct iwl_trans - transport common data 971 * 972 * @csme_own - true if we couldn't get ownership on the device 973 * @ops - pointer to iwl_trans_ops 974 * @op_mode - pointer to the op_mode 975 * @trans_cfg: the trans-specific configuration part 976 * @cfg - pointer to the configuration 977 * @drv - pointer to iwl_drv 978 * @status: a bit-mask of transport status flags 979 * @dev - pointer to struct device * that represents the device 980 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 981 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 982 * @hw_rf_id a u32 with the device RF ID 983 * @hw_crf_id a u32 with the device CRF ID 984 * @hw_cdb_id a u32 with the device CDB ID 985 * @hw_id: a u32 with the ID of the device / sub-device. 986 * Set during transport allocation. 987 * @hw_id_str: a string with info about HW ID. Set during transport allocation. 988 * @hw_rev_step: The mac step of the HW 989 * @pm_support: set to true in start_hw if link pm is supported 990 * @ltr_enabled: set to true if the LTR is enabled 991 * @wide_cmd_header: true when ucode supports wide command header format 992 * @wait_command_queue: wait queue for sync commands 993 * @num_rx_queues: number of RX queues allocated by the transport; 994 * the transport must set this before calling iwl_drv_start() 995 * @iml_len: the length of the image loader 996 * @iml: a pointer to the image loader itself 997 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 998 * The user should use iwl_trans_{alloc,free}_tx_cmd. 999 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 1000 * starting the firmware, used for tracing 1001 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 1002 * start of the 802.11 header in the @rx_mpdu_cmd 1003 * @dflt_pwr_limit: default power limit fetched from the platform (ACPI) 1004 * @system_pm_mode: the system-wide power management mode in use. 1005 * This mode is set dynamically, depending on the WoWLAN values 1006 * configured from the userspace at runtime. 1007 * @iwl_trans_txqs: transport tx queues data. 1008 * @mbx_addr_0_step: step address data 0 1009 * @mbx_addr_1_step: step address data 1 1010 */ 1011 struct iwl_trans { 1012 bool csme_own; 1013 const struct iwl_trans_ops *ops; 1014 struct iwl_op_mode *op_mode; 1015 const struct iwl_cfg_trans_params *trans_cfg; 1016 const struct iwl_cfg *cfg; 1017 struct iwl_drv *drv; 1018 enum iwl_trans_state state; 1019 unsigned long status; 1020 1021 struct device *dev; 1022 u32 max_skb_frags; 1023 u32 hw_rev; 1024 u32 hw_rev_step; 1025 u32 hw_rf_id; 1026 u32 hw_crf_id; 1027 u32 hw_cdb_id; 1028 u32 hw_id; 1029 char hw_id_str[52]; 1030 u32 sku_id[3]; 1031 1032 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 1033 1034 bool pm_support; 1035 bool ltr_enabled; 1036 u8 pnvm_loaded:1; 1037 u8 reduce_power_loaded:1; 1038 1039 const struct iwl_hcmd_arr *command_groups; 1040 int command_groups_size; 1041 bool wide_cmd_header; 1042 1043 wait_queue_head_t wait_command_queue; 1044 u8 num_rx_queues; 1045 1046 size_t iml_len; 1047 u8 *iml; 1048 1049 /* The following fields are internal only */ 1050 struct kmem_cache *dev_cmd_pool; 1051 char dev_cmd_pool_name[50]; 1052 1053 struct dentry *dbgfs_dir; 1054 1055 #ifdef CONFIG_LOCKDEP 1056 struct lockdep_map sync_cmd_lockdep_map; 1057 #endif 1058 1059 struct iwl_trans_debug dbg; 1060 struct iwl_self_init_dram init_dram; 1061 1062 enum iwl_plat_pm_mode system_pm_mode; 1063 1064 const char *name; 1065 struct iwl_trans_txqs txqs; 1066 u32 mbx_addr_0_step; 1067 u32 mbx_addr_1_step; 1068 1069 /* pointer to trans specific struct */ 1070 /*Ensure that this pointer will always be aligned to sizeof pointer */ 1071 char trans_specific[] __aligned(sizeof(void *)); 1072 }; 1073 1074 const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 1075 int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 1076 1077 static inline void iwl_trans_configure(struct iwl_trans *trans, 1078 const struct iwl_trans_config *trans_cfg) 1079 { 1080 trans->op_mode = trans_cfg->op_mode; 1081 1082 trans->ops->configure(trans, trans_cfg); 1083 WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)); 1084 } 1085 1086 static inline int iwl_trans_start_hw(struct iwl_trans *trans) 1087 { 1088 might_sleep(); 1089 1090 return trans->ops->start_hw(trans); 1091 } 1092 1093 static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) 1094 { 1095 might_sleep(); 1096 1097 if (trans->ops->op_mode_leave) 1098 trans->ops->op_mode_leave(trans); 1099 1100 trans->op_mode = NULL; 1101 1102 trans->state = IWL_TRANS_NO_FW; 1103 } 1104 1105 static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1106 { 1107 might_sleep(); 1108 1109 trans->state = IWL_TRANS_FW_ALIVE; 1110 1111 trans->ops->fw_alive(trans, scd_addr); 1112 } 1113 1114 static inline int iwl_trans_start_fw(struct iwl_trans *trans, 1115 const struct fw_img *fw, 1116 bool run_in_rfkill) 1117 { 1118 int ret; 1119 1120 might_sleep(); 1121 1122 WARN_ON_ONCE(!trans->rx_mpdu_cmd); 1123 1124 clear_bit(STATUS_FW_ERROR, &trans->status); 1125 ret = trans->ops->start_fw(trans, fw, run_in_rfkill); 1126 if (ret == 0) 1127 trans->state = IWL_TRANS_FW_STARTED; 1128 1129 return ret; 1130 } 1131 1132 static inline void iwl_trans_stop_device(struct iwl_trans *trans) 1133 { 1134 might_sleep(); 1135 1136 trans->ops->stop_device(trans); 1137 1138 trans->state = IWL_TRANS_NO_FW; 1139 } 1140 1141 static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, 1142 bool reset) 1143 { 1144 might_sleep(); 1145 if (!trans->ops->d3_suspend) 1146 return 0; 1147 1148 return trans->ops->d3_suspend(trans, test, reset); 1149 } 1150 1151 static inline int iwl_trans_d3_resume(struct iwl_trans *trans, 1152 enum iwl_d3_status *status, 1153 bool test, bool reset) 1154 { 1155 might_sleep(); 1156 if (!trans->ops->d3_resume) 1157 return 0; 1158 1159 return trans->ops->d3_resume(trans, status, test, reset); 1160 } 1161 1162 static inline struct iwl_trans_dump_data * 1163 iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask, 1164 const struct iwl_dump_sanitize_ops *sanitize_ops, 1165 void *sanitize_ctx) 1166 { 1167 if (!trans->ops->dump_data) 1168 return NULL; 1169 return trans->ops->dump_data(trans, dump_mask, 1170 sanitize_ops, sanitize_ctx); 1171 } 1172 1173 static inline struct iwl_device_tx_cmd * 1174 iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 1175 { 1176 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC); 1177 } 1178 1179 int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 1180 1181 static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 1182 struct iwl_device_tx_cmd *dev_cmd) 1183 { 1184 kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 1185 } 1186 1187 static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 1188 struct iwl_device_tx_cmd *dev_cmd, int queue) 1189 { 1190 if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) 1191 return -EIO; 1192 1193 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1194 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1195 return -EIO; 1196 } 1197 1198 return trans->ops->tx(trans, skb, dev_cmd, queue); 1199 } 1200 1201 static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, 1202 int ssn, struct sk_buff_head *skbs) 1203 { 1204 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1205 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1206 return; 1207 } 1208 1209 trans->ops->reclaim(trans, queue, ssn, skbs); 1210 } 1211 1212 static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, 1213 int ptr) 1214 { 1215 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1216 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1217 return; 1218 } 1219 1220 trans->ops->set_q_ptrs(trans, queue, ptr); 1221 } 1222 1223 static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 1224 bool configure_scd) 1225 { 1226 trans->ops->txq_disable(trans, queue, configure_scd); 1227 } 1228 1229 static inline bool 1230 iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 1231 const struct iwl_trans_txq_scd_cfg *cfg, 1232 unsigned int queue_wdg_timeout) 1233 { 1234 might_sleep(); 1235 1236 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1237 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1238 return false; 1239 } 1240 1241 return trans->ops->txq_enable(trans, queue, ssn, 1242 cfg, queue_wdg_timeout); 1243 } 1244 1245 static inline int 1246 iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 1247 struct iwl_trans_rxq_dma_data *data) 1248 { 1249 if (WARN_ON_ONCE(!trans->ops->rxq_dma_data)) 1250 return -ENOTSUPP; 1251 1252 return trans->ops->rxq_dma_data(trans, queue, data); 1253 } 1254 1255 static inline void 1256 iwl_trans_txq_free(struct iwl_trans *trans, int queue) 1257 { 1258 if (WARN_ON_ONCE(!trans->ops->txq_free)) 1259 return; 1260 1261 trans->ops->txq_free(trans, queue); 1262 } 1263 1264 static inline int 1265 iwl_trans_txq_alloc(struct iwl_trans *trans, 1266 u32 flags, u32 sta_mask, u8 tid, 1267 int size, unsigned int wdg_timeout) 1268 { 1269 might_sleep(); 1270 1271 if (WARN_ON_ONCE(!trans->ops->txq_alloc)) 1272 return -ENOTSUPP; 1273 1274 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1275 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1276 return -EIO; 1277 } 1278 1279 return trans->ops->txq_alloc(trans, flags, sta_mask, tid, 1280 size, wdg_timeout); 1281 } 1282 1283 static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 1284 int queue, bool shared_mode) 1285 { 1286 if (trans->ops->txq_set_shared_mode) 1287 trans->ops->txq_set_shared_mode(trans, queue, shared_mode); 1288 } 1289 1290 static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1291 int fifo, int sta_id, int tid, 1292 int frame_limit, u16 ssn, 1293 unsigned int queue_wdg_timeout) 1294 { 1295 struct iwl_trans_txq_scd_cfg cfg = { 1296 .fifo = fifo, 1297 .sta_id = sta_id, 1298 .tid = tid, 1299 .frame_limit = frame_limit, 1300 .aggregate = sta_id >= 0, 1301 }; 1302 1303 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1304 } 1305 1306 static inline 1307 void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1308 unsigned int queue_wdg_timeout) 1309 { 1310 struct iwl_trans_txq_scd_cfg cfg = { 1311 .fifo = fifo, 1312 .sta_id = -1, 1313 .tid = IWL_MAX_TID_COUNT, 1314 .frame_limit = IWL_FRAME_LIMIT, 1315 .aggregate = false, 1316 }; 1317 1318 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1319 } 1320 1321 static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1322 unsigned long txqs, 1323 bool freeze) 1324 { 1325 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1326 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1327 return; 1328 } 1329 1330 if (trans->ops->freeze_txq_timer) 1331 trans->ops->freeze_txq_timer(trans, txqs, freeze); 1332 } 1333 1334 static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans, 1335 bool block) 1336 { 1337 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1338 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1339 return; 1340 } 1341 1342 if (trans->ops->block_txq_ptrs) 1343 trans->ops->block_txq_ptrs(trans, block); 1344 } 1345 1346 static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, 1347 u32 txqs) 1348 { 1349 if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty)) 1350 return -ENOTSUPP; 1351 1352 /* No need to wait if the firmware is not alive */ 1353 if (trans->state != IWL_TRANS_FW_ALIVE) { 1354 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1355 return -EIO; 1356 } 1357 1358 return trans->ops->wait_tx_queues_empty(trans, txqs); 1359 } 1360 1361 static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue) 1362 { 1363 if (WARN_ON_ONCE(!trans->ops->wait_txq_empty)) 1364 return -ENOTSUPP; 1365 1366 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1367 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1368 return -EIO; 1369 } 1370 1371 return trans->ops->wait_txq_empty(trans, queue); 1372 } 1373 1374 static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1375 { 1376 trans->ops->write8(trans, ofs, val); 1377 } 1378 1379 static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1380 { 1381 trans->ops->write32(trans, ofs, val); 1382 } 1383 1384 static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) 1385 { 1386 return trans->ops->read32(trans, ofs); 1387 } 1388 1389 static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) 1390 { 1391 return trans->ops->read_prph(trans, ofs); 1392 } 1393 1394 static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, 1395 u32 val) 1396 { 1397 return trans->ops->write_prph(trans, ofs, val); 1398 } 1399 1400 static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1401 void *buf, int dwords) 1402 { 1403 return trans->ops->read_mem(trans, addr, buf, dwords); 1404 } 1405 1406 #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1407 do { \ 1408 if (__builtin_constant_p(bufsize)) \ 1409 BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1410 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1411 } while (0) 1412 1413 static inline int iwl_trans_write_imr_mem(struct iwl_trans *trans, 1414 u32 dst_addr, u64 src_addr, 1415 u32 byte_cnt) 1416 { 1417 if (trans->ops->imr_dma_data) 1418 return trans->ops->imr_dma_data(trans, dst_addr, src_addr, byte_cnt); 1419 return 0; 1420 } 1421 1422 static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1423 { 1424 u32 value; 1425 1426 if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) 1427 return 0xa5a5a5a5; 1428 1429 return value; 1430 } 1431 1432 static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1433 const void *buf, int dwords) 1434 { 1435 return trans->ops->write_mem(trans, addr, buf, dwords); 1436 } 1437 1438 static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1439 u32 val) 1440 { 1441 return iwl_trans_write_mem(trans, addr, &val, 1); 1442 } 1443 1444 static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) 1445 { 1446 if (trans->ops->set_pmi) 1447 trans->ops->set_pmi(trans, state); 1448 } 1449 1450 static inline int iwl_trans_sw_reset(struct iwl_trans *trans, 1451 bool retake_ownership) 1452 { 1453 if (trans->ops->sw_reset) 1454 return trans->ops->sw_reset(trans, retake_ownership); 1455 return 0; 1456 } 1457 1458 static inline void 1459 iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) 1460 { 1461 trans->ops->set_bits_mask(trans, reg, mask, value); 1462 } 1463 1464 #define iwl_trans_grab_nic_access(trans) \ 1465 __cond_lock(nic_access, \ 1466 likely((trans)->ops->grab_nic_access(trans))) 1467 1468 static inline void __releases(nic_access) 1469 iwl_trans_release_nic_access(struct iwl_trans *trans) 1470 { 1471 trans->ops->release_nic_access(trans); 1472 __release(nic_access); 1473 } 1474 1475 static inline void iwl_trans_fw_error(struct iwl_trans *trans, bool sync) 1476 { 1477 if (WARN_ON_ONCE(!trans->op_mode)) 1478 return; 1479 1480 /* prevent double restarts due to the same erroneous FW */ 1481 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) { 1482 iwl_op_mode_nic_error(trans->op_mode, sync); 1483 trans->state = IWL_TRANS_NO_FW; 1484 } 1485 } 1486 1487 static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1488 { 1489 return trans->state == IWL_TRANS_FW_ALIVE; 1490 } 1491 1492 static inline void iwl_trans_sync_nmi(struct iwl_trans *trans) 1493 { 1494 if (trans->ops->sync_nmi) 1495 trans->ops->sync_nmi(trans); 1496 } 1497 1498 void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr, 1499 u32 sw_err_bit); 1500 1501 static inline int iwl_trans_set_pnvm(struct iwl_trans *trans, 1502 const void *data, u32 len) 1503 { 1504 if (trans->ops->set_pnvm) { 1505 int ret = trans->ops->set_pnvm(trans, data, len); 1506 1507 if (ret) 1508 return ret; 1509 } 1510 1511 trans->pnvm_loaded = true; 1512 1513 return 0; 1514 } 1515 1516 static inline int iwl_trans_set_reduce_power(struct iwl_trans *trans, 1517 const void *data, u32 len) 1518 { 1519 if (trans->ops->set_reduce_power) { 1520 int ret = trans->ops->set_reduce_power(trans, data, len); 1521 1522 if (ret) 1523 return ret; 1524 } 1525 1526 trans->reduce_power_loaded = true; 1527 return 0; 1528 } 1529 1530 static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1531 { 1532 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1533 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1534 } 1535 1536 static inline void iwl_trans_interrupts(struct iwl_trans *trans, bool enable) 1537 { 1538 if (trans->ops->interrupts) 1539 trans->ops->interrupts(trans, enable); 1540 } 1541 1542 /***************************************************** 1543 * transport helper functions 1544 *****************************************************/ 1545 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1546 struct device *dev, 1547 const struct iwl_trans_ops *ops, 1548 const struct iwl_cfg_trans_params *cfg_trans); 1549 int iwl_trans_init(struct iwl_trans *trans); 1550 void iwl_trans_free(struct iwl_trans *trans); 1551 1552 /***************************************************** 1553 * driver (transport) register/unregister functions 1554 ******************************************************/ 1555 int __must_check iwl_pci_register_driver(void); 1556 void iwl_pci_unregister_driver(void); 1557 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan); 1558 1559 #endif /* __iwl_trans_h__ */ 1560