1e705c121SKalle Valo /******************************************************************************
2e705c121SKalle Valo  *
3e705c121SKalle Valo  * This file is provided under a dual BSD/GPLv2 license.  When using or
4e705c121SKalle Valo  * redistributing this file, you may do so under either license.
5e705c121SKalle Valo  *
6e705c121SKalle Valo  * GPL LICENSE SUMMARY
7e705c121SKalle Valo  *
8e705c121SKalle Valo  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9e705c121SKalle Valo  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
106b35ff91SSara Sharon  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11700b3799SShahar S Matityahu  * Copyright(c) 2018 - 2019 Intel Corporation
12e705c121SKalle Valo  *
13e705c121SKalle Valo  * This program is free software; you can redistribute it and/or modify
14e705c121SKalle Valo  * it under the terms of version 2 of the GNU General Public License as
15e705c121SKalle Valo  * published by the Free Software Foundation.
16e705c121SKalle Valo  *
17e705c121SKalle Valo  * This program is distributed in the hope that it will be useful, but
18e705c121SKalle Valo  * WITHOUT ANY WARRANTY; without even the implied warranty of
19e705c121SKalle Valo  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
20e705c121SKalle Valo  * General Public License for more details.
21e705c121SKalle Valo  *
22e705c121SKalle Valo  * The full GNU General Public License is included in this distribution
23e705c121SKalle Valo  * in the file called COPYING.
24e705c121SKalle Valo  *
25e705c121SKalle Valo  * Contact Information:
26cb2f8277SEmmanuel Grumbach  *  Intel Linux Wireless <linuxwifi@intel.com>
27e705c121SKalle Valo  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28e705c121SKalle Valo  *
29e705c121SKalle Valo  * BSD LICENSE
30e705c121SKalle Valo  *
31e705c121SKalle Valo  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32e705c121SKalle Valo  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
336b35ff91SSara Sharon  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34700b3799SShahar S Matityahu  * Copyright(c) 2018 - 2019 Intel Corporation
35e705c121SKalle Valo  * All rights reserved.
36e705c121SKalle Valo  *
37e705c121SKalle Valo  * Redistribution and use in source and binary forms, with or without
38e705c121SKalle Valo  * modification, are permitted provided that the following conditions
39e705c121SKalle Valo  * are met:
40e705c121SKalle Valo  *
41e705c121SKalle Valo  *  * Redistributions of source code must retain the above copyright
42e705c121SKalle Valo  *    notice, this list of conditions and the following disclaimer.
43e705c121SKalle Valo  *  * Redistributions in binary form must reproduce the above copyright
44e705c121SKalle Valo  *    notice, this list of conditions and the following disclaimer in
45e705c121SKalle Valo  *    the documentation and/or other materials provided with the
46e705c121SKalle Valo  *    distribution.
47e705c121SKalle Valo  *  * Neither the name Intel Corporation nor the names of its
48e705c121SKalle Valo  *    contributors may be used to endorse or promote products derived
49e705c121SKalle Valo  *    from this software without specific prior written permission.
50e705c121SKalle Valo  *
51e705c121SKalle Valo  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52e705c121SKalle Valo  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53e705c121SKalle Valo  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54e705c121SKalle Valo  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55e705c121SKalle Valo  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56e705c121SKalle Valo  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57e705c121SKalle Valo  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58e705c121SKalle Valo  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59e705c121SKalle Valo  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60e705c121SKalle Valo  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61e705c121SKalle Valo  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62e705c121SKalle Valo  *
63e705c121SKalle Valo  *****************************************************************************/
64e705c121SKalle Valo #ifndef __iwl_trans_h__
65e705c121SKalle Valo #define __iwl_trans_h__
66e705c121SKalle Valo 
67e705c121SKalle Valo #include <linux/ieee80211.h>
68e705c121SKalle Valo #include <linux/mm.h> /* for page_address */
69e705c121SKalle Valo #include <linux/lockdep.h>
7039bdb17eSSharon Dvir #include <linux/kernel.h>
71e705c121SKalle Valo 
72e705c121SKalle Valo #include "iwl-debug.h"
73e705c121SKalle Valo #include "iwl-config.h"
74d962f9b1SJohannes Berg #include "fw/img.h"
75e705c121SKalle Valo #include "iwl-op-mode.h"
76d172a5efSJohannes Berg #include "fw/api/cmdhdr.h"
77d172a5efSJohannes Berg #include "fw/api/txq.h"
78f14cda6fSSara Sharon #include "fw/api/dbg-tlv.h"
79f14cda6fSSara Sharon #include "iwl-dbg-tlv.h"
80e705c121SKalle Valo 
81e705c121SKalle Valo /**
82e705c121SKalle Valo  * DOC: Transport layer - what is it ?
83e705c121SKalle Valo  *
84e705c121SKalle Valo  * The transport layer is the layer that deals with the HW directly. It provides
85e705c121SKalle Valo  * an abstraction of the underlying HW to the upper layer. The transport layer
86e705c121SKalle Valo  * doesn't provide any policy, algorithm or anything of this kind, but only
87e705c121SKalle Valo  * mechanisms to make the HW do something. It is not completely stateless but
88e705c121SKalle Valo  * close to it.
89e705c121SKalle Valo  * We will have an implementation for each different supported bus.
90e705c121SKalle Valo  */
91e705c121SKalle Valo 
92e705c121SKalle Valo /**
93e705c121SKalle Valo  * DOC: Life cycle of the transport layer
94e705c121SKalle Valo  *
95e705c121SKalle Valo  * The transport layer has a very precise life cycle.
96e705c121SKalle Valo  *
97e705c121SKalle Valo  *	1) A helper function is called during the module initialization and
98e705c121SKalle Valo  *	   registers the bus driver's ops with the transport's alloc function.
99e705c121SKalle Valo  *	2) Bus's probe calls to the transport layer's allocation functions.
100e705c121SKalle Valo  *	   Of course this function is bus specific.
101e705c121SKalle Valo  *	3) This allocation functions will spawn the upper layer which will
102e705c121SKalle Valo  *	   register mac80211.
103e705c121SKalle Valo  *
104e705c121SKalle Valo  *	4) At some point (i.e. mac80211's start call), the op_mode will call
105e705c121SKalle Valo  *	   the following sequence:
106e705c121SKalle Valo  *	   start_hw
107e705c121SKalle Valo  *	   start_fw
108e705c121SKalle Valo  *
109e705c121SKalle Valo  *	5) Then when finished (or reset):
110e705c121SKalle Valo  *	   stop_device
111e705c121SKalle Valo  *
112e705c121SKalle Valo  *	6) Eventually, the free function will be called.
113e705c121SKalle Valo  */
114e705c121SKalle Valo 
115e705c121SKalle Valo #define FH_RSCSR_FRAME_SIZE_MSK		0x00003FFF	/* bits 0-13 */
116e705c121SKalle Valo #define FH_RSCSR_FRAME_INVALID		0x55550000
117e705c121SKalle Valo #define FH_RSCSR_FRAME_ALIGN		0x40
118fbe41127SSara Sharon #define FH_RSCSR_RPA_EN			BIT(25)
1199d0fc5a5SDavid Spinadel #define FH_RSCSR_RADA_EN		BIT(26)
120ab2e696bSSara Sharon #define FH_RSCSR_RXQ_POS		16
121ab2e696bSSara Sharon #define FH_RSCSR_RXQ_MASK		0x3F0000
122e705c121SKalle Valo 
123e705c121SKalle Valo struct iwl_rx_packet {
124e705c121SKalle Valo 	/*
125e705c121SKalle Valo 	 * The first 4 bytes of the RX frame header contain both the RX frame
126e705c121SKalle Valo 	 * size and some flags.
127e705c121SKalle Valo 	 * Bit fields:
128e705c121SKalle Valo 	 * 31:    flag flush RB request
129e705c121SKalle Valo 	 * 30:    flag ignore TC (terminal counter) request
130e705c121SKalle Valo 	 * 29:    flag fast IRQ request
1319d0fc5a5SDavid Spinadel 	 * 28-27: Reserved
1329d0fc5a5SDavid Spinadel 	 * 26:    RADA enabled
133fbe41127SSara Sharon 	 * 25:    Offload enabled
134ab2e696bSSara Sharon 	 * 24:    RPF enabled
135ab2e696bSSara Sharon 	 * 23:    RSS enabled
136ab2e696bSSara Sharon 	 * 22:    Checksum enabled
137ab2e696bSSara Sharon 	 * 21-16: RX queue
138ab2e696bSSara Sharon 	 * 15-14: Reserved
139e705c121SKalle Valo 	 * 13-00: RX frame size
140e705c121SKalle Valo 	 */
141e705c121SKalle Valo 	__le32 len_n_flags;
142e705c121SKalle Valo 	struct iwl_cmd_header hdr;
143e705c121SKalle Valo 	u8 data[];
144e705c121SKalle Valo } __packed;
145e705c121SKalle Valo 
146e705c121SKalle Valo static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)
147e705c121SKalle Valo {
148e705c121SKalle Valo 	return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
149e705c121SKalle Valo }
150e705c121SKalle Valo 
151e705c121SKalle Valo static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)
152e705c121SKalle Valo {
153e705c121SKalle Valo 	return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);
154e705c121SKalle Valo }
155e705c121SKalle Valo 
156e705c121SKalle Valo /**
157e705c121SKalle Valo  * enum CMD_MODE - how to send the host commands ?
158e705c121SKalle Valo  *
159e705c121SKalle Valo  * @CMD_ASYNC: Return right away and don't wait for the response
160e705c121SKalle Valo  * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of
161e705c121SKalle Valo  *	the response. The caller needs to call iwl_free_resp when done.
162dcbb4746SEmmanuel Grumbach  * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be
163dcbb4746SEmmanuel Grumbach  *	called after this command completes. Valid only with CMD_ASYNC.
164e705c121SKalle Valo  */
165e705c121SKalle Valo enum CMD_MODE {
166e705c121SKalle Valo 	CMD_ASYNC		= BIT(0),
167e705c121SKalle Valo 	CMD_WANT_SKB		= BIT(1),
168e705c121SKalle Valo 	CMD_SEND_IN_RFKILL	= BIT(2),
169043fa901SEmmanuel Grumbach 	CMD_WANT_ASYNC_CALLBACK	= BIT(3),
170e705c121SKalle Valo };
171e705c121SKalle Valo 
172e705c121SKalle Valo #define DEF_CMD_PAYLOAD_SIZE 320
173e705c121SKalle Valo 
174e705c121SKalle Valo /**
175e705c121SKalle Valo  * struct iwl_device_cmd
176e705c121SKalle Valo  *
177e705c121SKalle Valo  * For allocation of the command and tx queues, this establishes the overall
178e705c121SKalle Valo  * size of the largest command we send to uCode, except for commands that
179e705c121SKalle Valo  * aren't fully copied and use other TFD space.
180e705c121SKalle Valo  */
181e705c121SKalle Valo struct iwl_device_cmd {
182e705c121SKalle Valo 	union {
183e705c121SKalle Valo 		struct {
184e705c121SKalle Valo 			struct iwl_cmd_header hdr;	/* uCode API */
185e705c121SKalle Valo 			u8 payload[DEF_CMD_PAYLOAD_SIZE];
186e705c121SKalle Valo 		};
187e705c121SKalle Valo 		struct {
188e705c121SKalle Valo 			struct iwl_cmd_header_wide hdr_wide;
189e705c121SKalle Valo 			u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -
190e705c121SKalle Valo 					sizeof(struct iwl_cmd_header_wide) +
191e705c121SKalle Valo 					sizeof(struct iwl_cmd_header)];
192e705c121SKalle Valo 		};
193e705c121SKalle Valo 	};
194e705c121SKalle Valo } __packed;
195e705c121SKalle Valo 
196e705c121SKalle Valo #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
197e705c121SKalle Valo 
198e705c121SKalle Valo /*
199e705c121SKalle Valo  * number of transfer buffers (fragments) per transmit frame descriptor;
200e705c121SKalle Valo  * this is just the driver's idea, the hardware supports 20
201e705c121SKalle Valo  */
202e705c121SKalle Valo #define IWL_MAX_CMD_TBS_PER_TFD	2
203e705c121SKalle Valo 
204e705c121SKalle Valo /**
205b8aed81cSJohannes Berg  * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command
206e705c121SKalle Valo  *
207e705c121SKalle Valo  * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's
208e705c121SKalle Valo  *	ring. The transport layer doesn't map the command's buffer to DMA, but
209e705c121SKalle Valo  *	rather copies it to a previously allocated DMA buffer. This flag tells
210e705c121SKalle Valo  *	the transport layer not to copy the command, but to map the existing
211e705c121SKalle Valo  *	buffer (that is passed in) instead. This saves the memcpy and allows
212e705c121SKalle Valo  *	commands that are bigger than the fixed buffer to be submitted.
213e705c121SKalle Valo  *	Note that a TFD entry after a NOCOPY one cannot be a normal copied one.
214e705c121SKalle Valo  * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this
215e705c121SKalle Valo  *	chunk internally and free it again after the command completes. This
216e705c121SKalle Valo  *	can (currently) be used only once per command.
217e705c121SKalle Valo  *	Note that a TFD entry after a DUP one cannot be a normal copied one.
218e705c121SKalle Valo  */
219e705c121SKalle Valo enum iwl_hcmd_dataflag {
220e705c121SKalle Valo 	IWL_HCMD_DFL_NOCOPY	= BIT(0),
221e705c121SKalle Valo 	IWL_HCMD_DFL_DUP	= BIT(1),
222e705c121SKalle Valo };
223e705c121SKalle Valo 
22422463857SShahar S Matityahu enum iwl_error_event_table_status {
22522463857SShahar S Matityahu 	IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0),
22622463857SShahar S Matityahu 	IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1),
22722463857SShahar S Matityahu 	IWL_ERROR_EVENT_TABLE_UMAC = BIT(2),
22822463857SShahar S Matityahu };
22922463857SShahar S Matityahu 
230e705c121SKalle Valo /**
231e705c121SKalle Valo  * struct iwl_host_cmd - Host command to the uCode
232e705c121SKalle Valo  *
233e705c121SKalle Valo  * @data: array of chunks that composes the data of the host command
234e705c121SKalle Valo  * @resp_pkt: response packet, if %CMD_WANT_SKB was set
235e705c121SKalle Valo  * @_rx_page_order: (internally used to free response packet)
236e705c121SKalle Valo  * @_rx_page_addr: (internally used to free response packet)
237e705c121SKalle Valo  * @flags: can be CMD_*
238e705c121SKalle Valo  * @len: array of the lengths of the chunks in data
239e705c121SKalle Valo  * @dataflags: IWL_HCMD_DFL_*
240e705c121SKalle Valo  * @id: command id of the host command, for wide commands encoding the
241e705c121SKalle Valo  *	version and group as well
242e705c121SKalle Valo  */
243e705c121SKalle Valo struct iwl_host_cmd {
244e705c121SKalle Valo 	const void *data[IWL_MAX_CMD_TBS_PER_TFD];
245e705c121SKalle Valo 	struct iwl_rx_packet *resp_pkt;
246e705c121SKalle Valo 	unsigned long _rx_page_addr;
247e705c121SKalle Valo 	u32 _rx_page_order;
248e705c121SKalle Valo 
249e705c121SKalle Valo 	u32 flags;
250e705c121SKalle Valo 	u32 id;
251e705c121SKalle Valo 	u16 len[IWL_MAX_CMD_TBS_PER_TFD];
252e705c121SKalle Valo 	u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];
253e705c121SKalle Valo };
254e705c121SKalle Valo 
255e705c121SKalle Valo static inline void iwl_free_resp(struct iwl_host_cmd *cmd)
256e705c121SKalle Valo {
257e705c121SKalle Valo 	free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);
258e705c121SKalle Valo }
259e705c121SKalle Valo 
260e705c121SKalle Valo struct iwl_rx_cmd_buffer {
261e705c121SKalle Valo 	struct page *_page;
262e705c121SKalle Valo 	int _offset;
263e705c121SKalle Valo 	bool _page_stolen;
264e705c121SKalle Valo 	u32 _rx_page_order;
265e705c121SKalle Valo 	unsigned int truesize;
266e705c121SKalle Valo };
267e705c121SKalle Valo 
268e705c121SKalle Valo static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)
269e705c121SKalle Valo {
270e705c121SKalle Valo 	return (void *)((unsigned long)page_address(r->_page) + r->_offset);
271e705c121SKalle Valo }
272e705c121SKalle Valo 
273e705c121SKalle Valo static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)
274e705c121SKalle Valo {
275e705c121SKalle Valo 	return r->_offset;
276e705c121SKalle Valo }
277e705c121SKalle Valo 
278e705c121SKalle Valo static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
279e705c121SKalle Valo {
280e705c121SKalle Valo 	r->_page_stolen = true;
281e705c121SKalle Valo 	get_page(r->_page);
282e705c121SKalle Valo 	return r->_page;
283e705c121SKalle Valo }
284e705c121SKalle Valo 
285e705c121SKalle Valo static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)
286e705c121SKalle Valo {
287e705c121SKalle Valo 	__free_pages(r->_page, r->_rx_page_order);
288e705c121SKalle Valo }
289e705c121SKalle Valo 
290e705c121SKalle Valo #define MAX_NO_RECLAIM_CMDS	6
291e705c121SKalle Valo 
292e705c121SKalle Valo #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
293e705c121SKalle Valo 
294e705c121SKalle Valo /*
295e705c121SKalle Valo  * Maximum number of HW queues the transport layer
296e705c121SKalle Valo  * currently supports
297e705c121SKalle Valo  */
298e705c121SKalle Valo #define IWL_MAX_HW_QUEUES		32
299e982bc2cSSara Sharon #define IWL_MAX_TVQM_QUEUES		512
300e982bc2cSSara Sharon 
301e705c121SKalle Valo #define IWL_MAX_TID_COUNT	8
302c65f4e03SSara Sharon #define IWL_MGMT_TID		15
303e705c121SKalle Valo #define IWL_FRAME_LIMIT	64
304e705c121SKalle Valo #define IWL_MAX_RX_HW_QUEUES	16
305e705c121SKalle Valo 
306e705c121SKalle Valo /**
307e705c121SKalle Valo  * enum iwl_wowlan_status - WoWLAN image/device status
308e705c121SKalle Valo  * @IWL_D3_STATUS_ALIVE: firmware is still running after resume
309e705c121SKalle Valo  * @IWL_D3_STATUS_RESET: device was reset while suspended
310e705c121SKalle Valo  */
311e705c121SKalle Valo enum iwl_d3_status {
312e705c121SKalle Valo 	IWL_D3_STATUS_ALIVE,
313e705c121SKalle Valo 	IWL_D3_STATUS_RESET,
314e705c121SKalle Valo };
315e705c121SKalle Valo 
316e705c121SKalle Valo /**
317e705c121SKalle Valo  * enum iwl_trans_status: transport status flags
318e705c121SKalle Valo  * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed
319e705c121SKalle Valo  * @STATUS_DEVICE_ENABLED: APM is enabled
320e705c121SKalle Valo  * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
321e705c121SKalle Valo  * @STATUS_INT_ENABLED: interrupts are enabled
322326477e4SJohannes Berg  * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch
323326477e4SJohannes Berg  * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode
324e705c121SKalle Valo  * @STATUS_FW_ERROR: the fw is in error state
325e705c121SKalle Valo  * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands
326e705c121SKalle Valo  *	are sent
327e705c121SKalle Valo  * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent
328e705c121SKalle Valo  * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation
329e705c121SKalle Valo  */
330e705c121SKalle Valo enum iwl_trans_status {
331e705c121SKalle Valo 	STATUS_SYNC_HCMD_ACTIVE,
332e705c121SKalle Valo 	STATUS_DEVICE_ENABLED,
333e705c121SKalle Valo 	STATUS_TPOWER_PMI,
334e705c121SKalle Valo 	STATUS_INT_ENABLED,
335326477e4SJohannes Berg 	STATUS_RFKILL_HW,
336326477e4SJohannes Berg 	STATUS_RFKILL_OPMODE,
337e705c121SKalle Valo 	STATUS_FW_ERROR,
338e705c121SKalle Valo 	STATUS_TRANS_GOING_IDLE,
339e705c121SKalle Valo 	STATUS_TRANS_IDLE,
340e705c121SKalle Valo 	STATUS_TRANS_DEAD,
341e705c121SKalle Valo };
342e705c121SKalle Valo 
3436c4fbcbcSEmmanuel Grumbach static inline int
3446c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)
3456c4fbcbcSEmmanuel Grumbach {
3466c4fbcbcSEmmanuel Grumbach 	switch (rb_size) {
3471a4968d1SGolan Ben Ami 	case IWL_AMSDU_2K:
3481a4968d1SGolan Ben Ami 		return get_order(2 * 1024);
3496c4fbcbcSEmmanuel Grumbach 	case IWL_AMSDU_4K:
3506c4fbcbcSEmmanuel Grumbach 		return get_order(4 * 1024);
3516c4fbcbcSEmmanuel Grumbach 	case IWL_AMSDU_8K:
3526c4fbcbcSEmmanuel Grumbach 		return get_order(8 * 1024);
3536c4fbcbcSEmmanuel Grumbach 	case IWL_AMSDU_12K:
3546c4fbcbcSEmmanuel Grumbach 		return get_order(12 * 1024);
3556c4fbcbcSEmmanuel Grumbach 	default:
3566c4fbcbcSEmmanuel Grumbach 		WARN_ON(1);
3576c4fbcbcSEmmanuel Grumbach 		return -1;
3586c4fbcbcSEmmanuel Grumbach 	}
3596c4fbcbcSEmmanuel Grumbach }
3606c4fbcbcSEmmanuel Grumbach 
36139bdb17eSSharon Dvir struct iwl_hcmd_names {
36239bdb17eSSharon Dvir 	u8 cmd_id;
36339bdb17eSSharon Dvir 	const char *const cmd_name;
36439bdb17eSSharon Dvir };
36539bdb17eSSharon Dvir 
36639bdb17eSSharon Dvir #define HCMD_NAME(x)	\
36739bdb17eSSharon Dvir 	{ .cmd_id = x, .cmd_name = #x }
36839bdb17eSSharon Dvir 
36939bdb17eSSharon Dvir struct iwl_hcmd_arr {
37039bdb17eSSharon Dvir 	const struct iwl_hcmd_names *arr;
37139bdb17eSSharon Dvir 	int size;
37239bdb17eSSharon Dvir };
37339bdb17eSSharon Dvir 
37439bdb17eSSharon Dvir #define HCMD_ARR(x)	\
37539bdb17eSSharon Dvir 	{ .arr = x, .size = ARRAY_SIZE(x) }
37639bdb17eSSharon Dvir 
377e705c121SKalle Valo /**
378e705c121SKalle Valo  * struct iwl_trans_config - transport configuration
379e705c121SKalle Valo  *
380e705c121SKalle Valo  * @op_mode: pointer to the upper layer.
381e705c121SKalle Valo  * @cmd_queue: the index of the command queue.
382e705c121SKalle Valo  *	Must be set before start_fw.
383e705c121SKalle Valo  * @cmd_fifo: the fifo for host commands
384e705c121SKalle Valo  * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue.
385e705c121SKalle Valo  * @no_reclaim_cmds: Some devices erroneously don't set the
386e705c121SKalle Valo  *	SEQ_RX_FRAME bit on some notifications, this is the
387e705c121SKalle Valo  *	list of such notifications to filter. Max length is
388e705c121SKalle Valo  *	%MAX_NO_RECLAIM_CMDS.
389e705c121SKalle Valo  * @n_no_reclaim_cmds: # of commands in list
3906c4fbcbcSEmmanuel Grumbach  * @rx_buf_size: RX buffer size needed for A-MSDUs
391e705c121SKalle Valo  *	if unset 4k will be the RX buffer size
392e705c121SKalle Valo  * @bc_table_dword: set to true if the BC table expects the byte count to be
393e705c121SKalle Valo  *	in DWORD (as opposed to bytes)
394e705c121SKalle Valo  * @scd_set_active: should the transport configure the SCD for HCMD queue
39541837ca9SEmmanuel Grumbach  * @sw_csum_tx: transport should compute the TCP checksum
39639bdb17eSSharon Dvir  * @command_groups: array of command groups, each member is an array of the
39739bdb17eSSharon Dvir  *	commands in the group; for debugging only
39839bdb17eSSharon Dvir  * @command_groups_size: number of command groups, to avoid illegal access
39921cb3222SJohannes Berg  * @cb_data_offs: offset inside skb->cb to store transport data at, must have
40021cb3222SJohannes Berg  *	space for at least two pointers
401e705c121SKalle Valo  */
402e705c121SKalle Valo struct iwl_trans_config {
403e705c121SKalle Valo 	struct iwl_op_mode *op_mode;
404e705c121SKalle Valo 
405e705c121SKalle Valo 	u8 cmd_queue;
406e705c121SKalle Valo 	u8 cmd_fifo;
407e705c121SKalle Valo 	unsigned int cmd_q_wdg_timeout;
408e705c121SKalle Valo 	const u8 *no_reclaim_cmds;
409e705c121SKalle Valo 	unsigned int n_no_reclaim_cmds;
410e705c121SKalle Valo 
4116c4fbcbcSEmmanuel Grumbach 	enum iwl_amsdu_size rx_buf_size;
412e705c121SKalle Valo 	bool bc_table_dword;
413e705c121SKalle Valo 	bool scd_set_active;
41441837ca9SEmmanuel Grumbach 	bool sw_csum_tx;
41539bdb17eSSharon Dvir 	const struct iwl_hcmd_arr *command_groups;
41639bdb17eSSharon Dvir 	int command_groups_size;
417e705c121SKalle Valo 
41821cb3222SJohannes Berg 	u8 cb_data_offs;
419e705c121SKalle Valo };
420e705c121SKalle Valo 
421e705c121SKalle Valo struct iwl_trans_dump_data {
422e705c121SKalle Valo 	u32 len;
423e705c121SKalle Valo 	u8 data[];
424e705c121SKalle Valo };
425e705c121SKalle Valo 
426e705c121SKalle Valo struct iwl_trans;
427e705c121SKalle Valo 
428e705c121SKalle Valo struct iwl_trans_txq_scd_cfg {
429e705c121SKalle Valo 	u8 fifo;
4302a2e9d10SLiad Kaufman 	u8 sta_id;
431e705c121SKalle Valo 	u8 tid;
432e705c121SKalle Valo 	bool aggregate;
433e705c121SKalle Valo 	int frame_limit;
434e705c121SKalle Valo };
435e705c121SKalle Valo 
4366b35ff91SSara Sharon /**
43792536c96SSara Sharon  * struct iwl_trans_rxq_dma_data - RX queue DMA data
43892536c96SSara Sharon  * @fr_bd_cb: DMA address of free BD cyclic buffer
43992536c96SSara Sharon  * @fr_bd_wid: Initial write index of the free BD cyclic buffer
44092536c96SSara Sharon  * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
44192536c96SSara Sharon  * @ur_bd_cb: DMA address of used BD cyclic buffer
44292536c96SSara Sharon  */
44392536c96SSara Sharon struct iwl_trans_rxq_dma_data {
44492536c96SSara Sharon 	u64 fr_bd_cb;
44592536c96SSara Sharon 	u32 fr_bd_wid;
44692536c96SSara Sharon 	u64 urbd_stts_wrptr;
44792536c96SSara Sharon 	u64 ur_bd_cb;
44892536c96SSara Sharon };
44992536c96SSara Sharon 
45092536c96SSara Sharon /**
451e705c121SKalle Valo  * struct iwl_trans_ops - transport specific operations
452e705c121SKalle Valo  *
453e705c121SKalle Valo  * All the handlers MUST be implemented
454e705c121SKalle Valo  *
455bab3cb92SEmmanuel Grumbach  * @start_hw: starts the HW. From that point on, the HW can send interrupts.
456bab3cb92SEmmanuel Grumbach  *	May sleep.
457e705c121SKalle Valo  * @op_mode_leave: Turn off the HW RF kill indication if on
458e705c121SKalle Valo  *	May sleep
459e705c121SKalle Valo  * @start_fw: allocates and inits all the resources for the transport
460e705c121SKalle Valo  *	layer. Also kick a fw image.
461e705c121SKalle Valo  *	May sleep
462e705c121SKalle Valo  * @fw_alive: called when the fw sends alive notification. If the fw provides
463e705c121SKalle Valo  *	the SCD base address in SRAM, then provide it here, or 0 otherwise.
464e705c121SKalle Valo  *	May sleep
465e705c121SKalle Valo  * @stop_device: stops the whole device (embedded CPU put to reset) and stops
466bab3cb92SEmmanuel Grumbach  *	the HW. From that point on, the HW will be stopped but will still issue
467bab3cb92SEmmanuel Grumbach  *	an interrupt if the HW RF kill switch is triggered.
468e705c121SKalle Valo  *	This callback must do the right thing and not crash even if %start_hw()
469e705c121SKalle Valo  *	was called but not &start_fw(). May sleep.
470e705c121SKalle Valo  * @d3_suspend: put the device into the correct mode for WoWLAN during
471e705c121SKalle Valo  *	suspend. This is optional, if not implemented WoWLAN will not be
472e705c121SKalle Valo  *	supported. This callback may sleep.
473e705c121SKalle Valo  * @d3_resume: resume the device after WoWLAN, enabling the opmode to
474e705c121SKalle Valo  *	talk to the WoWLAN image to get its status. This is optional, if not
475e705c121SKalle Valo  *	implemented WoWLAN will not be supported. This callback may sleep.
476e705c121SKalle Valo  * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted.
477e705c121SKalle Valo  *	If RFkill is asserted in the middle of a SYNC host command, it must
478e705c121SKalle Valo  *	return -ERFKILL straight away.
479e705c121SKalle Valo  *	May sleep only if CMD_ASYNC is not set
4803f73b8caSEmmanuel Grumbach  * @tx: send an skb. The transport relies on the op_mode to zero the
4816eb5e529SEmmanuel Grumbach  *	the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all
4826eb5e529SEmmanuel Grumbach  *	the CSUM will be taken care of (TCP CSUM and IP header in case of
4836eb5e529SEmmanuel Grumbach  *	IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP
4846eb5e529SEmmanuel Grumbach  *	header if it is IPv4.
485e705c121SKalle Valo  *	Must be atomic
486e705c121SKalle Valo  * @reclaim: free packet until ssn. Returns a list of freed packets.
487e705c121SKalle Valo  *	Must be atomic
488e705c121SKalle Valo  * @txq_enable: setup a queue. To setup an AC queue, use the
489e705c121SKalle Valo  *	iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before
490e705c121SKalle Valo  *	this one. The op_mode must not configure the HCMD queue. The scheduler
491e705c121SKalle Valo  *	configuration may be %NULL, in which case the hardware will not be
492dcfbd67bSEmmanuel Grumbach  *	configured. If true is returned, the operation mode needs to increment
493dcfbd67bSEmmanuel Grumbach  *	the sequence number of the packets routed to this queue because of a
494dcfbd67bSEmmanuel Grumbach  *	hardware scheduler bug. May sleep.
495e705c121SKalle Valo  * @txq_disable: de-configure a Tx queue to send AMPDUs
496e705c121SKalle Valo  *	Must be atomic
49742db09c1SLiad Kaufman  * @txq_set_shared_mode: change Tx queue shared/unshared marking
498d6d517b7SSara Sharon  * @wait_tx_queues_empty: wait until tx queues are empty. May sleep.
499d6d517b7SSara Sharon  * @wait_txq_empty: wait until specific tx queue is empty. May sleep.
500e705c121SKalle Valo  * @freeze_txq_timer: prevents the timer of the queue from firing until the
501e705c121SKalle Valo  *	queue is set to awake. Must be atomic.
5020cd58eaaSEmmanuel Grumbach  * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note
5030cd58eaaSEmmanuel Grumbach  *	that the transport needs to refcount the calls since this function
5040cd58eaaSEmmanuel Grumbach  *	will be called several times with block = true, and then the queues
5050cd58eaaSEmmanuel Grumbach  *	need to be unblocked only after the same number of calls with
5060cd58eaaSEmmanuel Grumbach  *	block = false.
507e705c121SKalle Valo  * @write8: write a u8 to a register at offset ofs from the BAR
508e705c121SKalle Valo  * @write32: write a u32 to a register at offset ofs from the BAR
509e705c121SKalle Valo  * @read32: read a u32 register at offset ofs from the BAR
510e705c121SKalle Valo  * @read_prph: read a DWORD from a periphery register
511e705c121SKalle Valo  * @write_prph: write a DWORD to a periphery register
512e705c121SKalle Valo  * @read_mem: read device's SRAM in DWORD
513e705c121SKalle Valo  * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory
514e705c121SKalle Valo  *	will be zeroed.
515e705c121SKalle Valo  * @configure: configure parameters required by the transport layer from
516e705c121SKalle Valo  *	the op_mode. May be called several times before start_fw, can't be
517e705c121SKalle Valo  *	called after that.
518e705c121SKalle Valo  * @set_pmi: set the power pmi state
519e705c121SKalle Valo  * @grab_nic_access: wake the NIC to be able to access non-HBUS regs.
520e705c121SKalle Valo  *	Sleeping is not allowed between grab_nic_access and
521e705c121SKalle Valo  *	release_nic_access.
522e705c121SKalle Valo  * @release_nic_access: let the NIC go to sleep. The "flags" parameter
523e705c121SKalle Valo  *	must be the same one that was sent before to the grab_nic_access.
524e705c121SKalle Valo  * @set_bits_mask - set SRAM register according to value and mask.
525e705c121SKalle Valo  * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last
526e705c121SKalle Valo  *	TX'ed commands and similar. The buffer will be vfree'd by the caller.
527e705c121SKalle Valo  *	Note that the transport must fill in the proper file headers.
528f7805b33SLior Cohen  * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup
529f7805b33SLior Cohen  *	of the trans debugfs
530e705c121SKalle Valo  */
531e705c121SKalle Valo struct iwl_trans_ops {
532e705c121SKalle Valo 
533bab3cb92SEmmanuel Grumbach 	int (*start_hw)(struct iwl_trans *iwl_trans);
534e705c121SKalle Valo 	void (*op_mode_leave)(struct iwl_trans *iwl_trans);
535e705c121SKalle Valo 	int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw,
536e705c121SKalle Valo 			bool run_in_rfkill);
537e705c121SKalle Valo 	void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr);
538bab3cb92SEmmanuel Grumbach 	void (*stop_device)(struct iwl_trans *trans);
539e705c121SKalle Valo 
540e5f3f215SHaim Dreyfuss 	int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset);
541e705c121SKalle Valo 	int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status,
54223ae6128SMatti Gottlieb 			 bool test, bool reset);
543e705c121SKalle Valo 
544e705c121SKalle Valo 	int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
545e705c121SKalle Valo 
546e705c121SKalle Valo 	int (*tx)(struct iwl_trans *trans, struct sk_buff *skb,
547e705c121SKalle Valo 		  struct iwl_device_cmd *dev_cmd, int queue);
548e705c121SKalle Valo 	void (*reclaim)(struct iwl_trans *trans, int queue, int ssn,
549e705c121SKalle Valo 			struct sk_buff_head *skbs);
550e705c121SKalle Valo 
551ba7136f3SAlex Malamud 	void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr);
552ba7136f3SAlex Malamud 
553dcfbd67bSEmmanuel Grumbach 	bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,
554e705c121SKalle Valo 			   const struct iwl_trans_txq_scd_cfg *cfg,
555e705c121SKalle Valo 			   unsigned int queue_wdg_timeout);
556e705c121SKalle Valo 	void (*txq_disable)(struct iwl_trans *trans, int queue,
557e705c121SKalle Valo 			    bool configure_scd);
5582f7a3863SLuca Coelho 	/* 22000 functions */
5596b35ff91SSara Sharon 	int (*txq_alloc)(struct iwl_trans *trans,
5601169310fSGolan Ben Ami 			 __le16 flags, u8 sta_id, u8 tid,
5615369774cSSara Sharon 			 int cmd_id, int size,
5626b35ff91SSara Sharon 			 unsigned int queue_wdg_timeout);
5636b35ff91SSara Sharon 	void (*txq_free)(struct iwl_trans *trans, int queue);
56492536c96SSara Sharon 	int (*rxq_dma_data)(struct iwl_trans *trans, int queue,
56592536c96SSara Sharon 			    struct iwl_trans_rxq_dma_data *data);
566e705c121SKalle Valo 
56742db09c1SLiad Kaufman 	void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,
56842db09c1SLiad Kaufman 				    bool shared);
56942db09c1SLiad Kaufman 
570a1a57877SSara Sharon 	int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm);
571d6d517b7SSara Sharon 	int (*wait_txq_empty)(struct iwl_trans *trans, int queue);
572e705c121SKalle Valo 	void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs,
573e705c121SKalle Valo 				 bool freeze);
5740cd58eaaSEmmanuel Grumbach 	void (*block_txq_ptrs)(struct iwl_trans *trans, bool block);
575e705c121SKalle Valo 
576e705c121SKalle Valo 	void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);
577e705c121SKalle Valo 	void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);
578e705c121SKalle Valo 	u32 (*read32)(struct iwl_trans *trans, u32 ofs);
579e705c121SKalle Valo 	u32 (*read_prph)(struct iwl_trans *trans, u32 ofs);
580e705c121SKalle Valo 	void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);
581e705c121SKalle Valo 	int (*read_mem)(struct iwl_trans *trans, u32 addr,
582e705c121SKalle Valo 			void *buf, int dwords);
583e705c121SKalle Valo 	int (*write_mem)(struct iwl_trans *trans, u32 addr,
584e705c121SKalle Valo 			 const void *buf, int dwords);
585e705c121SKalle Valo 	void (*configure)(struct iwl_trans *trans,
586e705c121SKalle Valo 			  const struct iwl_trans_config *trans_cfg);
587e705c121SKalle Valo 	void (*set_pmi)(struct iwl_trans *trans, bool state);
588870c2a11SGolan Ben Ami 	void (*sw_reset)(struct iwl_trans *trans);
58923ba9340SEmmanuel Grumbach 	bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags);
590e705c121SKalle Valo 	void (*release_nic_access)(struct iwl_trans *trans,
591e705c121SKalle Valo 				   unsigned long *flags);
592e705c121SKalle Valo 	void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
593e705c121SKalle Valo 			      u32 value);
594e705c121SKalle Valo 	int  (*suspend)(struct iwl_trans *trans);
595e705c121SKalle Valo 	void (*resume)(struct iwl_trans *trans);
596e705c121SKalle Valo 
597e705c121SKalle Valo 	struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans,
59879f033f6SSara Sharon 						 u32 dump_mask);
599f7805b33SLior Cohen 	void (*debugfs_cleanup)(struct iwl_trans *trans);
600d1967ce6SShahar S Matityahu 	void (*sync_nmi)(struct iwl_trans *trans);
601e705c121SKalle Valo };
602e705c121SKalle Valo 
603e705c121SKalle Valo /**
604e705c121SKalle Valo  * enum iwl_trans_state - state of the transport layer
605e705c121SKalle Valo  *
606e705c121SKalle Valo  * @IWL_TRANS_NO_FW: no fw has sent an alive response
607e705c121SKalle Valo  * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response
608e705c121SKalle Valo  */
609e705c121SKalle Valo enum iwl_trans_state {
610e705c121SKalle Valo 	IWL_TRANS_NO_FW = 0,
611e705c121SKalle Valo 	IWL_TRANS_FW_ALIVE	= 1,
612e705c121SKalle Valo };
613e705c121SKalle Valo 
614e705c121SKalle Valo /**
615b7282643SLuca Coelho  * DOC: Platform power management
616e705c121SKalle Valo  *
617b7282643SLuca Coelho  * In system-wide power management the entire platform goes into a low
618b7282643SLuca Coelho  * power state (e.g. idle or suspend to RAM) at the same time and the
619b7282643SLuca Coelho  * device is configured as a wakeup source for the entire platform.
620b7282643SLuca Coelho  * This is usually triggered by userspace activity (e.g. the user
621b7282643SLuca Coelho  * presses the suspend button or a power management daemon decides to
622b7282643SLuca Coelho  * put the platform in low power mode).  The device's behavior in this
623b7282643SLuca Coelho  * mode is dictated by the wake-on-WLAN configuration.
624b7282643SLuca Coelho  *
625b7282643SLuca Coelho  * The terms used for the device's behavior are as follows:
626b7282643SLuca Coelho  *
627b7282643SLuca Coelho  *	- D0: the device is fully powered and the host is awake;
628b7282643SLuca Coelho  *	- D3: the device is in low power mode and only reacts to
629b7282643SLuca Coelho  *		specific events (e.g. magic-packet received or scan
630b7282643SLuca Coelho  *		results found);
631b7282643SLuca Coelho  *
632b7282643SLuca Coelho  * These terms reflect the power modes in the firmware and are not to
633f60e2750SEmmanuel Grumbach  * be confused with the physical device power state.
634e705c121SKalle Valo  */
635b7282643SLuca Coelho 
636b7282643SLuca Coelho /**
637b7282643SLuca Coelho  * enum iwl_plat_pm_mode - platform power management mode
638b7282643SLuca Coelho  *
639b7282643SLuca Coelho  * This enumeration describes the device's platform power management
640f60e2750SEmmanuel Grumbach  * behavior when in system-wide suspend (i.e WoWLAN).
641b7282643SLuca Coelho  *
642b7282643SLuca Coelho  * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this
643f60e2750SEmmanuel Grumbach  *	device.  In system-wide suspend mode, it means that the all
644f60e2750SEmmanuel Grumbach  *	connections will be closed automatically by mac80211 before
645f60e2750SEmmanuel Grumbach  *	the platform is suspended.
646b7282643SLuca Coelho  * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN).
647b7282643SLuca Coelho  */
648b7282643SLuca Coelho enum iwl_plat_pm_mode {
649b7282643SLuca Coelho 	IWL_PLAT_PM_MODE_DISABLED,
650b7282643SLuca Coelho 	IWL_PLAT_PM_MODE_D3,
651e705c121SKalle Valo };
652e705c121SKalle Valo 
653341bd290SShahar S Matityahu /**
654341bd290SShahar S Matityahu  * enum iwl_ini_cfg_state
655341bd290SShahar S Matityahu  * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given
656341bd290SShahar S Matityahu  * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded
657341bd290SShahar S Matityahu  * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs
658341bd290SShahar S Matityahu  *	are corrupted. The rest of the debug TLVs will still be used
659341bd290SShahar S Matityahu  */
660341bd290SShahar S Matityahu enum iwl_ini_cfg_state {
661341bd290SShahar S Matityahu 	IWL_INI_CFG_STATE_NOT_LOADED,
662341bd290SShahar S Matityahu 	IWL_INI_CFG_STATE_LOADED,
663341bd290SShahar S Matityahu 	IWL_INI_CFG_STATE_CORRUPTED,
664341bd290SShahar S Matityahu };
665341bd290SShahar S Matityahu 
666b8a7547dSShahar S Matityahu /* Max time to wait for nmi interrupt */
667b8a7547dSShahar S Matityahu #define IWL_TRANS_NMI_TIMEOUT (HZ / 4)
668b8a7547dSShahar S Matityahu 
66988964b2eSSara Sharon /**
67088964b2eSSara Sharon  * struct iwl_dram_data
67188964b2eSSara Sharon  * @physical: page phy pointer
67288964b2eSSara Sharon  * @block: pointer to the allocated block/page
67388964b2eSSara Sharon  * @size: size of the block/page
67488964b2eSSara Sharon  */
67588964b2eSSara Sharon struct iwl_dram_data {
67688964b2eSSara Sharon 	dma_addr_t physical;
67788964b2eSSara Sharon 	void *block;
67888964b2eSSara Sharon 	int size;
67988964b2eSSara Sharon };
6804cbb8e50SLuciano Coelho 
681e705c121SKalle Valo /**
682593fae3eSShahar S Matityahu  * struct iwl_fw_mon - fw monitor per allocation id
683593fae3eSShahar S Matityahu  * @num_frags: number of fragments
684593fae3eSShahar S Matityahu  * @frags: an array of DRAM buffer fragments
685593fae3eSShahar S Matityahu  */
686593fae3eSShahar S Matityahu struct iwl_fw_mon {
687593fae3eSShahar S Matityahu 	u32 num_frags;
688593fae3eSShahar S Matityahu 	struct iwl_dram_data *frags;
689593fae3eSShahar S Matityahu };
690593fae3eSShahar S Matityahu 
691593fae3eSShahar S Matityahu /**
692505a00c0SShahar S Matityahu  * struct iwl_self_init_dram - dram data used by self init process
693505a00c0SShahar S Matityahu  * @fw: lmac and umac dram data
694505a00c0SShahar S Matityahu  * @fw_cnt: total number of items in array
695505a00c0SShahar S Matityahu  * @paging: paging dram data
696505a00c0SShahar S Matityahu  * @paging_cnt: total number of items in array
697505a00c0SShahar S Matityahu  */
698505a00c0SShahar S Matityahu struct iwl_self_init_dram {
699505a00c0SShahar S Matityahu 	struct iwl_dram_data *fw;
700505a00c0SShahar S Matityahu 	int fw_cnt;
701505a00c0SShahar S Matityahu 	struct iwl_dram_data *paging;
702505a00c0SShahar S Matityahu 	int paging_cnt;
703505a00c0SShahar S Matityahu };
704505a00c0SShahar S Matityahu 
705505a00c0SShahar S Matityahu /**
70691c28b83SShahar S Matityahu  * struct iwl_trans_debug - transport debug related data
70791c28b83SShahar S Matityahu  *
70891c28b83SShahar S Matityahu  * @n_dest_reg: num of reg_ops in %dbg_dest_tlv
70991c28b83SShahar S Matityahu  * @rec_on: true iff there is a fw debug recording currently active
71091c28b83SShahar S Matityahu  * @dest_tlv: points to the destination TLV for debug
71191c28b83SShahar S Matityahu  * @conf_tlv: array of pointers to configuration TLVs for debug
71291c28b83SShahar S Matityahu  * @trigger_tlv: array of pointers to triggers TLVs for debug
71391c28b83SShahar S Matityahu  * @lmac_error_event_table: addrs of lmacs error tables
71491c28b83SShahar S Matityahu  * @umac_error_event_table: addr of umac error table
71591c28b83SShahar S Matityahu  * @error_event_table_tlv_status: bitmap that indicates what error table
71691c28b83SShahar S Matityahu  *	pointers was recevied via TLV. uses enum &iwl_error_event_table_status
717341bd290SShahar S Matityahu  * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state
718341bd290SShahar S Matityahu  * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state
719593fae3eSShahar S Matityahu  * @fw_mon_cfg: debug buffer allocation configuration
720593fae3eSShahar S Matityahu  * @fw_mon_ini: DRAM buffer fragments per allocation id
72169f0e505SShahar S Matityahu  * @fw_mon: DRAM buffer for firmware monitor
72291c28b83SShahar S Matityahu  * @hw_error: equals true if hw error interrupt was received from the FW
723029c25f3SShahar S Matityahu  * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location
7243b589d56SShahar S Matityahu  * @active_regions: active regions
725677d25b2SShahar S Matityahu  * @debug_info_tlv_list: list of debug info TLVs
726a9248de4SShahar S Matityahu  * @time_point: array of debug time points
727cf29c5b6SShahar S Matityahu  * @domains_bitmap: bitmap of active domains other than
728cf29c5b6SShahar S Matityahu  *	&IWL_FW_INI_DOMAIN_ALWAYS_ON
72991c28b83SShahar S Matityahu  */
73091c28b83SShahar S Matityahu struct iwl_trans_debug {
73191c28b83SShahar S Matityahu 	u8 n_dest_reg;
73291c28b83SShahar S Matityahu 	bool rec_on;
73391c28b83SShahar S Matityahu 
73491c28b83SShahar S Matityahu 	const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv;
73591c28b83SShahar S Matityahu 	const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX];
73691c28b83SShahar S Matityahu 	struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv;
73791c28b83SShahar S Matityahu 
73891c28b83SShahar S Matityahu 	u32 lmac_error_event_table[2];
73991c28b83SShahar S Matityahu 	u32 umac_error_event_table;
74091c28b83SShahar S Matityahu 	unsigned int error_event_table_tlv_status;
74191c28b83SShahar S Matityahu 
742341bd290SShahar S Matityahu 	enum iwl_ini_cfg_state internal_ini_cfg;
743341bd290SShahar S Matityahu 	enum iwl_ini_cfg_state external_ini_cfg;
74491c28b83SShahar S Matityahu 
745593fae3eSShahar S Matityahu 	struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM];
746593fae3eSShahar S Matityahu 	struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM];
747593fae3eSShahar S Matityahu 
74869f0e505SShahar S Matityahu 	struct iwl_dram_data fw_mon;
74991c28b83SShahar S Matityahu 
75091c28b83SShahar S Matityahu 	bool hw_error;
751029c25f3SShahar S Matityahu 	enum iwl_fw_ini_buffer_location ini_dest;
7523b589d56SShahar S Matityahu 
7533b589d56SShahar S Matityahu 	struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID];
754677d25b2SShahar S Matityahu 	struct list_head debug_info_tlv_list;
755a9248de4SShahar S Matityahu 	struct iwl_dbg_tlv_time_point_data
756a9248de4SShahar S Matityahu 		time_point[IWL_FW_INI_TIME_POINT_NUM];
757cf29c5b6SShahar S Matityahu 
758cf29c5b6SShahar S Matityahu 	u32 domains_bitmap;
75991c28b83SShahar S Matityahu };
76091c28b83SShahar S Matityahu 
76191c28b83SShahar S Matityahu /**
762e705c121SKalle Valo  * struct iwl_trans - transport common data
763e705c121SKalle Valo  *
764e705c121SKalle Valo  * @ops - pointer to iwl_trans_ops
765e705c121SKalle Valo  * @op_mode - pointer to the op_mode
766286ca8ebSLuca Coelho  * @trans_cfg: the trans-specific configuration part
767e705c121SKalle Valo  * @cfg - pointer to the configuration
7686f482e37SSara Sharon  * @drv - pointer to iwl_drv
769e705c121SKalle Valo  * @status: a bit-mask of transport status flags
770e705c121SKalle Valo  * @dev - pointer to struct device * that represents the device
771e705c121SKalle Valo  * @max_skb_frags: maximum number of fragments an SKB can have when transmitted.
772e705c121SKalle Valo  *	0 indicates that frag SKBs (NETIF_F_SG) aren't supported.
7731afb0ae4SHaim Dreyfuss  * @hw_rf_id a u32 with the device RF ID
774e705c121SKalle Valo  * @hw_id: a u32 with the ID of the device / sub-device.
775e705c121SKalle Valo  *	Set during transport allocation.
776e705c121SKalle Valo  * @hw_id_str: a string with info about HW ID. Set during transport allocation.
777e705c121SKalle Valo  * @pm_support: set to true in start_hw if link pm is supported
778e705c121SKalle Valo  * @ltr_enabled: set to true if the LTR is enabled
7795b88792cSSara Sharon  * @wide_cmd_header: true when ucode supports wide command header format
780e705c121SKalle Valo  * @num_rx_queues: number of RX queues allocated by the transport;
781e705c121SKalle Valo  *	the transport must set this before calling iwl_drv_start()
782132db31cSGolan Ben-Ami  * @iml_len: the length of the image loader
783132db31cSGolan Ben-Ami  * @iml: a pointer to the image loader itself
784e705c121SKalle Valo  * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
785e705c121SKalle Valo  *	The user should use iwl_trans_{alloc,free}_tx_cmd.
786e705c121SKalle Valo  * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before
787e705c121SKalle Valo  *	starting the firmware, used for tracing
788e705c121SKalle Valo  * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the
789e705c121SKalle Valo  *	start of the 802.11 header in the @rx_mpdu_cmd
790e705c121SKalle Valo  * @dflt_pwr_limit: default power limit fetched from the platform (ACPI)
791b7282643SLuca Coelho  * @system_pm_mode: the system-wide power management mode in use.
792b7282643SLuca Coelho  *	This mode is set dynamically, depending on the WoWLAN values
793b7282643SLuca Coelho  *	configured from the userspace at runtime.
794e705c121SKalle Valo  */
795e705c121SKalle Valo struct iwl_trans {
796e705c121SKalle Valo 	const struct iwl_trans_ops *ops;
797e705c121SKalle Valo 	struct iwl_op_mode *op_mode;
798286ca8ebSLuca Coelho 	const struct iwl_cfg_trans_params *trans_cfg;
799e705c121SKalle Valo 	const struct iwl_cfg *cfg;
8006f482e37SSara Sharon 	struct iwl_drv *drv;
801e705c121SKalle Valo 	enum iwl_trans_state state;
802e705c121SKalle Valo 	unsigned long status;
803e705c121SKalle Valo 
804e705c121SKalle Valo 	struct device *dev;
805e705c121SKalle Valo 	u32 max_skb_frags;
806e705c121SKalle Valo 	u32 hw_rev;
8071afb0ae4SHaim Dreyfuss 	u32 hw_rf_id;
808e705c121SKalle Valo 	u32 hw_id;
809e705c121SKalle Valo 	char hw_id_str[52];
810e705c121SKalle Valo 
811e705c121SKalle Valo 	u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
812e705c121SKalle Valo 
813e705c121SKalle Valo 	bool pm_support;
814e705c121SKalle Valo 	bool ltr_enabled;
815e705c121SKalle Valo 
81639bdb17eSSharon Dvir 	const struct iwl_hcmd_arr *command_groups;
81739bdb17eSSharon Dvir 	int command_groups_size;
8185b88792cSSara Sharon 	bool wide_cmd_header;
81939bdb17eSSharon Dvir 
820e705c121SKalle Valo 	u8 num_rx_queues;
821e705c121SKalle Valo 
822132db31cSGolan Ben-Ami 	size_t iml_len;
823132db31cSGolan Ben-Ami 	u8 *iml;
824132db31cSGolan Ben-Ami 
825e705c121SKalle Valo 	/* The following fields are internal only */
826e705c121SKalle Valo 	struct kmem_cache *dev_cmd_pool;
827e705c121SKalle Valo 	char dev_cmd_pool_name[50];
828e705c121SKalle Valo 
829e705c121SKalle Valo 	struct dentry *dbgfs_dir;
830e705c121SKalle Valo 
831e705c121SKalle Valo #ifdef CONFIG_LOCKDEP
832e705c121SKalle Valo 	struct lockdep_map sync_cmd_lockdep_map;
833e705c121SKalle Valo #endif
834e705c121SKalle Valo 
83591c28b83SShahar S Matityahu 	struct iwl_trans_debug dbg;
836505a00c0SShahar S Matityahu 	struct iwl_self_init_dram init_dram;
837e705c121SKalle Valo 
838b7282643SLuca Coelho 	enum iwl_plat_pm_mode system_pm_mode;
839700b3799SShahar S Matityahu 
840e705c121SKalle Valo 	/* pointer to trans specific struct */
841e705c121SKalle Valo 	/*Ensure that this pointer will always be aligned to sizeof pointer */
842e705c121SKalle Valo 	char trans_specific[0] __aligned(sizeof(void *));
843e705c121SKalle Valo };
844e705c121SKalle Valo 
84539bdb17eSSharon Dvir const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);
84639bdb17eSSharon Dvir int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);
84739bdb17eSSharon Dvir 
848e705c121SKalle Valo static inline void iwl_trans_configure(struct iwl_trans *trans,
849e705c121SKalle Valo 				       const struct iwl_trans_config *trans_cfg)
850e705c121SKalle Valo {
851e705c121SKalle Valo 	trans->op_mode = trans_cfg->op_mode;
852e705c121SKalle Valo 
853e705c121SKalle Valo 	trans->ops->configure(trans, trans_cfg);
85439bdb17eSSharon Dvir 	WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg));
855e705c121SKalle Valo }
856e705c121SKalle Valo 
857bab3cb92SEmmanuel Grumbach static inline int iwl_trans_start_hw(struct iwl_trans *trans)
858e705c121SKalle Valo {
859e705c121SKalle Valo 	might_sleep();
860e705c121SKalle Valo 
861bab3cb92SEmmanuel Grumbach 	return trans->ops->start_hw(trans);
862e705c121SKalle Valo }
863e705c121SKalle Valo 
864e705c121SKalle Valo static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans)
865e705c121SKalle Valo {
866e705c121SKalle Valo 	might_sleep();
867e705c121SKalle Valo 
868e705c121SKalle Valo 	if (trans->ops->op_mode_leave)
869e705c121SKalle Valo 		trans->ops->op_mode_leave(trans);
870e705c121SKalle Valo 
871e705c121SKalle Valo 	trans->op_mode = NULL;
872e705c121SKalle Valo 
873e705c121SKalle Valo 	trans->state = IWL_TRANS_NO_FW;
874e705c121SKalle Valo }
875e705c121SKalle Valo 
876e705c121SKalle Valo static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr)
877e705c121SKalle Valo {
878e705c121SKalle Valo 	might_sleep();
879e705c121SKalle Valo 
880e705c121SKalle Valo 	trans->state = IWL_TRANS_FW_ALIVE;
881e705c121SKalle Valo 
882e705c121SKalle Valo 	trans->ops->fw_alive(trans, scd_addr);
883e705c121SKalle Valo }
884e705c121SKalle Valo 
885e705c121SKalle Valo static inline int iwl_trans_start_fw(struct iwl_trans *trans,
886e705c121SKalle Valo 				     const struct fw_img *fw,
887e705c121SKalle Valo 				     bool run_in_rfkill)
888e705c121SKalle Valo {
889e705c121SKalle Valo 	might_sleep();
890e705c121SKalle Valo 
891e705c121SKalle Valo 	WARN_ON_ONCE(!trans->rx_mpdu_cmd);
892e705c121SKalle Valo 
893e705c121SKalle Valo 	clear_bit(STATUS_FW_ERROR, &trans->status);
894e705c121SKalle Valo 	return trans->ops->start_fw(trans, fw, run_in_rfkill);
895e705c121SKalle Valo }
896e705c121SKalle Valo 
897bab3cb92SEmmanuel Grumbach static inline void iwl_trans_stop_device(struct iwl_trans *trans)
898e705c121SKalle Valo {
899e705c121SKalle Valo 	might_sleep();
900e705c121SKalle Valo 
901bab3cb92SEmmanuel Grumbach 	trans->ops->stop_device(trans);
902e705c121SKalle Valo 
903e705c121SKalle Valo 	trans->state = IWL_TRANS_NO_FW;
904e705c121SKalle Valo }
905e705c121SKalle Valo 
906e5f3f215SHaim Dreyfuss static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test,
90723ae6128SMatti Gottlieb 				       bool reset)
908e705c121SKalle Valo {
909e705c121SKalle Valo 	might_sleep();
910e5f3f215SHaim Dreyfuss 	if (!trans->ops->d3_suspend)
911e5f3f215SHaim Dreyfuss 		return 0;
912e5f3f215SHaim Dreyfuss 
913e5f3f215SHaim Dreyfuss 	return trans->ops->d3_suspend(trans, test, reset);
914e705c121SKalle Valo }
915e705c121SKalle Valo 
916e705c121SKalle Valo static inline int iwl_trans_d3_resume(struct iwl_trans *trans,
917e705c121SKalle Valo 				      enum iwl_d3_status *status,
91823ae6128SMatti Gottlieb 				      bool test, bool reset)
919e705c121SKalle Valo {
920e705c121SKalle Valo 	might_sleep();
921e705c121SKalle Valo 	if (!trans->ops->d3_resume)
922e705c121SKalle Valo 		return 0;
923e705c121SKalle Valo 
92423ae6128SMatti Gottlieb 	return trans->ops->d3_resume(trans, status, test, reset);
925e705c121SKalle Valo }
926e705c121SKalle Valo 
927e705c121SKalle Valo static inline int iwl_trans_suspend(struct iwl_trans *trans)
928e705c121SKalle Valo {
929e705c121SKalle Valo 	if (!trans->ops->suspend)
930e705c121SKalle Valo 		return 0;
931e705c121SKalle Valo 
932e705c121SKalle Valo 	return trans->ops->suspend(trans);
933e705c121SKalle Valo }
934e705c121SKalle Valo 
935e705c121SKalle Valo static inline void iwl_trans_resume(struct iwl_trans *trans)
936e705c121SKalle Valo {
937e705c121SKalle Valo 	if (trans->ops->resume)
938e705c121SKalle Valo 		trans->ops->resume(trans);
939e705c121SKalle Valo }
940e705c121SKalle Valo 
941e705c121SKalle Valo static inline struct iwl_trans_dump_data *
94279f033f6SSara Sharon iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask)
943e705c121SKalle Valo {
944e705c121SKalle Valo 	if (!trans->ops->dump_data)
945e705c121SKalle Valo 		return NULL;
94679f033f6SSara Sharon 	return trans->ops->dump_data(trans, dump_mask);
947e705c121SKalle Valo }
948e705c121SKalle Valo 
949e705c121SKalle Valo static inline struct iwl_device_cmd *
950e705c121SKalle Valo iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)
951e705c121SKalle Valo {
9520ae0bb3fSLuca Coelho 	return kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC);
953e705c121SKalle Valo }
954e705c121SKalle Valo 
95592fe8343SEmmanuel Grumbach int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
95692fe8343SEmmanuel Grumbach 
957e705c121SKalle Valo static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,
958e705c121SKalle Valo 					 struct iwl_device_cmd *dev_cmd)
959e705c121SKalle Valo {
9601ea423b0SLuca Coelho 	kmem_cache_free(trans->dev_cmd_pool, dev_cmd);
961e705c121SKalle Valo }
962e705c121SKalle Valo 
963e705c121SKalle Valo static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
964e705c121SKalle Valo 			       struct iwl_device_cmd *dev_cmd, int queue)
965e705c121SKalle Valo {
966e705c121SKalle Valo 	if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status)))
967e705c121SKalle Valo 		return -EIO;
968e705c121SKalle Valo 
969e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
970e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
971e5d15cb5SEliad Peller 		return -EIO;
972e5d15cb5SEliad Peller 	}
973e705c121SKalle Valo 
974e705c121SKalle Valo 	return trans->ops->tx(trans, skb, dev_cmd, queue);
975e705c121SKalle Valo }
976e705c121SKalle Valo 
977e705c121SKalle Valo static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue,
978e705c121SKalle Valo 				     int ssn, struct sk_buff_head *skbs)
979e705c121SKalle Valo {
980e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
981e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
982e5d15cb5SEliad Peller 		return;
983e5d15cb5SEliad Peller 	}
984e705c121SKalle Valo 
985e705c121SKalle Valo 	trans->ops->reclaim(trans, queue, ssn, skbs);
986e705c121SKalle Valo }
987e705c121SKalle Valo 
988ba7136f3SAlex Malamud static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue,
989ba7136f3SAlex Malamud 					int ptr)
990ba7136f3SAlex Malamud {
991ba7136f3SAlex Malamud 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
992ba7136f3SAlex Malamud 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
993ba7136f3SAlex Malamud 		return;
994ba7136f3SAlex Malamud 	}
995ba7136f3SAlex Malamud 
996ba7136f3SAlex Malamud 	trans->ops->set_q_ptrs(trans, queue, ptr);
997ba7136f3SAlex Malamud }
998ba7136f3SAlex Malamud 
999e705c121SKalle Valo static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
1000e705c121SKalle Valo 					 bool configure_scd)
1001e705c121SKalle Valo {
1002e705c121SKalle Valo 	trans->ops->txq_disable(trans, queue, configure_scd);
1003e705c121SKalle Valo }
1004e705c121SKalle Valo 
1005dcfbd67bSEmmanuel Grumbach static inline bool
1006e705c121SKalle Valo iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
1007e705c121SKalle Valo 			 const struct iwl_trans_txq_scd_cfg *cfg,
1008e705c121SKalle Valo 			 unsigned int queue_wdg_timeout)
1009e705c121SKalle Valo {
1010e705c121SKalle Valo 	might_sleep();
1011e705c121SKalle Valo 
1012e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1013e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1014dcfbd67bSEmmanuel Grumbach 		return false;
1015e5d15cb5SEliad Peller 	}
1016e705c121SKalle Valo 
1017dcfbd67bSEmmanuel Grumbach 	return trans->ops->txq_enable(trans, queue, ssn,
1018dcfbd67bSEmmanuel Grumbach 				      cfg, queue_wdg_timeout);
1019e705c121SKalle Valo }
1020e705c121SKalle Valo 
102192536c96SSara Sharon static inline int
102292536c96SSara Sharon iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,
102392536c96SSara Sharon 			   struct iwl_trans_rxq_dma_data *data)
102492536c96SSara Sharon {
102592536c96SSara Sharon 	if (WARN_ON_ONCE(!trans->ops->rxq_dma_data))
102692536c96SSara Sharon 		return -ENOTSUPP;
102792536c96SSara Sharon 
102892536c96SSara Sharon 	return trans->ops->rxq_dma_data(trans, queue, data);
102992536c96SSara Sharon }
103092536c96SSara Sharon 
10316b35ff91SSara Sharon static inline void
10326b35ff91SSara Sharon iwl_trans_txq_free(struct iwl_trans *trans, int queue)
10336b35ff91SSara Sharon {
10346b35ff91SSara Sharon 	if (WARN_ON_ONCE(!trans->ops->txq_free))
10356b35ff91SSara Sharon 		return;
10366b35ff91SSara Sharon 
10376b35ff91SSara Sharon 	trans->ops->txq_free(trans, queue);
10386b35ff91SSara Sharon }
10396b35ff91SSara Sharon 
10406b35ff91SSara Sharon static inline int
10416b35ff91SSara Sharon iwl_trans_txq_alloc(struct iwl_trans *trans,
10421169310fSGolan Ben Ami 		    __le16 flags, u8 sta_id, u8 tid,
10435369774cSSara Sharon 		    int cmd_id, int size,
10445369774cSSara Sharon 		    unsigned int wdg_timeout)
10456b35ff91SSara Sharon {
10466b35ff91SSara Sharon 	might_sleep();
10476b35ff91SSara Sharon 
10486b35ff91SSara Sharon 	if (WARN_ON_ONCE(!trans->ops->txq_alloc))
10496b35ff91SSara Sharon 		return -ENOTSUPP;
10506b35ff91SSara Sharon 
10516b35ff91SSara Sharon 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
10526b35ff91SSara Sharon 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
10536b35ff91SSara Sharon 		return -EIO;
10546b35ff91SSara Sharon 	}
10556b35ff91SSara Sharon 
10561169310fSGolan Ben Ami 	return trans->ops->txq_alloc(trans, flags, sta_id, tid,
10571169310fSGolan Ben Ami 				     cmd_id, size, wdg_timeout);
10586b35ff91SSara Sharon }
10596b35ff91SSara Sharon 
106042db09c1SLiad Kaufman static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,
106142db09c1SLiad Kaufman 						 int queue, bool shared_mode)
106242db09c1SLiad Kaufman {
106342db09c1SLiad Kaufman 	if (trans->ops->txq_set_shared_mode)
106442db09c1SLiad Kaufman 		trans->ops->txq_set_shared_mode(trans, queue, shared_mode);
106542db09c1SLiad Kaufman }
106642db09c1SLiad Kaufman 
1067e705c121SKalle Valo static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
1068e705c121SKalle Valo 					int fifo, int sta_id, int tid,
1069e705c121SKalle Valo 					int frame_limit, u16 ssn,
1070e705c121SKalle Valo 					unsigned int queue_wdg_timeout)
1071e705c121SKalle Valo {
1072e705c121SKalle Valo 	struct iwl_trans_txq_scd_cfg cfg = {
1073e705c121SKalle Valo 		.fifo = fifo,
1074e705c121SKalle Valo 		.sta_id = sta_id,
1075e705c121SKalle Valo 		.tid = tid,
1076e705c121SKalle Valo 		.frame_limit = frame_limit,
1077e705c121SKalle Valo 		.aggregate = sta_id >= 0,
1078e705c121SKalle Valo 	};
1079e705c121SKalle Valo 
1080e705c121SKalle Valo 	iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);
1081e705c121SKalle Valo }
1082e705c121SKalle Valo 
1083e705c121SKalle Valo static inline
1084e705c121SKalle Valo void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,
1085e705c121SKalle Valo 			     unsigned int queue_wdg_timeout)
1086e705c121SKalle Valo {
1087e705c121SKalle Valo 	struct iwl_trans_txq_scd_cfg cfg = {
1088e705c121SKalle Valo 		.fifo = fifo,
1089e705c121SKalle Valo 		.sta_id = -1,
1090e705c121SKalle Valo 		.tid = IWL_MAX_TID_COUNT,
1091e705c121SKalle Valo 		.frame_limit = IWL_FRAME_LIMIT,
1092e705c121SKalle Valo 		.aggregate = false,
1093e705c121SKalle Valo 	};
1094e705c121SKalle Valo 
1095e705c121SKalle Valo 	iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);
1096e705c121SKalle Valo }
1097e705c121SKalle Valo 
1098e705c121SKalle Valo static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,
1099e705c121SKalle Valo 					      unsigned long txqs,
1100e705c121SKalle Valo 					      bool freeze)
1101e705c121SKalle Valo {
1102e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1103e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1104e5d15cb5SEliad Peller 		return;
1105e5d15cb5SEliad Peller 	}
1106e705c121SKalle Valo 
1107e705c121SKalle Valo 	if (trans->ops->freeze_txq_timer)
1108e705c121SKalle Valo 		trans->ops->freeze_txq_timer(trans, txqs, freeze);
1109e705c121SKalle Valo }
1110e705c121SKalle Valo 
11110cd58eaaSEmmanuel Grumbach static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans,
11120cd58eaaSEmmanuel Grumbach 					    bool block)
11130cd58eaaSEmmanuel Grumbach {
1114e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
11150cd58eaaSEmmanuel Grumbach 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1116e5d15cb5SEliad Peller 		return;
1117e5d15cb5SEliad Peller 	}
11180cd58eaaSEmmanuel Grumbach 
11190cd58eaaSEmmanuel Grumbach 	if (trans->ops->block_txq_ptrs)
11200cd58eaaSEmmanuel Grumbach 		trans->ops->block_txq_ptrs(trans, block);
11210cd58eaaSEmmanuel Grumbach }
11220cd58eaaSEmmanuel Grumbach 
1123a1a57877SSara Sharon static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans,
1124e705c121SKalle Valo 						 u32 txqs)
1125e705c121SKalle Valo {
1126d6d517b7SSara Sharon 	if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty))
1127d6d517b7SSara Sharon 		return -ENOTSUPP;
1128d6d517b7SSara Sharon 
1129e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1130e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1131e5d15cb5SEliad Peller 		return -EIO;
1132e5d15cb5SEliad Peller 	}
1133e705c121SKalle Valo 
1134a1a57877SSara Sharon 	return trans->ops->wait_tx_queues_empty(trans, txqs);
1135e705c121SKalle Valo }
1136e705c121SKalle Valo 
1137d6d517b7SSara Sharon static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue)
1138d6d517b7SSara Sharon {
1139d6d517b7SSara Sharon 	if (WARN_ON_ONCE(!trans->ops->wait_txq_empty))
1140d6d517b7SSara Sharon 		return -ENOTSUPP;
1141d6d517b7SSara Sharon 
1142d6d517b7SSara Sharon 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1143d6d517b7SSara Sharon 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1144d6d517b7SSara Sharon 		return -EIO;
1145d6d517b7SSara Sharon 	}
1146d6d517b7SSara Sharon 
1147d6d517b7SSara Sharon 	return trans->ops->wait_txq_empty(trans, queue);
1148d6d517b7SSara Sharon }
1149d6d517b7SSara Sharon 
1150e705c121SKalle Valo static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1151e705c121SKalle Valo {
1152e705c121SKalle Valo 	trans->ops->write8(trans, ofs, val);
1153e705c121SKalle Valo }
1154e705c121SKalle Valo 
1155e705c121SKalle Valo static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1156e705c121SKalle Valo {
1157e705c121SKalle Valo 	trans->ops->write32(trans, ofs, val);
1158e705c121SKalle Valo }
1159e705c121SKalle Valo 
1160e705c121SKalle Valo static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs)
1161e705c121SKalle Valo {
1162e705c121SKalle Valo 	return trans->ops->read32(trans, ofs);
1163e705c121SKalle Valo }
1164e705c121SKalle Valo 
1165e705c121SKalle Valo static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)
1166e705c121SKalle Valo {
1167e705c121SKalle Valo 	return trans->ops->read_prph(trans, ofs);
1168e705c121SKalle Valo }
1169e705c121SKalle Valo 
1170e705c121SKalle Valo static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs,
1171e705c121SKalle Valo 					u32 val)
1172e705c121SKalle Valo {
1173e705c121SKalle Valo 	return trans->ops->write_prph(trans, ofs, val);
1174e705c121SKalle Valo }
1175e705c121SKalle Valo 
1176e705c121SKalle Valo static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
1177e705c121SKalle Valo 				     void *buf, int dwords)
1178e705c121SKalle Valo {
1179e705c121SKalle Valo 	return trans->ops->read_mem(trans, addr, buf, dwords);
1180e705c121SKalle Valo }
1181e705c121SKalle Valo 
1182e705c121SKalle Valo #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize)		      \
1183e705c121SKalle Valo 	do {								      \
1184e705c121SKalle Valo 		if (__builtin_constant_p(bufsize))			      \
1185e705c121SKalle Valo 			BUILD_BUG_ON((bufsize) % sizeof(u32));		      \
1186e705c121SKalle Valo 		iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\
1187e705c121SKalle Valo 	} while (0)
1188e705c121SKalle Valo 
1189e705c121SKalle Valo static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
1190e705c121SKalle Valo {
1191e705c121SKalle Valo 	u32 value;
1192e705c121SKalle Valo 
1193e705c121SKalle Valo 	if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1)))
1194e705c121SKalle Valo 		return 0xa5a5a5a5;
1195e705c121SKalle Valo 
1196e705c121SKalle Valo 	return value;
1197e705c121SKalle Valo }
1198e705c121SKalle Valo 
1199e705c121SKalle Valo static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
1200e705c121SKalle Valo 				      const void *buf, int dwords)
1201e705c121SKalle Valo {
1202e705c121SKalle Valo 	return trans->ops->write_mem(trans, addr, buf, dwords);
1203e705c121SKalle Valo }
1204e705c121SKalle Valo 
1205e705c121SKalle Valo static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
1206e705c121SKalle Valo 					u32 val)
1207e705c121SKalle Valo {
1208e705c121SKalle Valo 	return iwl_trans_write_mem(trans, addr, &val, 1);
1209e705c121SKalle Valo }
1210e705c121SKalle Valo 
1211e705c121SKalle Valo static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state)
1212e705c121SKalle Valo {
1213e705c121SKalle Valo 	if (trans->ops->set_pmi)
1214e705c121SKalle Valo 		trans->ops->set_pmi(trans, state);
1215e705c121SKalle Valo }
1216e705c121SKalle Valo 
1217870c2a11SGolan Ben Ami static inline void iwl_trans_sw_reset(struct iwl_trans *trans)
1218870c2a11SGolan Ben Ami {
1219870c2a11SGolan Ben Ami 	if (trans->ops->sw_reset)
1220870c2a11SGolan Ben Ami 		trans->ops->sw_reset(trans);
1221870c2a11SGolan Ben Ami }
1222870c2a11SGolan Ben Ami 
1223e705c121SKalle Valo static inline void
1224e705c121SKalle Valo iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
1225e705c121SKalle Valo {
1226e705c121SKalle Valo 	trans->ops->set_bits_mask(trans, reg, mask, value);
1227e705c121SKalle Valo }
1228e705c121SKalle Valo 
122923ba9340SEmmanuel Grumbach #define iwl_trans_grab_nic_access(trans, flags)	\
1230e705c121SKalle Valo 	__cond_lock(nic_access,				\
123123ba9340SEmmanuel Grumbach 		    likely((trans)->ops->grab_nic_access(trans, flags)))
1232e705c121SKalle Valo 
1233e705c121SKalle Valo static inline void __releases(nic_access)
1234e705c121SKalle Valo iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags)
1235e705c121SKalle Valo {
1236e705c121SKalle Valo 	trans->ops->release_nic_access(trans, flags);
1237e705c121SKalle Valo 	__release(nic_access);
1238e705c121SKalle Valo }
1239e705c121SKalle Valo 
1240e705c121SKalle Valo static inline void iwl_trans_fw_error(struct iwl_trans *trans)
1241e705c121SKalle Valo {
1242e705c121SKalle Valo 	if (WARN_ON_ONCE(!trans->op_mode))
1243e705c121SKalle Valo 		return;
1244e705c121SKalle Valo 
1245e705c121SKalle Valo 	/* prevent double restarts due to the same erroneous FW */
1246e705c121SKalle Valo 	if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status))
1247e705c121SKalle Valo 		iwl_op_mode_nic_error(trans->op_mode);
1248e705c121SKalle Valo }
1249e705c121SKalle Valo 
1250d1967ce6SShahar S Matityahu static inline void iwl_trans_sync_nmi(struct iwl_trans *trans)
1251d1967ce6SShahar S Matityahu {
1252d1967ce6SShahar S Matityahu 	if (trans->ops->sync_nmi)
1253d1967ce6SShahar S Matityahu 		trans->ops->sync_nmi(trans);
1254d1967ce6SShahar S Matityahu }
1255d1967ce6SShahar S Matityahu 
1256a1af4c48SShahar S Matityahu static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans)
1257a1af4c48SShahar S Matityahu {
1258341bd290SShahar S Matityahu 	return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED ||
1259341bd290SShahar S Matityahu 		trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED;
1260a1af4c48SShahar S Matityahu }
1261a1af4c48SShahar S Matityahu 
1262e705c121SKalle Valo /*****************************************************
1263e705c121SKalle Valo  * transport helper functions
1264e705c121SKalle Valo  *****************************************************/
1265e705c121SKalle Valo struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
1266e705c121SKalle Valo 				  struct device *dev,
12671ea423b0SLuca Coelho 				  const struct iwl_trans_ops *ops);
1268e705c121SKalle Valo void iwl_trans_free(struct iwl_trans *trans);
1269e705c121SKalle Valo 
1270e705c121SKalle Valo /*****************************************************
1271e705c121SKalle Valo * driver (transport) register/unregister functions
1272e705c121SKalle Valo ******************************************************/
1273e705c121SKalle Valo int __must_check iwl_pci_register_driver(void);
1274e705c121SKalle Valo void iwl_pci_unregister_driver(void);
1275e705c121SKalle Valo 
1276e705c121SKalle Valo #endif /* __iwl_trans_h__ */
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